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-rw-r--r--drivers/net/forcedeth.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 5b68dc20168d..5b910cf63740 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -13,7 +13,7 @@
13 * Copyright (C) 2004 Andrew de Quincey (wol support) 13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane 14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification) 15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation 16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 * 17 *
18 * This program is free software; you can redistribute it and/or modify 18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by 19 * it under the terms of the GNU General Public License as published by
@@ -39,7 +39,7 @@
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic. 40 * superfluous timer interrupts from the nic.
41 */ 41 */
42#define FORCEDETH_VERSION "0.61" 42#define FORCEDETH_VERSION "0.62"
43#define DRV_NAME "forcedeth" 43#define DRV_NAME "forcedeth"
44 44
45#include <linux/module.h> 45#include <linux/module.h>
@@ -2096,14 +2096,15 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2096 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); 2096 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2097 } 2097 }
2098 2098
2099 spin_lock_irqsave(&np->lock, flags);
2099 empty_slots = nv_get_empty_tx_slots(np); 2100 empty_slots = nv_get_empty_tx_slots(np);
2100 if (unlikely(empty_slots <= entries)) { 2101 if (unlikely(empty_slots <= entries)) {
2101 spin_lock_irqsave(&np->lock, flags);
2102 netif_stop_queue(dev); 2102 netif_stop_queue(dev);
2103 np->tx_stop = 1; 2103 np->tx_stop = 1;
2104 spin_unlock_irqrestore(&np->lock, flags); 2104 spin_unlock_irqrestore(&np->lock, flags);
2105 return NETDEV_TX_BUSY; 2105 return NETDEV_TX_BUSY;
2106 } 2106 }
2107 spin_unlock_irqrestore(&np->lock, flags);
2107 2108
2108 start_tx = put_tx = np->put_tx.orig; 2109 start_tx = put_tx = np->put_tx.orig;
2109 2110
@@ -2214,14 +2215,15 @@ static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2214 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); 2215 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2215 } 2216 }
2216 2217
2218 spin_lock_irqsave(&np->lock, flags);
2217 empty_slots = nv_get_empty_tx_slots(np); 2219 empty_slots = nv_get_empty_tx_slots(np);
2218 if (unlikely(empty_slots <= entries)) { 2220 if (unlikely(empty_slots <= entries)) {
2219 spin_lock_irqsave(&np->lock, flags);
2220 netif_stop_queue(dev); 2221 netif_stop_queue(dev);
2221 np->tx_stop = 1; 2222 np->tx_stop = 1;
2222 spin_unlock_irqrestore(&np->lock, flags); 2223 spin_unlock_irqrestore(&np->lock, flags);
2223 return NETDEV_TX_BUSY; 2224 return NETDEV_TX_BUSY;
2224 } 2225 }
2226 spin_unlock_irqrestore(&np->lock, flags);
2225 2227
2226 start_tx = put_tx = np->put_tx.ex; 2228 start_tx = put_tx = np->put_tx.ex;
2227 start_tx_ctx = np->put_tx_ctx; 2229 start_tx_ctx = np->put_tx_ctx;
@@ -3403,10 +3405,10 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
3403 3405
3404#ifdef CONFIG_FORCEDETH_NAPI 3406#ifdef CONFIG_FORCEDETH_NAPI
3405 if (events & NVREG_IRQ_RX_ALL) { 3407 if (events & NVREG_IRQ_RX_ALL) {
3408 spin_lock(&np->lock);
3406 netif_rx_schedule(&np->napi); 3409 netif_rx_schedule(&np->napi);
3407 3410
3408 /* Disable furthur receive irq's */ 3411 /* Disable furthur receive irq's */
3409 spin_lock(&np->lock);
3410 np->irqmask &= ~NVREG_IRQ_RX_ALL; 3412 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3411 3413
3412 if (np->msi_flags & NV_MSI_X_ENABLED) 3414 if (np->msi_flags & NV_MSI_X_ENABLED)
@@ -3520,10 +3522,10 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3520 3522
3521#ifdef CONFIG_FORCEDETH_NAPI 3523#ifdef CONFIG_FORCEDETH_NAPI
3522 if (events & NVREG_IRQ_RX_ALL) { 3524 if (events & NVREG_IRQ_RX_ALL) {
3525 spin_lock(&np->lock);
3523 netif_rx_schedule(&np->napi); 3526 netif_rx_schedule(&np->napi);
3524 3527
3525 /* Disable furthur receive irq's */ 3528 /* Disable furthur receive irq's */
3526 spin_lock(&np->lock);
3527 np->irqmask &= ~NVREG_IRQ_RX_ALL; 3529 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3528 3530
3529 if (np->msi_flags & NV_MSI_X_ENABLED) 3531 if (np->msi_flags & NV_MSI_X_ENABLED)
@@ -6167,19 +6169,19 @@ static struct pci_device_id pci_tbl[] = {
6167 }, 6169 },
6168 { /* MCP79 Ethernet Controller */ 6170 { /* MCP79 Ethernet Controller */
6169 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), 6171 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6170 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6172 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6171 }, 6173 },
6172 { /* MCP79 Ethernet Controller */ 6174 { /* MCP79 Ethernet Controller */
6173 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), 6175 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6174 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6176 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6175 }, 6177 },
6176 { /* MCP79 Ethernet Controller */ 6178 { /* MCP79 Ethernet Controller */
6177 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), 6179 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6178 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6180 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6179 }, 6181 },
6180 { /* MCP79 Ethernet Controller */ 6182 { /* MCP79 Ethernet Controller */
6181 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), 6183 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6182 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6184 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6183 }, 6185 },
6184 {0,}, 6186 {0,},
6185}; 6187};