diff options
Diffstat (limited to 'drivers/net/forcedeth.c')
| -rw-r--r-- | drivers/net/forcedeth.c | 310 |
1 files changed, 202 insertions, 108 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index d6eefdb71c17..22aec6ed80f5 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
| @@ -95,6 +95,8 @@ | |||
| 95 | * of nv_remove | 95 | * of nv_remove |
| 96 | * 0.42: 06 Aug 2005: Fix lack of link speed initialization | 96 | * 0.42: 06 Aug 2005: Fix lack of link speed initialization |
| 97 | * in the second (and later) nv_open call | 97 | * in the second (and later) nv_open call |
| 98 | * 0.43: 10 Aug 2005: Add support for tx checksum. | ||
| 99 | * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation. | ||
| 98 | * | 100 | * |
| 99 | * Known bugs: | 101 | * Known bugs: |
| 100 | * We suspect that on some hardware no TX done interrupts are generated. | 102 | * We suspect that on some hardware no TX done interrupts are generated. |
| @@ -106,7 +108,7 @@ | |||
| 106 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | 108 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
| 107 | * superfluous timer interrupts from the nic. | 109 | * superfluous timer interrupts from the nic. |
| 108 | */ | 110 | */ |
| 109 | #define FORCEDETH_VERSION "0.41" | 111 | #define FORCEDETH_VERSION "0.44" |
| 110 | #define DRV_NAME "forcedeth" | 112 | #define DRV_NAME "forcedeth" |
| 111 | 113 | ||
| 112 | #include <linux/module.h> | 114 | #include <linux/module.h> |
| @@ -145,6 +147,7 @@ | |||
| 145 | #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */ | 147 | #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */ |
| 146 | #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */ | 148 | #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */ |
| 147 | #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */ | 149 | #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */ |
| 150 | #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */ | ||
| 148 | 151 | ||
| 149 | enum { | 152 | enum { |
| 150 | NvRegIrqStatus = 0x000, | 153 | NvRegIrqStatus = 0x000, |
| @@ -241,6 +244,9 @@ enum { | |||
| 241 | #define NVREG_TXRXCTL_IDLE 0x0008 | 244 | #define NVREG_TXRXCTL_IDLE 0x0008 |
| 242 | #define NVREG_TXRXCTL_RESET 0x0010 | 245 | #define NVREG_TXRXCTL_RESET 0x0010 |
| 243 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | 246 | #define NVREG_TXRXCTL_RXCHECK 0x0400 |
| 247 | #define NVREG_TXRXCTL_DESC_1 0 | ||
| 248 | #define NVREG_TXRXCTL_DESC_2 0x02100 | ||
| 249 | #define NVREG_TXRXCTL_DESC_3 0x02200 | ||
| 244 | NvRegMIIStatus = 0x180, | 250 | NvRegMIIStatus = 0x180, |
| 245 | #define NVREG_MIISTAT_ERROR 0x0001 | 251 | #define NVREG_MIISTAT_ERROR 0x0001 |
| 246 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | 252 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 |
| @@ -335,6 +341,10 @@ typedef union _ring_type { | |||
| 335 | /* error and valid are the same for both */ | 341 | /* error and valid are the same for both */ |
| 336 | #define NV_TX2_ERROR (1<<30) | 342 | #define NV_TX2_ERROR (1<<30) |
| 337 | #define NV_TX2_VALID (1<<31) | 343 | #define NV_TX2_VALID (1<<31) |
| 344 | #define NV_TX2_TSO (1<<28) | ||
| 345 | #define NV_TX2_TSO_SHIFT 14 | ||
| 346 | #define NV_TX2_CHECKSUM_L3 (1<<27) | ||
| 347 | #define NV_TX2_CHECKSUM_L4 (1<<26) | ||
| 338 | 348 | ||
| 339 | #define NV_RX_DESCRIPTORVALID (1<<16) | 349 | #define NV_RX_DESCRIPTORVALID (1<<16) |
| 340 | #define NV_RX_MISSEDFRAME (1<<17) | 350 | #define NV_RX_MISSEDFRAME (1<<17) |
| @@ -417,14 +427,14 @@ typedef union _ring_type { | |||
| 417 | 427 | ||
| 418 | /* | 428 | /* |
| 419 | * desc_ver values: | 429 | * desc_ver values: |
| 420 | * This field has two purposes: | 430 | * The nic supports three different descriptor types: |
| 421 | * - Newer nics uses a different ring layout. The layout is selected by | 431 | * - DESC_VER_1: Original |
| 422 | * comparing np->desc_ver with DESC_VER_xy. | 432 | * - DESC_VER_2: support for jumbo frames. |
| 423 | * - It contains bits that are forced on when writing to NvRegTxRxControl. | 433 | * - DESC_VER_3: 64-bit format. |
| 424 | */ | 434 | */ |
| 425 | #define DESC_VER_1 0x0 | 435 | #define DESC_VER_1 1 |
| 426 | #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK) | 436 | #define DESC_VER_2 2 |
| 427 | #define DESC_VER_3 (0x02200|NVREG_TXRXCTL_RXCHECK) | 437 | #define DESC_VER_3 3 |
| 428 | 438 | ||
| 429 | /* PHY defines */ | 439 | /* PHY defines */ |
| 430 | #define PHY_OUI_MARVELL 0x5043 | 440 | #define PHY_OUI_MARVELL 0x5043 |
| @@ -491,6 +501,7 @@ struct fe_priv { | |||
| 491 | u32 orig_mac[2]; | 501 | u32 orig_mac[2]; |
| 492 | u32 irqmask; | 502 | u32 irqmask; |
| 493 | u32 desc_ver; | 503 | u32 desc_ver; |
| 504 | u32 txrxctl_bits; | ||
| 494 | 505 | ||
| 495 | void __iomem *base; | 506 | void __iomem *base; |
| 496 | 507 | ||
| @@ -534,7 +545,7 @@ static inline struct fe_priv *get_nvpriv(struct net_device *dev) | |||
| 534 | 545 | ||
| 535 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | 546 | static inline u8 __iomem *get_hwbase(struct net_device *dev) |
| 536 | { | 547 | { |
| 537 | return get_nvpriv(dev)->base; | 548 | return ((struct fe_priv *)netdev_priv(dev))->base; |
| 538 | } | 549 | } |
| 539 | 550 | ||
| 540 | static inline void pci_push(u8 __iomem *base) | 551 | static inline void pci_push(u8 __iomem *base) |
| @@ -623,7 +634,7 @@ static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |||
| 623 | 634 | ||
| 624 | static int phy_reset(struct net_device *dev) | 635 | static int phy_reset(struct net_device *dev) |
| 625 | { | 636 | { |
| 626 | struct fe_priv *np = get_nvpriv(dev); | 637 | struct fe_priv *np = netdev_priv(dev); |
| 627 | u32 miicontrol; | 638 | u32 miicontrol; |
| 628 | unsigned int tries = 0; | 639 | unsigned int tries = 0; |
| 629 | 640 | ||
| @@ -726,7 +737,7 @@ static int phy_init(struct net_device *dev) | |||
| 726 | 737 | ||
| 727 | static void nv_start_rx(struct net_device *dev) | 738 | static void nv_start_rx(struct net_device *dev) |
| 728 | { | 739 | { |
| 729 | struct fe_priv *np = get_nvpriv(dev); | 740 | struct fe_priv *np = netdev_priv(dev); |
| 730 | u8 __iomem *base = get_hwbase(dev); | 741 | u8 __iomem *base = get_hwbase(dev); |
| 731 | 742 | ||
| 732 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | 743 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
| @@ -782,14 +793,14 @@ static void nv_stop_tx(struct net_device *dev) | |||
| 782 | 793 | ||
| 783 | static void nv_txrx_reset(struct net_device *dev) | 794 | static void nv_txrx_reset(struct net_device *dev) |
| 784 | { | 795 | { |
| 785 | struct fe_priv *np = get_nvpriv(dev); | 796 | struct fe_priv *np = netdev_priv(dev); |
| 786 | u8 __iomem *base = get_hwbase(dev); | 797 | u8 __iomem *base = get_hwbase(dev); |
| 787 | 798 | ||
| 788 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); | 799 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); |
| 789 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl); | 800 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
| 790 | pci_push(base); | 801 | pci_push(base); |
| 791 | udelay(NV_TXRX_RESET_DELAY); | 802 | udelay(NV_TXRX_RESET_DELAY); |
| 792 | writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl); | 803 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
| 793 | pci_push(base); | 804 | pci_push(base); |
| 794 | } | 805 | } |
| 795 | 806 | ||
| @@ -801,7 +812,7 @@ static void nv_txrx_reset(struct net_device *dev) | |||
| 801 | */ | 812 | */ |
| 802 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | 813 | static struct net_device_stats *nv_get_stats(struct net_device *dev) |
| 803 | { | 814 | { |
| 804 | struct fe_priv *np = get_nvpriv(dev); | 815 | struct fe_priv *np = netdev_priv(dev); |
| 805 | 816 | ||
| 806 | /* It seems that the nic always generates interrupts and doesn't | 817 | /* It seems that the nic always generates interrupts and doesn't |
| 807 | * accumulate errors internally. Thus the current values in np->stats | 818 | * accumulate errors internally. Thus the current values in np->stats |
| @@ -817,7 +828,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev) | |||
| 817 | */ | 828 | */ |
| 818 | static int nv_alloc_rx(struct net_device *dev) | 829 | static int nv_alloc_rx(struct net_device *dev) |
| 819 | { | 830 | { |
| 820 | struct fe_priv *np = get_nvpriv(dev); | 831 | struct fe_priv *np = netdev_priv(dev); |
| 821 | unsigned int refill_rx = np->refill_rx; | 832 | unsigned int refill_rx = np->refill_rx; |
| 822 | int nr; | 833 | int nr; |
| 823 | 834 | ||
| @@ -861,7 +872,7 @@ static int nv_alloc_rx(struct net_device *dev) | |||
| 861 | static void nv_do_rx_refill(unsigned long data) | 872 | static void nv_do_rx_refill(unsigned long data) |
| 862 | { | 873 | { |
| 863 | struct net_device *dev = (struct net_device *) data; | 874 | struct net_device *dev = (struct net_device *) data; |
| 864 | struct fe_priv *np = get_nvpriv(dev); | 875 | struct fe_priv *np = netdev_priv(dev); |
| 865 | 876 | ||
| 866 | disable_irq(dev->irq); | 877 | disable_irq(dev->irq); |
| 867 | if (nv_alloc_rx(dev)) { | 878 | if (nv_alloc_rx(dev)) { |
| @@ -875,7 +886,7 @@ static void nv_do_rx_refill(unsigned long data) | |||
| 875 | 886 | ||
| 876 | static void nv_init_rx(struct net_device *dev) | 887 | static void nv_init_rx(struct net_device *dev) |
| 877 | { | 888 | { |
| 878 | struct fe_priv *np = get_nvpriv(dev); | 889 | struct fe_priv *np = netdev_priv(dev); |
| 879 | int i; | 890 | int i; |
| 880 | 891 | ||
| 881 | np->cur_rx = RX_RING; | 892 | np->cur_rx = RX_RING; |
| @@ -889,15 +900,17 @@ static void nv_init_rx(struct net_device *dev) | |||
| 889 | 900 | ||
| 890 | static void nv_init_tx(struct net_device *dev) | 901 | static void nv_init_tx(struct net_device *dev) |
| 891 | { | 902 | { |
| 892 | struct fe_priv *np = get_nvpriv(dev); | 903 | struct fe_priv *np = netdev_priv(dev); |
| 893 | int i; | 904 | int i; |
| 894 | 905 | ||
| 895 | np->next_tx = np->nic_tx = 0; | 906 | np->next_tx = np->nic_tx = 0; |
| 896 | for (i = 0; i < TX_RING; i++) | 907 | for (i = 0; i < TX_RING; i++) { |
| 897 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | 908 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
| 898 | np->tx_ring.orig[i].FlagLen = 0; | 909 | np->tx_ring.orig[i].FlagLen = 0; |
| 899 | else | 910 | else |
| 900 | np->tx_ring.ex[i].FlagLen = 0; | 911 | np->tx_ring.ex[i].FlagLen = 0; |
| 912 | np->tx_skbuff[i] = NULL; | ||
| 913 | } | ||
| 901 | } | 914 | } |
| 902 | 915 | ||
| 903 | static int nv_init_ring(struct net_device *dev) | 916 | static int nv_init_ring(struct net_device *dev) |
| @@ -907,21 +920,44 @@ static int nv_init_ring(struct net_device *dev) | |||
| 907 | return nv_alloc_rx(dev); | 920 | return nv_alloc_rx(dev); |
| 908 | } | 921 | } |
| 909 | 922 | ||
| 923 | static void nv_release_txskb(struct net_device *dev, unsigned int skbnr) | ||
| 924 | { | ||
| 925 | struct fe_priv *np = netdev_priv(dev); | ||
| 926 | struct sk_buff *skb = np->tx_skbuff[skbnr]; | ||
| 927 | unsigned int j, entry, fragments; | ||
| 928 | |||
| 929 | dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d, skb %p\n", | ||
| 930 | dev->name, skbnr, np->tx_skbuff[skbnr]); | ||
| 931 | |||
| 932 | entry = skbnr; | ||
| 933 | if ((fragments = skb_shinfo(skb)->nr_frags) != 0) { | ||
| 934 | for (j = fragments; j >= 1; j--) { | ||
| 935 | skb_frag_t *frag = &skb_shinfo(skb)->frags[j-1]; | ||
| 936 | pci_unmap_page(np->pci_dev, np->tx_dma[entry], | ||
| 937 | frag->size, | ||
| 938 | PCI_DMA_TODEVICE); | ||
| 939 | entry = (entry - 1) % TX_RING; | ||
| 940 | } | ||
| 941 | } | ||
| 942 | pci_unmap_single(np->pci_dev, np->tx_dma[entry], | ||
| 943 | skb->len - skb->data_len, | ||
| 944 | PCI_DMA_TODEVICE); | ||
| 945 | dev_kfree_skb_irq(skb); | ||
| 946 | np->tx_skbuff[skbnr] = NULL; | ||
| 947 | } | ||
| 948 | |||
| 910 | static void nv_drain_tx(struct net_device *dev) | 949 | static void nv_drain_tx(struct net_device *dev) |
| 911 | { | 950 | { |
| 912 | struct fe_priv *np = get_nvpriv(dev); | 951 | struct fe_priv *np = netdev_priv(dev); |
| 913 | int i; | 952 | unsigned int i; |
| 953 | |||
| 914 | for (i = 0; i < TX_RING; i++) { | 954 | for (i = 0; i < TX_RING; i++) { |
| 915 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | 955 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
| 916 | np->tx_ring.orig[i].FlagLen = 0; | 956 | np->tx_ring.orig[i].FlagLen = 0; |
| 917 | else | 957 | else |
| 918 | np->tx_ring.ex[i].FlagLen = 0; | 958 | np->tx_ring.ex[i].FlagLen = 0; |
| 919 | if (np->tx_skbuff[i]) { | 959 | if (np->tx_skbuff[i]) { |
| 920 | pci_unmap_single(np->pci_dev, np->tx_dma[i], | 960 | nv_release_txskb(dev, i); |
| 921 | np->tx_skbuff[i]->len, | ||
| 922 | PCI_DMA_TODEVICE); | ||
| 923 | dev_kfree_skb(np->tx_skbuff[i]); | ||
| 924 | np->tx_skbuff[i] = NULL; | ||
| 925 | np->stats.tx_dropped++; | 961 | np->stats.tx_dropped++; |
| 926 | } | 962 | } |
| 927 | } | 963 | } |
| @@ -929,7 +965,7 @@ static void nv_drain_tx(struct net_device *dev) | |||
| 929 | 965 | ||
| 930 | static void nv_drain_rx(struct net_device *dev) | 966 | static void nv_drain_rx(struct net_device *dev) |
| 931 | { | 967 | { |
| 932 | struct fe_priv *np = get_nvpriv(dev); | 968 | struct fe_priv *np = netdev_priv(dev); |
| 933 | int i; | 969 | int i; |
| 934 | for (i = 0; i < RX_RING; i++) { | 970 | for (i = 0; i < RX_RING; i++) { |
| 935 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | 971 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
| @@ -959,28 +995,69 @@ static void drain_ring(struct net_device *dev) | |||
| 959 | */ | 995 | */ |
| 960 | static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | 996 | static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 961 | { | 997 | { |
| 962 | struct fe_priv *np = get_nvpriv(dev); | 998 | struct fe_priv *np = netdev_priv(dev); |
| 963 | int nr = np->next_tx % TX_RING; | 999 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
| 1000 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | ||
| 1001 | unsigned int nr = (np->next_tx + fragments) % TX_RING; | ||
| 1002 | unsigned int i; | ||
| 1003 | |||
| 1004 | spin_lock_irq(&np->lock); | ||
| 1005 | |||
| 1006 | if ((np->next_tx - np->nic_tx + fragments) > TX_LIMIT_STOP) { | ||
| 1007 | spin_unlock_irq(&np->lock); | ||
| 1008 | netif_stop_queue(dev); | ||
| 1009 | return NETDEV_TX_BUSY; | ||
| 1010 | } | ||
| 964 | 1011 | ||
| 965 | np->tx_skbuff[nr] = skb; | 1012 | np->tx_skbuff[nr] = skb; |
| 966 | np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len, | 1013 | |
| 967 | PCI_DMA_TODEVICE); | 1014 | if (fragments) { |
| 1015 | dprintk(KERN_DEBUG "%s: nv_start_xmit: buffer contains %d fragments\n", dev->name, fragments); | ||
| 1016 | /* setup descriptors in reverse order */ | ||
| 1017 | for (i = fragments; i >= 1; i--) { | ||
| 1018 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i-1]; | ||
| 1019 | np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset, frag->size, | ||
| 1020 | PCI_DMA_TODEVICE); | ||
| 968 | 1021 | ||
| 969 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | 1022 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
| 1023 | np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); | ||
| 1024 | np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra); | ||
| 1025 | } else { | ||
| 1026 | np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; | ||
| 1027 | np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; | ||
| 1028 | np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra); | ||
| 1029 | } | ||
| 1030 | |||
| 1031 | nr = (nr - 1) % TX_RING; | ||
| 1032 | |||
| 1033 | if (np->desc_ver == DESC_VER_1) | ||
| 1034 | tx_flags_extra &= ~NV_TX_LASTPACKET; | ||
| 1035 | else | ||
| 1036 | tx_flags_extra &= ~NV_TX2_LASTPACKET; | ||
| 1037 | } | ||
| 1038 | } | ||
| 1039 | |||
| 1040 | #ifdef NETIF_F_TSO | ||
| 1041 | if (skb_shinfo(skb)->tso_size) | ||
| 1042 | tx_flags_extra |= NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT); | ||
| 1043 | else | ||
| 1044 | #endif | ||
| 1045 | tx_flags_extra |= (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0); | ||
| 1046 | |||
| 1047 | np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len-skb->data_len, | ||
| 1048 | PCI_DMA_TODEVICE); | ||
| 1049 | |||
| 1050 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | ||
| 970 | np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); | 1051 | np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
| 971 | else { | 1052 | np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra); |
| 1053 | } else { | ||
| 972 | np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; | 1054 | np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
| 973 | np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; | 1055 | np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
| 974 | } | 1056 | np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra); |
| 1057 | } | ||
| 975 | 1058 | ||
| 976 | spin_lock_irq(&np->lock); | 1059 | dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission. tx_flags_extra: %x\n", |
| 977 | wmb(); | 1060 | dev->name, np->next_tx, tx_flags_extra); |
| 978 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | ||
| 979 | np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags ); | ||
| 980 | else | ||
| 981 | np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags ); | ||
| 982 | dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n", | ||
| 983 | dev->name, np->next_tx); | ||
| 984 | { | 1061 | { |
| 985 | int j; | 1062 | int j; |
| 986 | for (j=0; j<64; j++) { | 1063 | for (j=0; j<64; j++) { |
| @@ -991,15 +1068,13 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 991 | dprintk("\n"); | 1068 | dprintk("\n"); |
| 992 | } | 1069 | } |
| 993 | 1070 | ||
| 994 | np->next_tx++; | 1071 | np->next_tx += 1 + fragments; |
| 995 | 1072 | ||
| 996 | dev->trans_start = jiffies; | 1073 | dev->trans_start = jiffies; |
| 997 | if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP) | ||
| 998 | netif_stop_queue(dev); | ||
| 999 | spin_unlock_irq(&np->lock); | 1074 | spin_unlock_irq(&np->lock); |
| 1000 | writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl); | 1075 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
| 1001 | pci_push(get_hwbase(dev)); | 1076 | pci_push(get_hwbase(dev)); |
| 1002 | return 0; | 1077 | return NETDEV_TX_OK; |
| 1003 | } | 1078 | } |
| 1004 | 1079 | ||
| 1005 | /* | 1080 | /* |
| @@ -1009,9 +1084,10 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 1009 | */ | 1084 | */ |
| 1010 | static void nv_tx_done(struct net_device *dev) | 1085 | static void nv_tx_done(struct net_device *dev) |
| 1011 | { | 1086 | { |
| 1012 | struct fe_priv *np = get_nvpriv(dev); | 1087 | struct fe_priv *np = netdev_priv(dev); |
| 1013 | u32 Flags; | 1088 | u32 Flags; |
| 1014 | int i; | 1089 | unsigned int i; |
| 1090 | struct sk_buff *skb; | ||
| 1015 | 1091 | ||
| 1016 | while (np->nic_tx != np->next_tx) { | 1092 | while (np->nic_tx != np->next_tx) { |
| 1017 | i = np->nic_tx % TX_RING; | 1093 | i = np->nic_tx % TX_RING; |
| @@ -1026,35 +1102,38 @@ static void nv_tx_done(struct net_device *dev) | |||
| 1026 | if (Flags & NV_TX_VALID) | 1102 | if (Flags & NV_TX_VALID) |
| 1027 | break; | 1103 | break; |
| 1028 | if (np->desc_ver == DESC_VER_1) { | 1104 | if (np->desc_ver == DESC_VER_1) { |
| 1029 | if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| | 1105 | if (Flags & NV_TX_LASTPACKET) { |
| 1030 | NV_TX_UNDERFLOW|NV_TX_ERROR)) { | 1106 | skb = np->tx_skbuff[i]; |
| 1031 | if (Flags & NV_TX_UNDERFLOW) | 1107 | if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| |
| 1032 | np->stats.tx_fifo_errors++; | 1108 | NV_TX_UNDERFLOW|NV_TX_ERROR)) { |
| 1033 | if (Flags & NV_TX_CARRIERLOST) | 1109 | if (Flags & NV_TX_UNDERFLOW) |
| 1034 | np->stats.tx_carrier_errors++; | 1110 | np->stats.tx_fifo_errors++; |
| 1035 | np->stats.tx_errors++; | 1111 | if (Flags & NV_TX_CARRIERLOST) |
| 1036 | } else { | 1112 | np->stats.tx_carrier_errors++; |
| 1037 | np->stats.tx_packets++; | 1113 | np->stats.tx_errors++; |
| 1038 | np->stats.tx_bytes += np->tx_skbuff[i]->len; | 1114 | } else { |
| 1115 | np->stats.tx_packets++; | ||
| 1116 | np->stats.tx_bytes += skb->len; | ||
| 1117 | } | ||
| 1118 | nv_release_txskb(dev, i); | ||
| 1039 | } | 1119 | } |
| 1040 | } else { | 1120 | } else { |
| 1041 | if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| | 1121 | if (Flags & NV_TX2_LASTPACKET) { |
| 1042 | NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { | 1122 | skb = np->tx_skbuff[i]; |
| 1043 | if (Flags & NV_TX2_UNDERFLOW) | 1123 | if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| |
| 1044 | np->stats.tx_fifo_errors++; | 1124 | NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { |
| 1045 | if (Flags & NV_TX2_CARRIERLOST) | 1125 | if (Flags & NV_TX2_UNDERFLOW) |
| 1046 | np->stats.tx_carrier_errors++; | 1126 | np->stats.tx_fifo_errors++; |
| 1047 | np->stats.tx_errors++; | 1127 | if (Flags & NV_TX2_CARRIERLOST) |
| 1048 | } else { | 1128 | np->stats.tx_carrier_errors++; |
| 1049 | np->stats.tx_packets++; | 1129 | np->stats.tx_errors++; |
| 1050 | np->stats.tx_bytes += np->tx_skbuff[i]->len; | 1130 | } else { |
| 1131 | np->stats.tx_packets++; | ||
| 1132 | np->stats.tx_bytes += skb->len; | ||
| 1133 | } | ||
| 1134 | nv_release_txskb(dev, i); | ||
| 1051 | } | 1135 | } |
| 1052 | } | 1136 | } |
| 1053 | pci_unmap_single(np->pci_dev, np->tx_dma[i], | ||
| 1054 | np->tx_skbuff[i]->len, | ||
| 1055 | PCI_DMA_TODEVICE); | ||
| 1056 | dev_kfree_skb_irq(np->tx_skbuff[i]); | ||
| 1057 | np->tx_skbuff[i] = NULL; | ||
| 1058 | np->nic_tx++; | 1137 | np->nic_tx++; |
| 1059 | } | 1138 | } |
| 1060 | if (np->next_tx - np->nic_tx < TX_LIMIT_START) | 1139 | if (np->next_tx - np->nic_tx < TX_LIMIT_START) |
| @@ -1067,7 +1146,7 @@ static void nv_tx_done(struct net_device *dev) | |||
| 1067 | */ | 1146 | */ |
| 1068 | static void nv_tx_timeout(struct net_device *dev) | 1147 | static void nv_tx_timeout(struct net_device *dev) |
| 1069 | { | 1148 | { |
| 1070 | struct fe_priv *np = get_nvpriv(dev); | 1149 | struct fe_priv *np = netdev_priv(dev); |
| 1071 | u8 __iomem *base = get_hwbase(dev); | 1150 | u8 __iomem *base = get_hwbase(dev); |
| 1072 | 1151 | ||
| 1073 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, | 1152 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, |
| @@ -1200,7 +1279,7 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |||
| 1200 | 1279 | ||
| 1201 | static void nv_rx_process(struct net_device *dev) | 1280 | static void nv_rx_process(struct net_device *dev) |
| 1202 | { | 1281 | { |
| 1203 | struct fe_priv *np = get_nvpriv(dev); | 1282 | struct fe_priv *np = netdev_priv(dev); |
| 1204 | u32 Flags; | 1283 | u32 Flags; |
| 1205 | 1284 | ||
| 1206 | for (;;) { | 1285 | for (;;) { |
| @@ -1355,7 +1434,7 @@ static void set_bufsize(struct net_device *dev) | |||
| 1355 | */ | 1434 | */ |
| 1356 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | 1435 | static int nv_change_mtu(struct net_device *dev, int new_mtu) |
| 1357 | { | 1436 | { |
| 1358 | struct fe_priv *np = get_nvpriv(dev); | 1437 | struct fe_priv *np = netdev_priv(dev); |
| 1359 | int old_mtu; | 1438 | int old_mtu; |
| 1360 | 1439 | ||
| 1361 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | 1440 | if (new_mtu < 64 || new_mtu > np->pkt_limit) |
| @@ -1408,7 +1487,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu) | |||
| 1408 | writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), | 1487 | writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
| 1409 | base + NvRegRingSizes); | 1488 | base + NvRegRingSizes); |
| 1410 | pci_push(base); | 1489 | pci_push(base); |
| 1411 | writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl); | 1490 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
| 1412 | pci_push(base); | 1491 | pci_push(base); |
| 1413 | 1492 | ||
| 1414 | /* restart rx engine */ | 1493 | /* restart rx engine */ |
| @@ -1440,7 +1519,7 @@ static void nv_copy_mac_to_hw(struct net_device *dev) | |||
| 1440 | */ | 1519 | */ |
| 1441 | static int nv_set_mac_address(struct net_device *dev, void *addr) | 1520 | static int nv_set_mac_address(struct net_device *dev, void *addr) |
| 1442 | { | 1521 | { |
| 1443 | struct fe_priv *np = get_nvpriv(dev); | 1522 | struct fe_priv *np = netdev_priv(dev); |
| 1444 | struct sockaddr *macaddr = (struct sockaddr*)addr; | 1523 | struct sockaddr *macaddr = (struct sockaddr*)addr; |
| 1445 | 1524 | ||
| 1446 | if(!is_valid_ether_addr(macaddr->sa_data)) | 1525 | if(!is_valid_ether_addr(macaddr->sa_data)) |
| @@ -1475,7 +1554,7 @@ static int nv_set_mac_address(struct net_device *dev, void *addr) | |||
| 1475 | */ | 1554 | */ |
| 1476 | static void nv_set_multicast(struct net_device *dev) | 1555 | static void nv_set_multicast(struct net_device *dev) |
| 1477 | { | 1556 | { |
| 1478 | struct fe_priv *np = get_nvpriv(dev); | 1557 | struct fe_priv *np = netdev_priv(dev); |
| 1479 | u8 __iomem *base = get_hwbase(dev); | 1558 | u8 __iomem *base = get_hwbase(dev); |
| 1480 | u32 addr[2]; | 1559 | u32 addr[2]; |
| 1481 | u32 mask[2]; | 1560 | u32 mask[2]; |
| @@ -1535,7 +1614,7 @@ static void nv_set_multicast(struct net_device *dev) | |||
| 1535 | 1614 | ||
| 1536 | static int nv_update_linkspeed(struct net_device *dev) | 1615 | static int nv_update_linkspeed(struct net_device *dev) |
| 1537 | { | 1616 | { |
| 1538 | struct fe_priv *np = get_nvpriv(dev); | 1617 | struct fe_priv *np = netdev_priv(dev); |
| 1539 | u8 __iomem *base = get_hwbase(dev); | 1618 | u8 __iomem *base = get_hwbase(dev); |
| 1540 | int adv, lpa; | 1619 | int adv, lpa; |
| 1541 | int newls = np->linkspeed; | 1620 | int newls = np->linkspeed; |
| @@ -1705,7 +1784,7 @@ static void nv_link_irq(struct net_device *dev) | |||
| 1705 | static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) | 1784 | static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) |
| 1706 | { | 1785 | { |
| 1707 | struct net_device *dev = (struct net_device *) data; | 1786 | struct net_device *dev = (struct net_device *) data; |
| 1708 | struct fe_priv *np = get_nvpriv(dev); | 1787 | struct fe_priv *np = netdev_priv(dev); |
| 1709 | u8 __iomem *base = get_hwbase(dev); | 1788 | u8 __iomem *base = get_hwbase(dev); |
| 1710 | u32 events; | 1789 | u32 events; |
| 1711 | int i; | 1790 | int i; |
| @@ -1777,7 +1856,7 @@ static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) | |||
| 1777 | static void nv_do_nic_poll(unsigned long data) | 1856 | static void nv_do_nic_poll(unsigned long data) |
| 1778 | { | 1857 | { |
| 1779 | struct net_device *dev = (struct net_device *) data; | 1858 | struct net_device *dev = (struct net_device *) data; |
| 1780 | struct fe_priv *np = get_nvpriv(dev); | 1859 | struct fe_priv *np = netdev_priv(dev); |
| 1781 | u8 __iomem *base = get_hwbase(dev); | 1860 | u8 __iomem *base = get_hwbase(dev); |
| 1782 | 1861 | ||
| 1783 | disable_irq(dev->irq); | 1862 | disable_irq(dev->irq); |
| @@ -1801,7 +1880,7 @@ static void nv_poll_controller(struct net_device *dev) | |||
| 1801 | 1880 | ||
| 1802 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | 1881 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
| 1803 | { | 1882 | { |
| 1804 | struct fe_priv *np = get_nvpriv(dev); | 1883 | struct fe_priv *np = netdev_priv(dev); |
| 1805 | strcpy(info->driver, "forcedeth"); | 1884 | strcpy(info->driver, "forcedeth"); |
| 1806 | strcpy(info->version, FORCEDETH_VERSION); | 1885 | strcpy(info->version, FORCEDETH_VERSION); |
| 1807 | strcpy(info->bus_info, pci_name(np->pci_dev)); | 1886 | strcpy(info->bus_info, pci_name(np->pci_dev)); |
| @@ -1809,7 +1888,7 @@ static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |||
| 1809 | 1888 | ||
| 1810 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | 1889 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
| 1811 | { | 1890 | { |
| 1812 | struct fe_priv *np = get_nvpriv(dev); | 1891 | struct fe_priv *np = netdev_priv(dev); |
| 1813 | wolinfo->supported = WAKE_MAGIC; | 1892 | wolinfo->supported = WAKE_MAGIC; |
| 1814 | 1893 | ||
| 1815 | spin_lock_irq(&np->lock); | 1894 | spin_lock_irq(&np->lock); |
| @@ -1820,7 +1899,7 @@ static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |||
| 1820 | 1899 | ||
| 1821 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | 1900 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
| 1822 | { | 1901 | { |
| 1823 | struct fe_priv *np = get_nvpriv(dev); | 1902 | struct fe_priv *np = netdev_priv(dev); |
| 1824 | u8 __iomem *base = get_hwbase(dev); | 1903 | u8 __iomem *base = get_hwbase(dev); |
| 1825 | 1904 | ||
| 1826 | spin_lock_irq(&np->lock); | 1905 | spin_lock_irq(&np->lock); |
| @@ -2021,7 +2100,7 @@ static int nv_get_regs_len(struct net_device *dev) | |||
| 2021 | 2100 | ||
| 2022 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | 2101 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) |
| 2023 | { | 2102 | { |
| 2024 | struct fe_priv *np = get_nvpriv(dev); | 2103 | struct fe_priv *np = netdev_priv(dev); |
| 2025 | u8 __iomem *base = get_hwbase(dev); | 2104 | u8 __iomem *base = get_hwbase(dev); |
| 2026 | u32 *rbuf = buf; | 2105 | u32 *rbuf = buf; |
| 2027 | int i; | 2106 | int i; |
| @@ -2035,7 +2114,7 @@ static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void | |||
| 2035 | 2114 | ||
| 2036 | static int nv_nway_reset(struct net_device *dev) | 2115 | static int nv_nway_reset(struct net_device *dev) |
| 2037 | { | 2116 | { |
| 2038 | struct fe_priv *np = get_nvpriv(dev); | 2117 | struct fe_priv *np = netdev_priv(dev); |
| 2039 | int ret; | 2118 | int ret; |
| 2040 | 2119 | ||
| 2041 | spin_lock_irq(&np->lock); | 2120 | spin_lock_irq(&np->lock); |
| @@ -2065,11 +2144,12 @@ static struct ethtool_ops ops = { | |||
| 2065 | .get_regs_len = nv_get_regs_len, | 2144 | .get_regs_len = nv_get_regs_len, |
| 2066 | .get_regs = nv_get_regs, | 2145 | .get_regs = nv_get_regs, |
| 2067 | .nway_reset = nv_nway_reset, | 2146 | .nway_reset = nv_nway_reset, |
| 2147 | .get_perm_addr = ethtool_op_get_perm_addr, | ||
| 2068 | }; | 2148 | }; |
| 2069 | 2149 | ||
| 2070 | static int nv_open(struct net_device *dev) | 2150 | static int nv_open(struct net_device *dev) |
| 2071 | { | 2151 | { |
| 2072 | struct fe_priv *np = get_nvpriv(dev); | 2152 | struct fe_priv *np = netdev_priv(dev); |
| 2073 | u8 __iomem *base = get_hwbase(dev); | 2153 | u8 __iomem *base = get_hwbase(dev); |
| 2074 | int ret, oom, i; | 2154 | int ret, oom, i; |
| 2075 | 2155 | ||
| @@ -2114,9 +2194,9 @@ static int nv_open(struct net_device *dev) | |||
| 2114 | /* 5) continue setup */ | 2194 | /* 5) continue setup */ |
| 2115 | writel(np->linkspeed, base + NvRegLinkSpeed); | 2195 | writel(np->linkspeed, base + NvRegLinkSpeed); |
| 2116 | writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); | 2196 | writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); |
| 2117 | writel(np->desc_ver, base + NvRegTxRxControl); | 2197 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
| 2118 | pci_push(base); | 2198 | pci_push(base); |
| 2119 | writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl); | 2199 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
| 2120 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, | 2200 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
| 2121 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, | 2201 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, |
| 2122 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); | 2202 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); |
| @@ -2205,7 +2285,7 @@ out_drain: | |||
| 2205 | 2285 | ||
| 2206 | static int nv_close(struct net_device *dev) | 2286 | static int nv_close(struct net_device *dev) |
| 2207 | { | 2287 | { |
| 2208 | struct fe_priv *np = get_nvpriv(dev); | 2288 | struct fe_priv *np = netdev_priv(dev); |
| 2209 | u8 __iomem *base; | 2289 | u8 __iomem *base; |
| 2210 | 2290 | ||
| 2211 | spin_lock_irq(&np->lock); | 2291 | spin_lock_irq(&np->lock); |
| @@ -2261,7 +2341,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
| 2261 | if (!dev) | 2341 | if (!dev) |
| 2262 | goto out; | 2342 | goto out; |
| 2263 | 2343 | ||
| 2264 | np = get_nvpriv(dev); | 2344 | np = netdev_priv(dev); |
| 2265 | np->pci_dev = pci_dev; | 2345 | np->pci_dev = pci_dev; |
| 2266 | spin_lock_init(&np->lock); | 2346 | spin_lock_init(&np->lock); |
| 2267 | SET_MODULE_OWNER(dev); | 2347 | SET_MODULE_OWNER(dev); |
| @@ -2313,19 +2393,32 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
| 2313 | if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) { | 2393 | if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) { |
| 2314 | printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", | 2394 | printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", |
| 2315 | pci_name(pci_dev)); | 2395 | pci_name(pci_dev)); |
| 2396 | } else { | ||
| 2397 | dev->features |= NETIF_F_HIGHDMA; | ||
| 2316 | } | 2398 | } |
| 2399 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; | ||
| 2317 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | 2400 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { |
| 2318 | /* packet format 2: supports jumbo frames */ | 2401 | /* packet format 2: supports jumbo frames */ |
| 2319 | np->desc_ver = DESC_VER_2; | 2402 | np->desc_ver = DESC_VER_2; |
| 2403 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; | ||
| 2320 | } else { | 2404 | } else { |
| 2321 | /* original packet format */ | 2405 | /* original packet format */ |
| 2322 | np->desc_ver = DESC_VER_1; | 2406 | np->desc_ver = DESC_VER_1; |
| 2407 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; | ||
| 2323 | } | 2408 | } |
| 2324 | 2409 | ||
| 2325 | np->pkt_limit = NV_PKTLIMIT_1; | 2410 | np->pkt_limit = NV_PKTLIMIT_1; |
| 2326 | if (id->driver_data & DEV_HAS_LARGEDESC) | 2411 | if (id->driver_data & DEV_HAS_LARGEDESC) |
| 2327 | np->pkt_limit = NV_PKTLIMIT_2; | 2412 | np->pkt_limit = NV_PKTLIMIT_2; |
| 2328 | 2413 | ||
| 2414 | if (id->driver_data & DEV_HAS_CHECKSUM) { | ||
| 2415 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | ||
| 2416 | dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; | ||
| 2417 | #ifdef NETIF_F_TSO | ||
| 2418 | dev->features |= NETIF_F_TSO; | ||
| 2419 | #endif | ||
| 2420 | } | ||
| 2421 | |||
| 2329 | err = -ENOMEM; | 2422 | err = -ENOMEM; |
| 2330 | np->base = ioremap(addr, NV_PCI_REGSZ); | 2423 | np->base = ioremap(addr, NV_PCI_REGSZ); |
| 2331 | if (!np->base) | 2424 | if (!np->base) |
| @@ -2377,8 +2470,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
| 2377 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | 2470 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; |
| 2378 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | 2471 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
| 2379 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | 2472 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
| 2473 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | ||
| 2380 | 2474 | ||
| 2381 | if (!is_valid_ether_addr(dev->dev_addr)) { | 2475 | if (!is_valid_ether_addr(dev->perm_addr)) { |
| 2382 | /* | 2476 | /* |
| 2383 | * Bad mac address. At least one bios sets the mac address | 2477 | * Bad mac address. At least one bios sets the mac address |
| 2384 | * to 01:23:45:67:89:ab | 2478 | * to 01:23:45:67:89:ab |
| @@ -2403,9 +2497,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
| 2403 | np->wolenabled = 0; | 2497 | np->wolenabled = 0; |
| 2404 | 2498 | ||
| 2405 | if (np->desc_ver == DESC_VER_1) { | 2499 | if (np->desc_ver == DESC_VER_1) { |
| 2406 | np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID; | 2500 | np->tx_flags = NV_TX_VALID; |
| 2407 | } else { | 2501 | } else { |
| 2408 | np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID; | 2502 | np->tx_flags = NV_TX2_VALID; |
| 2409 | } | 2503 | } |
| 2410 | np->irqmask = NVREG_IRQMASK_WANTED; | 2504 | np->irqmask = NVREG_IRQMASK_WANTED; |
| 2411 | if (id->driver_data & DEV_NEED_TIMERIRQ) | 2505 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
| @@ -2494,7 +2588,7 @@ out: | |||
| 2494 | static void __devexit nv_remove(struct pci_dev *pci_dev) | 2588 | static void __devexit nv_remove(struct pci_dev *pci_dev) |
| 2495 | { | 2589 | { |
| 2496 | struct net_device *dev = pci_get_drvdata(pci_dev); | 2590 | struct net_device *dev = pci_get_drvdata(pci_dev); |
| 2497 | struct fe_priv *np = get_nvpriv(dev); | 2591 | struct fe_priv *np = netdev_priv(dev); |
| 2498 | 2592 | ||
| 2499 | unregister_netdev(dev); | 2593 | unregister_netdev(dev); |
| 2500 | 2594 | ||
| @@ -2525,35 +2619,35 @@ static struct pci_device_id pci_tbl[] = { | |||
| 2525 | }, | 2619 | }, |
| 2526 | { /* nForce3 Ethernet Controller */ | 2620 | { /* nForce3 Ethernet Controller */ |
| 2527 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), | 2621 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
| 2528 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC, | 2622 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
| 2529 | }, | 2623 | }, |
| 2530 | { /* nForce3 Ethernet Controller */ | 2624 | { /* nForce3 Ethernet Controller */ |
| 2531 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), | 2625 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
| 2532 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC, | 2626 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
| 2533 | }, | 2627 | }, |
| 2534 | { /* nForce3 Ethernet Controller */ | 2628 | { /* nForce3 Ethernet Controller */ |
| 2535 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), | 2629 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
| 2536 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC, | 2630 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
| 2537 | }, | 2631 | }, |
| 2538 | { /* nForce3 Ethernet Controller */ | 2632 | { /* nForce3 Ethernet Controller */ |
| 2539 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), | 2633 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
| 2540 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC, | 2634 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
| 2541 | }, | 2635 | }, |
| 2542 | { /* CK804 Ethernet Controller */ | 2636 | { /* CK804 Ethernet Controller */ |
| 2543 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), | 2637 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
| 2544 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA, | 2638 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
| 2545 | }, | 2639 | }, |
| 2546 | { /* CK804 Ethernet Controller */ | 2640 | { /* CK804 Ethernet Controller */ |
| 2547 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), | 2641 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
| 2548 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA, | 2642 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
| 2549 | }, | 2643 | }, |
| 2550 | { /* MCP04 Ethernet Controller */ | 2644 | { /* MCP04 Ethernet Controller */ |
| 2551 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), | 2645 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
| 2552 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA, | 2646 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
| 2553 | }, | 2647 | }, |
| 2554 | { /* MCP04 Ethernet Controller */ | 2648 | { /* MCP04 Ethernet Controller */ |
| 2555 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), | 2649 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
| 2556 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA, | 2650 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
| 2557 | }, | 2651 | }, |
| 2558 | { /* MCP51 Ethernet Controller */ | 2652 | { /* MCP51 Ethernet Controller */ |
| 2559 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), | 2653 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
| @@ -2565,11 +2659,11 @@ static struct pci_device_id pci_tbl[] = { | |||
| 2565 | }, | 2659 | }, |
| 2566 | { /* MCP55 Ethernet Controller */ | 2660 | { /* MCP55 Ethernet Controller */ |
| 2567 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), | 2661 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
| 2568 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA, | 2662 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
| 2569 | }, | 2663 | }, |
| 2570 | { /* MCP55 Ethernet Controller */ | 2664 | { /* MCP55 Ethernet Controller */ |
| 2571 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), | 2665 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
| 2572 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA, | 2666 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
| 2573 | }, | 2667 | }, |
| 2574 | {0,}, | 2668 | {0,}, |
| 2575 | }; | 2669 | }; |
