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path: root/drivers/net/forcedeth.c
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-rw-r--r--drivers/net/forcedeth.c432
1 files changed, 356 insertions, 76 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 8c4214b0ee1f..35f66d4a4595 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -96,6 +96,7 @@
96#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */ 96#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
97#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */ 97#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
98#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */ 98#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
99#define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */
99 100
100enum { 101enum {
101 NvRegIrqStatus = 0x000, 102 NvRegIrqStatus = 0x000,
@@ -174,11 +175,13 @@ enum {
174 NvRegReceiverStatus = 0x98, 175 NvRegReceiverStatus = 0x98,
175#define NVREG_RCVSTAT_BUSY 0x01 176#define NVREG_RCVSTAT_BUSY 0x01
176 177
177 NvRegRandomSeed = 0x9c, 178 NvRegSlotTime = 0x9c,
178#define NVREG_RNDSEED_MASK 0x00ff 179#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
179#define NVREG_RNDSEED_FORCE 0x7f00 180#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
180#define NVREG_RNDSEED_FORCE2 0x2d00 181#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
181#define NVREG_RNDSEED_FORCE3 0x7400 182#define NVREG_SLOTTIME_HALF 0x0000ff00
183#define NVREG_SLOTTIME_DEFAULT 0x00007f00
184#define NVREG_SLOTTIME_MASK 0x000000ff
182 185
183 NvRegTxDeferral = 0xA0, 186 NvRegTxDeferral = 0xA0,
184#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f 187#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
@@ -201,6 +204,11 @@ enum {
201 204
202 NvRegPhyInterface = 0xC0, 205 NvRegPhyInterface = 0xC0,
203#define PHY_RGMII 0x10000000 206#define PHY_RGMII 0x10000000
207 NvRegBackOffControl = 0xC4,
208#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210#define NVREG_BKOFFCTRL_SELECT 24
211#define NVREG_BKOFFCTRL_GEAR 12
204 212
205 NvRegTxRingPhysAddr = 0x100, 213 NvRegTxRingPhysAddr = 0x100,
206 NvRegRxRingPhysAddr = 0x104, 214 NvRegRxRingPhysAddr = 0x104,
@@ -352,6 +360,7 @@ union ring_type {
352 360
353#define NV_TX_LASTPACKET (1<<16) 361#define NV_TX_LASTPACKET (1<<16)
354#define NV_TX_RETRYERROR (1<<19) 362#define NV_TX_RETRYERROR (1<<19)
363#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
355#define NV_TX_FORCED_INTERRUPT (1<<24) 364#define NV_TX_FORCED_INTERRUPT (1<<24)
356#define NV_TX_DEFERRED (1<<26) 365#define NV_TX_DEFERRED (1<<26)
357#define NV_TX_CARRIERLOST (1<<27) 366#define NV_TX_CARRIERLOST (1<<27)
@@ -362,6 +371,7 @@ union ring_type {
362 371
363#define NV_TX2_LASTPACKET (1<<29) 372#define NV_TX2_LASTPACKET (1<<29)
364#define NV_TX2_RETRYERROR (1<<18) 373#define NV_TX2_RETRYERROR (1<<18)
374#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
365#define NV_TX2_FORCED_INTERRUPT (1<<30) 375#define NV_TX2_FORCED_INTERRUPT (1<<30)
366#define NV_TX2_DEFERRED (1<<25) 376#define NV_TX2_DEFERRED (1<<25)
367#define NV_TX2_CARRIERLOST (1<<26) 377#define NV_TX2_CARRIERLOST (1<<26)
@@ -473,16 +483,22 @@ union ring_type {
473#define DESC_VER_3 3 483#define DESC_VER_3 3
474 484
475/* PHY defines */ 485/* PHY defines */
476#define PHY_OUI_MARVELL 0x5043 486#define PHY_OUI_MARVELL 0x5043
477#define PHY_OUI_CICADA 0x03f1 487#define PHY_OUI_CICADA 0x03f1
478#define PHY_OUI_VITESSE 0x01c1 488#define PHY_OUI_VITESSE 0x01c1
479#define PHY_OUI_REALTEK 0x0732 489#define PHY_OUI_REALTEK 0x0732
490#define PHY_OUI_REALTEK2 0x0020
480#define PHYID1_OUI_MASK 0x03ff 491#define PHYID1_OUI_MASK 0x03ff
481#define PHYID1_OUI_SHFT 6 492#define PHYID1_OUI_SHFT 6
482#define PHYID2_OUI_MASK 0xfc00 493#define PHYID2_OUI_MASK 0xfc00
483#define PHYID2_OUI_SHFT 10 494#define PHYID2_OUI_SHFT 10
484#define PHYID2_MODEL_MASK 0x03f0 495#define PHYID2_MODEL_MASK 0x03f0
485#define PHY_MODEL_MARVELL_E3016 0x220 496#define PHY_MODEL_REALTEK_8211 0x0110
497#define PHY_REV_MASK 0x0001
498#define PHY_REV_REALTEK_8211B 0x0000
499#define PHY_REV_REALTEK_8211C 0x0001
500#define PHY_MODEL_REALTEK_8201 0x0200
501#define PHY_MODEL_MARVELL_E3016 0x0220
486#define PHY_MARVELL_E3016_INITMASK 0x0300 502#define PHY_MARVELL_E3016_INITMASK 0x0300
487#define PHY_CICADA_INIT1 0x0f000 503#define PHY_CICADA_INIT1 0x0f000
488#define PHY_CICADA_INIT2 0x0e00 504#define PHY_CICADA_INIT2 0x0e00
@@ -509,10 +525,18 @@ union ring_type {
509#define PHY_REALTEK_INIT_REG1 0x1f 525#define PHY_REALTEK_INIT_REG1 0x1f
510#define PHY_REALTEK_INIT_REG2 0x19 526#define PHY_REALTEK_INIT_REG2 0x19
511#define PHY_REALTEK_INIT_REG3 0x13 527#define PHY_REALTEK_INIT_REG3 0x13
528#define PHY_REALTEK_INIT_REG4 0x14
529#define PHY_REALTEK_INIT_REG5 0x18
530#define PHY_REALTEK_INIT_REG6 0x11
512#define PHY_REALTEK_INIT1 0x0000 531#define PHY_REALTEK_INIT1 0x0000
513#define PHY_REALTEK_INIT2 0x8e00 532#define PHY_REALTEK_INIT2 0x8e00
514#define PHY_REALTEK_INIT3 0x0001 533#define PHY_REALTEK_INIT3 0x0001
515#define PHY_REALTEK_INIT4 0xad17 534#define PHY_REALTEK_INIT4 0xad17
535#define PHY_REALTEK_INIT5 0xfb54
536#define PHY_REALTEK_INIT6 0xf5c7
537#define PHY_REALTEK_INIT7 0x1000
538#define PHY_REALTEK_INIT8 0x0003
539#define PHY_REALTEK_INIT_MSK1 0x0003
516 540
517#define PHY_GIGABIT 0x0100 541#define PHY_GIGABIT 0x0100
518 542
@@ -691,6 +715,7 @@ struct fe_priv {
691 int wolenabled; 715 int wolenabled;
692 unsigned int phy_oui; 716 unsigned int phy_oui;
693 unsigned int phy_model; 717 unsigned int phy_model;
718 unsigned int phy_rev;
694 u16 gigabit; 719 u16 gigabit;
695 int intr_test; 720 int intr_test;
696 int recover_error; 721 int recover_error;
@@ -704,6 +729,7 @@ struct fe_priv {
704 u32 txrxctl_bits; 729 u32 txrxctl_bits;
705 u32 vlanctl_bits; 730 u32 vlanctl_bits;
706 u32 driver_data; 731 u32 driver_data;
732 u32 device_id;
707 u32 register_size; 733 u32 register_size;
708 int rx_csum; 734 int rx_csum;
709 u32 mac_in_use; 735 u32 mac_in_use;
@@ -814,6 +840,16 @@ enum {
814}; 840};
815static int dma_64bit = NV_DMA_64BIT_ENABLED; 841static int dma_64bit = NV_DMA_64BIT_ENABLED;
816 842
843/*
844 * Crossover Detection
845 * Realtek 8201 phy + some OEM boards do not work properly.
846 */
847enum {
848 NV_CROSSOVER_DETECTION_DISABLED,
849 NV_CROSSOVER_DETECTION_ENABLED
850};
851static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
852
817static inline struct fe_priv *get_nvpriv(struct net_device *dev) 853static inline struct fe_priv *get_nvpriv(struct net_device *dev)
818{ 854{
819 return netdev_priv(dev); 855 return netdev_priv(dev);
@@ -1078,25 +1114,53 @@ static int phy_init(struct net_device *dev)
1078 } 1114 }
1079 } 1115 }
1080 if (np->phy_oui == PHY_OUI_REALTEK) { 1116 if (np->phy_oui == PHY_OUI_REALTEK) {
1081 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1117 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1082 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1118 np->phy_rev == PHY_REV_REALTEK_8211B) {
1083 return PHY_ERROR; 1119 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1084 } 1120 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1085 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { 1121 return PHY_ERROR;
1086 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1122 }
1087 return PHY_ERROR; 1123 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1088 } 1124 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1089 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { 1125 return PHY_ERROR;
1090 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1126 }
1091 return PHY_ERROR; 1127 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1092 } 1128 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1093 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { 1129 return PHY_ERROR;
1094 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1130 }
1095 return PHY_ERROR; 1131 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1132 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1133 return PHY_ERROR;
1134 }
1135 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1136 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1137 return PHY_ERROR;
1138 }
1139 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1140 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1141 return PHY_ERROR;
1142 }
1143 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1144 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145 return PHY_ERROR;
1146 }
1096 } 1147 }
1097 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1148 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1098 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1149 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1099 return PHY_ERROR; 1150 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1151 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1152 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1153 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1154 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1155 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1156 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1157 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1158 phy_reserved |= PHY_REALTEK_INIT7;
1159 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1160 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1161 return PHY_ERROR;
1162 }
1163 }
1100 } 1164 }
1101 } 1165 }
1102 1166
@@ -1236,26 +1300,71 @@ static int phy_init(struct net_device *dev)
1236 } 1300 }
1237 } 1301 }
1238 if (np->phy_oui == PHY_OUI_REALTEK) { 1302 if (np->phy_oui == PHY_OUI_REALTEK) {
1239 /* reset could have cleared these out, set them back */ 1303 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1240 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1304 np->phy_rev == PHY_REV_REALTEK_8211B) {
1241 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1305 /* reset could have cleared these out, set them back */
1242 return PHY_ERROR; 1306 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1243 } 1307 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { 1308 return PHY_ERROR;
1245 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1309 }
1246 return PHY_ERROR; 1310 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1247 } 1311 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1248 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { 1312 return PHY_ERROR;
1249 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1313 }
1250 return PHY_ERROR; 1314 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1251 } 1315 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { 1316 return PHY_ERROR;
1253 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1317 }
1254 return PHY_ERROR; 1318 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1319 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1320 return PHY_ERROR;
1321 }
1322 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1323 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324 return PHY_ERROR;
1325 }
1326 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1327 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328 return PHY_ERROR;
1329 }
1330 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1331 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332 return PHY_ERROR;
1333 }
1255 } 1334 }
1256 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1335 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1257 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1336 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1258 return PHY_ERROR; 1337 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1338 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1339 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1340 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1341 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1342 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1343 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1344 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1345 phy_reserved |= PHY_REALTEK_INIT7;
1346 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1347 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1348 return PHY_ERROR;
1349 }
1350 }
1351 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1352 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1353 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1354 return PHY_ERROR;
1355 }
1356 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1357 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1358 phy_reserved |= PHY_REALTEK_INIT3;
1359 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1360 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1361 return PHY_ERROR;
1362 }
1363 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1364 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1365 return PHY_ERROR;
1366 }
1367 }
1259 } 1368 }
1260 } 1369 }
1261 1370
@@ -1769,6 +1878,115 @@ static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1769 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); 1878 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1770} 1879}
1771 1880
1881static void nv_legacybackoff_reseed(struct net_device *dev)
1882{
1883 u8 __iomem *base = get_hwbase(dev);
1884 u32 reg;
1885 u32 low;
1886 int tx_status = 0;
1887
1888 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1889 get_random_bytes(&low, sizeof(low));
1890 reg |= low & NVREG_SLOTTIME_MASK;
1891
1892 /* Need to stop tx before change takes effect.
1893 * Caller has already gained np->lock.
1894 */
1895 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1896 if (tx_status)
1897 nv_stop_tx(dev);
1898 nv_stop_rx(dev);
1899 writel(reg, base + NvRegSlotTime);
1900 if (tx_status)
1901 nv_start_tx(dev);
1902 nv_start_rx(dev);
1903}
1904
1905/* Gear Backoff Seeds */
1906#define BACKOFF_SEEDSET_ROWS 8
1907#define BACKOFF_SEEDSET_LFSRS 15
1908
1909/* Known Good seed sets */
1910static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1911 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1912 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1913 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1914 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1915 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1916 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1917 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
1918 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1919
1920static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1921 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1922 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1923 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1924 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1925 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1926 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1927 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1928 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1929
1930static void nv_gear_backoff_reseed(struct net_device *dev)
1931{
1932 u8 __iomem *base = get_hwbase(dev);
1933 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
1934 u32 temp, seedset, combinedSeed;
1935 int i;
1936
1937 /* Setup seed for free running LFSR */
1938 /* We are going to read the time stamp counter 3 times
1939 and swizzle bits around to increase randomness */
1940 get_random_bytes(&miniseed1, sizeof(miniseed1));
1941 miniseed1 &= 0x0fff;
1942 if (miniseed1 == 0)
1943 miniseed1 = 0xabc;
1944
1945 get_random_bytes(&miniseed2, sizeof(miniseed2));
1946 miniseed2 &= 0x0fff;
1947 if (miniseed2 == 0)
1948 miniseed2 = 0xabc;
1949 miniseed2_reversed =
1950 ((miniseed2 & 0xF00) >> 8) |
1951 (miniseed2 & 0x0F0) |
1952 ((miniseed2 & 0x00F) << 8);
1953
1954 get_random_bytes(&miniseed3, sizeof(miniseed3));
1955 miniseed3 &= 0x0fff;
1956 if (miniseed3 == 0)
1957 miniseed3 = 0xabc;
1958 miniseed3_reversed =
1959 ((miniseed3 & 0xF00) >> 8) |
1960 (miniseed3 & 0x0F0) |
1961 ((miniseed3 & 0x00F) << 8);
1962
1963 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
1964 (miniseed2 ^ miniseed3_reversed);
1965
1966 /* Seeds can not be zero */
1967 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
1968 combinedSeed |= 0x08;
1969 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
1970 combinedSeed |= 0x8000;
1971
1972 /* No need to disable tx here */
1973 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
1974 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
1975 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
1976 writel(temp,base + NvRegBackOffControl);
1977
1978 /* Setup seeds for all gear LFSRs. */
1979 get_random_bytes(&seedset, sizeof(seedset));
1980 seedset = seedset % BACKOFF_SEEDSET_ROWS;
1981 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
1982 {
1983 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
1984 temp |= main_seedset[seedset][i-1] & 0x3ff;
1985 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
1986 writel(temp, base + NvRegBackOffControl);
1987 }
1988}
1989
1772/* 1990/*
1773 * nv_start_xmit: dev->hard_start_xmit function 1991 * nv_start_xmit: dev->hard_start_xmit function
1774 * Called with netif_tx_lock held. 1992 * Called with netif_tx_lock held.
@@ -2088,6 +2306,8 @@ static void nv_tx_done(struct net_device *dev)
2088 dev->stats.tx_fifo_errors++; 2306 dev->stats.tx_fifo_errors++;
2089 if (flags & NV_TX_CARRIERLOST) 2307 if (flags & NV_TX_CARRIERLOST)
2090 dev->stats.tx_carrier_errors++; 2308 dev->stats.tx_carrier_errors++;
2309 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2310 nv_legacybackoff_reseed(dev);
2091 dev->stats.tx_errors++; 2311 dev->stats.tx_errors++;
2092 } else { 2312 } else {
2093 dev->stats.tx_packets++; 2313 dev->stats.tx_packets++;
@@ -2103,6 +2323,8 @@ static void nv_tx_done(struct net_device *dev)
2103 dev->stats.tx_fifo_errors++; 2323 dev->stats.tx_fifo_errors++;
2104 if (flags & NV_TX2_CARRIERLOST) 2324 if (flags & NV_TX2_CARRIERLOST)
2105 dev->stats.tx_carrier_errors++; 2325 dev->stats.tx_carrier_errors++;
2326 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2327 nv_legacybackoff_reseed(dev);
2106 dev->stats.tx_errors++; 2328 dev->stats.tx_errors++;
2107 } else { 2329 } else {
2108 dev->stats.tx_packets++; 2330 dev->stats.tx_packets++;
@@ -2144,6 +2366,15 @@ static void nv_tx_done_optimized(struct net_device *dev, int limit)
2144 if (flags & NV_TX2_LASTPACKET) { 2366 if (flags & NV_TX2_LASTPACKET) {
2145 if (!(flags & NV_TX2_ERROR)) 2367 if (!(flags & NV_TX2_ERROR))
2146 dev->stats.tx_packets++; 2368 dev->stats.tx_packets++;
2369 else {
2370 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2371 if (np->driver_data & DEV_HAS_GEAR_MODE)
2372 nv_gear_backoff_reseed(dev);
2373 else
2374 nv_legacybackoff_reseed(dev);
2375 }
2376 }
2377
2147 dev_kfree_skb_any(np->get_tx_ctx->skb); 2378 dev_kfree_skb_any(np->get_tx_ctx->skb);
2148 np->get_tx_ctx->skb = NULL; 2379 np->get_tx_ctx->skb = NULL;
2149 2380
@@ -2905,15 +3136,14 @@ set_speed:
2905 } 3136 }
2906 3137
2907 if (np->gigabit == PHY_GIGABIT) { 3138 if (np->gigabit == PHY_GIGABIT) {
2908 phyreg = readl(base + NvRegRandomSeed); 3139 phyreg = readl(base + NvRegSlotTime);
2909 phyreg &= ~(0x3FF00); 3140 phyreg &= ~(0x3FF00);
2910 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) 3141 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
2911 phyreg |= NVREG_RNDSEED_FORCE3; 3142 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
2912 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) 3143 phyreg |= NVREG_SLOTTIME_10_100_FULL;
2913 phyreg |= NVREG_RNDSEED_FORCE2;
2914 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) 3144 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2915 phyreg |= NVREG_RNDSEED_FORCE; 3145 phyreg |= NVREG_SLOTTIME_1000_FULL;
2916 writel(phyreg, base + NvRegRandomSeed); 3146 writel(phyreg, base + NvRegSlotTime);
2917 } 3147 }
2918 3148
2919 phyreg = readl(base + NvRegPhyInterface); 3149 phyreg = readl(base + NvRegPhyInterface);
@@ -4843,6 +5073,7 @@ static int nv_open(struct net_device *dev)
4843 u8 __iomem *base = get_hwbase(dev); 5073 u8 __iomem *base = get_hwbase(dev);
4844 int ret = 1; 5074 int ret = 1;
4845 int oom, i; 5075 int oom, i;
5076 u32 low;
4846 5077
4847 dprintk(KERN_DEBUG "nv_open: begin\n"); 5078 dprintk(KERN_DEBUG "nv_open: begin\n");
4848 5079
@@ -4902,8 +5133,20 @@ static int nv_open(struct net_device *dev)
4902 writel(np->rx_buf_sz, base + NvRegOffloadConfig); 5133 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4903 5134
4904 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); 5135 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4905 get_random_bytes(&i, sizeof(i)); 5136
4906 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); 5137 get_random_bytes(&low, sizeof(low));
5138 low &= NVREG_SLOTTIME_MASK;
5139 if (np->desc_ver == DESC_VER_1) {
5140 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5141 } else {
5142 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5143 /* setup legacy backoff */
5144 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5145 } else {
5146 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5147 nv_gear_backoff_reseed(dev);
5148 }
5149 }
4907 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); 5150 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4908 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); 5151 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4909 if (poll_interval == -1) { 5152 if (poll_interval == -1) {
@@ -5110,6 +5353,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5110 5353
5111 /* copy of driver data */ 5354 /* copy of driver data */
5112 np->driver_data = id->driver_data; 5355 np->driver_data = id->driver_data;
5356 /* copy of device id */
5357 np->device_id = id->device;
5113 5358
5114 /* handle different descriptor versions */ 5359 /* handle different descriptor versions */
5115 if (id->driver_data & DEV_HAS_HIGH_DMA) { 5360 if (id->driver_data & DEV_HAS_HIGH_DMA) {
@@ -5399,6 +5644,14 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5399 pci_name(pci_dev), id1, id2, phyaddr); 5644 pci_name(pci_dev), id1, id2, phyaddr);
5400 np->phyaddr = phyaddr; 5645 np->phyaddr = phyaddr;
5401 np->phy_oui = id1 | id2; 5646 np->phy_oui = id1 | id2;
5647
5648 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5649 if (np->phy_oui == PHY_OUI_REALTEK2)
5650 np->phy_oui = PHY_OUI_REALTEK;
5651 /* Setup phy revision for Realtek */
5652 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5653 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5654
5402 break; 5655 break;
5403 } 5656 }
5404 if (i == 33) { 5657 if (i == 33) {
@@ -5477,6 +5730,28 @@ out:
5477 return err; 5730 return err;
5478} 5731}
5479 5732
5733static void nv_restore_phy(struct net_device *dev)
5734{
5735 struct fe_priv *np = netdev_priv(dev);
5736 u16 phy_reserved, mii_control;
5737
5738 if (np->phy_oui == PHY_OUI_REALTEK &&
5739 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5740 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5741 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5742 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5743 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5744 phy_reserved |= PHY_REALTEK_INIT8;
5745 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5746 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5747
5748 /* restart auto negotiation */
5749 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5750 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5751 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5752 }
5753}
5754
5480static void __devexit nv_remove(struct pci_dev *pci_dev) 5755static void __devexit nv_remove(struct pci_dev *pci_dev)
5481{ 5756{
5482 struct net_device *dev = pci_get_drvdata(pci_dev); 5757 struct net_device *dev = pci_get_drvdata(pci_dev);
@@ -5493,6 +5768,9 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
5493 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV, 5768 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5494 base + NvRegTransmitPoll); 5769 base + NvRegTransmitPoll);
5495 5770
5771 /* restore any phy related changes */
5772 nv_restore_phy(dev);
5773
5496 /* free all structures */ 5774 /* free all structures */
5497 free_rings(dev); 5775 free_rings(dev);
5498 iounmap(get_hwbase(dev)); 5776 iounmap(get_hwbase(dev));
@@ -5632,83 +5910,83 @@ static struct pci_device_id pci_tbl[] = {
5632 }, 5910 },
5633 { /* MCP65 Ethernet Controller */ 5911 { /* MCP65 Ethernet Controller */
5634 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), 5912 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5635 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT, 5913 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5636 }, 5914 },
5637 { /* MCP65 Ethernet Controller */ 5915 { /* MCP65 Ethernet Controller */
5638 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), 5916 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5639 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT, 5917 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5640 }, 5918 },
5641 { /* MCP65 Ethernet Controller */ 5919 { /* MCP65 Ethernet Controller */
5642 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), 5920 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5643 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT, 5921 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5644 }, 5922 },
5645 { /* MCP65 Ethernet Controller */ 5923 { /* MCP65 Ethernet Controller */
5646 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), 5924 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5647 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT, 5925 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5648 }, 5926 },
5649 { /* MCP67 Ethernet Controller */ 5927 { /* MCP67 Ethernet Controller */
5650 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24), 5928 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5651 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5929 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5652 }, 5930 },
5653 { /* MCP67 Ethernet Controller */ 5931 { /* MCP67 Ethernet Controller */
5654 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25), 5932 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5655 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5933 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5656 }, 5934 },
5657 { /* MCP67 Ethernet Controller */ 5935 { /* MCP67 Ethernet Controller */
5658 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26), 5936 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5659 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5937 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5660 }, 5938 },
5661 { /* MCP67 Ethernet Controller */ 5939 { /* MCP67 Ethernet Controller */
5662 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27), 5940 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5663 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5941 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5664 }, 5942 },
5665 { /* MCP73 Ethernet Controller */ 5943 { /* MCP73 Ethernet Controller */
5666 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28), 5944 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
5667 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5945 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5668 }, 5946 },
5669 { /* MCP73 Ethernet Controller */ 5947 { /* MCP73 Ethernet Controller */
5670 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29), 5948 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
5671 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5949 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5672 }, 5950 },
5673 { /* MCP73 Ethernet Controller */ 5951 { /* MCP73 Ethernet Controller */
5674 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30), 5952 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
5675 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5953 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5676 }, 5954 },
5677 { /* MCP73 Ethernet Controller */ 5955 { /* MCP73 Ethernet Controller */
5678 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31), 5956 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
5679 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5957 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5680 }, 5958 },
5681 { /* MCP77 Ethernet Controller */ 5959 { /* MCP77 Ethernet Controller */
5682 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), 5960 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
5683 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5961 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5684 }, 5962 },
5685 { /* MCP77 Ethernet Controller */ 5963 { /* MCP77 Ethernet Controller */
5686 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), 5964 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
5687 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5965 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5688 }, 5966 },
5689 { /* MCP77 Ethernet Controller */ 5967 { /* MCP77 Ethernet Controller */
5690 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), 5968 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
5691 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5969 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5692 }, 5970 },
5693 { /* MCP77 Ethernet Controller */ 5971 { /* MCP77 Ethernet Controller */
5694 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), 5972 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
5695 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5973 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5696 }, 5974 },
5697 { /* MCP79 Ethernet Controller */ 5975 { /* MCP79 Ethernet Controller */
5698 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), 5976 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
5699 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5977 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5700 }, 5978 },
5701 { /* MCP79 Ethernet Controller */ 5979 { /* MCP79 Ethernet Controller */
5702 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), 5980 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
5703 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5981 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5704 }, 5982 },
5705 { /* MCP79 Ethernet Controller */ 5983 { /* MCP79 Ethernet Controller */
5706 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), 5984 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
5707 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5985 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5708 }, 5986 },
5709 { /* MCP79 Ethernet Controller */ 5987 { /* MCP79 Ethernet Controller */
5710 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), 5988 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
5711 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5989 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5712 }, 5990 },
5713 {0,}, 5991 {0,},
5714}; 5992};
@@ -5744,6 +6022,8 @@ module_param(msix, int, 0);
5744MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); 6022MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5745module_param(dma_64bit, int, 0); 6023module_param(dma_64bit, int, 0);
5746MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); 6024MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6025module_param(phy_cross, int, 0);
6026MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
5747 6027
5748MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); 6028MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5749MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); 6029MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-29 13:00:34 -0500