aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/forcedeth.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r--drivers/net/forcedeth.c240
1 files changed, 125 insertions, 115 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 9f6a68fb7b45..b60a3041b64c 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -77,27 +77,31 @@
77 * Hardware access: 77 * Hardware access:
78 */ 78 */
79 79
80#define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */ 80#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
81#define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */ 81#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
82#define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */ 82#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
83#define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */ 83#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
84#define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */ 84#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
85#define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */ 85#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
86#define DEV_HAS_MSI 0x000040 /* device supports MSI */ 86#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
87#define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */ 87#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
88#define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */ 88#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
89#define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */ 89#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
90#define DEV_HAS_STATISTICS_V2 0x000600 /* device supports hw statistics version 2 */ 90#define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */
91#define DEV_HAS_STATISTICS_V3 0x000e00 /* device supports hw statistics version 3 */ 91#define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */
92#define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */ 92#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
93#define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */ 93#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
94#define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */ 94#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
95#define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */ 95#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
96#define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */ 96#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
97#define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */ 97#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
98#define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */ 98#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
99#define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */ 99#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
100#define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */ 100#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
101#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
102#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
103#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
104#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
101 105
102enum { 106enum {
103 NvRegIrqStatus = 0x000, 107 NvRegIrqStatus = 0x000,
@@ -343,6 +347,7 @@ enum {
343#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 347#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
344#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 348#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
345#define NVREG_POWERSTATE2_PHY_RESET 0x0004 349#define NVREG_POWERSTATE2_PHY_RESET 0x0004
350#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
346}; 351};
347 352
348/* Big endian: should work, but is untested */ 353/* Big endian: should work, but is untested */
@@ -1023,6 +1028,23 @@ static int using_multi_irqs(struct net_device *dev)
1023 return 1; 1028 return 1;
1024} 1029}
1025 1030
1031static void nv_txrx_gate(struct net_device *dev, bool gate)
1032{
1033 struct fe_priv *np = get_nvpriv(dev);
1034 u8 __iomem *base = get_hwbase(dev);
1035 u32 powerstate;
1036
1037 if (!np->mac_in_use &&
1038 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1039 powerstate = readl(base + NvRegPowerState2);
1040 if (gate)
1041 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1042 else
1043 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1044 writel(powerstate, base + NvRegPowerState2);
1045 }
1046}
1047
1026static void nv_enable_irq(struct net_device *dev) 1048static void nv_enable_irq(struct net_device *dev)
1027{ 1049{
1028 struct fe_priv *np = get_nvpriv(dev); 1050 struct fe_priv *np = get_nvpriv(dev);
@@ -1253,14 +1275,7 @@ static int phy_init(struct net_device *dev)
1253 } 1275 }
1254 } 1276 }
1255 if (np->phy_model == PHY_MODEL_REALTEK_8201) { 1277 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1256 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 || 1278 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1257 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1258 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1259 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1260 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1261 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1262 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1263 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1264 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1279 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1265 phy_reserved |= PHY_REALTEK_INIT7; 1280 phy_reserved |= PHY_REALTEK_INIT7;
1266 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { 1281 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
@@ -1451,14 +1466,7 @@ static int phy_init(struct net_device *dev)
1451 } 1466 }
1452 } 1467 }
1453 if (np->phy_model == PHY_MODEL_REALTEK_8201) { 1468 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1454 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 || 1469 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1455 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1456 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1457 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1458 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1459 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1460 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1461 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1462 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1470 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1463 phy_reserved |= PHY_REALTEK_INIT7; 1471 phy_reserved |= PHY_REALTEK_INIT7;
1464 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { 1472 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
@@ -3403,12 +3411,14 @@ static void nv_linkchange(struct net_device *dev)
3403 if (!netif_carrier_ok(dev)) { 3411 if (!netif_carrier_ok(dev)) {
3404 netif_carrier_on(dev); 3412 netif_carrier_on(dev);
3405 printk(KERN_INFO "%s: link up.\n", dev->name); 3413 printk(KERN_INFO "%s: link up.\n", dev->name);
3414 nv_txrx_gate(dev, false);
3406 nv_start_rx(dev); 3415 nv_start_rx(dev);
3407 } 3416 }
3408 } else { 3417 } else {
3409 if (netif_carrier_ok(dev)) { 3418 if (netif_carrier_ok(dev)) {
3410 netif_carrier_off(dev); 3419 netif_carrier_off(dev);
3411 printk(KERN_INFO "%s: link down.\n", dev->name); 3420 printk(KERN_INFO "%s: link down.\n", dev->name);
3421 nv_txrx_gate(dev, true);
3412 nv_stop_rx(dev); 3422 nv_stop_rx(dev);
3413 } 3423 }
3414 } 3424 }
@@ -5336,6 +5346,7 @@ static int nv_open(struct net_device *dev)
5336 mii_rw(dev, np->phyaddr, MII_BMCR, 5346 mii_rw(dev, np->phyaddr, MII_BMCR,
5337 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); 5347 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5338 5348
5349 nv_txrx_gate(dev, false);
5339 /* erase previous misconfiguration */ 5350 /* erase previous misconfiguration */
5340 if (np->driver_data & DEV_HAS_POWER_CNTRL) 5351 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5341 nv_mac_reset(dev); 5352 nv_mac_reset(dev);
@@ -5523,12 +5534,14 @@ static int nv_close(struct net_device *dev)
5523 nv_drain_rxtx(dev); 5534 nv_drain_rxtx(dev);
5524 5535
5525 if (np->wolenabled || !phy_power_down) { 5536 if (np->wolenabled || !phy_power_down) {
5537 nv_txrx_gate(dev, false);
5526 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); 5538 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5527 nv_start_rx(dev); 5539 nv_start_rx(dev);
5528 } else { 5540 } else {
5529 /* power down phy */ 5541 /* power down phy */
5530 mii_rw(dev, np->phyaddr, MII_BMCR, 5542 mii_rw(dev, np->phyaddr, MII_BMCR,
5531 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); 5543 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5544 nv_txrx_gate(dev, true);
5532 } 5545 }
5533 5546
5534 /* FIXME: power down nic */ 5547 /* FIXME: power down nic */
@@ -5821,8 +5834,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5821 /* take phy and nic out of low power mode */ 5834 /* take phy and nic out of low power mode */
5822 powerstate = readl(base + NvRegPowerState2); 5835 powerstate = readl(base + NvRegPowerState2);
5823 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; 5836 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5824 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || 5837 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5825 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5826 pci_dev->revision >= 0xA3) 5838 pci_dev->revision >= 0xA3)
5827 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; 5839 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5828 writel(powerstate, base + NvRegPowerState2); 5840 writel(powerstate, base + NvRegPowerState2);
@@ -5878,14 +5890,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5878 /* Limit the number of tx's outstanding for hw bug */ 5890 /* Limit the number of tx's outstanding for hw bug */
5879 if (id->driver_data & DEV_NEED_TX_LIMIT) { 5891 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5880 np->tx_limit = 1; 5892 np->tx_limit = 1;
5881 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 || 5893 if ((id->driver_data & DEV_NEED_TX_LIMIT2) &&
5882 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5883 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5884 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5885 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5886 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5887 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5888 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5889 pci_dev->revision >= 0xA2) 5894 pci_dev->revision >= 0xA2)
5890 np->tx_limit = 0; 5895 np->tx_limit = 0;
5891 } 5896 }
@@ -6135,7 +6140,8 @@ static int nv_resume(struct pci_dev *pdev)
6135 for (i = 0;i <= np->register_size/sizeof(u32); i++) 6140 for (i = 0;i <= np->register_size/sizeof(u32); i++)
6136 writel(np->saved_config_space[i], base+i*sizeof(u32)); 6141 writel(np->saved_config_space[i], base+i*sizeof(u32));
6137 6142
6138 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE); 6143 if (np->driver_data & DEV_NEED_MSI_FIX)
6144 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6139 6145
6140 /* restore phy state, including autoneg */ 6146 /* restore phy state, including autoneg */
6141 phy_init(dev); 6147 phy_init(dev);
@@ -6184,160 +6190,164 @@ static void nv_shutdown(struct pci_dev *pdev)
6184 6190
6185static struct pci_device_id pci_tbl[] = { 6191static struct pci_device_id pci_tbl[] = {
6186 { /* nForce Ethernet Controller */ 6192 { /* nForce Ethernet Controller */
6187 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), 6193 PCI_DEVICE(0x10DE, 0x01C3),
6188 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 6194 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6189 }, 6195 },
6190 { /* nForce2 Ethernet Controller */ 6196 { /* nForce2 Ethernet Controller */
6191 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), 6197 PCI_DEVICE(0x10DE, 0x0066),
6192 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 6198 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6193 }, 6199 },
6194 { /* nForce3 Ethernet Controller */ 6200 { /* nForce3 Ethernet Controller */
6195 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), 6201 PCI_DEVICE(0x10DE, 0x00D6),
6196 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, 6202 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6197 }, 6203 },
6198 { /* nForce3 Ethernet Controller */ 6204 { /* nForce3 Ethernet Controller */
6199 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), 6205 PCI_DEVICE(0x10DE, 0x0086),
6200 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6206 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6201 }, 6207 },
6202 { /* nForce3 Ethernet Controller */ 6208 { /* nForce3 Ethernet Controller */
6203 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), 6209 PCI_DEVICE(0x10DE, 0x008C),
6204 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6210 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6205 }, 6211 },
6206 { /* nForce3 Ethernet Controller */ 6212 { /* nForce3 Ethernet Controller */
6207 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), 6213 PCI_DEVICE(0x10DE, 0x00E6),
6208 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6214 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6209 }, 6215 },
6210 { /* nForce3 Ethernet Controller */ 6216 { /* nForce3 Ethernet Controller */
6211 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), 6217 PCI_DEVICE(0x10DE, 0x00DF),
6212 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, 6218 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6213 }, 6219 },
6214 { /* CK804 Ethernet Controller */ 6220 { /* CK804 Ethernet Controller */
6215 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), 6221 PCI_DEVICE(0x10DE, 0x0056),
6216 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6222 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6217 }, 6223 },
6218 { /* CK804 Ethernet Controller */ 6224 { /* CK804 Ethernet Controller */
6219 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), 6225 PCI_DEVICE(0x10DE, 0x0057),
6220 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6226 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6221 }, 6227 },
6222 { /* MCP04 Ethernet Controller */ 6228 { /* MCP04 Ethernet Controller */
6223 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), 6229 PCI_DEVICE(0x10DE, 0x0037),
6224 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6230 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6225 }, 6231 },
6226 { /* MCP04 Ethernet Controller */ 6232 { /* MCP04 Ethernet Controller */
6227 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), 6233 PCI_DEVICE(0x10DE, 0x0038),
6228 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, 6234 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6229 }, 6235 },
6230 { /* MCP51 Ethernet Controller */ 6236 { /* MCP51 Ethernet Controller */
6231 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), 6237 PCI_DEVICE(0x10DE, 0x0268),
6232 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, 6238 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6233 }, 6239 },
6234 { /* MCP51 Ethernet Controller */ 6240 { /* MCP51 Ethernet Controller */
6235 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), 6241 PCI_DEVICE(0x10DE, 0x0269),
6236 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, 6242 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6237 }, 6243 },
6238 { /* MCP55 Ethernet Controller */ 6244 { /* MCP55 Ethernet Controller */
6239 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), 6245 PCI_DEVICE(0x10DE, 0x0372),
6240 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, 6246 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6241 }, 6247 },
6242 { /* MCP55 Ethernet Controller */ 6248 { /* MCP55 Ethernet Controller */
6243 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), 6249 PCI_DEVICE(0x10DE, 0x0373),
6244 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, 6250 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6245 }, 6251 },
6246 { /* MCP61 Ethernet Controller */ 6252 { /* MCP61 Ethernet Controller */
6247 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), 6253 PCI_DEVICE(0x10DE, 0x03E5),
6248 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6254 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6249 }, 6255 },
6250 { /* MCP61 Ethernet Controller */ 6256 { /* MCP61 Ethernet Controller */
6251 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), 6257 PCI_DEVICE(0x10DE, 0x03E6),
6252 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6258 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6253 }, 6259 },
6254 { /* MCP61 Ethernet Controller */ 6260 { /* MCP61 Ethernet Controller */
6255 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), 6261 PCI_DEVICE(0x10DE, 0x03EE),
6256 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6262 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6257 }, 6263 },
6258 { /* MCP61 Ethernet Controller */ 6264 { /* MCP61 Ethernet Controller */
6259 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), 6265 PCI_DEVICE(0x10DE, 0x03EF),
6260 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 6266 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6261 }, 6267 },
6262 { /* MCP65 Ethernet Controller */ 6268 { /* MCP65 Ethernet Controller */
6263 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), 6269 PCI_DEVICE(0x10DE, 0x0450),
6264 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6270 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6265 }, 6271 },
6266 { /* MCP65 Ethernet Controller */ 6272 { /* MCP65 Ethernet Controller */
6267 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), 6273 PCI_DEVICE(0x10DE, 0x0451),
6268 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6274 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6269 }, 6275 },
6270 { /* MCP65 Ethernet Controller */ 6276 { /* MCP65 Ethernet Controller */
6271 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), 6277 PCI_DEVICE(0x10DE, 0x0452),
6272 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6278 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6273 }, 6279 },
6274 { /* MCP65 Ethernet Controller */ 6280 { /* MCP65 Ethernet Controller */
6275 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), 6281 PCI_DEVICE(0x10DE, 0x0453),
6276 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6282 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6277 }, 6283 },
6278 { /* MCP67 Ethernet Controller */ 6284 { /* MCP67 Ethernet Controller */
6279 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24), 6285 PCI_DEVICE(0x10DE, 0x054C),
6280 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6286 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6281 }, 6287 },
6282 { /* MCP67 Ethernet Controller */ 6288 { /* MCP67 Ethernet Controller */
6283 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25), 6289 PCI_DEVICE(0x10DE, 0x054D),
6284 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6290 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6285 }, 6291 },
6286 { /* MCP67 Ethernet Controller */ 6292 { /* MCP67 Ethernet Controller */
6287 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26), 6293 PCI_DEVICE(0x10DE, 0x054E),
6288 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6294 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6289 }, 6295 },
6290 { /* MCP67 Ethernet Controller */ 6296 { /* MCP67 Ethernet Controller */
6291 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27), 6297 PCI_DEVICE(0x10DE, 0x054F),
6292 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, 6298 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6293 }, 6299 },
6294 { /* MCP73 Ethernet Controller */ 6300 { /* MCP73 Ethernet Controller */
6295 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28), 6301 PCI_DEVICE(0x10DE, 0x07DC),
6296 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6302 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6297 }, 6303 },
6298 { /* MCP73 Ethernet Controller */ 6304 { /* MCP73 Ethernet Controller */
6299 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29), 6305 PCI_DEVICE(0x10DE, 0x07DD),
6300 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6306 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6301 }, 6307 },
6302 { /* MCP73 Ethernet Controller */ 6308 { /* MCP73 Ethernet Controller */
6303 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30), 6309 PCI_DEVICE(0x10DE, 0x07DE),
6304 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6310 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6305 }, 6311 },
6306 { /* MCP73 Ethernet Controller */ 6312 { /* MCP73 Ethernet Controller */
6307 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31), 6313 PCI_DEVICE(0x10DE, 0x07DF),
6308 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, 6314 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6309 }, 6315 },
6310 { /* MCP77 Ethernet Controller */ 6316 { /* MCP77 Ethernet Controller */
6311 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), 6317 PCI_DEVICE(0x10DE, 0x0760),
6312 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6318 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6313 }, 6319 },
6314 { /* MCP77 Ethernet Controller */ 6320 { /* MCP77 Ethernet Controller */
6315 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), 6321 PCI_DEVICE(0x10DE, 0x0761),
6316 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6322 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6317 }, 6323 },
6318 { /* MCP77 Ethernet Controller */ 6324 { /* MCP77 Ethernet Controller */
6319 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), 6325 PCI_DEVICE(0x10DE, 0x0762),
6320 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6326 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6321 }, 6327 },
6322 { /* MCP77 Ethernet Controller */ 6328 { /* MCP77 Ethernet Controller */
6323 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), 6329 PCI_DEVICE(0x10DE, 0x0763),
6324 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6330 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6325 }, 6331 },
6326 { /* MCP79 Ethernet Controller */ 6332 { /* MCP79 Ethernet Controller */
6327 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), 6333 PCI_DEVICE(0x10DE, 0x0AB0),
6328 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6334 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6329 }, 6335 },
6330 { /* MCP79 Ethernet Controller */ 6336 { /* MCP79 Ethernet Controller */
6331 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), 6337 PCI_DEVICE(0x10DE, 0x0AB1),
6332 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6338 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6333 }, 6339 },
6334 { /* MCP79 Ethernet Controller */ 6340 { /* MCP79 Ethernet Controller */
6335 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), 6341 PCI_DEVICE(0x10DE, 0x0AB2),
6336 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6342 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6337 }, 6343 },
6338 { /* MCP79 Ethernet Controller */ 6344 { /* MCP79 Ethernet Controller */
6339 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), 6345 PCI_DEVICE(0x10DE, 0x0AB3),
6340 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6346 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6347 },
6348 { /* MCP89 Ethernet Controller */
6349 PCI_DEVICE(0x10DE, 0x0D7D),
6350 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6341 }, 6351 },
6342 {0,}, 6352 {0,},
6343}; 6353};
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 14:51:16 -0400