diff options
Diffstat (limited to 'drivers/net/forcedeth.c')
-rw-r--r-- | drivers/net/forcedeth.c | 111 |
1 files changed, 56 insertions, 55 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 2f48fe9a29a7..93f2b7a22160 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
@@ -234,6 +234,7 @@ enum { | |||
234 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | 234 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 |
235 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | 235 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 |
236 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | 236 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 |
237 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 | ||
237 | NvRegTransmitterStatus = 0x088, | 238 | NvRegTransmitterStatus = 0x088, |
238 | #define NVREG_XMITSTAT_BUSY 0x01 | 239 | #define NVREG_XMITSTAT_BUSY 0x01 |
239 | 240 | ||
@@ -249,6 +250,7 @@ enum { | |||
249 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | 250 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE |
250 | NvRegReceiverControl = 0x094, | 251 | NvRegReceiverControl = 0x094, |
251 | #define NVREG_RCVCTL_START 0x01 | 252 | #define NVREG_RCVCTL_START 0x01 |
253 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 | ||
252 | NvRegReceiverStatus = 0x98, | 254 | NvRegReceiverStatus = 0x98, |
253 | #define NVREG_RCVSTAT_BUSY 0x01 | 255 | #define NVREG_RCVSTAT_BUSY 0x01 |
254 | 256 | ||
@@ -1169,16 +1171,21 @@ static void nv_start_rx(struct net_device *dev) | |||
1169 | { | 1171 | { |
1170 | struct fe_priv *np = netdev_priv(dev); | 1172 | struct fe_priv *np = netdev_priv(dev); |
1171 | u8 __iomem *base = get_hwbase(dev); | 1173 | u8 __iomem *base = get_hwbase(dev); |
1174 | u32 rx_ctrl = readl(base + NvRegReceiverControl); | ||
1172 | 1175 | ||
1173 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | 1176 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
1174 | /* Already running? Stop it. */ | 1177 | /* Already running? Stop it. */ |
1175 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | 1178 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1176 | writel(0, base + NvRegReceiverControl); | 1179 | rx_ctrl &= ~NVREG_RCVCTL_START; |
1180 | writel(rx_ctrl, base + NvRegReceiverControl); | ||
1177 | pci_push(base); | 1181 | pci_push(base); |
1178 | } | 1182 | } |
1179 | writel(np->linkspeed, base + NvRegLinkSpeed); | 1183 | writel(np->linkspeed, base + NvRegLinkSpeed); |
1180 | pci_push(base); | 1184 | pci_push(base); |
1181 | writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); | 1185 | rx_ctrl |= NVREG_RCVCTL_START; |
1186 | if (np->mac_in_use) | ||
1187 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; | ||
1188 | writel(rx_ctrl, base + NvRegReceiverControl); | ||
1182 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", | 1189 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
1183 | dev->name, np->duplex, np->linkspeed); | 1190 | dev->name, np->duplex, np->linkspeed); |
1184 | pci_push(base); | 1191 | pci_push(base); |
@@ -1186,39 +1193,59 @@ static void nv_start_rx(struct net_device *dev) | |||
1186 | 1193 | ||
1187 | static void nv_stop_rx(struct net_device *dev) | 1194 | static void nv_stop_rx(struct net_device *dev) |
1188 | { | 1195 | { |
1196 | struct fe_priv *np = netdev_priv(dev); | ||
1189 | u8 __iomem *base = get_hwbase(dev); | 1197 | u8 __iomem *base = get_hwbase(dev); |
1198 | u32 rx_ctrl = readl(base + NvRegReceiverControl); | ||
1190 | 1199 | ||
1191 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); | 1200 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); |
1192 | writel(0, base + NvRegReceiverControl); | 1201 | if (!np->mac_in_use) |
1202 | rx_ctrl &= ~NVREG_RCVCTL_START; | ||
1203 | else | ||
1204 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | ||
1205 | writel(rx_ctrl, base + NvRegReceiverControl); | ||
1193 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, | 1206 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1194 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, | 1207 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, |
1195 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); | 1208 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); |
1196 | 1209 | ||
1197 | udelay(NV_RXSTOP_DELAY2); | 1210 | udelay(NV_RXSTOP_DELAY2); |
1198 | writel(0, base + NvRegLinkSpeed); | 1211 | if (!np->mac_in_use) |
1212 | writel(0, base + NvRegLinkSpeed); | ||
1199 | } | 1213 | } |
1200 | 1214 | ||
1201 | static void nv_start_tx(struct net_device *dev) | 1215 | static void nv_start_tx(struct net_device *dev) |
1202 | { | 1216 | { |
1217 | struct fe_priv *np = netdev_priv(dev); | ||
1203 | u8 __iomem *base = get_hwbase(dev); | 1218 | u8 __iomem *base = get_hwbase(dev); |
1219 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); | ||
1204 | 1220 | ||
1205 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); | 1221 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); |
1206 | writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); | 1222 | tx_ctrl |= NVREG_XMITCTL_START; |
1223 | if (np->mac_in_use) | ||
1224 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | ||
1225 | writel(tx_ctrl, base + NvRegTransmitterControl); | ||
1207 | pci_push(base); | 1226 | pci_push(base); |
1208 | } | 1227 | } |
1209 | 1228 | ||
1210 | static void nv_stop_tx(struct net_device *dev) | 1229 | static void nv_stop_tx(struct net_device *dev) |
1211 | { | 1230 | { |
1231 | struct fe_priv *np = netdev_priv(dev); | ||
1212 | u8 __iomem *base = get_hwbase(dev); | 1232 | u8 __iomem *base = get_hwbase(dev); |
1233 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); | ||
1213 | 1234 | ||
1214 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); | 1235 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); |
1215 | writel(0, base + NvRegTransmitterControl); | 1236 | if (!np->mac_in_use) |
1237 | tx_ctrl &= ~NVREG_XMITCTL_START; | ||
1238 | else | ||
1239 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | ||
1240 | writel(tx_ctrl, base + NvRegTransmitterControl); | ||
1216 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, | 1241 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1217 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, | 1242 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, |
1218 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); | 1243 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); |
1219 | 1244 | ||
1220 | udelay(NV_TXSTOP_DELAY2); | 1245 | udelay(NV_TXSTOP_DELAY2); |
1221 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); | 1246 | if (!np->mac_in_use) |
1247 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | ||
1248 | base + NvRegTransmitPoll); | ||
1222 | } | 1249 | } |
1223 | 1250 | ||
1224 | static void nv_txrx_reset(struct net_device *dev) | 1251 | static void nv_txrx_reset(struct net_device *dev) |
@@ -4148,20 +4175,6 @@ static int nv_mgmt_acquire_sema(struct net_device *dev) | |||
4148 | return 0; | 4175 | return 0; |
4149 | } | 4176 | } |
4150 | 4177 | ||
4151 | /* Indicate to mgmt unit whether driver is loaded or not */ | ||
4152 | static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded) | ||
4153 | { | ||
4154 | u8 __iomem *base = get_hwbase(dev); | ||
4155 | u32 tx_ctrl; | ||
4156 | |||
4157 | tx_ctrl = readl(base + NvRegTransmitterControl); | ||
4158 | if (loaded) | ||
4159 | tx_ctrl |= NVREG_XMITCTL_HOST_LOADED; | ||
4160 | else | ||
4161 | tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED; | ||
4162 | writel(tx_ctrl, base + NvRegTransmitterControl); | ||
4163 | } | ||
4164 | |||
4165 | static int nv_open(struct net_device *dev) | 4178 | static int nv_open(struct net_device *dev) |
4166 | { | 4179 | { |
4167 | struct fe_priv *np = netdev_priv(dev); | 4180 | struct fe_priv *np = netdev_priv(dev); |
@@ -4659,33 +4672,24 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
4659 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | 4672 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
4660 | 4673 | ||
4661 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | 4674 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { |
4662 | writel(0x1, base + 0x204); pci_push(base); | ||
4663 | msleep(500); | ||
4664 | /* management unit running on the mac? */ | 4675 | /* management unit running on the mac? */ |
4665 | np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST; | 4676 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) { |
4666 | if (np->mac_in_use) { | 4677 | np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST; |
4667 | u32 mgmt_sync; | 4678 | dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use); |
4668 | /* management unit setup the phy already? */ | 4679 | for (i = 0; i < 5000; i++) { |
4669 | mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK; | 4680 | msleep(1); |
4670 | if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) { | 4681 | if (nv_mgmt_acquire_sema(dev)) { |
4671 | if (!nv_mgmt_acquire_sema(dev)) { | 4682 | /* management unit setup the phy already? */ |
4672 | for (i = 0; i < 5000; i++) { | 4683 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == |
4673 | msleep(1); | 4684 | NVREG_XMITCTL_SYNC_PHY_INIT) { |
4674 | mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK; | 4685 | /* phy is inited by mgmt unit */ |
4675 | if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) | 4686 | phyinitialized = 1; |
4676 | continue; | 4687 | dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev)); |
4677 | if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) | 4688 | } else { |
4678 | phyinitialized = 1; | 4689 | /* we need to init the phy */ |
4679 | break; | ||
4680 | } | 4690 | } |
4681 | } else { | 4691 | break; |
4682 | /* we need to init the phy */ | ||
4683 | } | 4692 | } |
4684 | } else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) { | ||
4685 | /* phy is inited by SMU */ | ||
4686 | phyinitialized = 1; | ||
4687 | } else { | ||
4688 | /* we need to init the phy */ | ||
4689 | } | 4693 | } |
4690 | } | 4694 | } |
4691 | } | 4695 | } |
@@ -4724,10 +4728,12 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
4724 | if (!phyinitialized) { | 4728 | if (!phyinitialized) { |
4725 | /* reset it */ | 4729 | /* reset it */ |
4726 | phy_init(dev); | 4730 | phy_init(dev); |
4727 | } | 4731 | } else { |
4728 | 4732 | /* see if it is a gigabit phy */ | |
4729 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | 4733 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
4730 | nv_mgmt_driver_loaded(dev, 1); | 4734 | if (mii_status & PHY_GIGABIT) { |
4735 | np->gigabit = PHY_GIGABIT; | ||
4736 | } | ||
4731 | } | 4737 | } |
4732 | 4738 | ||
4733 | /* set default link speed settings */ | 4739 | /* set default link speed settings */ |
@@ -4749,8 +4755,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
4749 | out_error: | 4755 | out_error: |
4750 | if (phystate_orig) | 4756 | if (phystate_orig) |
4751 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | 4757 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); |
4752 | if (np->mac_in_use) | ||
4753 | nv_mgmt_driver_loaded(dev, 0); | ||
4754 | pci_set_drvdata(pci_dev, NULL); | 4758 | pci_set_drvdata(pci_dev, NULL); |
4755 | out_freering: | 4759 | out_freering: |
4756 | free_rings(dev); | 4760 | free_rings(dev); |
@@ -4780,9 +4784,6 @@ static void __devexit nv_remove(struct pci_dev *pci_dev) | |||
4780 | writel(np->orig_mac[0], base + NvRegMacAddrA); | 4784 | writel(np->orig_mac[0], base + NvRegMacAddrA); |
4781 | writel(np->orig_mac[1], base + NvRegMacAddrB); | 4785 | writel(np->orig_mac[1], base + NvRegMacAddrB); |
4782 | 4786 | ||
4783 | if (np->mac_in_use) | ||
4784 | nv_mgmt_driver_loaded(dev, 0); | ||
4785 | |||
4786 | /* free all structures */ | 4787 | /* free all structures */ |
4787 | free_rings(dev); | 4788 | free_rings(dev); |
4788 | iounmap(get_hwbase(dev)); | 4789 | iounmap(get_hwbase(dev)); |