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path: root/drivers/net/forcedeth.c
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-rw-r--r--drivers/net/forcedeth.c110
1 files changed, 70 insertions, 40 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 01b38b092c76..053971e5fc94 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -77,26 +77,27 @@
77 * Hardware access: 77 * Hardware access:
78 */ 78 */
79 79
80#define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */ 80#define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
81#define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */ 81#define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
82#define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */ 82#define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
83#define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */ 83#define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
84#define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */ 84#define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */
85#define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */ 85#define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */
86#define DEV_HAS_MSI 0x00040 /* device supports MSI */ 86#define DEV_HAS_MSI 0x000040 /* device supports MSI */
87#define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */ 87#define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */
88#define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */ 88#define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */
89#define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */ 89#define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */
90#define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */ 90#define DEV_HAS_STATISTICS_V2 0x000400 /* device supports hw statistics version 2 */
91#define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */ 91#define DEV_HAS_STATISTICS_V3 0x000800 /* device supports hw statistics version 3 */
92#define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */ 92#define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */
93#define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */ 93#define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */
94#define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */ 94#define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */
95#define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */ 95#define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */
96#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */ 96#define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */
97#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */ 97#define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */
98#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */ 98#define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */
99#define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */ 99#define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */
100#define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */
100 101
101enum { 102enum {
102 NvRegIrqStatus = 0x000, 103 NvRegIrqStatus = 0x000,
@@ -248,6 +249,8 @@ enum {
248#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 249#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 250#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 251#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
252 NvRegTxPauseFrameLimit = 0x174,
253#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
251 NvRegMIIStatus = 0x180, 254 NvRegMIIStatus = 0x180,
252#define NVREG_MIISTAT_ERROR 0x0001 255#define NVREG_MIISTAT_ERROR 0x0001
253#define NVREG_MIISTAT_LINKCHANGE 0x0008 256#define NVREG_MIISTAT_LINKCHANGE 0x0008
@@ -270,6 +273,9 @@ enum {
270#define NVREG_MIICTL_WRITE 0x00400 273#define NVREG_MIICTL_WRITE 0x00400
271#define NVREG_MIICTL_ADDRSHIFT 5 274#define NVREG_MIICTL_ADDRSHIFT 5
272 NvRegMIIData = 0x194, 275 NvRegMIIData = 0x194,
276 NvRegTxUnicast = 0x1a0,
277 NvRegTxMulticast = 0x1a4,
278 NvRegTxBroadcast = 0x1a8,
273 NvRegWakeUpFlags = 0x200, 279 NvRegWakeUpFlags = 0x200,
274#define NVREG_WAKEUPFLAGS_VAL 0x7770 280#define NVREG_WAKEUPFLAGS_VAL 0x7770
275#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 281#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
@@ -402,6 +408,7 @@ union ring_type {
402#define NV_RX_FRAMINGERR (1<<29) 408#define NV_RX_FRAMINGERR (1<<29)
403#define NV_RX_ERROR (1<<30) 409#define NV_RX_ERROR (1<<30)
404#define NV_RX_AVAIL (1<<31) 410#define NV_RX_AVAIL (1<<31)
411#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
405 412
406#define NV_RX2_CHECKSUMMASK (0x1C000000) 413#define NV_RX2_CHECKSUMMASK (0x1C000000)
407#define NV_RX2_CHECKSUM_IP (0x10000000) 414#define NV_RX2_CHECKSUM_IP (0x10000000)
@@ -419,6 +426,7 @@ union ring_type {
419/* error and avail are the same for both */ 426/* error and avail are the same for both */
420#define NV_RX2_ERROR (1<<30) 427#define NV_RX2_ERROR (1<<30)
421#define NV_RX2_AVAIL (1<<31) 428#define NV_RX2_AVAIL (1<<31)
429#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
422 430
423#define NV_RX3_VLAN_TAG_PRESENT (1<<16) 431#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
424#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) 432#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
@@ -616,7 +624,12 @@ static const struct nv_ethtool_str nv_estats_str[] = {
616 { "rx_bytes" }, 624 { "rx_bytes" },
617 { "tx_pause" }, 625 { "tx_pause" },
618 { "rx_pause" }, 626 { "rx_pause" },
619 { "rx_drop_frame" } 627 { "rx_drop_frame" },
628
629 /* version 3 stats */
630 { "tx_unicast" },
631 { "tx_multicast" },
632 { "tx_broadcast" }
620}; 633};
621 634
622struct nv_ethtool_stats { 635struct nv_ethtool_stats {
@@ -652,9 +665,15 @@ struct nv_ethtool_stats {
652 u64 tx_pause; 665 u64 tx_pause;
653 u64 rx_pause; 666 u64 rx_pause;
654 u64 rx_drop_frame; 667 u64 rx_drop_frame;
668
669 /* version 3 stats */
670 u64 tx_unicast;
671 u64 tx_multicast;
672 u64 tx_broadcast;
655}; 673};
656 674
657#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) 675#define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
676#define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
658#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) 677#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
659 678
660/* diagnostics */ 679/* diagnostics */
@@ -1628,6 +1647,12 @@ static void nv_get_hw_stats(struct net_device *dev)
1628 np->estats.rx_pause += readl(base + NvRegRxPause); 1647 np->estats.rx_pause += readl(base + NvRegRxPause);
1629 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); 1648 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1630 } 1649 }
1650
1651 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1652 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1653 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1654 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1655 }
1631} 1656}
1632 1657
1633/* 1658/*
@@ -1641,7 +1666,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev)
1641 struct fe_priv *np = netdev_priv(dev); 1666 struct fe_priv *np = netdev_priv(dev);
1642 1667
1643 /* If the nic supports hw counters then retrieve latest values */ 1668 /* If the nic supports hw counters then retrieve latest values */
1644 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) { 1669 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1645 nv_get_hw_stats(dev); 1670 nv_get_hw_stats(dev);
1646 1671
1647 /* copy to net_device stats */ 1672 /* copy to net_device stats */
@@ -2632,7 +2657,7 @@ static int nv_rx_process(struct net_device *dev, int limit)
2632 if (likely(flags & NV_RX_DESCRIPTORVALID)) { 2657 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2633 len = flags & LEN_MASK_V1; 2658 len = flags & LEN_MASK_V1;
2634 if (unlikely(flags & NV_RX_ERROR)) { 2659 if (unlikely(flags & NV_RX_ERROR)) {
2635 if (flags & NV_RX_ERROR4) { 2660 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2636 len = nv_getlen(dev, skb->data, len); 2661 len = nv_getlen(dev, skb->data, len);
2637 if (len < 0) { 2662 if (len < 0) {
2638 dev->stats.rx_errors++; 2663 dev->stats.rx_errors++;
@@ -2641,7 +2666,7 @@ static int nv_rx_process(struct net_device *dev, int limit)
2641 } 2666 }
2642 } 2667 }
2643 /* framing errors are soft errors */ 2668 /* framing errors are soft errors */
2644 else if (flags & NV_RX_FRAMINGERR) { 2669 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2645 if (flags & NV_RX_SUBSTRACT1) { 2670 if (flags & NV_RX_SUBSTRACT1) {
2646 len--; 2671 len--;
2647 } 2672 }
@@ -2667,7 +2692,7 @@ static int nv_rx_process(struct net_device *dev, int limit)
2667 if (likely(flags & NV_RX2_DESCRIPTORVALID)) { 2692 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2668 len = flags & LEN_MASK_V2; 2693 len = flags & LEN_MASK_V2;
2669 if (unlikely(flags & NV_RX2_ERROR)) { 2694 if (unlikely(flags & NV_RX2_ERROR)) {
2670 if (flags & NV_RX2_ERROR4) { 2695 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2671 len = nv_getlen(dev, skb->data, len); 2696 len = nv_getlen(dev, skb->data, len);
2672 if (len < 0) { 2697 if (len < 0) {
2673 dev->stats.rx_errors++; 2698 dev->stats.rx_errors++;
@@ -2676,7 +2701,7 @@ static int nv_rx_process(struct net_device *dev, int limit)
2676 } 2701 }
2677 } 2702 }
2678 /* framing errors are soft errors */ 2703 /* framing errors are soft errors */
2679 else if (flags & NV_RX2_FRAMINGERR) { 2704 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2680 if (flags & NV_RX2_SUBSTRACT1) { 2705 if (flags & NV_RX2_SUBSTRACT1) {
2681 len--; 2706 len--;
2682 } 2707 }
@@ -2766,7 +2791,7 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
2766 if (likely(flags & NV_RX2_DESCRIPTORVALID)) { 2791 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2767 len = flags & LEN_MASK_V2; 2792 len = flags & LEN_MASK_V2;
2768 if (unlikely(flags & NV_RX2_ERROR)) { 2793 if (unlikely(flags & NV_RX2_ERROR)) {
2769 if (flags & NV_RX2_ERROR4) { 2794 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2770 len = nv_getlen(dev, skb->data, len); 2795 len = nv_getlen(dev, skb->data, len);
2771 if (len < 0) { 2796 if (len < 0) {
2772 dev_kfree_skb(skb); 2797 dev_kfree_skb(skb);
@@ -2774,7 +2799,7 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
2774 } 2799 }
2775 } 2800 }
2776 /* framing errors are soft errors */ 2801 /* framing errors are soft errors */
2777 else if (flags & NV_RX2_FRAMINGERR) { 2802 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2778 if (flags & NV_RX2_SUBSTRACT1) { 2803 if (flags & NV_RX2_SUBSTRACT1) {
2779 len--; 2804 len--;
2780 } 2805 }
@@ -3053,8 +3078,11 @@ static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3053 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; 3078 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3054 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) 3079 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3055 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; 3080 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3056 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) 3081 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3057 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; 3082 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3083 /* limit the number of tx pause frames to a default of 8 */
3084 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3085 }
3058 writel(pause_enable, base + NvRegTxPauseFrame); 3086 writel(pause_enable, base + NvRegTxPauseFrame);
3059 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); 3087 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3060 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; 3088 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
@@ -4740,6 +4768,8 @@ static int nv_get_sset_count(struct net_device *dev, int sset)
4740 return NV_DEV_STATISTICS_V1_COUNT; 4768 return NV_DEV_STATISTICS_V1_COUNT;
4741 else if (np->driver_data & DEV_HAS_STATISTICS_V2) 4769 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4742 return NV_DEV_STATISTICS_V2_COUNT; 4770 return NV_DEV_STATISTICS_V2_COUNT;
4771 else if (np->driver_data & DEV_HAS_STATISTICS_V3)
4772 return NV_DEV_STATISTICS_V3_COUNT;
4743 else 4773 else
4744 return 0; 4774 return 0;
4745 default: 4775 default:
@@ -5324,7 +5354,7 @@ static int nv_open(struct net_device *dev)
5324 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); 5354 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5325 5355
5326 /* start statistics timer */ 5356 /* start statistics timer */
5327 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) 5357 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5328 mod_timer(&np->stats_poll, 5358 mod_timer(&np->stats_poll,
5329 round_jiffies(jiffies + STATS_INTERVAL)); 5359 round_jiffies(jiffies + STATS_INTERVAL));
5330 5360
@@ -5428,7 +5458,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5428 if (err < 0) 5458 if (err < 0)
5429 goto out_disable; 5459 goto out_disable;
5430 5460
5431 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2)) 5461 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5432 np->register_size = NV_PCI_REGSZ_VER3; 5462 np->register_size = NV_PCI_REGSZ_VER3;
5433 else if (id->driver_data & DEV_HAS_STATISTICS_V1) 5463 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5434 np->register_size = NV_PCI_REGSZ_VER2; 5464 np->register_size = NV_PCI_REGSZ_VER2;
@@ -6083,35 +6113,35 @@ static struct pci_device_id pci_tbl[] = {
6083 }, 6113 },
6084 { /* MCP77 Ethernet Controller */ 6114 { /* MCP77 Ethernet Controller */
6085 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), 6115 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6086 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6116 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6087 }, 6117 },
6088 { /* MCP77 Ethernet Controller */ 6118 { /* MCP77 Ethernet Controller */
6089 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), 6119 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6090 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6120 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6091 }, 6121 },
6092 { /* MCP77 Ethernet Controller */ 6122 { /* MCP77 Ethernet Controller */
6093 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), 6123 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6094 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6124 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6095 }, 6125 },
6096 { /* MCP77 Ethernet Controller */ 6126 { /* MCP77 Ethernet Controller */
6097 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), 6127 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6098 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6128 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6099 }, 6129 },
6100 { /* MCP79 Ethernet Controller */ 6130 { /* MCP79 Ethernet Controller */
6101 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), 6131 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6102 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6132 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6103 }, 6133 },
6104 { /* MCP79 Ethernet Controller */ 6134 { /* MCP79 Ethernet Controller */
6105 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), 6135 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6106 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6136 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6107 }, 6137 },
6108 { /* MCP79 Ethernet Controller */ 6138 { /* MCP79 Ethernet Controller */
6109 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), 6139 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6110 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6140 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6111 }, 6141 },
6112 { /* MCP79 Ethernet Controller */ 6142 { /* MCP79 Ethernet Controller */
6113 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), 6143 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6114 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, 6144 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6115 }, 6145 },
6116 {0,}, 6146 {0,},
6117}; 6147};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 10:47:53 -0500