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path: root/drivers/net/fec.c
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Diffstat (limited to 'drivers/net/fec.c')
-rw-r--r--drivers/net/fec.c39
1 files changed, 4 insertions, 35 deletions
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 6ac1b90c5820..5ca2d6bcc23a 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1615,10 +1615,6 @@ int __init fec_enet_init(struct net_device *dev, int index)
1615 fep->hwp = (void __iomem *)dev->base_addr; 1615 fep->hwp = (void __iomem *)dev->base_addr;
1616 fep->netdev = dev; 1616 fep->netdev = dev;
1617 1617
1618 /* Whack a reset. We should wait for this. */
1619 writel(1, fep->hwp + FEC_ECNTRL);
1620 udelay(10);
1621
1622 /* Set the Ethernet address */ 1618 /* Set the Ethernet address */
1623#ifdef CONFIG_M5272 1619#ifdef CONFIG_M5272
1624 fec_get_mac(dev); 1620 fec_get_mac(dev);
@@ -1640,11 +1636,6 @@ int __init fec_enet_init(struct net_device *dev, int index)
1640 fep->rx_bd_base = cbd_base; 1636 fep->rx_bd_base = cbd_base;
1641 fep->tx_bd_base = cbd_base + RX_RING_SIZE; 1637 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1642 1638
1643 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1644 fep->cur_rx = fep->rx_bd_base;
1645
1646 fep->skb_cur = fep->skb_dirty = 0;
1647
1648 /* Initialize the receive buffer descriptors. */ 1639 /* Initialize the receive buffer descriptors. */
1649 bdp = fep->rx_bd_base; 1640 bdp = fep->rx_bd_base;
1650 for (i=0; i<FEC_ENET_RX_PAGES; i++) { 1641 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
@@ -1688,25 +1679,9 @@ int __init fec_enet_init(struct net_device *dev, int index)
1688 bdp--; 1679 bdp--;
1689 bdp->cbd_sc |= BD_SC_WRAP; 1680 bdp->cbd_sc |= BD_SC_WRAP;
1690 1681
1691 /* Set receive and transmit descriptor base */
1692 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1693 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1694 fep->hwp + FEC_X_DES_START);
1695
1696#ifdef HAVE_mii_link_interrupt 1682#ifdef HAVE_mii_link_interrupt
1697 fec_request_mii_intr(dev); 1683 fec_request_mii_intr(dev);
1698#endif 1684#endif
1699
1700 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1701 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1702 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1703 writel(2, fep->hwp + FEC_ECNTRL);
1704 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1705#ifndef CONFIG_M5272
1706 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1707 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1708#endif
1709
1710 /* The FEC Ethernet specific entries in the device structure */ 1685 /* The FEC Ethernet specific entries in the device structure */
1711 dev->open = fec_enet_open; 1686 dev->open = fec_enet_open;
1712 dev->hard_start_xmit = fec_enet_start_xmit; 1687 dev->hard_start_xmit = fec_enet_start_xmit;
@@ -1719,21 +1694,11 @@ int __init fec_enet_init(struct net_device *dev, int index)
1719 mii_cmds[i].mii_next = &mii_cmds[i+1]; 1694 mii_cmds[i].mii_next = &mii_cmds[i+1];
1720 mii_free = mii_cmds; 1695 mii_free = mii_cmds;
1721 1696
1722 /* setup MII interface */
1723 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1724 writel(0, fep->hwp + FEC_X_CNTRL);
1725
1726 /* Set MII speed to 2.5 MHz */ 1697 /* Set MII speed to 2.5 MHz */
1727 fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999) 1698 fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999)
1728 / 2500000) / 2) & 0x3F) << 1; 1699 / 2500000) / 2) & 0x3F) << 1;
1729 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1730 fec_restart(dev, 0); 1700 fec_restart(dev, 0);
1731 1701
1732 /* Clear and enable interrupts */
1733 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1734 writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII,
1735 fep->hwp + FEC_IMASK);
1736
1737 /* Queue up command to detect the PHY and initialize the 1702 /* Queue up command to detect the PHY and initialize the
1738 * remainder of the interface. 1703 * remainder of the interface.
1739 */ 1704 */
@@ -1768,6 +1733,10 @@ fec_restart(struct net_device *dev, int duplex)
1768 /* Reset all multicast. */ 1733 /* Reset all multicast. */
1769 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1734 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1770 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1735 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1736#ifndef CONFIG_M5272
1737 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1738 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1739#endif
1771 1740
1772 /* Set maximum receive buffer size. */ 1741 /* Set maximum receive buffer size. */
1773 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 1742 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);