25 files changed, 897 insertions, 1186 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
index 4dd18a1f45d2..e73c2c355993 100644
--- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
@@ -26,8 +26,7 @@
 *******************************************************************************/
-/*
+/* 80003ES2LAN Gigabit Ethernet Controller (Copper)
- * 80003ES2LAN Gigabit Ethernet Controller (Copper)
 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
 */
@@ -80,7 +79,8 @@
                                                           1 = 50-80M
                                                           2 = 80-110M
                                                           3 = 110-140M
-                                                           4 = >140M */
+                                                           4 = >140M
+                                                        */
 /* Kumeran Mode Control Register (Page 193, Register 16) */
 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
@@ -95,8 +95,7 @@
 /* In-Band Control Register (Page 194, Register 18) */
 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
-/*
+/* A table for the GG82563 cable length where the range is defined
- * A table for the GG82563 cable length where the range is defined
 * with a lower bound at "index" and the upper bound at
 * "index + 5".
 */
@@ -183,8 +182,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
        size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
                          E1000_EECD_SIZE_EX_SHIFT);
-        /*
+        /* Added to a constant, "size" becomes the left-shift value
-         * Added to a constant, "size" becomes the left-shift value
         * for setting word_size.
         */
        size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -375,8 +373,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
                if (!(swfw_sync & (fwmask | swmask)))
                        break;
-                /*
+                /* Firmware currently using resource (fwmask)
-                 * Firmware currently using resource (fwmask)
                 * or other software thread using resource (swmask)
                 */
                e1000e_put_hw_semaphore(hw);
@@ -442,8 +439,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
        if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
                page_select = GG82563_PHY_PAGE_SELECT;
        } else {
-                /*
+                /* Use Alternative Page Select register to access
-                 * Use Alternative Page Select register to access
                 * registers 30 and 31
                 */
                page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -457,8 +453,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
        }
        if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
-                /*
+                /* The "ready" bit in the MDIC register may be incorrectly set
-                 * The "ready" bit in the MDIC register may be incorrectly set
                 * before the device has completed the "Page Select" MDI
                 * transaction.  So we wait 200us after each MDI command...
                 */
@@ -513,8 +508,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
        if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
                page_select = GG82563_PHY_PAGE_SELECT;
        } else {
-                /*
+                /* Use Alternative Page Select register to access
-                 * Use Alternative Page Select register to access
                 * registers 30 and 31
                 */
                page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -528,8 +522,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
        }
        if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
-                /*
+                /* The "ready" bit in the MDIC register may be incorrectly set
-                 * The "ready" bit in the MDIC register may be incorrectly set
                 * before the device has completed the "Page Select" MDI
                 * transaction.  So we wait 200us after each MDI command...
                 */
@@ -618,8 +611,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
        u16 phy_data;
        bool link;
-        /*
+        /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
-         * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
         * forced whenever speed and duplex are forced.
         */
        ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -657,8 +649,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
                        return ret_val;
                if (!link) {
-                        /*
+                        /* We didn't get link.
-                         * We didn't get link.
                         * Reset the DSP and cross our fingers.
                         */
                        ret_val = e1000e_phy_reset_dsp(hw);
@@ -677,8 +668,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Resetting the phy means we need to verify the TX_CLK corresponds
-         * Resetting the phy means we need to verify the TX_CLK corresponds
         * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
         */
        phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
@@ -687,8 +677,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
        else
                phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
-        /*
+        /* In addition, we must re-enable CRS on Tx for both half and full
-         * In addition, we must re-enable CRS on Tx for both half and full
         * duplex.
         */
        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -766,8 +755,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
        s32 ret_val;
        u16 kum_reg_data;
-        /*
+        /* Prevent the PCI-E bus from sticking if there is no TLP connection
-         * Prevent the PCI-E bus from sticking if there is no TLP connection
         * on the last TLP read/write transaction when MAC is reset.
         */
        ret_val = e1000e_disable_pcie_master(hw);
@@ -899,8 +887,7 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
                        hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
        }
-        /*
+        /* Clear all of the statistics registers (clear on read).  It is
-         * Clear all of the statistics registers (clear on read).  It is
         * important that we do this after we have tried to establish link
         * because the symbol error count will increment wildly if there
         * is no link.
@@ -945,8 +932,7 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
                reg |= (1 << 28);
        ew32(TARC(1), reg);
-        /*
+        /* Disable IPv6 extension header parsing because some malformed
-         * Disable IPv6 extension header parsing because some malformed
         * IPv6 headers can hang the Rx.
         */
        reg = er32(RFCTL);
@@ -979,8 +965,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Options:
-         * Options:
         *   MDI/MDI-X = 0 (default)
         *   0 - Auto for all speeds
         *   1 - MDI mode
@@ -1006,8 +991,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
                break;
        }
-        /*
+        /* Options:
-         * Options:
         *   disable_polarity_correction = 0 (default)
         *       Automatic Correction for Reversed Cable Polarity
         *   0 - Disabled
@@ -1065,8 +1049,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Do not init these registers when the HW is in IAMT mode, since the
-         * Do not init these registers when the HW is in IAMT mode, since the
         * firmware will have already initialized them.  We only initialize
         * them if the HW is not in IAMT mode.
         */
@@ -1087,8 +1070,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
                        return ret_val;
        }
-        /*
+        /* Workaround: Disable padding in Kumeran interface in the MAC
-         * Workaround: Disable padding in Kumeran interface in the MAC
         * and in the PHY to avoid CRC errors.
         */
        ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
@@ -1121,8 +1103,7 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
        ew32(CTRL, ctrl);
-        /*
+        /* Set the mac to wait the maximum time between each
-         * Set the mac to wait the maximum time between each
         * iteration and increase the max iterations when
         * polling the phy; this fixes erroneous timeouts at 10Mbps.
         */
@@ -1352,8 +1333,7 @@ static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
 {
        s32 ret_val = 0;
-        /*
+        /* If there's an alternate MAC address place it in RAR0
-         * If there's an alternate MAC address place it in RAR0
         * so that it will override the Si installed default perm
         * address.
         */
diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c
index c98586408005..c77d010d5c59 100644
--- a/drivers/net/ethernet/intel/e1000e/82571.c
+++ b/drivers/net/ethernet/intel/e1000e/82571.c
@@ -26,8 +26,7 @@
 *******************************************************************************/
-/*
+/* 82571EB Gigabit Ethernet Controller
- * 82571EB Gigabit Ethernet Controller
 * 82571EB Gigabit Ethernet Controller (Copper)
 * 82571EB Gigabit Ethernet Controller (Fiber)
 * 82571EB Dual Port Gigabit Mezzanine Adapter
@@ -191,8 +190,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
                if (((eecd >> 15) & 0x3) == 0x3) {
                        nvm->type = e1000_nvm_flash_hw;
                        nvm->word_size = 2048;
-                        /*
+                        /* Autonomous Flash update bit must be cleared due
-                         * Autonomous Flash update bit must be cleared due
                         * to Flash update issue.
                         */
                        eecd &= ~E1000_EECD_AUPDEN;
@@ -204,8 +202,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
                nvm->type = e1000_nvm_eeprom_spi;
                size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
                                  E1000_EECD_SIZE_EX_SHIFT);
-                /*
+                /* Added to a constant, "size" becomes the left-shift value
-                 * Added to a constant, "size" becomes the left-shift value
                 * for setting word_size.
                 */
                size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -291,8 +288,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
                /* FWSM register */
                mac->has_fwsm = true;
-                /*
+                /* ARC supported; valid only if manageability features are
-                 * ARC supported; valid only if manageability features are
                 * enabled.
                 */
                mac->arc_subsystem_valid = !!(er32(FWSM) &
@@ -314,8 +310,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
                break;
        }
-        /*
+        /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
-         * Ensure that the inter-port SWSM.SMBI lock bit is clear before
         * first NVM or PHY access. This should be done for single-port
         * devices, and for one port only on dual-port devices so that
         * for those devices we can still use the SMBI lock to synchronize
@@ -352,11 +347,8 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
                ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
        }
-        /*
+        /* Initialize device specific counter of SMBI acquisition timeouts. */
-         * Initialize device specific counter of SMBI acquisition
+        hw->dev_spec.e82571.smb_counter = 0;
-         * timeouts.
-         */
-         hw->dev_spec.e82571.smb_counter = 0;
        return 0;
 }
@@ -445,8 +437,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_82571:
        case e1000_82572:
-                /*
+                /* The 82571 firmware may still be configuring the PHY.
-                 * The 82571 firmware may still be configuring the PHY.
                 * In this case, we cannot access the PHY until the
                 * configuration is done.  So we explicitly set the
                 * PHY ID.
@@ -492,8 +483,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
        s32 fw_timeout = hw->nvm.word_size + 1;
        s32 i = 0;
-        /*
+        /* If we have timedout 3 times on trying to acquire
-         * If we have timedout 3 times on trying to acquire
         * the inter-port SMBI semaphore, there is old code
         * operating on the other port, and it is not
         * releasing SMBI. Modify the number of times that
@@ -787,8 +777,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* If our nvm is an EEPROM, then we're done
-         * If our nvm is an EEPROM, then we're done
         * otherwise, commit the checksum to the flash NVM.
         */
        if (hw->nvm.type != e1000_nvm_flash_hw)
@@ -806,8 +795,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
        /* Reset the firmware if using STM opcode. */
        if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
-                /*
+                /* The enabling of and the actual reset must be done
-                 * The enabling of and the actual reset must be done
                 * in two write cycles.
                 */
                ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
@@ -867,8 +855,7 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
        u32 i, eewr = 0;
        s32 ret_val = 0;
-        /*
+        /* A check for invalid values:  offset too large, too many words,
-         * A check for invalid values:  offset too large, too many words,
         * and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
@@ -957,8 +944,7 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
        } else {
                data &= ~IGP02E1000_PM_D0_LPLU;
                ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
-                /*
+                /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
-                 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
                 * during Dx states where the power conservation is most
                 * important.  During driver activity we should enable
                 * SmartSpeed, so performance is maintained.
@@ -1002,8 +988,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
        u32 ctrl, ctrl_ext, eecd, tctl;
        s32 ret_val;
-        /*
+        /* Prevent the PCI-E bus from sticking if there is no TLP connection
-         * Prevent the PCI-E bus from sticking if there is no TLP connection
         * on the last TLP read/write transaction when MAC is reset.
         */
        ret_val = e1000e_disable_pcie_master(hw);
@@ -1021,8 +1006,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
        usleep_range(10000, 20000);
-        /*
+        /* Must acquire the MDIO ownership before MAC reset.
-         * Must acquire the MDIO ownership before MAC reset.
         * Ownership defaults to firmware after a reset.
         */
        switch (hw->mac.type) {
@@ -1067,8 +1051,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
                /* We don't want to continue accessing MAC registers. */
                return ret_val;
-        /*
+        /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
-         * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
         * Need to wait for Phy configuration completion before accessing
         * NVM and Phy.
         */
@@ -1076,8 +1059,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_82571:
        case e1000_82572:
-                /*
+                /* REQ and GNT bits need to be cleared when using AUTO_RD
-                 * REQ and GNT bits need to be cleared when using AUTO_RD
                 * to access the EEPROM.
                 */
                eecd = er32(EECD);
@@ -1138,8 +1120,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
        e_dbg("Initializing the IEEE VLAN\n");
        mac->ops.clear_vfta(hw);
-        /* Setup the receive address. */
+        /* Setup the receive address.
-        /*
         * If, however, a locally administered address was assigned to the
         * 82571, we must reserve a RAR for it to work around an issue where
         * resetting one port will reload the MAC on the other port.
@@ -1183,8 +1164,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
                break;
        }
-        /*
+        /* Clear all of the statistics registers (clear on read).  It is
-         * Clear all of the statistics registers (clear on read).  It is
         * important that we do this after we have tried to establish link
         * because the symbol error count will increment wildly if there
         * is no link.
@@ -1281,8 +1261,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
                ew32(PBA_ECC, reg);
        }
-        /*
+        /* Workaround for hardware errata.
-         * Workaround for hardware errata.
         * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
         */
        if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
@@ -1291,8 +1270,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
                ew32(CTRL_EXT, reg);
        }
-        /*
+        /* Disable IPv6 extension header parsing because some malformed
-         * Disable IPv6 extension header parsing because some malformed
         * IPv6 headers can hang the Rx.
         */
        if (hw->mac.type <= e1000_82573) {
@@ -1309,8 +1287,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
                reg |= (1 << 22);
                ew32(GCR, reg);
-                /*
+                /* Workaround for hardware errata.
-                 * Workaround for hardware errata.
                 * apply workaround for hardware errata documented in errata
                 * docs Fixes issue where some error prone or unreliable PCIe
                 * completions are occurring, particularly with ASPM enabled.
@@ -1344,8 +1321,7 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
        case e1000_82574:
        case e1000_82583:
                if (hw->mng_cookie.vlan_id != 0) {
-                        /*
+                        /* The VFTA is a 4096b bit-field, each identifying
-                         * The VFTA is a 4096b bit-field, each identifying
                         * a single VLAN ID.  The following operations
                         * determine which 32b entry (i.e. offset) into the
                         * array we want to set the VLAN ID (i.e. bit) of
@@ -1362,8 +1338,7 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
                break;
        }
        for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
-                /*
+                /* If the offset we want to clear is the same offset of the
-                 * If the offset we want to clear is the same offset of the
                 * manageability VLAN ID, then clear all bits except that of
                 * the manageability unit.
                 */
@@ -1401,8 +1376,7 @@ static s32 e1000_led_on_82574(struct e1000_hw *hw)
        ctrl = hw->mac.ledctl_mode2;
        if (!(E1000_STATUS_LU & er32(STATUS))) {
-                /*
+                /* If no link, then turn LED on by setting the invert bit
-                 * If no link, then turn LED on by setting the invert bit
                 * for each LED that's "on" (0x0E) in ledctl_mode2.
                 */
                for (i = 0; i < 4; i++)
@@ -1427,8 +1401,7 @@ bool e1000_check_phy_82574(struct e1000_hw *hw)
        u16 receive_errors = 0;
        s32 ret_val = 0;
-        /*
+        /* Read PHY Receive Error counter first, if its is max - all F's then
-         * Read PHY Receive Error counter first, if its is max - all F's then
         * read the Base1000T status register If both are max then PHY is hung.
         */
        ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
@@ -1458,8 +1431,7 @@ bool e1000_check_phy_82574(struct e1000_hw *hw)
 **/
 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
 {
-        /*
+        /* 82573 does not have a word in the NVM to determine
-         * 82573 does not have a word in the NVM to determine
         * the default flow control setting, so we explicitly
         * set it to full.
         */
@@ -1526,8 +1498,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_82571:
        case e1000_82572:
-                /*
+                /* If SerDes loopback mode is entered, there is no form
-                 * If SerDes loopback mode is entered, there is no form
                 * of reset to take the adapter out of that mode.  So we
                 * have to explicitly take the adapter out of loopback
                 * mode.  This prevents drivers from twiddling their thumbs
@@ -1584,8 +1555,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                switch (mac->serdes_link_state) {
                case e1000_serdes_link_autoneg_complete:
                        if (!(status & E1000_STATUS_LU)) {
-                                /*
+                                /* We have lost link, retry autoneg before
-                                 * We have lost link, retry autoneg before
                                 * reporting link failure
                                 */
                                mac->serdes_link_state =
@@ -1598,8 +1568,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                        break;
                case e1000_serdes_link_forced_up:
-                        /*
+                        /* If we are receiving /C/ ordered sets, re-enable
-                         * If we are receiving /C/ ordered sets, re-enable
                         * auto-negotiation in the TXCW register and disable
                         * forced link in the Device Control register in an
                         * attempt to auto-negotiate with our link partner.
@@ -1619,8 +1588,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                case e1000_serdes_link_autoneg_progress:
                        if (rxcw & E1000_RXCW_C) {
-                                /*
+                                /* We received /C/ ordered sets, meaning the
-                                 * We received /C/ ordered sets, meaning the
                                 * link partner has autonegotiated, and we can
                                 * trust the Link Up (LU) status bit.
                                 */
@@ -1636,8 +1604,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                                        e_dbg("AN_PROG   -> DOWN\n");
                                }
                        } else {
-                                /*
+                                /* The link partner did not autoneg.
-                                 * The link partner did not autoneg.
                                 * Force link up and full duplex, and change
                                 * state to forced.
                                 */
@@ -1660,8 +1627,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                case e1000_serdes_link_down:
                default:
-                        /*
+                        /* The link was down but the receiver has now gained
-                         * The link was down but the receiver has now gained
                         * valid sync, so lets see if we can bring the link
                         * up.
                         */
@@ -1679,8 +1645,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                        mac->serdes_link_state = e1000_serdes_link_down;
                        e_dbg("ANYSTATE  -> DOWN\n");
                } else {
-                        /*
+                        /* Check several times, if SYNCH bit and CONFIG
-                         * Check several times, if SYNCH bit and CONFIG
                         * bit both are consistently 1 then simply ignore
                         * the IV bit and restart Autoneg
                         */
@@ -1780,8 +1745,7 @@ void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
        /* If workaround is activated... */
        if (state)
-                /*
+                /* Hold a copy of the LAA in RAR[14] This is done so that
-                 * Hold a copy of the LAA in RAR[14] This is done so that
                 * between the time RAR[0] gets clobbered and the time it
                 * gets fixed, the actual LAA is in one of the RARs and no
                 * incoming packets directed to this port are dropped.
@@ -1810,8 +1774,7 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
        if (nvm->type != e1000_nvm_flash_hw)
                return 0;
-        /*
+        /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
-         * Check bit 4 of word 10h.  If it is 0, firmware is done updating
         * 10h-12h.  Checksum may need to be fixed.
         */
        ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
@@ -1819,8 +1782,7 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
                return ret_val;
        if (!(data & 0x10)) {
-                /*
+                /* Read 0x23 and check bit 15.  This bit is a 1
-                 * Read 0x23 and check bit 15.  This bit is a 1
                 * when the checksum has already been fixed.  If
                 * the checksum is still wrong and this bit is a
                 * 1, we need to return bad checksum.  Otherwise,
@@ -1852,8 +1814,7 @@ static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
        if (hw->mac.type == e1000_82571) {
                s32 ret_val = 0;
-                /*
+                /* If there's an alternate MAC address place it in RAR0
-                 * If there's an alternate MAC address place it in RAR0
                 * so that it will override the Si installed default perm
                 * address.
                 */
diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h
index 76edbc1be33b..02a12b69555f 100644
--- a/drivers/net/ethernet/intel/e1000e/defines.h
+++ b/drivers/net/ethernet/intel/e1000e/defines.h
@@ -185,8 +185,7 @@
 #define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
-/*
+/* Use byte values for the following shift parameters
- * Use byte values for the following shift parameters
 * Usage:
 *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 *                  E1000_PSRCTL_BSIZE0_MASK) |
@@ -242,8 +241,7 @@
 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
-/*
+/* Bit definitions for the Management Data IO (MDIO) and Management Data
- * Bit definitions for the Management Data IO (MDIO) and Management Data
 * Clock (MDC) pins in the Device Control Register.
 */
@@ -424,8 +422,7 @@
 #define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
 #define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */
-/*
+/* This defines the bits that are set in the Interrupt Mask
- * This defines the bits that are set in the Interrupt Mask
 * Set/Read Register.  Each bit is documented below:
 *   o RXT0   = Receiver Timer Interrupt (ring 0)
 *   o TXDW   = Transmit Descriptor Written Back
@@ -475,8 +472,7 @@
 /* 802.1q VLAN Packet Size */
 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
-/* Receive Address */
+/* Receive Address
-/*
 * Number of high/low register pairs in the RAR. The RAR (Receive Address
 * Registers) holds the directed and multicast addresses that we monitor.
 * Technically, we have 16 spots.  However, we reserve one of these spots
@@ -723,8 +719,7 @@
 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
 #define MAX_PHY_MULTI_PAGE_REG 0xF
-/* Bit definitions for valid PHY IDs. */
+/* Bit definitions for valid PHY IDs.
-/*
 * I = Integrated
 * E = External
 */
@@ -762,8 +757,7 @@
 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
 /* Auto crossover enabled all speeds */
 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
-/*
+/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
- * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
 * 0=Normal 10BASE-T Rx Threshold
 */
 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
@@ -779,14 +773,12 @@
 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
-/*
+/* Number of times we will attempt to autonegotiate before downshifting if we
- * Number of times we will attempt to autonegotiate before downshifting if we
 * are the master
 */
 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
-/*
+/* Number of times we will attempt to autonegotiate before downshifting if we
- * Number of times we will attempt to autonegotiate before downshifting if we
 * are the slave
 */
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
@@ -808,8 +800,7 @@
 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
                           ((reg) & MAX_PHY_REG_ADDRESS))
-/*
+/* Bits...
- * Bits...
 * 15-5: page
 * 4-0: register offset
 */
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 04668b47a1df..6782a2eea1bc 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -161,8 +161,7 @@ struct e1000_info;
 /* Time to wait before putting the device into D3 if there's no link (in ms). */
 #define LINK_TIMEOUT            100
-/*
+/* Count for polling __E1000_RESET condition every 10-20msec.
- * Count for polling __E1000_RESET condition every 10-20msec.
 * Experimentation has shown the reset can take approximately 210msec.
 */
 #define E1000_CHECK_RESET_COUNT         25
@@ -172,8 +171,7 @@ struct e1000_info;
 #define BURST_RDTR                      0x20
 #define BURST_RADV                      0x20
-/*
+/* in the case of WTHRESH, it appears at least the 82571/2 hardware
- * in the case of WTHRESH, it appears at least the 82571/2 hardware
 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
 * WTHRESH=4, so a setting of 5 gives the most efficient bus
 * utilization but to avoid possible Tx stalls, set it to 1
@@ -214,8 +212,7 @@ struct e1000_ps_page {
        u64 dma; /* must be u64 - written to hw */
 };
-/*
+/* wrappers around a pointer to a socket buffer,
- * wrappers around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer
 */
 struct e1000_buffer {
@@ -305,9 +302,7 @@ struct e1000_adapter {
        u16 tx_itr;
        u16 rx_itr;
-        /*
+        /* Tx */
-         * Tx
-         */
        struct e1000_ring *tx_ring /* One per active queue */
                                                ____cacheline_aligned_in_smp;
        u32 tx_fifo_limit;
@@ -340,9 +335,7 @@ struct e1000_adapter {
        u32 tx_fifo_size;
        u32 tx_dma_failed;
-        /*
+        /* Rx */
-         * Rx
-         */
        bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
                          int work_to_do) ____cacheline_aligned_in_smp;
        void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c
index c11ac2756667..f95bc6ee1c22 100644
--- a/drivers/net/ethernet/intel/e1000e/ethtool.c
+++ b/drivers/net/ethernet/intel/e1000e/ethtool.c
@@ -214,7 +214,8 @@ static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx)
        mac->autoneg = 0;
        /* Make sure dplx is at most 1 bit and lsb of speed is not set
-         * for the switch() below to work */
+         * for the switch() below to work
+         */
        if ((spd & 1) || (dplx & ~1))
                goto err_inval;
@@ -263,8 +264,7 @@ static int e1000_set_settings(struct net_device *netdev,
        struct e1000_adapter *adapter = netdev_priv(netdev);
        struct e1000_hw *hw = &adapter->hw;
-        /*
+        /* When SoL/IDER sessions are active, autoneg/speed/duplex
-         * When SoL/IDER sessions are active, autoneg/speed/duplex
         * cannot be changed
         */
        if (hw->phy.ops.check_reset_block &&
@@ -273,8 +273,7 @@ static int e1000_set_settings(struct net_device *netdev,
                return -EINVAL;
        }
-        /*
+        /* MDI setting is only allowed when autoneg enabled because
-         * MDI setting is only allowed when autoneg enabled because
         * some hardware doesn't allow MDI setting when speed or
         * duplex is forced.
         */
@@ -316,8 +315,7 @@ static int e1000_set_settings(struct net_device *netdev,
        /* MDI-X => 2; MDI => 1; Auto => 3 */
        if (ecmd->eth_tp_mdix_ctrl) {
-                /*
+                /* fix up the value for auto (3 => 0) as zero is mapped
-                 * fix up the value for auto (3 => 0) as zero is mapped
                 * internally to auto
                 */
                if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
@@ -454,8 +452,8 @@ static void e1000_get_regs(struct net_device *netdev,
        regs_buff[12] = adapter->hw.phy.type;  /* PHY type (IGP=1, M88=0) */
        /* ethtool doesn't use anything past this point, so all this
-         * code is likely legacy junk for apps that may or may not
+         * code is likely legacy junk for apps that may or may not exist
-         * exist */
+         */
        if (hw->phy.type == e1000_phy_m88) {
                e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
                regs_buff[13] = (u32)phy_data; /* cable length */
@@ -598,8 +596,7 @@ static int e1000_set_eeprom(struct net_device *netdev,
        if (ret_val)
                goto out;
-        /*
+        /* Update the checksum over the first part of the EEPROM if needed
-         * Update the checksum over the first part of the EEPROM if needed
         * and flush shadow RAM for applicable controllers
         */
        if ((first_word <= NVM_CHECKSUM_REG) ||
@@ -623,8 +620,7 @@ static void e1000_get_drvinfo(struct net_device *netdev,
        strlcpy(drvinfo->version, e1000e_driver_version,
                sizeof(drvinfo->version));
-        /*
+        /* EEPROM image version # is reported as firmware version # for
-         * EEPROM image version # is reported as firmware version # for
         * PCI-E controllers
         */
        snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
@@ -708,8 +704,7 @@ static int e1000_set_ringparam(struct net_device *netdev,
        e1000e_down(adapter);
-        /*
+        /* We can't just free everything and then setup again, because the
-         * We can't just free everything and then setup again, because the
         * ISRs in MSI-X mode get passed pointers to the Tx and Rx ring
         * structs.  First, attempt to allocate new resources...
         */
@@ -813,8 +808,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
        u32 mask;
        u32 wlock_mac = 0;
-        /*
+        /* The status register is Read Only, so a write should fail.
-         * The status register is Read Only, so a write should fail.
         * Some bits that get toggled are ignored.
         */
        switch (mac->type) {
@@ -996,8 +990,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                }
                if (!shared_int) {
-                        /*
+                        /* Disable the interrupt to be reported in
-                         * Disable the interrupt to be reported in
                         * the cause register and then force the same
                         * interrupt and see if one gets posted.  If
                         * an interrupt was posted to the bus, the
@@ -1015,8 +1008,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                        }
                }
-                /*
+                /* Enable the interrupt to be reported in
-                 * Enable the interrupt to be reported in
                 * the cause register and then force the same
                 * interrupt and see if one gets posted.  If
                 * an interrupt was not posted to the bus, the
@@ -1034,8 +1026,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
                }
                if (!shared_int) {
-                        /*
+                        /* Disable the other interrupts to be reported in
-                         * Disable the other interrupts to be reported in
                         * the cause register and then force the other
                         * interrupts and see if any get posted.  If
                         * an interrupt was posted to the bus, the
@@ -1378,8 +1369,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
            hw->phy.type == e1000_phy_m88) {
                ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
        } else {
-                /*
+                /* Set the ILOS bit on the fiber Nic if half duplex link is
-                 * Set the ILOS bit on the fiber Nic if half duplex link is
                 * detected.
                 */
                if ((er32(STATUS) & E1000_STATUS_FD) == 0)
@@ -1388,8 +1378,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
        ew32(CTRL, ctrl_reg);
-        /*
+        /* Disable the receiver on the PHY so when a cable is plugged in, the
-         * Disable the receiver on the PHY so when a cable is plugged in, the
         * PHY does not begin to autoneg when a cable is reconnected to the NIC.
         */
        if (hw->phy.type == e1000_phy_m88)
@@ -1408,8 +1397,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
        /* special requirements for 82571/82572 fiber adapters */
-        /*
+        /* jump through hoops to make sure link is up because serdes
-         * jump through hoops to make sure link is up because serdes
         * link is hardwired up
         */
        ctrl |= E1000_CTRL_SLU;
@@ -1429,8 +1417,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
                ew32(CTRL, ctrl);
        }
-        /*
+        /* special write to serdes control register to enable SerDes analog
-         * special write to serdes control register to enable SerDes analog
         * loopback
         */
 #define E1000_SERDES_LB_ON 0x410
@@ -1448,8 +1435,7 @@ static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter)
        u32 ctrlext = er32(CTRL_EXT);
        u32 ctrl = er32(CTRL);
-        /*
+        /* save CTRL_EXT to restore later, reuse an empty variable (unused
-         * save CTRL_EXT to restore later, reuse an empty variable (unused
         * on mac_type 80003es2lan)
         */
        adapter->tx_fifo_head = ctrlext;
@@ -1585,8 +1571,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
        ew32(RDT(0), rx_ring->count - 1);
-        /*
+        /* Calculate the loop count based on the largest descriptor ring
-         * Calculate the loop count based on the largest descriptor ring
         * The idea is to wrap the largest ring a number of times using 64
         * send/receive pairs during each loop
         */
@@ -1627,8 +1612,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
                        l++;
                        if (l == rx_ring->count)
                                l = 0;
-                        /*
+                        /* time + 20 msecs (200 msecs on 2.4) is more than
-                         * time + 20 msecs (200 msecs on 2.4) is more than
                         * enough time to complete the receives, if it's
                         * exceeded, break and error off
                         */
@@ -1649,10 +1633,7 @@ static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
 {
        struct e1000_hw *hw = &adapter->hw;
-        /*
+        /* PHY loopback cannot be performed if SoL/IDER sessions are active */
-         * PHY loopback cannot be performed if SoL/IDER
-         * sessions are active
-         */
        if (hw->phy.ops.check_reset_block &&
            hw->phy.ops.check_reset_block(hw)) {
                e_err("Cannot do PHY loopback test when SoL/IDER is active.\n");
@@ -1686,8 +1667,7 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
                int i = 0;
                hw->mac.serdes_has_link = false;
-                /*
+                /* On some blade server designs, link establishment
-                 * On some blade server designs, link establishment
                 * could take as long as 2-3 minutes
                 */
                do {
@@ -1701,8 +1681,7 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
        } else {
                hw->mac.ops.check_for_link(hw);
                if (hw->mac.autoneg)
-                        /*
+                        /* On some Phy/switch combinations, link establishment
-                         * On some Phy/switch combinations, link establishment
                         * can take a few seconds more than expected.
                         */
                        msleep(5000);
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index d37bfd96c987..cf217777586c 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -85,8 +85,7 @@ enum e1e_registers {
        E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
        E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
        E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
-/*
+/* Convenience macros
- * Convenience macros
 *
 * Note: "_n" is the queue number of the register to be written to.
 *
@@ -800,8 +799,7 @@ struct e1000_mac_operations {
        s32  (*read_mac_addr)(struct e1000_hw *);
 };
-/*
+/* When to use various PHY register access functions:
- * When to use various PHY register access functions:
 *
 *                 Func   Caller
 *   Function      Does   Does    When to use
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index e3a7b07df629..976336547607 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -26,8 +26,7 @@
 *******************************************************************************/
-/*
+/* 82562G 10/100 Network Connection
- * 82562G 10/100 Network Connection
 * 82562G-2 10/100 Network Connection
 * 82562GT 10/100 Network Connection
 * 82562GT-2 10/100 Network Connection
@@ -354,8 +353,7 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
                return true;
        }
-        /*
+        /* In case the PHY needs to be in mdio slow mode,
-         * In case the PHY needs to be in mdio slow mode,
         * set slow mode and try to get the PHY id again.
         */
        hw->phy.ops.release(hw);
@@ -386,8 +384,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
                return ret_val;
        }
-        /*
+        /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
-         * The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
         * inaccessible and resetting the PHY is not blocked, toggle the
         * LANPHYPC Value bit to force the interconnect to PCIe mode.
         */
@@ -396,8 +393,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
-                /*
+                /* Before toggling LANPHYPC, see if PHY is accessible by
-                 * Before toggling LANPHYPC, see if PHY is accessible by
                 * forcing MAC to SMBus mode first.
                 */
                mac_reg = er32(CTRL_EXT);
@@ -406,8 +402,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
                /* fall-through */
        case e1000_pch2lan:
-                /*
+                /* Gate automatic PHY configuration by hardware on
-                 * Gate automatic PHY configuration by hardware on
                 * non-managed 82579
                 */
                if ((hw->mac.type == e1000_pch2lan) &&
@@ -474,8 +469,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
        hw->phy.ops.release(hw);
-        /*
+        /* Reset the PHY before any access to it.  Doing so, ensures
-         * Reset the PHY before any access to it.  Doing so, ensures
         * that the PHY is in a known good state before we read/write
         * PHY registers.  The generic reset is sufficient here,
         * because we haven't determined the PHY type yet.
@@ -536,8 +530,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                        /* fall-through */
                case e1000_pch2lan:
                case e1000_pch_lpt:
-                        /*
+                        /* In case the PHY needs to be in mdio slow mode,
-                         * In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
                        ret_val = e1000_set_mdio_slow_mode_hv(hw);
@@ -593,8 +586,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
        phy->ops.power_up               = e1000_power_up_phy_copper;
        phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
-        /*
+        /* We may need to do this twice - once for IGP and if that fails,
-         * We may need to do this twice - once for IGP and if that fails,
         * we'll set BM func pointers and try again
         */
        ret_val = e1000e_determine_phy_address(hw);
@@ -679,8 +671,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
        gfpreg = er32flash(ICH_FLASH_GFPREG);
-        /*
+        /* sector_X_addr is a "sector"-aligned address (4096 bytes)
-         * sector_X_addr is a "sector"-aligned address (4096 bytes)
         * Add 1 to sector_end_addr since this sector is included in
         * the overall size.
         */
@@ -690,8 +681,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
        /* flash_base_addr is byte-aligned */
        nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
-        /*
+        /* find total size of the NVM, then cut in half since the total
-         * find total size of the NVM, then cut in half since the total
         * size represents two separate NVM banks.
         */
        nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
@@ -788,8 +778,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
        if (mac->type == e1000_ich8lan)
                e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
-        /*
+        /* Gate automatic PHY configuration by hardware on managed
-         * Gate automatic PHY configuration by hardware on managed
         * 82579 and i217
         */
        if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) &&
@@ -840,8 +829,7 @@ static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
                        goto release;
                e1e_rphy_locked(hw, I82579_EMI_DATA, &dev_spec->eee_lp_ability);
-                /*
+                /* EEE is not supported in 100Half, so ignore partner's EEE
-                 * EEE is not supported in 100Half, so ignore partner's EEE
                 * in 100 ability if full-duplex is not advertised.
                 */
                e1e_rphy_locked(hw, PHY_LP_ABILITY, &phy_reg);
@@ -869,8 +857,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
        bool link;
        u16 phy_reg;
-        /*
+        /* We only want to go out to the PHY registers to see if Auto-Neg
-         * We only want to go out to the PHY registers to see if Auto-Neg
         * has completed and/or if our link status has changed.  The
         * get_link_status flag is set upon receiving a Link Status
         * Change or Rx Sequence Error interrupt.
@@ -878,8 +865,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
        if (!mac->get_link_status)
                return 0;
-        /*
+        /* First we want to see if the MII Status Register reports
-         * First we want to see if the MII Status Register reports
         * link.  If so, then we want to get the current speed/duplex
         * of the PHY.
         */
@@ -914,8 +900,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                                return ret_val;
                }
-                /*
+                /* Workaround for PCHx parts in half-duplex:
-                 * Workaround for PCHx parts in half-duplex:
                 * Set the number of preambles removed from the packet
                 * when it is passed from the PHY to the MAC to prevent
                 * the MAC from misinterpreting the packet type.
@@ -932,8 +917,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                break;
        }
-        /*
+        /* Check if there was DownShift, must be checked
-         * Check if there was DownShift, must be checked
         * immediately after link-up
         */
        e1000e_check_downshift(hw);
@@ -943,22 +927,19 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* If we are forcing speed/duplex, then we simply return since
-         * If we are forcing speed/duplex, then we simply return since
         * we have already determined whether we have link or not.
         */
        if (!mac->autoneg)
                return -E1000_ERR_CONFIG;
-        /*
+        /* Auto-Neg is enabled.  Auto Speed Detection takes care
-         * Auto-Neg is enabled.  Auto Speed Detection takes care
         * of MAC speed/duplex configuration.  So we only need to
         * configure Collision Distance in the MAC.
         */
        mac->ops.config_collision_dist(hw);
-        /*
+        /* Configure Flow Control now that Auto-Neg has completed.
-         * Configure Flow Control now that Auto-Neg has completed.
         * First, we need to restore the desired flow control
         * settings because we may have had to re-autoneg with a
         * different link partner.
@@ -1000,8 +981,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
        if (rc)
                return rc;
-        /*
+        /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
-         * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
         * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
         */
        if ((adapter->hw.phy.type == e1000_phy_ife) ||
@@ -1191,8 +1171,7 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
 {
        u32 rar_low, rar_high;
-        /*
+        /* HW expects these in little endian so we reverse the byte order
-         * HW expects these in little endian so we reverse the byte order
         * from network order (big endian) to little endian
         */
        rar_low = ((u32)addr[0] |
@@ -1256,8 +1235,7 @@ static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
        u32 rar_low, rar_high;
        u32 wlock_mac;
-        /*
+        /* HW expects these in little endian so we reverse the byte order
-         * HW expects these in little endian so we reverse the byte order
         * from network order (big endian) to little endian
         */
        rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
@@ -1277,8 +1255,7 @@ static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
                return;
        }
-        /*
+        /* The manageability engine (ME) can lock certain SHRAR registers that
-         * The manageability engine (ME) can lock certain SHRAR registers that
         * it is using - those registers are unavailable for use.
         */
        if (index < hw->mac.rar_entry_count) {
@@ -1387,8 +1364,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        s32 ret_val = 0;
        u16 word_addr, reg_data, reg_addr, phy_page = 0;
-        /*
+        /* Initialize the PHY from the NVM on ICH platforms.  This
-         * Initialize the PHY from the NVM on ICH platforms.  This
         * is needed due to an issue where the NVM configuration is
         * not properly autoloaded after power transitions.
         * Therefore, after each PHY reset, we will load the
@@ -1422,8 +1398,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        if (!(data & sw_cfg_mask))
                goto release;
-        /*
+        /* Make sure HW does not configure LCD from PHY
-         * Make sure HW does not configure LCD from PHY
         * extended configuration before SW configuration
         */
        data = er32(EXTCNF_CTRL);
@@ -1443,8 +1418,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        if (((hw->mac.type == e1000_pchlan) &&
             !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
            (hw->mac.type > e1000_pchlan)) {
-                /*
+                /* HW configures the SMBus address and LEDs when the
-                 * HW configures the SMBus address and LEDs when the
                 * OEM and LCD Write Enable bits are set in the NVM.
                 * When both NVM bits are cleared, SW will configure
                 * them instead.
@@ -1748,8 +1722,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
        }
        if (hw->phy.type == e1000_phy_82578) {
-                /*
+                /* Return registers to default by doing a soft reset then
-                 * Return registers to default by doing a soft reset then
                 * writing 0x3140 to the control register.
                 */
                if (hw->phy.revision < 2) {
@@ -1769,8 +1742,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Configure the K1 Si workaround during phy reset assuming there is
-         * Configure the K1 Si workaround during phy reset assuming there is
         * link so that it disables K1 if link is in 1Gbps.
         */
        ret_val = e1000_k1_gig_workaround_hv(hw, true);
@@ -1853,8 +1825,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
                return ret_val;
        if (enable) {
-                /*
+                /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
-                 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
                 * SHRAL/H) and initial CRC values to the MAC
                 */
                for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
@@ -2131,8 +2102,7 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
                udelay(100);
        } while ((!data) && --loop);
-        /*
+        /* If basic configuration is incomplete before the above loop
-         * If basic configuration is incomplete before the above loop
         * count reaches 0, loading the configuration from NVM will
         * leave the PHY in a bad state possibly resulting in no link.
         */
@@ -2299,8 +2269,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
                if (phy->type != e1000_phy_igp_3)
                        return 0;
-                /*
+                /* Call gig speed drop workaround on LPLU before accessing
-                 * Call gig speed drop workaround on LPLU before accessing
                 * any PHY registers
                 */
                if (hw->mac.type == e1000_ich8lan)
@@ -2319,8 +2288,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
                if (phy->type != e1000_phy_igp_3)
                        return 0;
-                /*
+                /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
-                 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
                 * during Dx states where the power conservation is most
                 * important.  During driver activity we should enable
                 * SmartSpeed, so performance is maintained.
@@ -2382,8 +2350,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
                if (phy->type != e1000_phy_igp_3)
                        return 0;
-                /*
+                /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
-                 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
                 * during Dx states where the power conservation is most
                 * important.  During driver activity we should enable
                 * SmartSpeed, so performance is maintained.
@@ -2420,8 +2387,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
                if (phy->type != e1000_phy_igp_3)
                        return 0;
-                /*
+                /* Call gig speed drop workaround on LPLU before accessing
-                 * Call gig speed drop workaround on LPLU before accessing
                 * any PHY registers
                 */
                if (hw->mac.type == e1000_ich8lan)
@@ -2589,8 +2555,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
        ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
-        /*
+        /* Either we should have a hardware SPI cycle in progress
-         * Either we should have a hardware SPI cycle in progress
         * bit to check against, in order to start a new cycle or
         * FDONE bit should be changed in the hardware so that it
         * is 1 after hardware reset, which can then be used as an
@@ -2599,8 +2564,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
         */
        if (!hsfsts.hsf_status.flcinprog) {
-                /*
+                /* There is no cycle running at present,
-                 * There is no cycle running at present,
                 * so we can start a cycle.
                 * Begin by setting Flash Cycle Done.
                 */
@@ -2610,8 +2574,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
        } else {
                s32 i;
-                /*
+                /* Otherwise poll for sometime so the current
-                 * Otherwise poll for sometime so the current
                 * cycle has a chance to end before giving up.
                 */
                for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
@@ -2623,8 +2586,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
                        udelay(1);
                }
                if (!ret_val) {
-                        /*
+                        /* Successful in waiting for previous cycle to timeout,
-                         * Successful in waiting for previous cycle to timeout,
                         * now set the Flash Cycle Done.
                         */
                        hsfsts.hsf_status.flcdone = 1;
@@ -2753,8 +2715,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
                ret_val = e1000_flash_cycle_ich8lan(hw,
                                                ICH_FLASH_READ_COMMAND_TIMEOUT);
-                /*
+                /* Check if FCERR is set to 1, if set to 1, clear it
-                 * Check if FCERR is set to 1, if set to 1, clear it
                 * and try the whole sequence a few more times, else
                 * read in (shift in) the Flash Data0, the order is
                 * least significant byte first msb to lsb
@@ -2767,8 +2728,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
                                *data = (u16)(flash_data & 0x0000FFFF);
                        break;
                } else {
-                        /*
+                        /* If we've gotten here, then things are probably
-                         * If we've gotten here, then things are probably
                         * completely hosed, but if the error condition is
                         * detected, it won't hurt to give it another try...
                         * ICH_FLASH_CYCLE_REPEAT_COUNT times.
@@ -2849,8 +2809,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
        nvm->ops.acquire(hw);
-        /*
+        /* We're writing to the opposite bank so if we're on bank 1,
-         * We're writing to the opposite bank so if we're on bank 1,
         * write to bank 0 etc.  We also need to erase the segment that
         * is going to be written
         */
@@ -2875,8 +2834,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
        }
        for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
-                /*
+                /* Determine whether to write the value stored
-                 * Determine whether to write the value stored
                 * in the other NVM bank or a modified value stored
                 * in the shadow RAM
                 */
@@ -2890,8 +2848,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
                                break;
                }
-                /*
+                /* If the word is 0x13, then make sure the signature bits
-                 * If the word is 0x13, then make sure the signature bits
                 * (15:14) are 11b until the commit has completed.
                 * This will allow us to write 10b which indicates the
                 * signature is valid.  We want to do this after the write
@@ -2920,8 +2877,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
                        break;
        }
-        /*
+        /* Don't bother writing the segment valid bits if sector
-         * Don't bother writing the segment valid bits if sector
         * programming failed.
         */
        if (ret_val) {
@@ -2930,8 +2886,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
                goto release;
        }
-        /*
+        /* Finally validate the new segment by setting bit 15:14
-         * Finally validate the new segment by setting bit 15:14
         * to 10b in word 0x13 , this can be done without an
         * erase as well since these bits are 11 to start with
         * and we need to change bit 14 to 0b
@@ -2948,8 +2903,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
        if (ret_val)
                goto release;
-        /*
+        /* And invalidate the previously valid segment by setting
-         * And invalidate the previously valid segment by setting
         * its signature word (0x13) high_byte to 0b. This can be
         * done without an erase because flash erase sets all bits
         * to 1's. We can write 1's to 0's without an erase
@@ -2968,8 +2922,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
 release:
        nvm->ops.release(hw);
-        /*
+        /* Reload the EEPROM, or else modifications will not appear
-         * Reload the EEPROM, or else modifications will not appear
         * until after the next adapter reset.
         */
        if (!ret_val) {
@@ -2997,8 +2950,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
        s32 ret_val;
        u16 data;
-        /*
+        /* Read 0x19 and check bit 6.  If this bit is 0, the checksum
-         * Read 0x19 and check bit 6.  If this bit is 0, the checksum
         * needs to be fixed.  This bit is an indication that the NVM
         * was prepared by OEM software and did not calculate the
         * checksum...a likely scenario.
@@ -3048,8 +3000,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
        pr0.range.wpe = true;
        ew32flash(ICH_FLASH_PR0, pr0.regval);
-        /*
+        /* Lock down a subset of GbE Flash Control Registers, e.g.
-         * Lock down a subset of GbE Flash Control Registers, e.g.
         * PR0 to prevent the write-protection from being lifted.
         * Once FLOCKDN is set, the registers protected by it cannot
         * be written until FLOCKDN is cleared by a hardware reset.
@@ -3109,8 +3060,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
                ew32flash(ICH_FLASH_FDATA0, flash_data);
-                /*
+                /* check if FCERR is set to 1 , if set to 1, clear it
-                 * check if FCERR is set to 1 , if set to 1, clear it
                 * and try the whole sequence a few more times else done
                 */
                ret_val = e1000_flash_cycle_ich8lan(hw,
@@ -3118,8 +3068,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
                if (!ret_val)
                        break;
-                /*
+                /* If we're here, then things are most likely
-                 * If we're here, then things are most likely
                 * completely hosed, but if the error condition
                 * is detected, it won't hurt to give it another
                 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
@@ -3207,8 +3156,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
        hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
-        /*
+        /* Determine HW Sector size: Read BERASE bits of hw flash status
-         * Determine HW Sector size: Read BERASE bits of hw flash status
         * register
         * 00: The Hw sector is 256 bytes, hence we need to erase 16
         *     consecutive sectors.  The start index for the nth Hw sector
@@ -3253,16 +3201,14 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
                        if (ret_val)
                                return ret_val;
-                        /*
+                        /* Write a value 11 (block Erase) in Flash
-                         * Write a value 11 (block Erase) in Flash
                         * Cycle field in hw flash control
                         */
                        hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
                        hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
                        ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
-                        /*
+                        /* Write the last 24 bits of an index within the
-                         * Write the last 24 bits of an index within the
                         * block into Flash Linear address field in Flash
                         * Address.
                         */
@@ -3274,8 +3220,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
                        if (!ret_val)
                                break;
-                        /*
+                        /* Check if FCERR is set to 1.  If 1,
-                         * Check if FCERR is set to 1.  If 1,
                         * clear it and try the whole sequence
                         * a few more times else Done
                         */
@@ -3403,8 +3348,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
        ret_val = e1000e_get_bus_info_pcie(hw);
-        /*
+        /* ICH devices are "PCI Express"-ish.  They have
-         * ICH devices are "PCI Express"-ish.  They have
         * a configuration space, but do not contain
         * PCI Express Capability registers, so bus width
         * must be hardcoded.
@@ -3429,8 +3373,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
        u32 ctrl, reg;
        s32 ret_val;
-        /*
+        /* Prevent the PCI-E bus from sticking if there is no TLP connection
-         * Prevent the PCI-E bus from sticking if there is no TLP connection
         * on the last TLP read/write transaction when MAC is reset.
         */
        ret_val = e1000e_disable_pcie_master(hw);
@@ -3440,8 +3383,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
        e_dbg("Masking off all interrupts\n");
        ew32(IMC, 0xffffffff);
-        /*
+        /* Disable the Transmit and Receive units.  Then delay to allow
-         * Disable the Transmit and Receive units.  Then delay to allow
         * any pending transactions to complete before we hit the MAC
         * with the global reset.
         */
@@ -3474,15 +3416,13 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
        ctrl = er32(CTRL);
        if (!hw->phy.ops.check_reset_block(hw)) {
-                /*
+                /* Full-chip reset requires MAC and PHY reset at the same
-                 * Full-chip reset requires MAC and PHY reset at the same
                 * time to make sure the interface between MAC and the
                 * external PHY is reset.
                 */
                ctrl |= E1000_CTRL_PHY_RST;
-                /*
+                /* Gate automatic PHY configuration by hardware on
-                 * Gate automatic PHY configuration by hardware on
                 * non-managed 82579
                 */
                if ((hw->mac.type == e1000_pch2lan) &&
@@ -3516,8 +3456,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                        return ret_val;
        }
-        /*
+        /* For PCH, this write will make sure that any noise
-         * For PCH, this write will make sure that any noise
         * will be detected as a CRC error and be dropped rather than show up
         * as a bad packet to the DMA engine.
         */
@@ -3569,8 +3508,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
        for (i = 0; i < mac->mta_reg_count; i++)
                E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
-        /*
+        /* The 82578 Rx buffer will stall if wakeup is enabled in host and
-         * The 82578 Rx buffer will stall if wakeup is enabled in host and
         * the ME.  Disable wakeup by clearing the host wakeup bit.
         * Reset the phy after disabling host wakeup to reset the Rx buffer.
         */
@@ -3600,8 +3538,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
                 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
        ew32(TXDCTL(1), txdctl);
-        /*
+        /* ICH8 has opposite polarity of no_snoop bits.
-         * ICH8 has opposite polarity of no_snoop bits.
         * By default, we should use snoop behavior.
         */
        if (mac->type == e1000_ich8lan)
@@ -3614,8 +3551,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
        ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
        ew32(CTRL_EXT, ctrl_ext);
-        /*
+        /* Clear all of the statistics registers (clear on read).  It is
-         * Clear all of the statistics registers (clear on read).  It is
         * important that we do this after we have tried to establish link
         * because the symbol error count will increment wildly if there
         * is no link.
@@ -3676,15 +3612,13 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
                ew32(STATUS, reg);
        }
-        /*
+        /* work-around descriptor data corruption issue during nfs v2 udp
-         * work-around descriptor data corruption issue during nfs v2 udp
         * traffic, just disable the nfs filtering capability
         */
        reg = er32(RFCTL);
        reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
-        /*
+        /* Disable IPv6 extension header parsing because some malformed
-         * Disable IPv6 extension header parsing because some malformed
         * IPv6 headers can hang the Rx.
         */
        if (hw->mac.type == e1000_ich8lan)
@@ -3709,8 +3643,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
        if (hw->phy.ops.check_reset_block(hw))
                return 0;
-        /*
+        /* ICH parts do not have a word in the NVM to determine
-         * ICH parts do not have a word in the NVM to determine
         * the default flow control setting, so we explicitly
         * set it to full.
         */
@@ -3722,8 +3655,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
                        hw->fc.requested_mode = e1000_fc_full;
        }
-        /*
+        /* Save off the requested flow control mode for use later.  Depending
-         * Save off the requested flow control mode for use later.  Depending
         * on the link partner's capabilities, we may or may not use this mode.
         */
        hw->fc.current_mode = hw->fc.requested_mode;
@@ -3771,8 +3703,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
        ew32(CTRL, ctrl);
-        /*
+        /* Set the mac to wait the maximum time between each iteration
-         * Set the mac to wait the maximum time between each iteration
         * and increase the max iterations when polling the phy;
         * this fixes erroneous timeouts at 10Mbps.
         */
@@ -3892,8 +3823,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
        if (!dev_spec->kmrn_lock_loss_workaround_enabled)
                return 0;
-        /*
+        /* Make sure link is up before proceeding.  If not just return.
-         * Make sure link is up before proceeding.  If not just return.
         * Attempting this while link is negotiating fouled up link
         * stability
         */
@@ -3925,8 +3855,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
        ew32(PHY_CTRL, phy_ctrl);
-        /*
+        /* Call gig speed drop workaround on Gig disable before accessing
-         * Call gig speed drop workaround on Gig disable before accessing
         * any PHY registers
         */
        e1000e_gig_downshift_workaround_ich8lan(hw);
@@ -3983,8 +3912,7 @@ void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
                        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
                ew32(PHY_CTRL, reg);
-                /*
+                /* Call gig speed drop workaround on Gig disable before
-                 * Call gig speed drop workaround on Gig disable before
                 * accessing any PHY registers
                 */
                if (hw->mac.type == e1000_ich8lan)
@@ -4078,8 +4006,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
                                goto release;
                        e1e_rphy_locked(hw, I82579_EMI_DATA, &eee_advert);
-                        /*
+                        /* Disable LPLU if both link partners support 100BaseT
-                         * Disable LPLU if both link partners support 100BaseT
                         * EEE and 100Full is advertised on both ends of the
                         * link.
                         */
@@ -4091,8 +4018,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
                                              E1000_PHY_CTRL_NOND0A_LPLU);
                }
-                /*
+                /* For i217 Intel Rapid Start Technology support,
-                 * For i217 Intel Rapid Start Technology support,
                 * when the system is going into Sx and no manageability engine
                 * is present, the driver must configure proxy to reset only on
                 * power good.  LPI (Low Power Idle) state must also reset only
@@ -4106,8 +4032,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
                        phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
                        e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
-                        /*
+                        /* Set bit enable LPI (EEE) to reset only on
-                         * Set bit enable LPI (EEE) to reset only on
                         * power good.
                         */
                        e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
@@ -4120,8 +4045,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
                        e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
                }
-                /*
+                /* Enable MTA to reset for Intel Rapid Start Technology
-                 * Enable MTA to reset for Intel Rapid Start Technology
                 * Support
                 */
                e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
@@ -4175,8 +4099,7 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
                return;
        }
-        /*
+        /* For i217 Intel Rapid Start Technology support when the system
-         * For i217 Intel Rapid Start Technology support when the system
         * is transitioning from Sx and no manageability engine is present
         * configure SMBus to restore on reset, disable proxy, and enable
         * the reset on MTA (Multicast table array).
@@ -4191,8 +4114,7 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
                }
                if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
-                        /*
+                        /* Restore clear on SMB if no manageability engine
-                         * Restore clear on SMB if no manageability engine
                         * is present
                         */
                        ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
@@ -4298,8 +4220,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
        u16 data = (u16)hw->mac.ledctl_mode2;
        u32 i, led;
-        /*
+        /* If no link, then turn LED on by setting the invert bit
-         * If no link, then turn LED on by setting the invert bit
         * for each LED that's mode is "link_up" in ledctl_mode2.
         */
        if (!(er32(STATUS) & E1000_STATUS_LU)) {
@@ -4329,8 +4250,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
        u16 data = (u16)hw->mac.ledctl_mode1;
        u32 i, led;
-        /*
+        /* If no link, then turn LED off by clearing the invert bit
-         * If no link, then turn LED off by clearing the invert bit
         * for each LED that's mode is "link_up" in ledctl_mode1.
         */
        if (!(er32(STATUS) & E1000_STATUS_LU)) {
@@ -4375,8 +4295,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
        } else {
                ret_val = e1000e_get_auto_rd_done(hw);
                if (ret_val) {
-                        /*
+                        /* When auto config read does not complete, do not
-                         * When auto config read does not complete, do not
                         * return with an error. This can happen in situations
                         * where there is no eeprom and prevents getting link.
                         */
diff --git a/drivers/net/ethernet/intel/e1000e/mac.c b/drivers/net/ethernet/intel/e1000e/mac.c
index a13439928488..54d9dafaf126 100644
--- a/drivers/net/ethernet/intel/e1000e/mac.c
+++ b/drivers/net/ethernet/intel/e1000e/mac.c
@@ -73,8 +73,7 @@ void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
        struct e1000_bus_info *bus = &hw->bus;
        u32 reg;
-        /*
+        /* The status register reports the correct function number
-         * The status register reports the correct function number
         * for the device regardless of function swap state.
         */
        reg = er32(STATUS);
@@ -210,8 +209,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
                return 0;
        }
-        /*
+        /* We have a valid alternate MAC address, and we want to treat it the
-         * We have a valid alternate MAC address, and we want to treat it the
         * same as the normal permanent MAC address stored by the HW into the
         * RAR. Do this by mapping this address into RAR0.
         */
@@ -233,8 +231,7 @@ void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
 {
        u32 rar_low, rar_high;
-        /*
+        /* HW expects these in little endian so we reverse the byte order
-         * HW expects these in little endian so we reverse the byte order
         * from network order (big endian) to little endian
         */
        rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
@@ -246,8 +243,7 @@ void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
        if (rar_low || rar_high)
                rar_high |= E1000_RAH_AV;
-        /*
+        /* Some bridges will combine consecutive 32-bit writes into
-         * Some bridges will combine consecutive 32-bit writes into
         * a single burst write, which will malfunction on some parts.
         * The flushes avoid this.
         */
@@ -273,15 +269,13 @@ static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
        /* Register count multiplied by bits per register */
        hash_mask = (hw->mac.mta_reg_count * 32) - 1;
-        /*
+        /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
-         * For a mc_filter_type of 0, bit_shift is the number of left-shifts
         * where 0xFF would still fall within the hash mask.
         */
        while (hash_mask >> bit_shift != 0xFF)
                bit_shift++;
-        /*
+        /* The portion of the address that is used for the hash table
-         * The portion of the address that is used for the hash table
         * is determined by the mc_filter_type setting.
         * The algorithm is such that there is a total of 8 bits of shifting.
         * The bit_shift for a mc_filter_type of 0 represents the number of
@@ -423,8 +417,7 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
        s32 ret_val;
        bool link;
-        /*
+        /* We only want to go out to the PHY registers to see if Auto-Neg
-         * We only want to go out to the PHY registers to see if Auto-Neg
         * has completed and/or if our link status has changed.  The
         * get_link_status flag is set upon receiving a Link Status
         * Change or Rx Sequence Error interrupt.
@@ -432,8 +425,7 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
        if (!mac->get_link_status)
                return 0;
-        /*
+        /* First we want to see if the MII Status Register reports
-         * First we want to see if the MII Status Register reports
         * link.  If so, then we want to get the current speed/duplex
         * of the PHY.
         */
@@ -446,28 +438,24 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
        mac->get_link_status = false;
-        /*
+        /* Check if there was DownShift, must be checked
-         * Check if there was DownShift, must be checked
         * immediately after link-up
         */
        e1000e_check_downshift(hw);
-        /*
+        /* If we are forcing speed/duplex, then we simply return since
-         * If we are forcing speed/duplex, then we simply return since
         * we have already determined whether we have link or not.
         */
        if (!mac->autoneg)
                return -E1000_ERR_CONFIG;
-        /*
+        /* Auto-Neg is enabled.  Auto Speed Detection takes care
-         * Auto-Neg is enabled.  Auto Speed Detection takes care
         * of MAC speed/duplex configuration.  So we only need to
         * configure Collision Distance in the MAC.
         */
        mac->ops.config_collision_dist(hw);
-        /*
+        /* Configure Flow Control now that Auto-Neg has completed.
-         * Configure Flow Control now that Auto-Neg has completed.
         * First, we need to restore the desired flow control
         * settings because we may have had to re-autoneg with a
         * different link partner.
@@ -498,8 +486,7 @@ s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
        status = er32(STATUS);
        rxcw = er32(RXCW);
-        /*
+        /* If we don't have link (auto-negotiation failed or link partner
-         * If we don't have link (auto-negotiation failed or link partner
         * cannot auto-negotiate), the cable is plugged in (we have signal),
         * and our link partner is not trying to auto-negotiate with us (we
         * are receiving idles or data), we need to force link up. We also
@@ -530,8 +517,7 @@ s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
                        return ret_val;
                }
        } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
-                /*
+                /* If we are forcing link and we are receiving /C/ ordered
-                 * If we are forcing link and we are receiving /C/ ordered
                 * sets, re-enable auto-negotiation in the TXCW register
                 * and disable forced link in the Device Control register
                 * in an attempt to auto-negotiate with our link partner.
@@ -565,8 +551,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
        status = er32(STATUS);
        rxcw = er32(RXCW);
-        /*
+        /* If we don't have link (auto-negotiation failed or link partner
-         * If we don't have link (auto-negotiation failed or link partner
         * cannot auto-negotiate), and our link partner is not trying to
         * auto-negotiate with us (we are receiving idles or data),
         * we need to force link up. We also need to give auto-negotiation
@@ -595,8 +580,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
                        return ret_val;
                }
        } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
-                /*
+                /* If we are forcing link and we are receiving /C/ ordered
-                 * If we are forcing link and we are receiving /C/ ordered
                 * sets, re-enable auto-negotiation in the TXCW register
                 * and disable forced link in the Device Control register
                 * in an attempt to auto-negotiate with our link partner.
@@ -607,8 +591,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
                mac->serdes_has_link = true;
        } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
-                /*
+                /* If we force link for non-auto-negotiation switch, check
-                 * If we force link for non-auto-negotiation switch, check
                 * link status based on MAC synchronization for internal
                 * serdes media type.
                 */
@@ -665,8 +648,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
        s32 ret_val;
        u16 nvm_data;
-        /*
+        /* Read and store word 0x0F of the EEPROM. This word contains bits
-         * Read and store word 0x0F of the EEPROM. This word contains bits
         * that determine the hardware's default PAUSE (flow control) mode,
         * a bit that determines whether the HW defaults to enabling or
         * disabling auto-negotiation, and the direction of the
@@ -705,15 +687,13 @@ s32 e1000e_setup_link_generic(struct e1000_hw *hw)
 {
        s32 ret_val;
-        /*
+        /* In the case of the phy reset being blocked, we already have a link.
-         * In the case of the phy reset being blocked, we already have a link.
         * We do not need to set it up again.
         */
        if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
                return 0;
-        /*
+        /* If requested flow control is set to default, set flow control
-         * If requested flow control is set to default, set flow control
         * based on the EEPROM flow control settings.
         */
        if (hw->fc.requested_mode == e1000_fc_default) {
@@ -722,8 +702,7 @@ s32 e1000e_setup_link_generic(struct e1000_hw *hw)
                        return ret_val;
        }
-        /*
+        /* Save off the requested flow control mode for use later.  Depending
-         * Save off the requested flow control mode for use later.  Depending
         * on the link partner's capabilities, we may or may not use this mode.
         */
        hw->fc.current_mode = hw->fc.requested_mode;
@@ -735,8 +714,7 @@ s32 e1000e_setup_link_generic(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Initialize the flow control address, type, and PAUSE timer
-         * Initialize the flow control address, type, and PAUSE timer
         * registers to their default values.  This is done even if flow
         * control is disabled, because it does not hurt anything to
         * initialize these registers.
@@ -763,8 +741,7 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
        struct e1000_mac_info *mac = &hw->mac;
        u32 txcw;
-        /*
+        /* Check for a software override of the flow control settings, and
-         * Check for a software override of the flow control settings, and
         * setup the device accordingly.  If auto-negotiation is enabled, then
         * software will have to set the "PAUSE" bits to the correct value in
         * the Transmit Config Word Register (TXCW) and re-start auto-
@@ -786,8 +763,7 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
                break;
        case e1000_fc_rx_pause:
-                /*
+                /* Rx Flow control is enabled and Tx Flow control is disabled
-                 * Rx Flow control is enabled and Tx Flow control is disabled
                 * by a software over-ride. Since there really isn't a way to
                 * advertise that we are capable of Rx Pause ONLY, we will
                 * advertise that we support both symmetric and asymmetric Rx
@@ -797,15 +773,13 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
                break;
        case e1000_fc_tx_pause:
-                /*
+                /* Tx Flow control is enabled, and Rx Flow control is disabled,
-                 * Tx Flow control is enabled, and Rx Flow control is disabled,
                 * by a software over-ride.
                 */
                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
                break;
        case e1000_fc_full:
-                /*
+                /* Flow control (both Rx and Tx) is enabled by a software
-                 * Flow control (both Rx and Tx) is enabled by a software
                 * over-ride.
                 */
                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
@@ -835,8 +809,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
        u32 i, status;
        s32 ret_val;
-        /*
+        /* If we have a signal (the cable is plugged in, or assumed true for
-         * If we have a signal (the cable is plugged in, or assumed true for
         * serdes media) then poll for a "Link-Up" indication in the Device
         * Status Register.  Time-out if a link isn't seen in 500 milliseconds
         * seconds (Auto-negotiation should complete in less than 500
@@ -851,8 +824,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
        if (i == FIBER_LINK_UP_LIMIT) {
                e_dbg("Never got a valid link from auto-neg!!!\n");
                mac->autoneg_failed = true;
-                /*
+                /* AutoNeg failed to achieve a link, so we'll call
-                 * AutoNeg failed to achieve a link, so we'll call
                 * mac->check_for_link. This routine will force the
                 * link up if we detect a signal. This will allow us to
                 * communicate with non-autonegotiating link partners.
@@ -894,8 +866,7 @@ s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Since auto-negotiation is enabled, take the link out of reset (the
-         * Since auto-negotiation is enabled, take the link out of reset (the
         * link will be in reset, because we previously reset the chip). This
         * will restart auto-negotiation.  If auto-negotiation is successful
         * then the link-up status bit will be set and the flow control enable
@@ -907,8 +878,7 @@ s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
        e1e_flush();
        usleep_range(1000, 2000);
-        /*
+        /* For these adapters, the SW definable pin 1 is set when the optics
-         * For these adapters, the SW definable pin 1 is set when the optics
         * detect a signal.  If we have a signal, then poll for a "Link-Up"
         * indication.
         */
@@ -954,16 +924,14 @@ s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
 {
        u32 fcrtl = 0, fcrth = 0;
-        /*
+        /* Set the flow control receive threshold registers.  Normally,
-         * Set the flow control receive threshold registers.  Normally,
         * these registers will be set to a default threshold that may be
         * adjusted later by the driver's runtime code.  However, if the
         * ability to transmit pause frames is not enabled, then these
         * registers will be set to 0.
         */
        if (hw->fc.current_mode & e1000_fc_tx_pause) {
-                /*
+                /* We need to set up the Receive Threshold high and low water
-                 * We need to set up the Receive Threshold high and low water
                 * marks as well as (optionally) enabling the transmission of
                 * XON frames.
                 */
@@ -995,8 +963,7 @@ s32 e1000e_force_mac_fc(struct e1000_hw *hw)
        ctrl = er32(CTRL);
-        /*
+        /* Because we didn't get link via the internal auto-negotiation
-         * Because we didn't get link via the internal auto-negotiation
         * mechanism (we either forced link or we got link via PHY
         * auto-neg), we have to manually enable/disable transmit an
         * receive flow control.
@@ -1057,8 +1024,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
        u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
        u16 speed, duplex;
-        /*
+        /* Check for the case where we have fiber media and auto-neg failed
-         * Check for the case where we have fiber media and auto-neg failed
         * so we had to force link.  In this case, we need to force the
         * configuration of the MAC to match the "fc" parameter.
         */
@@ -1076,15 +1042,13 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                return ret_val;
        }
-        /*
+        /* Check for the case where we have copper media and auto-neg is
-         * Check for the case where we have copper media and auto-neg is
         * enabled.  In this case, we need to check and see if Auto-Neg
         * has completed, and if so, how the PHY and link partner has
         * flow control configured.
         */
        if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
-                /*
+                /* Read the MII Status Register and check to see if AutoNeg
-                 * Read the MII Status Register and check to see if AutoNeg
                 * has completed.  We read this twice because this reg has
                 * some "sticky" (latched) bits.
                 */
@@ -1100,8 +1064,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                        return ret_val;
                }
-                /*
+                /* The AutoNeg process has completed, so we now need to
-                 * The AutoNeg process has completed, so we now need to
                 * read both the Auto Negotiation Advertisement
                 * Register (Address 4) and the Auto_Negotiation Base
                 * Page Ability Register (Address 5) to determine how
@@ -1115,8 +1078,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                if (ret_val)
                        return ret_val;
-                /*
+                /* Two bits in the Auto Negotiation Advertisement Register
-                 * Two bits in the Auto Negotiation Advertisement Register
                 * (Address 4) and two bits in the Auto Negotiation Base
                 * Page Ability Register (Address 5) determine flow control
                 * for both the PHY and the link partner.  The following
@@ -1151,8 +1113,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                 */
                if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
-                        /*
+                        /* Now we need to check if the user selected Rx ONLY
-                         * Now we need to check if the user selected Rx ONLY
                         * of pause frames.  In this case, we had to advertise
                         * FULL flow control because we could not advertise Rx
                         * ONLY. Hence, we must now check to see if we need to
@@ -1166,8 +1127,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                                e_dbg("Flow Control = Rx PAUSE frames only.\n");
                        }
                }
-                /*
+                /* For receiving PAUSE frames ONLY.
-                 * For receiving PAUSE frames ONLY.
                 *
                 *   LOCAL DEVICE  |   LINK PARTNER
                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
@@ -1181,8 +1141,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                        hw->fc.current_mode = e1000_fc_tx_pause;
                        e_dbg("Flow Control = Tx PAUSE frames only.\n");
                }
-                /*
+                /* For transmitting PAUSE frames ONLY.
-                 * For transmitting PAUSE frames ONLY.
                 *
                 *   LOCAL DEVICE  |   LINK PARTNER
                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
@@ -1196,16 +1155,14 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                        hw->fc.current_mode = e1000_fc_rx_pause;
                        e_dbg("Flow Control = Rx PAUSE frames only.\n");
                } else {
-                        /*
+                        /* Per the IEEE spec, at this point flow control
-                         * Per the IEEE spec, at this point flow control
                         * should be disabled.
                         */
                        hw->fc.current_mode = e1000_fc_none;
                        e_dbg("Flow Control = NONE.\n");
                }
-                /*
+                /* Now we need to do one last check...  If we auto-
-                 * Now we need to do one last check...  If we auto-
                 * negotiated to HALF DUPLEX, flow control should not be
                 * enabled per IEEE 802.3 spec.
                 */
@@ -1218,8 +1175,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                if (duplex == HALF_DUPLEX)
                        hw->fc.current_mode = e1000_fc_none;
-                /*
+                /* Now we call a subroutine to actually force the MAC
-                 * Now we call a subroutine to actually force the MAC
                 * controller to use the correct flow control settings.
                 */
                ret_val = e1000e_force_mac_fc(hw);
@@ -1520,8 +1476,7 @@ s32 e1000e_blink_led_generic(struct e1000_hw *hw)
                ledctl_blink = E1000_LEDCTL_LED0_BLINK |
                    (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
        } else {
-                /*
+                /* set the blink bit for each LED that's "on" (0x0E)
-                 * set the blink bit for each LED that's "on" (0x0E)
                 * in ledctl_mode2
                 */
                ledctl_blink = hw->mac.ledctl_mode2;
diff --git a/drivers/net/ethernet/intel/e1000e/manage.c b/drivers/net/ethernet/intel/e1000e/manage.c
index bacc950fc684..6dc47beb3adc 100644
--- a/drivers/net/ethernet/intel/e1000e/manage.c
+++ b/drivers/net/ethernet/intel/e1000e/manage.c
@@ -143,8 +143,7 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
                return hw->mac.tx_pkt_filtering;
        }
-        /*
+        /* If we can't read from the host interface for whatever
-         * If we can't read from the host interface for whatever
         * reason, disable filtering.
         */
        ret_val = e1000_mng_enable_host_if(hw);
@@ -163,8 +162,7 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
        hdr->checksum = 0;
        csum = e1000_calculate_checksum((u8 *)hdr,
                                        E1000_MNG_DHCP_COOKIE_LENGTH);
-        /*
+        /* If either the checksums or signature don't match, then
-         * If either the checksums or signature don't match, then
         * the cookie area isn't considered valid, in which case we
         * take the safe route of assuming Tx filtering is enabled.
         */
@@ -252,8 +250,7 @@ static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
        /* Calculate length in DWORDs */
        length >>= 2;
-        /*
+        /* The device driver writes the relevant command block into the
-         * The device driver writes the relevant command block into the
         * ram area.
         */
        for (i = 0; i < length; i++) {
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index dadb13be479a..6d06ed4e34b1 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -146,9 +146,11 @@ static const struct e1000_reg_info e1000_reg_info_tbl[] = {
        {0, NULL}
 };
-/*
+/**
 * e1000_regdump - register printout routine
- */
+ * @hw: pointer to the HW structure
+ * @reginfo: pointer to the register info table
+ **/
 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
 {
        int n = 0;
@@ -196,9 +198,10 @@ static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
        }
 }
-/*
+/**
 * e1000e_dump - Print registers, Tx-ring and Rx-ring
- */
+ * @adapter: board private structure
+ **/
 static void e1000e_dump(struct e1000_adapter *adapter)
 {
        struct net_device *netdev = adapter->netdev;
@@ -623,8 +626,7 @@ map_skb:
                rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
                if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
-                        /*
+                        /* Force memory writes to complete before letting h/w
-                         * Force memory writes to complete before letting h/w
                         * know there are new descriptors to fetch.  (Only
                         * applicable for weak-ordered memory model archs,
                         * such as IA-64).
@@ -692,8 +694,7 @@ static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
                                        goto no_buffers;
                                }
                        }
-                        /*
+                        /* Refresh the desc even if buffer_addrs
-                         * Refresh the desc even if buffer_addrs
                         * didn't change because each write-back
                         * erases this info.
                         */
@@ -726,8 +727,7 @@ static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
                rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
                if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
-                        /*
+                        /* Force memory writes to complete before letting h/w
-                         * Force memory writes to complete before letting h/w
                         * know there are new descriptors to fetch.  (Only
                         * applicable for weak-ordered memory model archs,
                         * such as IA-64).
@@ -817,7 +817,8 @@ check_page:
                /* Force memory writes to complete before letting h/w
                 * know there are new descriptors to fetch.  (Only
                 * applicable for weak-ordered memory model archs,
-                 * such as IA-64). */
+                 * such as IA-64).
+                 */
                wmb();
                if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
                        e1000e_update_rdt_wa(rx_ring, i);
@@ -891,8 +892,7 @@ static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
                length = le16_to_cpu(rx_desc->wb.upper.length);
-                /*
+                /* !EOP means multiple descriptors were used to store a single
-                 * !EOP means multiple descriptors were used to store a single
                 * packet, if that's the case we need to toss it.  In fact, we
                 * need to toss every packet with the EOP bit clear and the
                 * next frame that _does_ have the EOP bit set, as it is by
@@ -933,8 +933,7 @@ static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
                total_rx_bytes += length;
                total_rx_packets++;
-                /*
+                /* code added for copybreak, this should improve
-                 * code added for copybreak, this should improve
                 * performance for small packets with large amounts
                 * of reassembly being done in the stack
                 */
@@ -1032,15 +1031,13 @@ static void e1000_print_hw_hang(struct work_struct *work)
        if (!adapter->tx_hang_recheck &&
            (adapter->flags2 & FLAG2_DMA_BURST)) {
-                /*
+                /* May be block on write-back, flush and detect again
-                 * May be block on write-back, flush and detect again
                 * flush pending descriptor writebacks to memory
                 */
                ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
                /* execute the writes immediately */
                e1e_flush();
-                /*
+                /* Due to rare timing issues, write to TIDV again to ensure
-                 * Due to rare timing issues, write to TIDV again to ensure
                 * the write is successful
                 */
                ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
@@ -1169,8 +1166,7 @@ static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
        }
        if (adapter->detect_tx_hung) {
-                /*
+                /* Detect a transmit hang in hardware, this serializes the
-                 * Detect a transmit hang in hardware, this serializes the
                 * check with the clearing of time_stamp and movement of i
                 */
                adapter->detect_tx_hung = false;
@@ -1270,14 +1266,12 @@ static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
                skb_put(skb, length);
                {
-                        /*
+                        /* this looks ugly, but it seems compiler issues make
-                         * this looks ugly, but it seems compiler issues make
                         * it more efficient than reusing j
                         */
                        int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
-                        /*
+                        /* page alloc/put takes too long and effects small
-                         * page alloc/put takes too long and effects small
                         * packet throughput, so unsplit small packets and
                         * save the alloc/put only valid in softirq (napi)
                         * context to call kmap_*
@@ -1288,8 +1282,7 @@ static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
                                ps_page = &buffer_info->ps_pages[0];
-                                /*
+                                /* there is no documentation about how to call
-                                 * there is no documentation about how to call
                                 * kmap_atomic, so we can't hold the mapping
                                 * very long
                                 */
@@ -1486,14 +1479,16 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
                                    skb_shinfo(rxtop)->nr_frags,
                                    buffer_info->page, 0, length);
                                /* re-use the current skb, we only consumed the
-                                 * page */
+                                 * page
+                                 */
                                buffer_info->skb = skb;
                                skb = rxtop;
                                rxtop = NULL;
                                e1000_consume_page(buffer_info, skb, length);
                        } else {
                                /* no chain, got EOP, this buf is the packet
-                                 * copybreak to save the put_page/alloc_page */
+                                 * copybreak to save the put_page/alloc_page
+                                 */
                                if (length <= copybreak &&
                                    skb_tailroom(skb) >= length) {
                                        u8 *vaddr;
@@ -1502,7 +1497,8 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
                                               length);
                                        kunmap_atomic(vaddr);
                                        /* re-use the page, so don't erase
-                                         * buffer_info->page */
+                                         * buffer_info->page
+                                         */
                                        skb_put(skb, length);
                                } else {
                                        skb_fill_page_desc(skb, 0,
@@ -1656,22 +1652,17 @@ static irqreturn_t e1000_intr_msi(int irq, void *data)
        struct e1000_hw *hw = &adapter->hw;
        u32 icr = er32(ICR);
-        /*
+        /* read ICR disables interrupts using IAM */
-         * read ICR disables interrupts using IAM
-         */
        if (icr & E1000_ICR_LSC) {
                hw->mac.get_link_status = true;
-                /*
+                /* ICH8 workaround-- Call gig speed drop workaround on cable
-                 * ICH8 workaround-- Call gig speed drop workaround on cable
                 * disconnect (LSC) before accessing any PHY registers
                 */
                if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
                    (!(er32(STATUS) & E1000_STATUS_LU)))
                        schedule_work(&adapter->downshift_task);
-                /*
+                /* 80003ES2LAN workaround-- For packet buffer work-around on
-                 * 80003ES2LAN workaround-- For packet buffer work-around on
                 * link down event; disable receives here in the ISR and reset
                 * adapter in watchdog
                 */
@@ -1713,31 +1704,27 @@ static irqreturn_t e1000_intr(int irq, void *data)
        if (!icr || test_bit(__E1000_DOWN, &adapter->state))
                return IRQ_NONE;  /* Not our interrupt */
-        /*
+        /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
-         * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
         * not set, then the adapter didn't send an interrupt
         */
        if (!(icr & E1000_ICR_INT_ASSERTED))
                return IRQ_NONE;
-        /*
+        /* Interrupt Auto-Mask...upon reading ICR,
-         * Interrupt Auto-Mask...upon reading ICR,
         * interrupts are masked.  No need for the
         * IMC write
         */
        if (icr & E1000_ICR_LSC) {
                hw->mac.get_link_status = true;
-                /*
+                /* ICH8 workaround-- Call gig speed drop workaround on cable
-                 * ICH8 workaround-- Call gig speed drop workaround on cable
                 * disconnect (LSC) before accessing any PHY registers
                 */
                if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
                    (!(er32(STATUS) & E1000_STATUS_LU)))
                        schedule_work(&adapter->downshift_task);
-                /*
+                /* 80003ES2LAN workaround--
-                 * 80003ES2LAN workaround--
                 * For packet buffer work-around on link down event;
                 * disable receives here in the ISR and
                 * reset adapter in watchdog
@@ -2469,8 +2456,7 @@ static void e1000_set_itr(struct e1000_adapter *adapter)
 set_itr_now:
        if (new_itr != adapter->itr) {
-                /*
+                /* this attempts to bias the interrupt rate towards Bulk
-                 * this attempts to bias the interrupt rate towards Bulk
                 * by adding intermediate steps when interrupt rate is
                 * increasing
                 */
@@ -2740,8 +2726,7 @@ static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
        manc = er32(MANC);
-        /*
+        /* enable receiving management packets to the host. this will probably
-         * enable receiving management packets to the host. this will probably
         * generate destination unreachable messages from the host OS, but
         * the packets will be handled on SMBUS
         */
@@ -2754,8 +2739,7 @@ static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
                break;
        case e1000_82574:
        case e1000_82583:
-                /*
+                /* Check if IPMI pass-through decision filter already exists;
-                 * Check if IPMI pass-through decision filter already exists;
                 * if so, enable it.
                 */
                for (i = 0, j = 0; i < 8; i++) {
@@ -2827,8 +2811,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
                u32 txdctl = er32(TXDCTL(0));
                txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
                            E1000_TXDCTL_WTHRESH);
-                /*
+                /* set up some performance related parameters to encourage the
-                 * set up some performance related parameters to encourage the
                 * hardware to use the bus more efficiently in bursts, depends
                 * on the tx_int_delay to be enabled,
                 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
@@ -2845,8 +2828,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
        if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
                tarc = er32(TARC(0));
-                /*
+                /* set the speed mode bit, we'll clear it if we're not at
-                 * set the speed mode bit, we'll clear it if we're not at
                 * gigabit link later
                 */
 #define SPEED_MODE_BIT (1 << 21)
@@ -2967,8 +2949,7 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
        rfctl |= E1000_RFCTL_EXTEN;
        ew32(RFCTL, rfctl);
-        /*
+        /* 82571 and greater support packet-split where the protocol
-         * 82571 and greater support packet-split where the protocol
         * header is placed in skb->data and the packet data is
         * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
         * In the case of a non-split, skb->data is linearly filled,
@@ -3016,7 +2997,8 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
        /* This is useful for sniffing bad packets. */
        if (adapter->netdev->features & NETIF_F_RXALL) {
                /* UPE and MPE will be handled by normal PROMISC logic
-                 * in e1000e_set_rx_mode */
+                 * in e1000e_set_rx_mode
+                 */
                rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
                         E1000_RCTL_BAM | /* RX All Bcast Pkts */
                         E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
@@ -3071,8 +3053,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
        usleep_range(10000, 20000);
        if (adapter->flags2 & FLAG2_DMA_BURST) {
-                /*
+                /* set the writeback threshold (only takes effect if the RDTR
-                 * set the writeback threshold (only takes effect if the RDTR
                 * is set). set GRAN=1 and write back up to 0x4 worth, and
                 * enable prefetching of 0x20 Rx descriptors
                 * granularity = 01
@@ -3083,8 +3064,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
                ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
                ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
-                /*
+                /* override the delay timers for enabling bursting, only if
-                 * override the delay timers for enabling bursting, only if
                 * the value was not set by the user via module options
                 */
                if (adapter->rx_int_delay == DEFAULT_RDTR)
@@ -3108,8 +3088,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
        ew32(CTRL_EXT, ctrl_ext);
        e1e_flush();
-        /*
+        /* Setup the HW Rx Head and Tail Descriptor Pointers and
-         * Setup the HW Rx Head and Tail Descriptor Pointers and
         * the Base and Length of the Rx Descriptor Ring
         */
        rdba = rx_ring->dma;
@@ -3130,8 +3109,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
        ew32(RXCSUM, rxcsum);
        if (adapter->hw.mac.type == e1000_pch2lan) {
-                /*
+                /* With jumbo frames, excessive C-state transition
-                 * With jumbo frames, excessive C-state transition
                 * latencies result in dropped transactions.
                 */
                if (adapter->netdev->mtu > ETH_DATA_LEN) {
@@ -3216,8 +3194,7 @@ static int e1000e_write_uc_addr_list(struct net_device *netdev)
        if (!netdev_uc_empty(netdev) && rar_entries) {
                struct netdev_hw_addr *ha;
-                /*
+                /* write the addresses in reverse order to avoid write
-                 * write the addresses in reverse order to avoid write
                 * combining
                 */
                netdev_for_each_uc_addr(ha, netdev) {
@@ -3269,8 +3246,7 @@ static void e1000e_set_rx_mode(struct net_device *netdev)
                if (netdev->flags & IFF_ALLMULTI) {
                        rctl |= E1000_RCTL_MPE;
                } else {
-                        /*
+                        /* Write addresses to the MTA, if the attempt fails
-                         * Write addresses to the MTA, if the attempt fails
                         * then we should just turn on promiscuous mode so
                         * that we can at least receive multicast traffic
                         */
@@ -3279,8 +3255,7 @@ static void e1000e_set_rx_mode(struct net_device *netdev)
                                rctl |= E1000_RCTL_MPE;
                }
                e1000e_vlan_filter_enable(adapter);
-                /*
+                /* Write addresses to available RAR registers, if there is not
-                 * Write addresses to available RAR registers, if there is not
                 * sufficient space to store all the addresses then enable
                 * unicast promiscuous mode
                 */
@@ -3315,8 +3290,7 @@ static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
        for (i = 0; i < 32; i++)
                ew32(RETA(i), 0);
-        /*
+        /* Disable raw packet checksumming so that RSS hash is placed in
-         * Disable raw packet checksumming so that RSS hash is placed in
         * descriptor on writeback.
         */
        rxcsum = er32(RXCSUM);
@@ -3408,8 +3382,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
        ew32(PBA, pba);
        if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
-                /*
+                /* To maintain wire speed transmits, the Tx FIFO should be
-                 * To maintain wire speed transmits, the Tx FIFO should be
                 * large enough to accommodate two full transmit packets,
                 * rounded up to the next 1KB and expressed in KB.  Likewise,
                 * the Rx FIFO should be large enough to accommodate at least
@@ -3421,8 +3394,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
                tx_space = pba >> 16;
                /* lower 16 bits has Rx packet buffer allocation size in KB */
                pba &= 0xffff;
-                /*
+                /* the Tx fifo also stores 16 bytes of information about the Tx
-                 * the Tx fifo also stores 16 bytes of information about the Tx
                 * but don't include ethernet FCS because hardware appends it
                 */
                min_tx_space = (adapter->max_frame_size +
@@ -3435,8 +3407,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
                min_rx_space = ALIGN(min_rx_space, 1024);
                min_rx_space >>= 10;
-                /*
+                /* If current Tx allocation is less than the min Tx FIFO size,
-                 * If current Tx allocation is less than the min Tx FIFO size,
                 * and the min Tx FIFO size is less than the current Rx FIFO
                 * allocation, take space away from current Rx allocation
                 */
@@ -3444,8 +3415,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
                    ((min_tx_space - tx_space) < pba)) {
                        pba -= min_tx_space - tx_space;
-                        /*
+                        /* if short on Rx space, Rx wins and must trump Tx
-                         * if short on Rx space, Rx wins and must trump Tx
                         * adjustment
                         */
                        if (pba < min_rx_space)
@@ -3455,8 +3425,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
                ew32(PBA, pba);
        }
-        /*
+        /* flow control settings
-         * flow control settings
         *
         * The high water mark must be low enough to fit one full frame
         * (or the size used for early receive) above it in the Rx FIFO.
@@ -3490,8 +3459,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
                fc->low_water = fc->high_water - 8;
                break;
        case e1000_pchlan:
-                /*
+                /* Workaround PCH LOM adapter hangs with certain network
-                 * Workaround PCH LOM adapter hangs with certain network
                 * loads.  If hangs persist, try disabling Tx flow control.
                 */
                if (adapter->netdev->mtu > ETH_DATA_LEN) {
@@ -3516,8 +3484,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
                break;
        }
-        /*
+        /* Alignment of Tx data is on an arbitrary byte boundary with the
-         * Alignment of Tx data is on an arbitrary byte boundary with the
         * maximum size per Tx descriptor limited only to the transmit
         * allocation of the packet buffer minus 96 bytes with an upper
         * limit of 24KB due to receive synchronization limitations.
@@ -3525,8 +3492,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
        adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
                                       24 << 10);
-        /*
+        /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
-         * Disable Adaptive Interrupt Moderation if 2 full packets cannot
         * fit in receive buffer.
         */
        if (adapter->itr_setting & 0x3) {
@@ -3549,8 +3515,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
        /* Allow time for pending master requests to run */
        mac->ops.reset_hw(hw);
-        /*
+        /* For parts with AMT enabled, let the firmware know
-         * For parts with AMT enabled, let the firmware know
         * that the network interface is in control
         */
        if (adapter->flags & FLAG_HAS_AMT)
@@ -3579,8 +3544,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
        if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
            !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
                u16 phy_data = 0;
-                /*
+                /* speed up time to link by disabling smart power down, ignore
-                 * speed up time to link by disabling smart power down, ignore
                 * the return value of this function because there is nothing
                 * different we would do if it failed
                 */
@@ -3628,8 +3592,7 @@ static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
        /* execute the writes immediately */
        e1e_flush();
-        /*
+        /* due to rare timing issues, write to TIDV/RDTR again to ensure the
-         * due to rare timing issues, write to TIDV/RDTR again to ensure the
         * write is successful
         */
        ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
@@ -3647,8 +3610,7 @@ void e1000e_down(struct e1000_adapter *adapter)
        struct e1000_hw *hw = &adapter->hw;
        u32 tctl, rctl;
-        /*
+        /* signal that we're down so the interrupt handler does not
-         * signal that we're down so the interrupt handler does not
         * reschedule our watchdog timer
         */
        set_bit(__E1000_DOWN, &adapter->state);
@@ -3691,8 +3653,7 @@ void e1000e_down(struct e1000_adapter *adapter)
        if (!pci_channel_offline(adapter->pdev))
                e1000e_reset(adapter);
-        /*
+        /* TODO: for power management, we could drop the link and
-         * TODO: for power management, we could drop the link and
         * pci_disable_device here.
         */
 }
@@ -3755,8 +3716,7 @@ static irqreturn_t e1000_intr_msi_test(int irq, void *data)
        e_dbg("icr is %08X\n", icr);
        if (icr & E1000_ICR_RXSEQ) {
                adapter->flags &= ~FLAG_MSI_TEST_FAILED;
-                /*
+                /* Force memory writes to complete before acknowledging the
-                 * Force memory writes to complete before acknowledging the
                 * interrupt is handled.
                 */
                wmb();
@@ -3786,7 +3746,8 @@ static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
        e1000e_reset_interrupt_capability(adapter);
        /* Assume that the test fails, if it succeeds then the test
-         * MSI irq handler will unset this flag */
+         * MSI irq handler will unset this flag
+         */
        adapter->flags |= FLAG_MSI_TEST_FAILED;
        err = pci_enable_msi(adapter->pdev);
@@ -3800,8 +3761,7 @@ static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
                goto msi_test_failed;
        }
-        /*
+        /* Force memory writes to complete before enabling and firing an
-         * Force memory writes to complete before enabling and firing an
         * interrupt.
         */
        wmb();
@@ -3901,8 +3861,7 @@ static int e1000_open(struct net_device *netdev)
        if (err)
                goto err_setup_rx;
-        /*
+        /* If AMT is enabled, let the firmware know that the network
-         * If AMT is enabled, let the firmware know that the network
         * interface is now open and reset the part to a known state.
         */
        if (adapter->flags & FLAG_HAS_AMT) {
@@ -3923,8 +3882,7 @@ static int e1000_open(struct net_device *netdev)
                                   PM_QOS_CPU_DMA_LATENCY,
                                   PM_QOS_DEFAULT_VALUE);
-        /*
+        /* before we allocate an interrupt, we must be ready to handle it.
-         * before we allocate an interrupt, we must be ready to handle it.
         * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
         * as soon as we call pci_request_irq, so we have to setup our
         * clean_rx handler before we do so.
@@ -3935,8 +3893,7 @@ static int e1000_open(struct net_device *netdev)
        if (err)
                goto err_req_irq;
-        /*
+        /* Work around PCIe errata with MSI interrupts causing some chipsets to
-         * Work around PCIe errata with MSI interrupts causing some chipsets to
         * ignore e1000e MSI messages, which means we need to test our MSI
         * interrupt now
         */
@@ -4017,16 +3974,14 @@ static int e1000_close(struct net_device *netdev)
        e1000e_free_tx_resources(adapter->tx_ring);
        e1000e_free_rx_resources(adapter->rx_ring);
-        /*
+        /* kill manageability vlan ID if supported, but not if a vlan with
-         * kill manageability vlan ID if supported, but not if a vlan with
         * the same ID is registered on the host OS (let 8021q kill it)
         */
        if (adapter->hw.mng_cookie.status &
            E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
                e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
-        /*
+        /* If AMT is enabled, let the firmware know that the network
-         * If AMT is enabled, let the firmware know that the network
         * interface is now closed
         */
        if ((adapter->flags & FLAG_HAS_AMT) &&
@@ -4065,8 +4020,7 @@ static int e1000_set_mac(struct net_device *netdev, void *p)
                /* activate the work around */
                e1000e_set_laa_state_82571(&adapter->hw, 1);
-                /*
+                /* Hold a copy of the LAA in RAR[14] This is done so that
-                 * Hold a copy of the LAA in RAR[14] This is done so that
                 * between the time RAR[0] gets clobbered  and the time it
                 * gets fixed (in e1000_watchdog), the actual LAA is in one
                 * of the RARs and no incoming packets directed to this port
@@ -4099,10 +4053,13 @@ static void e1000e_update_phy_task(struct work_struct *work)
        e1000_get_phy_info(&adapter->hw);
 }
-/*
+/**
+ * e1000_update_phy_info - timre call-back to update PHY info
+ * @data: pointer to adapter cast into an unsigned long
+ *
 * Need to wait a few seconds after link up to get diagnostic information from
 * the phy
- */
+ **/
 static void e1000_update_phy_info(unsigned long data)
 {
        struct e1000_adapter *adapter = (struct e1000_adapter *) data;
@@ -4129,8 +4086,7 @@ static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
        if (ret_val)
                return;
-        /*
+        /* A page set is expensive so check if already on desired page.
-         * A page set is expensive so check if already on desired page.
         * If not, set to the page with the PHY status registers.
         */
        hw->phy.addr = 1;
@@ -4201,8 +4157,7 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)
        struct e1000_hw *hw = &adapter->hw;
        struct pci_dev *pdev = adapter->pdev;
-        /*
+        /* Prevent stats update while adapter is being reset, or if the pci
-         * Prevent stats update while adapter is being reset, or if the pci
         * connection is down.
         */
        if (adapter->link_speed == 0)
@@ -4270,8 +4225,7 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)
        /* Rx Errors */
-        /*
+        /* RLEC on some newer hardware can be incorrect so build
-         * RLEC on some newer hardware can be incorrect so build
         * our own version based on RUC and ROC
         */
        netdev->stats.rx_errors = adapter->stats.rxerrc +
@@ -4323,8 +4277,7 @@ static void e1000_phy_read_status(struct e1000_adapter *adapter)
                if (ret_val)
                        e_warn("Error reading PHY register\n");
        } else {
-                /*
+                /* Do not read PHY registers if link is not up
-                 * Do not read PHY registers if link is not up
                 * Set values to typical power-on defaults
                 */
                phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
@@ -4362,8 +4315,7 @@ static bool e1000e_has_link(struct e1000_adapter *adapter)
        bool link_active = false;
        s32 ret_val = 0;
-        /*
+        /* get_link_status is set on LSC (link status) interrupt or
-         * get_link_status is set on LSC (link status) interrupt or
         * Rx sequence error interrupt.  get_link_status will stay
         * false until the check_for_link establishes link
         * for copper adapters ONLY
@@ -4415,8 +4367,7 @@ static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
 {
        struct e1000_hw *hw = &adapter->hw;
-        /*
+        /* With 82574 controllers, PHY needs to be checked periodically
-         * With 82574 controllers, PHY needs to be checked periodically
         * for hung state and reset, if two calls return true
         */
        if (e1000_check_phy_82574(hw))
@@ -4484,8 +4435,7 @@ static void e1000_watchdog_task(struct work_struct *work)
                                                   &adapter->link_speed,
                                                   &adapter->link_duplex);
                        e1000_print_link_info(adapter);
-                        /*
+                        /* On supported PHYs, check for duplex mismatch only
-                         * On supported PHYs, check for duplex mismatch only
                         * if link has autonegotiated at 10/100 half
                         */
                        if ((hw->phy.type == e1000_phy_igp_3 ||
@@ -4515,8 +4465,7 @@ static void e1000_watchdog_task(struct work_struct *work)
                                break;
                        }
-                        /*
+                        /* workaround: re-program speed mode bit after
-                         * workaround: re-program speed mode bit after
                         * link-up event
                         */
                        if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
@@ -4527,8 +4476,7 @@ static void e1000_watchdog_task(struct work_struct *work)
                                ew32(TARC(0), tarc0);
                        }
-                        /*
+                        /* disable TSO for pcie and 10/100 speeds, to avoid
-                         * disable TSO for pcie and 10/100 speeds, to avoid
                         * some hardware issues
                         */
                        if (!(adapter->flags & FLAG_TSO_FORCE)) {
@@ -4549,16 +4497,14 @@ static void e1000_watchdog_task(struct work_struct *work)
                                }
                        }
-                        /*
+                        /* enable transmits in the hardware, need to do this
-                         * enable transmits in the hardware, need to do this
                         * after setting TARC(0)
                         */
                        tctl = er32(TCTL);
                        tctl |= E1000_TCTL_EN;
                        ew32(TCTL, tctl);
-                        /*
+                        /* Perform any post-link-up configuration before
-                         * Perform any post-link-up configuration before
                         * reporting link up.
                         */
                        if (phy->ops.cfg_on_link_up)
@@ -4609,8 +4555,7 @@ link_up:
        if (!netif_carrier_ok(netdev) &&
            (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
-                /*
+                /* We've lost link, so the controller stops DMA,
-                 * We've lost link, so the controller stops DMA,
                 * but we've got queued Tx work that's never going
                 * to get done, so reset controller to flush Tx.
                 * (Do the reset outside of interrupt context).
@@ -4622,8 +4567,7 @@ link_up:
        /* Simple mode for Interrupt Throttle Rate (ITR) */
        if (adapter->itr_setting == 4) {
-                /*
+                /* Symmetric Tx/Rx gets a reduced ITR=2000;
-                 * Symmetric Tx/Rx gets a reduced ITR=2000;
                 * Total asymmetrical Tx or Rx gets ITR=8000;
                 * everyone else is between 2000-8000.
                 */
@@ -4648,8 +4592,7 @@ link_up:
        /* Force detection of hung controller every watchdog period */
        adapter->detect_tx_hung = true;
-        /*
+        /* With 82571 controllers, LAA may be overwritten due to controller
-         * With 82571 controllers, LAA may be overwritten due to controller
         * reset from the other port. Set the appropriate LAA in RAR[0]
         */
        if (e1000e_get_laa_state_82571(hw))
@@ -4948,8 +4891,7 @@ static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
        if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
                tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
-        /*
+        /* Force memory writes to complete before letting h/w
-         * Force memory writes to complete before letting h/w
         * know there are new descriptors to fetch.  (Only
         * applicable for weak-ordered memory model archs,
         * such as IA-64).
@@ -4963,8 +4905,7 @@ static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
        else
                writel(i, tx_ring->tail);
-        /*
+        /* we need this if more than one processor can write to our tail
-         * we need this if more than one processor can write to our tail
         * at a time, it synchronizes IO on IA64/Altix systems
         */
        mmiowb();
@@ -5014,15 +4955,13 @@ static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
        struct e1000_adapter *adapter = tx_ring->adapter;
        netif_stop_queue(adapter->netdev);
-        /*
+        /* Herbert's original patch had:
-         * Herbert's original patch had:
         *  smp_mb__after_netif_stop_queue();
         * but since that doesn't exist yet, just open code it.
         */
        smp_mb();
-        /*
+        /* We need to check again in a case another CPU has just
-         * We need to check again in a case another CPU has just
         * made room available.
         */
        if (e1000_desc_unused(tx_ring) < size)
@@ -5067,8 +5006,7 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
                return NETDEV_TX_OK;
        }
-        /*
+        /* The minimum packet size with TCTL.PSP set is 17 bytes so
-         * The minimum packet size with TCTL.PSP set is 17 bytes so
         * pad skb in order to meet this minimum size requirement
         */
        if (unlikely(skb->len < 17)) {
@@ -5082,14 +5020,12 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
        if (mss) {
                u8 hdr_len;
-                /*
+                /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
-                 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
                 * points to just header, pull a few bytes of payload from
                 * frags into skb->data
                 */
                hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
-                /*
+                /* we do this workaround for ES2LAN, but it is un-necessary,
-                 * we do this workaround for ES2LAN, but it is un-necessary,
                 * avoiding it could save a lot of cycles
                 */
                if (skb->data_len && (hdr_len == len)) {
@@ -5120,8 +5056,7 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
        if (adapter->hw.mac.tx_pkt_filtering)
                e1000_transfer_dhcp_info(adapter, skb);
-        /*
+        /* need: count + 2 desc gap to keep tail from touching
-         * need: count + 2 desc gap to keep tail from touching
         * head, otherwise try next time
         */
        if (e1000_maybe_stop_tx(tx_ring, count + 2))
@@ -5145,8 +5080,7 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
        else if (e1000_tx_csum(tx_ring, skb))
                tx_flags |= E1000_TX_FLAGS_CSUM;
-        /*
+        /* Old method was to assume IPv4 packet by default if TSO was enabled.
-         * Old method was to assume IPv4 packet by default if TSO was enabled.
         * 82571 hardware supports TSO capabilities for IPv6 as well...
         * no longer assume, we must.
         */
@@ -5233,8 +5167,7 @@ struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
        /* Rx Errors */
-        /*
+        /* RLEC on some newer hardware can be incorrect so build
-         * RLEC on some newer hardware can be incorrect so build
         * our own version based on RUC and ROC
         */
        stats->rx_errors = adapter->stats.rxerrc +
@@ -5303,8 +5236,7 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
        if (netif_running(netdev))
                e1000e_down(adapter);
-        /*
+        /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
-         * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
         * means we reserve 2 more, this pushes us to allocate from the next
         * larger slab size.
         * i.e. RXBUFFER_2048 --> size-4096 slab
@@ -5566,8 +5498,7 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
        if (adapter->hw.phy.type == e1000_phy_igp_3)
                e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
-        /*
+        /* Release control of h/w to f/w.  If f/w is AMT enabled, this
-         * Release control of h/w to f/w.  If f/w is AMT enabled, this
         * would have already happened in close and is redundant.
         */
        e1000e_release_hw_control(adapter);
@@ -5594,8 +5525,7 @@ static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
        struct net_device *netdev = pci_get_drvdata(pdev);
        struct e1000_adapter *adapter = netdev_priv(netdev);
-        /*
+        /* The pci-e switch on some quad port adapters will report a
-         * The pci-e switch on some quad port adapters will report a
         * correctable error when the MAC transitions from D0 to D3.  To
         * prevent this we need to mask off the correctable errors on the
         * downstream port of the pci-e switch.
@@ -5624,8 +5554,7 @@ static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
 #else
 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
 {
-        /*
+        /* Both device and parent should have the same ASPM setting.
-         * Both device and parent should have the same ASPM setting.
         * Disable ASPM in downstream component first and then upstream.
         */
        pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
@@ -5719,8 +5648,7 @@ static int __e1000_resume(struct pci_dev *pdev)
        netif_device_attach(netdev);
-        /*
+        /* If the controller has AMT, do not set DRV_LOAD until the interface
-         * If the controller has AMT, do not set DRV_LOAD until the interface
         * is up.  For all other cases, let the f/w know that the h/w is now
         * under the control of the driver.
         */
@@ -5848,7 +5776,10 @@ static irqreturn_t e1000_intr_msix(int irq, void *data)
        return IRQ_HANDLED;
 }
-/*
+/**
+ * e1000_netpoll
+ * @netdev: network interface device structure
+ *
 * Polling 'interrupt' - used by things like netconsole to send skbs
 * without having to re-enable interrupts. It's not called while
 * the interrupt routine is executing.
@@ -5973,8 +5904,7 @@ static void e1000_io_resume(struct pci_dev *pdev)
        netif_device_attach(netdev);
-        /*
+        /* If the controller has AMT, do not set DRV_LOAD until the interface
-         * If the controller has AMT, do not set DRV_LOAD until the interface
         * is up.  For all other cases, let the f/w know that the h/w is now
         * under the control of the driver.
         */
@@ -6273,14 +6203,12 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
        if (e1000e_enable_mng_pass_thru(&adapter->hw))
                adapter->flags |= FLAG_MNG_PT_ENABLED;
-        /*
+        /* before reading the NVM, reset the controller to
-         * before reading the NVM, reset the controller to
         * put the device in a known good starting state
         */
        adapter->hw.mac.ops.reset_hw(&adapter->hw);
-        /*
+        /* systems with ASPM and others may see the checksum fail on the first
-         * systems with ASPM and others may see the checksum fail on the first
         * attempt. Let's give it a few tries
         */
        for (i = 0;; i++) {
@@ -6335,8 +6263,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
        adapter->rx_ring->count = E1000_DEFAULT_RXD;
        adapter->tx_ring->count = E1000_DEFAULT_TXD;
-        /*
+        /* Initial Wake on LAN setting - If APM wake is enabled in
-         * Initial Wake on LAN setting - If APM wake is enabled in
         * the EEPROM, enable the ACPI Magic Packet filter
         */
        if (adapter->flags & FLAG_APME_IN_WUC) {
@@ -6360,8 +6287,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
        if (eeprom_data & eeprom_apme_mask)
                adapter->eeprom_wol |= E1000_WUFC_MAG;
-        /*
+        /* now that we have the eeprom settings, apply the special cases
-         * now that we have the eeprom settings, apply the special cases
         * where the eeprom may be wrong or the board simply won't support
         * wake on lan on a particular port
         */
@@ -6378,8 +6304,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
        /* reset the hardware with the new settings */
        e1000e_reset(adapter);
-        /*
+        /* If the controller has AMT, do not set DRV_LOAD until the interface
-         * If the controller has AMT, do not set DRV_LOAD until the interface
         * is up.  For all other cases, let the f/w know that the h/w is now
         * under the control of the driver.
         */
@@ -6442,8 +6367,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
        struct e1000_adapter *adapter = netdev_priv(netdev);
        bool down = test_bit(__E1000_DOWN, &adapter->state);
-        /*
+        /* The timers may be rescheduled, so explicitly disable them
-         * The timers may be rescheduled, so explicitly disable them
         * from being rescheduled.
         */
        if (!down)
@@ -6468,8 +6392,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
        if (pci_dev_run_wake(pdev))
                pm_runtime_get_noresume(&pdev->dev);
-        /*
+        /* Release control of h/w to f/w.  If f/w is AMT enabled, this
-         * Release control of h/w to f/w.  If f/w is AMT enabled, this
         * would have already happened in close and is redundant.
         */
        e1000e_release_hw_control(adapter);
diff --git a/drivers/net/ethernet/intel/e1000e/nvm.c b/drivers/net/ethernet/intel/e1000e/nvm.c
index a969f1af1b4e..b6468804cb2e 100644
--- a/drivers/net/ethernet/intel/e1000e/nvm.c
+++ b/drivers/net/ethernet/intel/e1000e/nvm.c
@@ -279,8 +279,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
                e1e_flush();
                udelay(1);
-                /*
+                /* Read "Status Register" repeatedly until the LSB is cleared.
-                 * Read "Status Register" repeatedly until the LSB is cleared.
                 * The EEPROM will signal that the command has been completed
                 * by clearing bit 0 of the internal status register.  If it's
                 * not cleared within 'timeout', then error out.
@@ -321,8 +320,7 @@ s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
        u32 i, eerd = 0;
        s32 ret_val = 0;
-        /*
+        /* A check for invalid values:  offset too large, too many words,
-         * A check for invalid values:  offset too large, too many words,
         * too many words for the offset, and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
@@ -364,8 +362,7 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
        s32 ret_val;
        u16 widx = 0;
-        /*
+        /* A check for invalid values:  offset too large, too many words,
-         * A check for invalid values:  offset too large, too many words,
         * and not enough words.
         */
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
@@ -393,8 +390,7 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
                e1000_standby_nvm(hw);
-                /*
+                /* Some SPI eeproms use the 8th address bit embedded in the
-                 * Some SPI eeproms use the 8th address bit embedded in the
                 * opcode
                 */
                if ((nvm->address_bits == 8) && (offset >= 128))
@@ -461,8 +457,7 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
                return ret_val;
        }
-        /*
+        /* if nvm_data is not ptr guard the PBA must be in legacy format which
-         * if nvm_data is not ptr guard the PBA must be in legacy format which
         * means pba_ptr is actually our second data word for the PBA number
         * and we can decode it into an ascii string
         */
diff --git a/drivers/net/ethernet/intel/e1000e/param.c b/drivers/net/ethernet/intel/e1000e/param.c
index dfbfa7fd98c3..1fbb31554e4d 100644
--- a/drivers/net/ethernet/intel/e1000e/param.c
+++ b/drivers/net/ethernet/intel/e1000e/param.c
@@ -32,11 +32,9 @@
 #include "e1000.h"
-/*
+/* This is the only thing that needs to be changed to adjust the
- * This is the only thing that needs to be changed to adjust the
 * maximum number of ports that the driver can manage.
 */
 #define E1000_MAX_NIC 32
 #define OPTION_UNSET   -1
@@ -49,12 +47,10 @@ module_param(copybreak, uint, 0644);
 MODULE_PARM_DESC(copybreak,
        "Maximum size of packet that is copied to a new buffer on receive");
-/*
+/* All parameters are treated the same, as an integer array of values.
- * All parameters are treated the same, as an integer array of values.
 * This macro just reduces the need to repeat the same declaration code
 * over and over (plus this helps to avoid typo bugs).
 */
 #define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
 #define E1000_PARAM(X, desc)                                    \
        static int __devinitdata X[E1000_MAX_NIC+1]             \
@@ -63,8 +59,7 @@ MODULE_PARM_DESC(copybreak,
        module_param_array_named(X, X, int, &num_##X, 0);       \
        MODULE_PARM_DESC(X, desc);
-/*
+/* Transmit Interrupt Delay in units of 1.024 microseconds
- * Transmit Interrupt Delay in units of 1.024 microseconds
 * Tx interrupt delay needs to typically be set to something non-zero
 *
 * Valid Range: 0-65535
@@ -74,8 +69,7 @@ E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
 #define MAX_TXDELAY 0xFFFF
 #define MIN_TXDELAY 0
-/*
+/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
- * Transmit Absolute Interrupt Delay in units of 1.024 microseconds
 *
 * Valid Range: 0-65535
 */
@@ -84,8 +78,7 @@ E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
 #define MAX_TXABSDELAY 0xFFFF
 #define MIN_TXABSDELAY 0
-/*
+/* Receive Interrupt Delay in units of 1.024 microseconds
- * Receive Interrupt Delay in units of 1.024 microseconds
 * hardware will likely hang if you set this to anything but zero.
 *
 * Valid Range: 0-65535
@@ -94,8 +87,7 @@ E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
 #define MAX_RXDELAY 0xFFFF
 #define MIN_RXDELAY 0
-/*
+/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
- * Receive Absolute Interrupt Delay in units of 1.024 microseconds
 *
 * Valid Range: 0-65535
 */
@@ -103,8 +95,7 @@ E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
 #define MAX_RXABSDELAY 0xFFFF
 #define MIN_RXABSDELAY 0
-/*
+/* Interrupt Throttle Rate (interrupts/sec)
- * Interrupt Throttle Rate (interrupts/sec)
 *
 * Valid Range: 100-100000 or one of: 0=off, 1=dynamic, 3=dynamic conservative
 */
@@ -113,8 +104,7 @@ E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
 #define MAX_ITR 100000
 #define MIN_ITR 100
-/*
+/* IntMode (Interrupt Mode)
- * IntMode (Interrupt Mode)
 *
 * Valid Range: varies depending on kernel configuration & hardware support
 *
@@ -132,8 +122,7 @@ E1000_PARAM(IntMode, "Interrupt Mode");
 #define MAX_INTMODE     2
 #define MIN_INTMODE     0
-/*
+/* Enable Smart Power Down of the PHY
- * Enable Smart Power Down of the PHY
 *
 * Valid Range: 0, 1
 *
@@ -141,8 +130,7 @@ E1000_PARAM(IntMode, "Interrupt Mode");
 */
 E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
-/*
+/* Enable Kumeran Lock Loss workaround
- * Enable Kumeran Lock Loss workaround
 *
 * Valid Range: 0, 1
 *
@@ -150,8 +138,7 @@ E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
 */
 E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
-/*
+/* Write Protect NVM
- * Write Protect NVM
 *
 * Valid Range: 0, 1
 *
@@ -159,8 +146,7 @@ E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
 */
 E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lead to corrupted NVM]");
-/*
+/* Enable CRC Stripping
- * Enable CRC Stripping
 *
 * Valid Range: 0, 1
 *
@@ -351,8 +337,7 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
                if (num_InterruptThrottleRate > bd) {
                        adapter->itr = InterruptThrottleRate[bd];
-                        /*
+                        /* Make sure a message is printed for non-special
-                         * Make sure a message is printed for non-special
                         * values. And in case of an invalid option, display
                         * warning, use default and go through itr/itr_setting
                         * adjustment logic below
@@ -361,14 +346,12 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
                            e1000_validate_option(&adapter->itr, &opt, adapter))
                                adapter->itr = opt.def;
                } else {
-                        /*
+                        /* If no option specified, use default value and go
-                         * If no option specified, use default value and go
                         * through the logic below to adjust itr/itr_setting
                         */
                        adapter->itr = opt.def;
-                        /*
+                        /* Make sure a message is printed for non-special
-                         * Make sure a message is printed for non-special
                         * default values
                         */
                        if (adapter->itr > 4)
@@ -400,8 +383,7 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
                                 opt.name);
                        break;
                default:
-                        /*
+                        /* Save the setting, because the dynamic bits
-                         * Save the setting, because the dynamic bits
                         * change itr.
                         *
                         * Clear the lower two bits because
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index fc62a3f3a5be..28b38ff37e84 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -193,8 +193,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
                return -E1000_ERR_PARAM;
        }
-        /*
+        /* Set up Op-code, Phy Address, and register offset in the MDI
-         * Set up Op-code, Phy Address, and register offset in the MDI
         * Control register.  The MAC will take care of interfacing with the
         * PHY to retrieve the desired data.
         */
@@ -204,8 +203,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
        ew32(MDIC, mdic);
-        /*
+        /* Poll the ready bit to see if the MDI read completed
-         * Poll the ready bit to see if the MDI read completed
         * Increasing the time out as testing showed failures with
         * the lower time out
         */
@@ -225,8 +223,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
        }
        *data = (u16) mdic;
-        /*
+        /* Allow some time after each MDIC transaction to avoid
-         * Allow some time after each MDIC transaction to avoid
         * reading duplicate data in the next MDIC transaction.
         */
        if (hw->mac.type == e1000_pch2lan)
@@ -253,8 +250,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
                return -E1000_ERR_PARAM;
        }
-        /*
+        /* Set up Op-code, Phy Address, and register offset in the MDI
-         * Set up Op-code, Phy Address, and register offset in the MDI
         * Control register.  The MAC will take care of interfacing with the
         * PHY to retrieve the desired data.
         */
@@ -265,8 +261,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
        ew32(MDIC, mdic);
-        /*
+        /* Poll the ready bit to see if the MDI read completed
-         * Poll the ready bit to see if the MDI read completed
         * Increasing the time out as testing showed failures with
         * the lower time out
         */
@@ -285,8 +280,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
                return -E1000_ERR_PHY;
        }
-        /*
+        /* Allow some time after each MDIC transaction to avoid
-         * Allow some time after each MDIC transaction to avoid
         * reading duplicate data in the next MDIC transaction.
         */
        if (hw->mac.type == e1000_pch2lan)
@@ -708,8 +702,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
        phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
-        /*
+        /* Options:
-         * Options:
         *   0 - Auto (default)
         *   1 - MDI mode
         *   2 - MDI-X mode
@@ -754,8 +747,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
        if (phy->type != e1000_phy_bm)
                phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-        /*
+        /* Options:
-         * Options:
         *   MDI/MDI-X = 0 (default)
         *   0 - Auto for all speeds
         *   1 - MDI mode
@@ -780,8 +772,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
                break;
        }
-        /*
+        /* Options:
-         * Options:
         *   disable_polarity_correction = 0 (default)
         *       Automatic Correction for Reversed Cable Polarity
         *   0 - Disabled
@@ -818,8 +809,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
        if ((phy->type == e1000_phy_m88) &&
            (phy->revision < E1000_REVISION_4) &&
            (phy->id != BME1000_E_PHY_ID_R2)) {
-                /*
+                /* Force TX_CLK in the Extended PHY Specific Control Register
-                 * Force TX_CLK in the Extended PHY Specific Control Register
                 * to 25MHz clock.
                 */
                ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
@@ -899,8 +889,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
                return ret_val;
        }
-        /*
+        /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
-         * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
         * timeout issues when LFS is enabled.
         */
        msleep(100);
@@ -936,8 +925,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
        /* set auto-master slave resolution settings */
        if (hw->mac.autoneg) {
-                /*
+                /* when autonegotiation advertisement is only 1000Mbps then we
-                 * when autonegotiation advertisement is only 1000Mbps then we
                 * should disable SmartSpeed and enable Auto MasterSlave
                 * resolution as hardware default.
                 */
@@ -1001,16 +989,14 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                        return ret_val;
        }
-        /*
+        /* Need to parse both autoneg_advertised and fc and set up
-         * Need to parse both autoneg_advertised and fc and set up
         * the appropriate PHY registers.  First we will parse for
         * autoneg_advertised software override.  Since we can advertise
         * a plethora of combinations, we need to check each bit
         * individually.
         */
-        /*
+        /* First we clear all the 10/100 mb speed bits in the Auto-Neg
-         * First we clear all the 10/100 mb speed bits in the Auto-Neg
         * Advertisement Register (Address 4) and the 1000 mb speed bits in
         * the  1000Base-T Control Register (Address 9).
         */
@@ -1056,8 +1042,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
        }
-        /*
+        /* Check for a software override of the flow control settings, and
-         * Check for a software override of the flow control settings, and
         * setup the PHY advertisement registers accordingly.  If
         * auto-negotiation is enabled, then software will have to set the
         * "PAUSE" bits to the correct value in the Auto-Negotiation
@@ -1076,15 +1061,13 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
         */
        switch (hw->fc.current_mode) {
        case e1000_fc_none:
-                /*
+                /* Flow control (Rx & Tx) is completely disabled by a
-                 * Flow control (Rx & Tx) is completely disabled by a
                 * software over-ride.
                 */
                mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
                break;
        case e1000_fc_rx_pause:
-                /*
+                /* Rx Flow control is enabled, and Tx Flow control is
-                 * Rx Flow control is enabled, and Tx Flow control is
                 * disabled, by a software over-ride.
                 *
                 * Since there really isn't a way to advertise that we are
@@ -1096,16 +1079,14 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
                break;
        case e1000_fc_tx_pause:
-                /*
+                /* Tx Flow control is enabled, and Rx Flow control is
-                 * Tx Flow control is enabled, and Rx Flow control is
                 * disabled, by a software over-ride.
                 */
                mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
                mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
                break;
        case e1000_fc_full:
-                /*
+                /* Flow control (both Rx and Tx) is enabled by a software
-                 * Flow control (both Rx and Tx) is enabled by a software
                 * over-ride.
                 */
                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
@@ -1142,14 +1123,12 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
        s32 ret_val;
        u16 phy_ctrl;
-        /*
+        /* Perform some bounds checking on the autoneg advertisement
-         * Perform some bounds checking on the autoneg advertisement
         * parameter.
         */
        phy->autoneg_advertised &= phy->autoneg_mask;
-        /*
+        /* If autoneg_advertised is zero, we assume it was not defaulted
-         * If autoneg_advertised is zero, we assume it was not defaulted
         * by the calling code so we set to advertise full capability.
         */
        if (!phy->autoneg_advertised)
@@ -1163,8 +1142,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
        }
        e_dbg("Restarting Auto-Neg\n");
-        /*
+        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
-         * Restart auto-negotiation by setting the Auto Neg Enable bit and
         * the Auto Neg Restart bit in the PHY control register.
         */
        ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
@@ -1176,8 +1154,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Does the user want to wait for Auto-Neg to complete here, or
-         * Does the user want to wait for Auto-Neg to complete here, or
         * check at a later time (for example, callback routine).
         */
        if (phy->autoneg_wait_to_complete) {
@@ -1208,16 +1185,14 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
        bool link;
        if (hw->mac.autoneg) {
-                /*
+                /* Setup autoneg and flow control advertisement and perform
-                 * Setup autoneg and flow control advertisement and perform
                 * autonegotiation.
                 */
                ret_val = e1000_copper_link_autoneg(hw);
                if (ret_val)
                        return ret_val;
        } else {
-                /*
+                /* PHY will be set to 10H, 10F, 100H or 100F
-                 * PHY will be set to 10H, 10F, 100H or 100F
                 * depending on user settings.
                 */
                e_dbg("Forcing Speed and Duplex\n");
@@ -1228,8 +1203,7 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
                }
        }
-        /*
+        /* Check link status. Wait up to 100 microseconds for link to become
-         * Check link status. Wait up to 100 microseconds for link to become
         * valid.
         */
        ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
@@ -1273,8 +1247,7 @@ s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
-         * Clear Auto-Crossover to force MDI manually.  IGP requires MDI
         * forced whenever speed and duplex are forced.
         */
        ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
@@ -1328,8 +1301,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
        u16 phy_data;
        bool link;
-        /*
+        /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
-         * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
         * forced whenever speed and duplex are forced.
         */
        ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1370,8 +1342,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
                        if (hw->phy.type != e1000_phy_m88) {
                                e_dbg("Link taking longer than expected.\n");
                        } else {
-                                /*
+                                /* We didn't get link.
-                                 * We didn't get link.
                                 * Reset the DSP and cross our fingers.
                                 */
                                ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
@@ -1398,8 +1369,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* Resetting the phy means we need to re-force TX_CLK in the
-         * Resetting the phy means we need to re-force TX_CLK in the
         * Extended PHY Specific Control Register to 25MHz clock from
         * the reset value of 2.5MHz.
         */
@@ -1408,8 +1378,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
        if (ret_val)
                return ret_val;
-        /*
+        /* In addition, we must re-enable CRS on Tx for both half and full
-         * In addition, we must re-enable CRS on Tx for both half and full
         * duplex.
         */
        ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1573,8 +1542,7 @@ s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
                ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
                if (ret_val)
                        return ret_val;
-                /*
+                /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
-                 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
                 * during Dx states where the power conservation is most
                 * important.  During driver activity we should enable
                 * SmartSpeed, so performance is maintained.
@@ -1702,8 +1670,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
        s32 ret_val;
        u16 data, offset, mask;
-        /*
+        /* Polarity is determined based on the speed of
-         * Polarity is determined based on the speed of
         * our connection.
         */
        ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
@@ -1715,8 +1682,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
                offset  = IGP01E1000_PHY_PCS_INIT_REG;
                mask    = IGP01E1000_PHY_POLARITY_MASK;
        } else {
-                /*
+                /* This really only applies to 10Mbps since
-                 * This really only applies to 10Mbps since
                 * there is no polarity for 100Mbps (always 0).
                 */
                offset  = IGP01E1000_PHY_PORT_STATUS;
@@ -1745,8 +1711,7 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw)
        s32 ret_val;
        u16 phy_data, offset, mask;
-        /*
+        /* Polarity is determined based on the reversal feature being enabled.
-         * Polarity is determined based on the reversal feature being enabled.
         */
        if (phy->polarity_correction) {
                offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
@@ -1791,8 +1756,7 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw)
                msleep(100);
        }
-        /*
+        /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
-         * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
         * has completed.
         */
        return ret_val;
@@ -1814,15 +1778,13 @@ s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
        u16 i, phy_status;
        for (i = 0; i < iterations; i++) {
-                /*
+                /* Some PHYs require the PHY_STATUS register to be read
-                 * Some PHYs require the PHY_STATUS register to be read
                 * twice due to the link bit being sticky.  No harm doing
                 * it across the board.
                 */
                ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
                if (ret_val)
-                        /*
+                        /* If the first read fails, another entity may have
-                         * If the first read fails, another entity may have
                         * ownership of the resources, wait and try again to
                         * see if they have relinquished the resources yet.
                         */
@@ -1913,8 +1875,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
                if (ret_val)
                        return ret_val;
-                /*
+                /* Getting bits 15:9, which represent the combination of
-                 * Getting bits 15:9, which represent the combination of
                 * coarse and fine gain values.  The result is a number
                 * that can be put into the lookup table to obtain the
                 * approximate cable length.
@@ -2285,15 +2246,13 @@ s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
        e1e_wphy(hw, 0x1796, 0x0008);
        /* Change cg_icount + enable integbp for channels BCD */
        e1e_wphy(hw, 0x1798, 0xD008);
-        /*
+        /* Change cg_icount + enable integbp + change prop_factor_master
-         * Change cg_icount + enable integbp + change prop_factor_master
         * to 8 for channel A
         */
        e1e_wphy(hw, 0x1898, 0xD918);
        /* Disable AHT in Slave mode on channel A */
        e1e_wphy(hw, 0x187A, 0x0800);
-        /*
+        /* Enable LPLU and disable AN to 1000 in non-D0a states,
-         * Enable LPLU and disable AN to 1000 in non-D0a states,
         * Enable SPD+B2B
         */
        e1e_wphy(hw, 0x0019, 0x008D);
@@ -2417,8 +2376,7 @@ s32 e1000e_determine_phy_address(struct e1000_hw *hw)
                        e1000e_get_phy_id(hw);
                        phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
-                        /*
+                        /* If phy_type is valid, break - we found our
-                         * If phy_type is valid, break - we found our
                         * PHY address
                         */
                        if (phy_type  != e1000_phy_unknown)
@@ -2478,8 +2436,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
        if (offset > MAX_PHY_MULTI_PAGE_REG) {
                u32 page_shift, page_select;
-                /*
+                /* Page select is register 31 for phy address 1 and 22 for
-                 * Page select is register 31 for phy address 1 and 22 for
                 * phy address 2 and 3. Page select is shifted only for
                 * phy address 1.
                 */
@@ -2537,8 +2494,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
        if (offset > MAX_PHY_MULTI_PAGE_REG) {
                u32 page_shift, page_select;
-                /*
+                /* Page select is register 31 for phy address 1 and 22 for
-                 * Page select is register 31 for phy address 1 and 22 for
                 * phy address 2 and 3. Page select is shifted only for
                 * phy address 1.
                 */
@@ -2683,8 +2639,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
                return ret_val;
        }
-        /*
+        /* Enable both PHY wakeup mode and Wakeup register page writes.
-         * Enable both PHY wakeup mode and Wakeup register page writes.
         * Prevent a power state change by disabling ME and Host PHY wakeup.
         */
        temp = *phy_reg;
@@ -2698,8 +2653,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
                return ret_val;
        }
-        /*
+        /* Select Host Wakeup Registers page - caller now able to write
-         * Select Host Wakeup Registers page - caller now able to write
         * registers on the Wakeup registers page
         */
        return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
@@ -3038,8 +2992,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
                if (page == HV_INTC_FC_PAGE_START)
                        page = 0;
-                /*
+                /* Workaround MDIO accesses being disabled after entering IEEE
-                 * Workaround MDIO accesses being disabled after entering IEEE
                 * Power Down (when bit 11 of the PHY Control register is set)
                 */
                if ((hw->phy.type == e1000_phy_82578) &&
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c
index 8c12dbd0d6ce..fdaaf2709d0a 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
@@ -1028,6 +1028,15 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw)
                 * continue to check for link.
                 */
                hw->mac.get_link_status = !hw->mac.serdes_has_link;
+                /* Configure Flow Control now that Auto-Neg has completed.
+                 * First, we need to restore the desired flow control
+                 * settings because we may have had to re-autoneg with a
+                 * different link partner.
+                 */
+                ret_val = igb_config_fc_after_link_up(hw);
+                if (ret_val)
+                        hw_dbg("Error configuring flow control\n");
        } else {
                ret_val = igb_check_for_copper_link(hw);
        }
@@ -1345,7 +1354,7 @@ out:
 **/
 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
 {
-        u32 ctrl_ext, ctrl_reg, reg;
+        u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
        bool pcs_autoneg;
        s32 ret_val = E1000_SUCCESS;
        u16 data;
@@ -1433,27 +1442,45 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
        reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
                E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
-        /*
-         * We force flow control to prevent the CTRL register values from being
-         * overwritten by the autonegotiated flow control values
-         */
-        reg |= E1000_PCS_LCTL_FORCE_FCTRL;
        if (pcs_autoneg) {
                /* Set PCS register for autoneg */
                reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
                       E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
+                /* Disable force flow control for autoneg */
+                reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
+                /* Configure flow control advertisement for autoneg */
+                anadv_reg = rd32(E1000_PCS_ANADV);
+                anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
+                switch (hw->fc.requested_mode) {
+                case e1000_fc_full:
+                case e1000_fc_rx_pause:
+                        anadv_reg |= E1000_TXCW_ASM_DIR;
+                        anadv_reg |= E1000_TXCW_PAUSE;
+                        break;
+                case e1000_fc_tx_pause:
+                        anadv_reg |= E1000_TXCW_ASM_DIR;
+                        break;
+                default:
+                        break;
+                }
+                wr32(E1000_PCS_ANADV, anadv_reg);
                hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
        } else {
                /* Set PCS register for forced link */
                reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
+                /* Force flow control for forced link */
+                reg |= E1000_PCS_LCTL_FORCE_FCTRL;
                hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
        }
        wr32(E1000_PCS_LCTL, reg);
-        if (!igb_sgmii_active_82575(hw))
+        if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
                igb_force_mac_fc(hw);
        return ret_val;
@@ -1927,6 +1954,12 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)
        hw->dev_spec._82575.global_device_reset = false;
+        /* due to hw errata, global device reset doesn't always
+         * work on 82580
+         */
+        if (hw->mac.type == e1000_82580)
+                global_device_reset = false;
        /* Get current control state. */
        ctrl = rd32(E1000_CTRL);
diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h
index 198d14848820..45dce06eff26 100644
--- a/drivers/net/ethernet/intel/igb/e1000_defines.h
+++ b/drivers/net/ethernet/intel/igb/e1000_defines.h
@@ -431,6 +431,10 @@
 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 #define FLOW_CONTROL_TYPE         0x8808
+/* Transmit Config Word */
+#define E1000_TXCW_ASM_DIR      0x00000100 /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE        0x00000080 /* TXCW sym pause request */
 /* 802.1q VLAN Packet Size */
 #define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
@@ -539,6 +543,9 @@
 /* mPHY Near End Digital Loopback Override Bit */
 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
+#define E1000_PCS_LCTL_FORCE_FCTRL      0x80
+#define E1000_PCS_LSTS_AN_COMPLETE      0x10000
 /* PHY Control Register */
 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/ethernet/intel/igb/e1000_i210.c
index 41474298d365..fbcdbebb0b5f 100644
--- a/drivers/net/ethernet/intel/igb/e1000_i210.c
+++ b/drivers/net/ethernet/intel/igb/e1000_i210.c
@@ -35,11 +35,42 @@
 #include "e1000_hw.h"
 #include "e1000_i210.h"
-static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw);
+/**
-static void igb_put_hw_semaphore_i210(struct e1000_hw *hw);
+ * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
-static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
+ *  @hw: pointer to the HW structure
-                                u16 *data);
+ *
-static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw);
+ *  Acquire the HW semaphore to access the PHY or NVM
+ */
+static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
+{
+        u32 swsm;
+        s32 ret_val = E1000_SUCCESS;
+        s32 timeout = hw->nvm.word_size + 1;
+        s32 i = 0;
+        /* Get the FW semaphore. */
+        for (i = 0; i < timeout; i++) {
+                swsm = rd32(E1000_SWSM);
+                wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
+                /* Semaphore acquired if bit latched */
+                if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
+                        break;
+                udelay(50);
+        }
+        if (i == timeout) {
+                /* Release semaphores */
+                igb_put_hw_semaphore(hw);
+                hw_dbg("Driver can't access the NVM\n");
+                ret_val = -E1000_ERR_NVM;
+                goto out;
+        }
+out:
+        return ret_val;
+}
 /**
 *  igb_acquire_nvm_i210 - Request for access to EEPROM
@@ -68,6 +99,23 @@ void igb_release_nvm_i210(struct e1000_hw *hw)
 }
 /**
+ *  igb_put_hw_semaphore_i210 - Release hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Release hardware semaphore used to access the PHY or NVM
+ */
+static void igb_put_hw_semaphore_i210(struct e1000_hw *hw)
+{
+        u32 swsm;
+        swsm = rd32(E1000_SWSM);
+        swsm &= ~E1000_SWSM_SWESMBI;
+        wr32(E1000_SWSM, swsm);
+}
+/**
 *  igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
 *  @hw: pointer to the HW structure
 *  @mask: specifies which semaphore to acquire
@@ -138,60 +186,6 @@ void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
 }
 /**
- *  igb_get_hw_semaphore_i210 - Acquire hardware semaphore
- *  @hw: pointer to the HW structure
- *
- *  Acquire the HW semaphore to access the PHY or NVM
- **/
-static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
-{
-        u32 swsm;
-        s32 ret_val = E1000_SUCCESS;
-        s32 timeout = hw->nvm.word_size + 1;
-        s32 i = 0;
-        /* Get the FW semaphore. */
-        for (i = 0; i < timeout; i++) {
-                swsm = rd32(E1000_SWSM);
-                wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
-                /* Semaphore acquired if bit latched */
-                if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
-                        break;
-                udelay(50);
-        }
-        if (i == timeout) {
-                /* Release semaphores */
-                igb_put_hw_semaphore(hw);
-                hw_dbg("Driver can't access the NVM\n");
-                ret_val = -E1000_ERR_NVM;
-                goto out;
-        }
-out:
-        return ret_val;
-}
-/**
- *  igb_put_hw_semaphore_i210 - Release hardware semaphore
- *  @hw: pointer to the HW structure
- *
- *  Release hardware semaphore used to access the PHY or NVM
- **/
-static void igb_put_hw_semaphore_i210(struct e1000_hw *hw)
-{
-        u32 swsm;
-        swsm = rd32(E1000_SWSM);
-        swsm &= ~E1000_SWSM_SWESMBI;
-        wr32(E1000_SWSM, swsm);
-}
-/**
 *  igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
 *  @hw: pointer to the HW structure
 *  @offset: offset of word in the Shadow Ram to read
@@ -229,49 +223,6 @@ s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
 }
 /**
- *  igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
- *  @hw: pointer to the HW structure
- *  @offset: offset within the Shadow RAM to be written to
- *  @words: number of words to write
- *  @data: 16 bit word(s) to be written to the Shadow RAM
- *
- *  Writes data to Shadow RAM at offset using EEWR register.
- *
- *  If e1000_update_nvm_checksum is not called after this function , the
- *  data will not be committed to FLASH and also Shadow RAM will most likely
- *  contain an invalid checksum.
- *
- *  If error code is returned, data and Shadow RAM may be inconsistent - buffer
- *  partially written.
- **/
-s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
-                              u16 *data)
-{
-        s32 status = E1000_SUCCESS;
-        u16 i, count;
-        /* We cannot hold synchronization semaphores for too long,
-         * because of forceful takeover procedure. However it is more efficient
-         * to write in bursts than synchronizing access for each word. */
-        for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
-                count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
-                        E1000_EERD_EEWR_MAX_COUNT : (words - i);
-                if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
-                        status = igb_write_nvm_srwr(hw, offset, count,
-                                                      data + i);
-                        hw->nvm.ops.release(hw);
-                } else {
-                        status = E1000_ERR_SWFW_SYNC;
-                }
-                if (status != E1000_SUCCESS)
-                        break;
-        }
-        return status;
-}
-/**
 *  igb_write_nvm_srwr - Write to Shadow Ram using EEWR
 *  @hw: pointer to the HW structure
 *  @offset: offset within the Shadow Ram to be written to
@@ -329,6 +280,50 @@ out:
 }
 /**
+ *  igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
+ *  @hw: pointer to the HW structure
+ *  @offset: offset within the Shadow RAM to be written to
+ *  @words: number of words to write
+ *  @data: 16 bit word(s) to be written to the Shadow RAM
+ *
+ *  Writes data to Shadow RAM at offset using EEWR register.
+ *
+ *  If e1000_update_nvm_checksum is not called after this function , the
+ *  data will not be committed to FLASH and also Shadow RAM will most likely
+ *  contain an invalid checksum.
+ *
+ *  If error code is returned, data and Shadow RAM may be inconsistent - buffer
+ *  partially written.
+ */
+s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
+                              u16 *data)
+{
+        s32 status = E1000_SUCCESS;
+        u16 i, count;
+        /* We cannot hold synchronization semaphores for too long,
+         * because of forceful takeover procedure. However it is more efficient
+         * to write in bursts than synchronizing access for each word.
+         */
+        for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
+                count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
+                        E1000_EERD_EEWR_MAX_COUNT : (words - i);
+                if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
+                        status = igb_write_nvm_srwr(hw, offset, count,
+                                                      data + i);
+                        hw->nvm.ops.release(hw);
+                } else {
+                        status = E1000_ERR_SWFW_SYNC;
+                }
+                if (status != E1000_SUCCESS)
+                        break;
+        }
+        return status;
+}
+/**
 *  igb_read_nvm_i211 - Read NVM wrapper function for I211
 *  @hw: pointer to the HW structure
 *  @address: the word address (aka eeprom offset) to read
@@ -350,16 +345,40 @@ s32 igb_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,
                if (ret_val != E1000_SUCCESS)
                        hw_dbg("MAC Addr not found in iNVM\n");
                break;
-        case NVM_ID_LED_SETTINGS:
        case NVM_INIT_CTRL_2:
+                ret_val = igb_read_invm_i211(hw, (u8)offset, data);
+                if (ret_val != E1000_SUCCESS) {
+                        *data = NVM_INIT_CTRL_2_DEFAULT_I211;
+                        ret_val = E1000_SUCCESS;
+                }
+                break;
        case NVM_INIT_CTRL_4:
+                ret_val = igb_read_invm_i211(hw, (u8)offset, data);
+                if (ret_val != E1000_SUCCESS) {
+                        *data = NVM_INIT_CTRL_4_DEFAULT_I211;
+                        ret_val = E1000_SUCCESS;
+                }
+                break;
        case NVM_LED_1_CFG:
+                ret_val = igb_read_invm_i211(hw, (u8)offset, data);
+                if (ret_val != E1000_SUCCESS) {
+                        *data = NVM_LED_1_CFG_DEFAULT_I211;
+                        ret_val = E1000_SUCCESS;
+                }
+                break;
        case NVM_LED_0_2_CFG:
                igb_read_invm_i211(hw, offset, data);
+                if (ret_val != E1000_SUCCESS) {
+                        *data = NVM_LED_0_2_CFG_DEFAULT_I211;
+                        ret_val = E1000_SUCCESS;
+                }
                break;
-        case NVM_COMPAT:
+        case NVM_ID_LED_SETTINGS:
-                *data = ID_LED_DEFAULT_I210;
+                ret_val = igb_read_invm_i211(hw, (u8)offset, data);
-                break;
+                if (ret_val != E1000_SUCCESS) {
+                        *data = ID_LED_RESERVED_FFFF;
+                        ret_val = E1000_SUCCESS;
+                }
        case NVM_SUB_DEV_ID:
                *data = hw->subsystem_device_id;
                break;
@@ -613,6 +632,28 @@ out:
 }
 /**
+ *  igb_pool_flash_update_done_i210 - Pool FLUDONE status.
+ *  @hw: pointer to the HW structure
+ *
+ */
+static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
+{
+        s32 ret_val = -E1000_ERR_NVM;
+        u32 i, reg;
+        for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
+                reg = rd32(E1000_EECD);
+                if (reg & E1000_EECD_FLUDONE_I210) {
+                        ret_val = E1000_SUCCESS;
+                        break;
+                }
+                udelay(5);
+        }
+        return ret_val;
+}
+/**
 *  igb_update_flash_i210 - Commit EEPROM to the flash
 *  @hw: pointer to the HW structure
 *
@@ -642,28 +683,6 @@ out:
 }
 /**
- *  igb_pool_flash_update_done_i210 - Pool FLUDONE status.
- *  @hw: pointer to the HW structure
- *
- **/
-s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
-{
-        s32 ret_val = -E1000_ERR_NVM;
-        u32 i, reg;
-        for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
-                reg = rd32(E1000_EECD);
-                if (reg & E1000_EECD_FLUDONE_I210) {
-                        ret_val = E1000_SUCCESS;
-                        break;
-                }
-                udelay(5);
-        }
-        return ret_val;
-}
-/**
 *  igb_valid_led_default_i210 - Verify a valid default LED config
 *  @hw: pointer to the HW structure
 *  @data: pointer to the NVM (EEPROM)
diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.h b/drivers/net/ethernet/intel/igb/e1000_i210.h
index 974d23584d70..1c89358a99ab 100644
--- a/drivers/net/ethernet/intel/igb/e1000_i210.h
+++ b/drivers/net/ethernet/intel/igb/e1000_i210.h
@@ -84,4 +84,10 @@ enum E1000_INVM_STRUCTURE_TYPE {
                                         (ID_LED_DEF1_DEF2 <<  4) | \
                                         (ID_LED_DEF1_DEF2))
+/* NVM offset defaults for i211 device */
+#define NVM_INIT_CTRL_2_DEFAULT_I211    0X7243
+#define NVM_INIT_CTRL_4_DEFAULT_I211    0x00C1
+#define NVM_LED_1_CFG_DEFAULT_I211      0x0184
+#define NVM_LED_0_2_CFG_DEFAULT_I211    0x200C
 #endif
diff --git a/drivers/net/ethernet/intel/igb/e1000_mac.c b/drivers/net/ethernet/intel/igb/e1000_mac.c
index 7acddfe9e6d5..101e6e4da97f 100644
--- a/drivers/net/ethernet/intel/igb/e1000_mac.c
+++ b/drivers/net/ethernet/intel/igb/e1000_mac.c
@@ -839,6 +839,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
 {
        struct e1000_mac_info *mac = &hw->mac;
        s32 ret_val = 0;
+        u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
        u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
        u16 speed, duplex;
@@ -1040,6 +1041,129 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
                        goto out;
                }
        }
+        /* Check for the case where we have SerDes media and auto-neg is
+         * enabled.  In this case, we need to check and see if Auto-Neg
+         * has completed, and if so, how the PHY and link partner has
+         * flow control configured.
+         */
+        if ((hw->phy.media_type == e1000_media_type_internal_serdes)
+                && mac->autoneg) {
+                /* Read the PCS_LSTS and check to see if AutoNeg
+                 * has completed.
+                 */
+                pcs_status_reg = rd32(E1000_PCS_LSTAT);
+                if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
+                        hw_dbg("PCS Auto Neg has not completed.\n");
+                        return ret_val;
+                }
+                /* The AutoNeg process has completed, so we now need to
+                 * read both the Auto Negotiation Advertisement
+                 * Register (PCS_ANADV) and the Auto_Negotiation Base
+                 * Page Ability Register (PCS_LPAB) to determine how
+                 * flow control was negotiated.
+                 */
+                pcs_adv_reg = rd32(E1000_PCS_ANADV);
+                pcs_lp_ability_reg = rd32(E1000_PCS_LPAB);
+                /* Two bits in the Auto Negotiation Advertisement Register
+                 * (PCS_ANADV) and two bits in the Auto Negotiation Base
+                 * Page Ability Register (PCS_LPAB) determine flow control
+                 * for both the PHY and the link partner.  The following
+                 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
+                 * 1999, describes these PAUSE resolution bits and how flow
+                 * control is determined based upon these settings.
+                 * NOTE:  DC = Don't Care
+                 *
+                 *   LOCAL DEVICE  |   LINK PARTNER
+                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
+                 *-------|---------|-------|---------|--------------------
+                 *   0   |    0    |  DC   |   DC    | e1000_fc_none
+                 *   0   |    1    |   0   |   DC    | e1000_fc_none
+                 *   0   |    1    |   1   |    0    | e1000_fc_none
+                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
+                 *   1   |    0    |   0   |   DC    | e1000_fc_none
+                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
+                 *   1   |    1    |   0   |    0    | e1000_fc_none
+                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
+                 *
+                 * Are both PAUSE bits set to 1?  If so, this implies
+                 * Symmetric Flow Control is enabled at both ends.  The
+                 * ASM_DIR bits are irrelevant per the spec.
+                 *
+                 * For Symmetric Flow Control:
+                 *
+                 *   LOCAL DEVICE  |   LINK PARTNER
+                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                 *-------|---------|-------|---------|--------------------
+                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
+                 *
+                 */
+                if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
+                    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
+                        /* Now we need to check if the user selected Rx ONLY
+                         * of pause frames.  In this case, we had to advertise
+                         * FULL flow control because we could not advertise Rx
+                         * ONLY. Hence, we must now check to see if we need to
+                         * turn OFF the TRANSMISSION of PAUSE frames.
+                         */
+                        if (hw->fc.requested_mode == e1000_fc_full) {
+                                hw->fc.current_mode = e1000_fc_full;
+                                hw_dbg("Flow Control = FULL.\n");
+                        } else {
+                                hw->fc.current_mode = e1000_fc_rx_pause;
+                                hw_dbg("Flow Control = Rx PAUSE frames only.\n");
+                        }
+                }
+                /* For receiving PAUSE frames ONLY.
+                 *
+                 *   LOCAL DEVICE  |   LINK PARTNER
+                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                 *-------|---------|-------|---------|--------------------
+                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
+                 */
+                else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
+                          (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
+                          (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
+                          (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
+                        hw->fc.current_mode = e1000_fc_tx_pause;
+                        hw_dbg("Flow Control = Tx PAUSE frames only.\n");
+                }
+                /* For transmitting PAUSE frames ONLY.
+                 *
+                 *   LOCAL DEVICE  |   LINK PARTNER
+                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                 *-------|---------|-------|---------|--------------------
+                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
+                 */
+                else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
+                         (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
+                         !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
+                         (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
+                        hw->fc.current_mode = e1000_fc_rx_pause;
+                        hw_dbg("Flow Control = Rx PAUSE frames only.\n");
+                } else {
+                        /* Per the IEEE spec, at this point flow control
+                         * should be disabled.
+                         */
+                        hw->fc.current_mode = e1000_fc_none;
+                        hw_dbg("Flow Control = NONE.\n");
+                }
+                /* Now we call a subroutine to actually force the MAC
+                 * controller to use the correct flow control settings.
+                 */
+                pcs_ctrl_reg = rd32(E1000_PCS_LCTL);
+                pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
+                wr32(E1000_PCS_LCTL, pcs_ctrl_reg);
+                ret_val = igb_force_mac_fc(hw);
+                if (ret_val) {
+                        hw_dbg("Error forcing flow control settings\n");
+                        return ret_val;
+                }
+        }
 out:
        return ret_val;
diff --git a/drivers/net/ethernet/intel/igb/e1000_nvm.c b/drivers/net/ethernet/intel/igb/e1000_nvm.c
index 7db3f80bcd57..fbb7604db364 100644
--- a/drivers/net/ethernet/intel/igb/e1000_nvm.c
+++ b/drivers/net/ethernet/intel/igb/e1000_nvm.c
@@ -438,7 +438,7 @@ out:
 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 {
        struct e1000_nvm_info *nvm = &hw->nvm;
-        s32 ret_val;
+        s32 ret_val = -E1000_ERR_NVM;
        u16 widx = 0;
        /*
@@ -448,22 +448,21 @@ s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
        if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
            (words == 0)) {
                hw_dbg("nvm parameter(s) out of bounds\n");
-                ret_val = -E1000_ERR_NVM;
+                return ret_val;
-                goto out;
        }
-        ret_val = hw->nvm.ops.acquire(hw);
-        if (ret_val)
-                goto out;
-        msleep(10);
        while (widx < words) {
                u8 write_opcode = NVM_WRITE_OPCODE_SPI;
-                ret_val = igb_ready_nvm_eeprom(hw);
+                ret_val = nvm->ops.acquire(hw);
                if (ret_val)
-                        goto release;
+                        return ret_val;
+                ret_val = igb_ready_nvm_eeprom(hw);
+                if (ret_val) {
+                        nvm->ops.release(hw);
+                        return ret_val;
+                }
                igb_standby_nvm(hw);
@@ -497,13 +496,10 @@ s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
                                break;
                        }
                }
+                usleep_range(1000, 2000);
+                nvm->ops.release(hw);
        }
-        msleep(10);
-release:
-        hw->nvm.ops.release(hw);
-out:
        return ret_val;
 }
diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h
index c15a4811b476..17f1686ee411 100644
--- a/drivers/net/ethernet/intel/igb/igb.h
+++ b/drivers/net/ethernet/intel/igb/igb.h
@@ -42,6 +42,8 @@
 struct igb_adapter;
+#define E1000_PCS_CFG_IGN_SD               1
 /* Interrupt defines */
 #define IGB_START_ITR                    648 /* ~6000 ints/sec */
 #define IGB_4K_ITR                       980
diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c
index e2288b5a9caa..bfe9208c4b18 100644
--- a/drivers/net/ethernet/intel/igb/igb_ethtool.c
+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c
@@ -1624,6 +1624,20 @@ static int igb_setup_loopback_test(struct igb_adapter *adapter)
                reg &= ~E1000_CONNSW_ENRGSRC;
                wr32(E1000_CONNSW, reg);
+                /* Unset sigdetect for SERDES loopback on
+                 * 82580 and i350 devices.
+                 */
+                switch (hw->mac.type) {
+                case e1000_82580:
+                case e1000_i350:
+                        reg = rd32(E1000_PCS_CFG0);
+                        reg |= E1000_PCS_CFG_IGN_SD;
+                        wr32(E1000_PCS_CFG0, reg);
+                        break;
+                default:
+                        break;
+                }
                /* Set PCS register for forced speed */
                reg = rd32(E1000_PCS_LCTL);
                reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
index efaf9a73cc79..50aa546b8c7a 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
@@ -47,23 +47,27 @@ static ssize_t ixgbe_dbg_reg_ops_read(struct file *filp, char __user *buffer,
                                    size_t count, loff_t *ppos)
 {
        struct ixgbe_adapter *adapter = filp->private_data;
-        char buf[256];
+        char *buf;
-        int bytes_not_copied;
        int len;
        /* don't allow partial reads */
        if (*ppos != 0)
                return 0;
-        len = snprintf(buf, sizeof(buf), "%s: %s\n",
+        buf = kasprintf(GFP_KERNEL, "%s: %s\n",
-                       adapter->netdev->name, ixgbe_dbg_reg_ops_buf);
+                        adapter->netdev->name,
-        if (count < len)
+                        ixgbe_dbg_reg_ops_buf);
+        if (!buf)
+                return -ENOMEM;
+        if (count < strlen(buf)) {
+                kfree(buf);
                return -ENOSPC;
-        bytes_not_copied = copy_to_user(buffer, buf, len);
+        }
-        if (bytes_not_copied < 0)
-                return bytes_not_copied;
+        len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
-        *ppos = len;
+        kfree(buf);
        return len;
 }
@@ -79,7 +83,7 @@ static ssize_t ixgbe_dbg_reg_ops_write(struct file *filp,
                                     size_t count, loff_t *ppos)
 {
        struct ixgbe_adapter *adapter = filp->private_data;
-        int bytes_not_copied;
+        int len;
        /* don't allow partial writes */
        if (*ppos != 0)
@@ -87,14 +91,15 @@ static ssize_t ixgbe_dbg_reg_ops_write(struct file *filp,
        if (count >= sizeof(ixgbe_dbg_reg_ops_buf))
                return -ENOSPC;
-        bytes_not_copied = copy_from_user(ixgbe_dbg_reg_ops_buf, buffer, count);
+        len = simple_write_to_buffer(ixgbe_dbg_reg_ops_buf,
-        if (bytes_not_copied < 0)
+                                     sizeof(ixgbe_dbg_reg_ops_buf)-1,
-                return bytes_not_copied;
+                                     ppos,
-        else if (bytes_not_copied < count)
+                                     buffer,
-                count -= bytes_not_copied;
+                                     count);
-        else
+        if (len < 0)
-                return -ENOSPC;
+                return len;
-        ixgbe_dbg_reg_ops_buf[count] = '\0';
+        ixgbe_dbg_reg_ops_buf[len] = '\0';
        if (strncmp(ixgbe_dbg_reg_ops_buf, "write", 5) == 0) {
                u32 reg, value;
@@ -147,23 +152,27 @@ static ssize_t ixgbe_dbg_netdev_ops_read(struct file *filp,
                                         size_t count, loff_t *ppos)
 {
        struct ixgbe_adapter *adapter = filp->private_data;
-        char buf[256];
+        char *buf;
-        int bytes_not_copied;
        int len;
        /* don't allow partial reads */
        if (*ppos != 0)
                return 0;
-        len = snprintf(buf, sizeof(buf), "%s: %s\n",
+        buf = kasprintf(GFP_KERNEL, "%s: %s\n",
-                       adapter->netdev->name, ixgbe_dbg_netdev_ops_buf);
+                        adapter->netdev->name,
-        if (count < len)
+                        ixgbe_dbg_netdev_ops_buf);
+        if (!buf)
+                return -ENOMEM;
+        if (count < strlen(buf)) {
+                kfree(buf);
                return -ENOSPC;
-        bytes_not_copied = copy_to_user(buffer, buf, len);
+        }
-        if (bytes_not_copied < 0)
-                return bytes_not_copied;
+        len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
-        *ppos = len;
+        kfree(buf);
        return len;
 }
@@ -179,7 +188,7 @@ static ssize_t ixgbe_dbg_netdev_ops_write(struct file *filp,
                                          size_t count, loff_t *ppos)
 {
        struct ixgbe_adapter *adapter = filp->private_data;
-        int bytes_not_copied;
+        int len;
        /* don't allow partial writes */
        if (*ppos != 0)
@@ -187,15 +196,15 @@ static ssize_t ixgbe_dbg_netdev_ops_write(struct file *filp,
        if (count >= sizeof(ixgbe_dbg_netdev_ops_buf))
                return -ENOSPC;
-        bytes_not_copied = copy_from_user(ixgbe_dbg_netdev_ops_buf,
+        len = simple_write_to_buffer(ixgbe_dbg_netdev_ops_buf,
-                                          buffer, count);
+                                     sizeof(ixgbe_dbg_netdev_ops_buf)-1,
-        if (bytes_not_copied < 0)
+                                     ppos,
-                return bytes_not_copied;
+                                     buffer,
-        else if (bytes_not_copied < count)
+                                     count);
-                count -= bytes_not_copied;
+        if (len < 0)
-        else
+                return len;
-                return -ENOSPC;
-        ixgbe_dbg_netdev_ops_buf[count] = '\0';
+        ixgbe_dbg_netdev_ops_buf[len] = '\0';
        if (strncmp(ixgbe_dbg_netdev_ops_buf, "tx_timeout", 10) == 0) {
                adapter->netdev->netdev_ops->ndo_tx_timeout(adapter->netdev);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 484bbedffe2a..79b834583188 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -1338,26 +1338,29 @@ static unsigned int ixgbe_get_headlen(unsigned char *data,
                if (hlen < sizeof(struct iphdr))
                        return hdr.network - data;
-                /* record next protocol */
+                /* record next protocol if header is present */
-                nexthdr = hdr.ipv4->protocol;
+                if (!hdr.ipv4->frag_off)
-                hdr.network += hlen;
+                        nexthdr = hdr.ipv4->protocol;
        } else if (protocol == __constant_htons(ETH_P_IPV6)) {
                if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
                        return max_len;
                /* record next protocol */
                nexthdr = hdr.ipv6->nexthdr;
-                hdr.network += sizeof(struct ipv6hdr);
+                hlen = sizeof(struct ipv6hdr);
 #ifdef IXGBE_FCOE
        } else if (protocol == __constant_htons(ETH_P_FCOE)) {
                if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
                        return max_len;
-                hdr.network += FCOE_HEADER_LEN;
+                hlen = FCOE_HEADER_LEN;
 #endif
        } else {
                return hdr.network - data;
        }
+        /* relocate pointer to start of L4 header */
+        hdr.network += hlen;
        /* finally sort out TCP/UDP */
        if (nexthdr == IPPROTO_TCP) {
                if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
diff --git a/drivers/net/ethernet/myricom/Kconfig b/drivers/net/ethernet/myricom/Kconfig
index 540f0c6fc160..3932d081fa21 100644
--- a/drivers/net/ethernet/myricom/Kconfig
+++ b/drivers/net/ethernet/myricom/Kconfig
@@ -23,7 +23,6 @@ config MYRI10GE
        depends on PCI && INET
        select FW_LOADER
        select CRC32
-        select INET_LRO
        ---help---
          This driver supports Myricom Myri-10G Dual Protocol interface in
          Ethernet mode. If the eeprom on your board is not recent enough,
diff --git a/drivers/net/ethernet/myricom/myri10ge/myri10ge.c b/drivers/net/ethernet/myricom/myri10ge/myri10ge.c
index 83516e3369c9..2fc984a03771 100644
--- a/drivers/net/ethernet/myricom/myri10ge/myri10ge.c
+++ b/drivers/net/ethernet/myricom/myri10ge/myri10ge.c
@@ -50,7 +50,6 @@
 #include <linux/etherdevice.h>
 #include <linux/if_ether.h>
 #include <linux/if_vlan.h>
-#include <linux/inet_lro.h>
 #include <linux/dca.h>
 #include <linux/ip.h>
 #include <linux/inet.h>
@@ -96,8 +95,6 @@ MODULE_LICENSE("Dual BSD/GPL");
 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
-#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
-#define MYRI10GE_LRO_MAX_PKTS 64
 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
@@ -165,8 +162,6 @@ struct myri10ge_rx_done {
        dma_addr_t bus;
        int cnt;
        int idx;
-        struct net_lro_mgr lro_mgr;
-        struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 };
 struct myri10ge_slice_netstats {
@@ -338,11 +333,6 @@ static int myri10ge_debug = -1;	/* defaults above */
 module_param(myri10ge_debug, int, 0);
 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
-static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
-module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
-MODULE_PARM_DESC(myri10ge_lro_max_pkts,
-                 "Number of LRO packets to be aggregated");
 static int myri10ge_fill_thresh = 256;
 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
@@ -1197,36 +1187,6 @@ static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
        }
 }
-static inline void
-myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
-                      struct skb_frag_struct *rx_frags, int len, int hlen)
-{
-        struct skb_frag_struct *skb_frags;
-        skb->len = skb->data_len = len;
-        /* attach the page(s) */
-        skb_frags = skb_shinfo(skb)->frags;
-        while (len > 0) {
-                memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
-                len -= skb_frag_size(rx_frags);
-                skb_frags++;
-                rx_frags++;
-                skb_shinfo(skb)->nr_frags++;
-        }
-        /* pskb_may_pull is not available in irq context, but
-         * skb_pull() (for ether_pad and eth_type_trans()) requires
-         * the beginning of the packet in skb_headlen(), move it
-         * manually */
-        skb_copy_to_linear_data(skb, va, hlen);
-        skb_shinfo(skb)->frags[0].page_offset += hlen;
-        skb_frag_size_sub(&skb_shinfo(skb)->frags[0], hlen);
-        skb->data_len -= hlen;
-        skb->tail += hlen;
-        skb_pull(skb, MXGEFW_PAD);
-}
 static void
 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
                        int bytes, int watchdog)
@@ -1304,18 +1264,50 @@ myri10ge_unmap_rx_page(struct pci_dev *pdev,
        }
 }
-#define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
+/*
-                                 * page into an skb */
+ * GRO does not support acceleration of tagged vlan frames, and
+ * this NIC does not support vlan tag offload, so we must pop
+ * the tag ourselves to be able to achieve GRO performance that
+ * is comparable to LRO.
+ */
+static inline void
+myri10ge_vlan_rx(struct net_device *dev, void *addr, struct sk_buff *skb)
+{
+        u8 *va;
+        struct vlan_ethhdr *veh;
+        struct skb_frag_struct *frag;
+        __wsum vsum;
+        va = addr;
+        va += MXGEFW_PAD;
+        veh = (struct vlan_ethhdr *)va;
+        if ((dev->features & NETIF_F_HW_VLAN_RX) == NETIF_F_HW_VLAN_RX &&
+            veh->h_vlan_proto == ntohs(ETH_P_8021Q)) {
+                /* fixup csum if needed */
+                if (skb->ip_summed == CHECKSUM_COMPLETE) {
+                        vsum = csum_partial(va + ETH_HLEN, VLAN_HLEN, 0);
+                        skb->csum = csum_sub(skb->csum, vsum);
+                }
+                /* pop tag */
+                __vlan_hwaccel_put_tag(skb, ntohs(veh->h_vlan_TCI));
+                memmove(va + VLAN_HLEN, va, 2 * ETH_ALEN);
+                skb->len -= VLAN_HLEN;
+                skb->data_len -= VLAN_HLEN;
+                frag = skb_shinfo(skb)->frags;
+                frag->page_offset += VLAN_HLEN;
+                skb_frag_size_set(frag, skb_frag_size(frag) - VLAN_HLEN);
+        }
+}
 static inline int
-myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum,
+myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum)
-                 bool lro_enabled)
 {
        struct myri10ge_priv *mgp = ss->mgp;
        struct sk_buff *skb;
-        struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
+        struct skb_frag_struct *rx_frags;
        struct myri10ge_rx_buf *rx;
-        int i, idx, hlen, remainder, bytes;
+        int i, idx, remainder, bytes;
        struct pci_dev *pdev = mgp->pdev;
        struct net_device *dev = mgp->dev;
        u8 *va;
@@ -1332,67 +1324,48 @@ myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum,
        idx = rx->cnt & rx->mask;
        va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
        prefetch(va);
+        skb = napi_get_frags(&ss->napi);
+        if (unlikely(skb == NULL)) {
+                ss->stats.rx_dropped++;
+                for (i = 0, remainder = len; remainder > 0; i++) {
+                        myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
+                        put_page(rx->info[idx].page);
+                        rx->cnt++;
+                        idx = rx->cnt & rx->mask;
+                        remainder -= MYRI10GE_ALLOC_SIZE;
+                }
+                return 0;
+        }
+        rx_frags = skb_shinfo(skb)->frags;
        /* Fill skb_frag_struct(s) with data from our receive */
        for (i = 0, remainder = len; remainder > 0; i++) {
                myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
-                __skb_frag_set_page(&rx_frags[i], rx->info[idx].page);
+                skb_fill_page_desc(skb, i, rx->info[idx].page,
-                rx_frags[i].page_offset = rx->info[idx].page_offset;
+                                   rx->info[idx].page_offset,
-                if (remainder < MYRI10GE_ALLOC_SIZE)
+                                   remainder < MYRI10GE_ALLOC_SIZE ?
-                        skb_frag_size_set(&rx_frags[i], remainder);
+                                   remainder : MYRI10GE_ALLOC_SIZE);
-                else
-                        skb_frag_size_set(&rx_frags[i], MYRI10GE_ALLOC_SIZE);
                rx->cnt++;
                idx = rx->cnt & rx->mask;
                remainder -= MYRI10GE_ALLOC_SIZE;
        }
-        if (lro_enabled) {
+        /* remove padding */
-                rx_frags[0].page_offset += MXGEFW_PAD;
+        rx_frags[0].page_offset += MXGEFW_PAD;
-                skb_frag_size_sub(&rx_frags[0], MXGEFW_PAD);
+        rx_frags[0].size -= MXGEFW_PAD;
-                len -= MXGEFW_PAD;
+        len -= MXGEFW_PAD;
-                lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
-                                  /* opaque, will come back in get_frag_header */
-                                  len, len,
-                                  (void *)(__force unsigned long)csum, csum);
-                return 1;
-        }
-        hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
-        /* allocate an skb to attach the page(s) to. This is done
-         * after trying LRO, so as to avoid skb allocation overheads */
-        skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
-        if (unlikely(skb == NULL)) {
-                ss->stats.rx_dropped++;
-                do {
-                        i--;
-                        __skb_frag_unref(&rx_frags[i]);
-                } while (i != 0);
-                return 0;
-        }
-        /* Attach the pages to the skb, and trim off any padding */
+        skb->len = len;
-        myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
+        skb->data_len = len;
-        if (skb_frag_size(&skb_shinfo(skb)->frags[0]) <= 0) {
+        skb->truesize += len;
-                skb_frag_unref(skb, 0);
+        if (dev->features & NETIF_F_RXCSUM) {
-                skb_shinfo(skb)->nr_frags = 0;
+                skb->ip_summed = CHECKSUM_COMPLETE;
-        } else {
+                skb->csum = csum;
-                skb->truesize += bytes * skb_shinfo(skb)->nr_frags;
        }
-        skb->protocol = eth_type_trans(skb, dev);
+        myri10ge_vlan_rx(mgp->dev, va, skb);
        skb_record_rx_queue(skb, ss - &mgp->ss[0]);
-        if (dev->features & NETIF_F_RXCSUM) {
+        napi_gro_frags(&ss->napi);
-                if ((skb->protocol == htons(ETH_P_IP)) ||
-                    (skb->protocol == htons(ETH_P_IPV6))) {
-                        skb->csum = csum;
-                        skb->ip_summed = CHECKSUM_COMPLETE;
-                } else
-                        myri10ge_vlan_ip_csum(skb, csum);
-        }
-        netif_receive_skb(skb);
        return 1;
 }
@@ -1480,18 +1453,11 @@ myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
        u16 length;
        __wsum checksum;
-        /*
-         * Prevent compiler from generating more than one ->features memory
-         * access to avoid theoretical race condition with functions that
-         * change NETIF_F_LRO flag at runtime.
-         */
-        bool lro_enabled = !!(ACCESS_ONCE(mgp->dev->features) & NETIF_F_LRO);
        while (rx_done->entry[idx].length != 0 && work_done < budget) {
                length = ntohs(rx_done->entry[idx].length);
                rx_done->entry[idx].length = 0;
                checksum = csum_unfold(rx_done->entry[idx].checksum);
-                rx_ok = myri10ge_rx_done(ss, length, checksum, lro_enabled);
+                rx_ok = myri10ge_rx_done(ss, length, checksum);
                rx_packets += rx_ok;
                rx_bytes += rx_ok * (unsigned long)length;
                cnt++;
@@ -1503,9 +1469,6 @@ myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
        ss->stats.rx_packets += rx_packets;
        ss->stats.rx_bytes += rx_bytes;
-        if (lro_enabled)
-                lro_flush_all(&rx_done->lro_mgr);
        /* restock receive rings if needed */
        if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
                myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
@@ -1779,7 +1742,6 @@ static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
        "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
        "rx_small_cnt", "rx_big_cnt",
        "wake_queue", "stop_queue", "tx_linearized",
-        "LRO aggregated", "LRO flushed", "LRO avg aggr", "LRO no_desc",
 };
 #define MYRI10GE_NET_STATS_LEN      21
@@ -1880,14 +1842,6 @@ myri10ge_get_ethtool_stats(struct net_device *netdev,
                data[i++] = (unsigned int)ss->tx.wake_queue;
                data[i++] = (unsigned int)ss->tx.stop_queue;
                data[i++] = (unsigned int)ss->tx.linearized;
-                data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
-                data[i++] = ss->rx_done.lro_mgr.stats.flushed;
-                if (ss->rx_done.lro_mgr.stats.flushed)
-                        data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
-                            ss->rx_done.lro_mgr.stats.flushed;
-                else
-                        data[i++] = 0;
-                data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
        }
 }
@@ -2271,67 +2225,6 @@ static void myri10ge_free_irq(struct myri10ge_priv *mgp)
                pci_disable_msix(pdev);
 }
-static int
-myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
-                         void **ip_hdr, void **tcpudp_hdr,
-                         u64 * hdr_flags, void *priv)
-{
-        struct ethhdr *eh;
-        struct vlan_ethhdr *veh;
-        struct iphdr *iph;
-        u8 *va = skb_frag_address(frag);
-        unsigned long ll_hlen;
-        /* passed opaque through lro_receive_frags() */
-        __wsum csum = (__force __wsum) (unsigned long)priv;
-        /* find the mac header, aborting if not IPv4 */
-        eh = (struct ethhdr *)va;
-        *mac_hdr = eh;
-        ll_hlen = ETH_HLEN;
-        if (eh->h_proto != htons(ETH_P_IP)) {
-                if (eh->h_proto == htons(ETH_P_8021Q)) {
-                        veh = (struct vlan_ethhdr *)va;
-                        if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
-                                return -1;
-                        ll_hlen += VLAN_HLEN;
-                        /*
-                         *  HW checksum starts ETH_HLEN bytes into
-                         *  frame, so we must subtract off the VLAN
-                         *  header's checksum before csum can be used
-                         */
-                        csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
-                                                           VLAN_HLEN, 0));
-                } else {
-                        return -1;
-                }
-        }
-        *hdr_flags = LRO_IPV4;
-        iph = (struct iphdr *)(va + ll_hlen);
-        *ip_hdr = iph;
-        if (iph->protocol != IPPROTO_TCP)
-                return -1;
-        if (ip_is_fragment(iph))
-                return -1;
-        *hdr_flags |= LRO_TCP;
-        *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
-        /* verify the IP checksum */
-        if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
-                return -1;
-        /* verify the  checksum */
-        if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
-                                       ntohs(iph->tot_len) - (iph->ihl << 2),
-                                       IPPROTO_TCP, csum)))
-                return -1;
-        return 0;
-}
 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
 {
        struct myri10ge_cmd cmd;
@@ -2402,7 +2295,6 @@ static int myri10ge_open(struct net_device *dev)
        struct myri10ge_cmd cmd;
        int i, status, big_pow2, slice;
        u8 *itable;
-        struct net_lro_mgr *lro_mgr;
        if (mgp->running != MYRI10GE_ETH_STOPPED)
                return -EBUSY;
@@ -2513,19 +2405,6 @@ static int myri10ge_open(struct net_device *dev)
                        goto abort_with_rings;
                }
-                lro_mgr = &ss->rx_done.lro_mgr;
-                lro_mgr->dev = dev;
-                lro_mgr->features = LRO_F_NAPI;
-                lro_mgr->ip_summed = CHECKSUM_COMPLETE;
-                lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
-                lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
-                lro_mgr->lro_arr = ss->rx_done.lro_desc;
-                lro_mgr->get_frag_header = myri10ge_get_frag_header;
-                lro_mgr->max_aggr = myri10ge_lro_max_pkts;
-                lro_mgr->frag_align_pad = 2;
-                if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
-                        lro_mgr->max_aggr = MAX_SKB_FRAGS;
                /* must happen prior to any irq */
                napi_enable(&(ss)->napi);
        }
@@ -3143,15 +3022,6 @@ static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
        return 0;
 }
-static netdev_features_t myri10ge_fix_features(struct net_device *dev,
-        netdev_features_t features)
-{
-        if (!(features & NETIF_F_RXCSUM))
-                features &= ~NETIF_F_LRO;
-        return features;
-}
 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
 {
        struct myri10ge_priv *mgp = netdev_priv(dev);
@@ -3878,7 +3748,6 @@ static const struct net_device_ops myri10ge_netdev_ops = {
        .ndo_get_stats64        = myri10ge_get_stats,
        .ndo_validate_addr      = eth_validate_addr,
        .ndo_change_mtu         = myri10ge_change_mtu,
-        .ndo_fix_features       = myri10ge_fix_features,
        .ndo_set_rx_mode        = myri10ge_set_multicast_list,
        .ndo_set_mac_address    = myri10ge_set_mac_address,
 };
@@ -4018,7 +3887,11 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        netdev->netdev_ops = &myri10ge_netdev_ops;
        netdev->mtu = myri10ge_initial_mtu;
-        netdev->hw_features = mgp->features | NETIF_F_LRO | NETIF_F_RXCSUM;
+        netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
+        /* fake NETIF_F_HW_VLAN_RX for good GRO performance */
+        netdev->hw_features |= NETIF_F_HW_VLAN_RX;
        netdev->features = netdev->hw_features;
        if (dac_enabled)