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-rw-r--r--drivers/net/ethernet/Kconfig1
-rw-r--r--drivers/net/ethernet/Makefile1
-rw-r--r--drivers/net/ethernet/micrel/Kconfig64
-rw-r--r--drivers/net/ethernet/micrel/Makefile9
-rw-r--r--drivers/net/ethernet/micrel/ks8695net.c1656
-rw-r--r--drivers/net/ethernet/micrel/ks8695net.h107
-rw-r--r--drivers/net/ethernet/micrel/ks8842.c1284
-rw-r--r--drivers/net/ethernet/micrel/ks8851.c1737
-rw-r--r--drivers/net/ethernet/micrel/ks8851.h309
-rw-r--r--drivers/net/ethernet/micrel/ks8851_mll.c1680
-rw-r--r--drivers/net/ethernet/micrel/ksz884x.c7289
11 files changed, 14137 insertions, 0 deletions
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 924c287aaaa9..d90f47f3b782 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -32,6 +32,7 @@ source "drivers/net/ethernet/i825xx/Kconfig"
32source "drivers/net/ethernet/xscale/Kconfig" 32source "drivers/net/ethernet/xscale/Kconfig"
33source "drivers/net/ethernet/marvell/Kconfig" 33source "drivers/net/ethernet/marvell/Kconfig"
34source "drivers/net/ethernet/mellanox/Kconfig" 34source "drivers/net/ethernet/mellanox/Kconfig"
35source "drivers/net/ethernet/micrel/Kconfig"
35source "drivers/net/ethernet/myricom/Kconfig" 36source "drivers/net/ethernet/myricom/Kconfig"
36source "drivers/net/ethernet/natsemi/Kconfig" 37source "drivers/net/ethernet/natsemi/Kconfig"
37source "drivers/net/ethernet/8390/Kconfig" 38source "drivers/net/ethernet/8390/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 025d7b763b91..cf27ae0eb3ec 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_NET_VENDOR_I825XX) += i825xx/
24obj-$(CONFIG_NET_VENDOR_XSCALE) += xscale/ 24obj-$(CONFIG_NET_VENDOR_XSCALE) += xscale/
25obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ 25obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
26obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ 26obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
27obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
27obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/ 28obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/
28obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/ 29obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/
29obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/ 30obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/
diff --git a/drivers/net/ethernet/micrel/Kconfig b/drivers/net/ethernet/micrel/Kconfig
new file mode 100644
index 000000000000..4227de6d11f2
--- /dev/null
+++ b/drivers/net/ethernet/micrel/Kconfig
@@ -0,0 +1,64 @@
1#
2# Micrel device configuration
3#
4
5config NET_VENDOR_MICREL
6 bool "Micrel devices"
7 depends on (HAS_IOMEM && DMA_ENGINE) || SPI || PCI || HAS_IOMEM || \
8 (ARM && ARCH_KS8695)
9 ---help---
10 If you have a network (Ethernet) card belonging to this class, say Y
11 and read the Ethernet-HOWTO, available from
12 <http://www.tldp.org/docs.html#howto>.
13
14 Note that the answer to this question doesn't directly affect the
15 kernel: saying N will just cause the configurator to skip all
16 the questions about Micrel devices. If you say Y, you will be asked
17 for your specific card in the following questions.
18
19if NET_VENDOR_MICREL
20
21config ARM_KS8695_ETHER
22 tristate "KS8695 Ethernet support"
23 depends on ARM && ARCH_KS8695
24 select MII
25 ---help---
26 If you wish to compile a kernel for the KS8695 and want to
27 use the internal ethernet then you should answer Y to this.
28
29config KS8842
30 tristate "Micrel KSZ8841/42 with generic bus interface"
31 depends on HAS_IOMEM && DMA_ENGINE
32 ---help---
33 This platform driver is for KSZ8841(1-port) / KS8842(2-port)
34 ethernet switch chip (managed, VLAN, QoS) from Micrel or
35 Timberdale(FPGA).
36
37config KS8851
38 tristate "Micrel KS8851 SPI"
39 depends on SPI
40 select MII
41 select CRC32
42 ---help---
43 SPI driver for Micrel KS8851 SPI attached network chip.
44
45config KS8851_MLL
46 tristate "Micrel KS8851 MLL"
47 depends on HAS_IOMEM
48 select MII
49 ---help---
50 This platform driver is for Micrel KS8851 Address/data bus
51 multiplexed network chip.
52
53config KSZ884X_PCI
54 tristate "Micrel KSZ8841/2 PCI"
55 depends on PCI
56 select MII
57 select CRC32
58 ---help---
59 This PCI driver is for Micrel KSZ8841/KSZ8842 PCI Ethernet chip.
60
61 To compile this driver as a module, choose M here. The module
62 will be called ksz884x.
63
64endif # NET_VENDOR_MICREL
diff --git a/drivers/net/ethernet/micrel/Makefile b/drivers/net/ethernet/micrel/Makefile
new file mode 100644
index 000000000000..c83e4bc50c73
--- /dev/null
+++ b/drivers/net/ethernet/micrel/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for the Micrel network device drivers.
3#
4
5obj-$(CONFIG_ARM_KS8695_ETHER) += ks8695net.o
6obj-$(CONFIG_KS8842) += ks8842.o
7obj-$(CONFIG_KS8851) += ks8851.o
8obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
9obj-$(CONFIG_KSZ884X_PCI) += ksz884x.o
diff --git a/drivers/net/ethernet/micrel/ks8695net.c b/drivers/net/ethernet/micrel/ks8695net.c
new file mode 100644
index 000000000000..c827a6097d02
--- /dev/null
+++ b/drivers/net/ethernet/micrel/ks8695net.c
@@ -0,0 +1,1656 @@
1/*
2 * Micrel KS8695 (Centaur) Ethernet.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * Copyright 2008 Simtec Electronics
15 * Daniel Silverstone <dsilvers@simtec.co.uk>
16 * Vincent Sanders <vince@simtec.co.uk>
17 */
18
19#include <linux/dma-mapping.h>
20#include <linux/module.h>
21#include <linux/ioport.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/skbuff.h>
27#include <linux/spinlock.h>
28#include <linux/crc32.h>
29#include <linux/mii.h>
30#include <linux/ethtool.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/irq.h>
34#include <linux/io.h>
35#include <linux/slab.h>
36
37#include <asm/irq.h>
38
39#include <mach/regs-switch.h>
40#include <mach/regs-misc.h>
41#include <asm/mach/irq.h>
42#include <mach/regs-irq.h>
43
44#include "ks8695net.h"
45
46#define MODULENAME "ks8695_ether"
47#define MODULEVERSION "1.02"
48
49/*
50 * Transmit and device reset timeout, default 5 seconds.
51 */
52static int watchdog = 5000;
53
54/* Hardware structures */
55
56/**
57 * struct rx_ring_desc - Receive descriptor ring element
58 * @status: The status of the descriptor element (E.g. who owns it)
59 * @length: The number of bytes in the block pointed to by data_ptr
60 * @data_ptr: The physical address of the data block to receive into
61 * @next_desc: The physical address of the next descriptor element.
62 */
63struct rx_ring_desc {
64 __le32 status;
65 __le32 length;
66 __le32 data_ptr;
67 __le32 next_desc;
68};
69
70/**
71 * struct tx_ring_desc - Transmit descriptor ring element
72 * @owner: Who owns the descriptor
73 * @status: The number of bytes in the block pointed to by data_ptr
74 * @data_ptr: The physical address of the data block to receive into
75 * @next_desc: The physical address of the next descriptor element.
76 */
77struct tx_ring_desc {
78 __le32 owner;
79 __le32 status;
80 __le32 data_ptr;
81 __le32 next_desc;
82};
83
84/**
85 * struct ks8695_skbuff - sk_buff wrapper for rx/tx rings.
86 * @skb: The buffer in the ring
87 * @dma_ptr: The mapped DMA pointer of the buffer
88 * @length: The number of bytes mapped to dma_ptr
89 */
90struct ks8695_skbuff {
91 struct sk_buff *skb;
92 dma_addr_t dma_ptr;
93 u32 length;
94};
95
96/* Private device structure */
97
98#define MAX_TX_DESC 8
99#define MAX_TX_DESC_MASK 0x7
100#define MAX_RX_DESC 16
101#define MAX_RX_DESC_MASK 0xf
102
103/*napi_weight have better more than rx DMA buffers*/
104#define NAPI_WEIGHT 64
105
106#define MAX_RXBUF_SIZE 0x700
107
108#define TX_RING_DMA_SIZE (sizeof(struct tx_ring_desc) * MAX_TX_DESC)
109#define RX_RING_DMA_SIZE (sizeof(struct rx_ring_desc) * MAX_RX_DESC)
110#define RING_DMA_SIZE (TX_RING_DMA_SIZE + RX_RING_DMA_SIZE)
111
112/**
113 * enum ks8695_dtype - Device type
114 * @KS8695_DTYPE_WAN: This device is a WAN interface
115 * @KS8695_DTYPE_LAN: This device is a LAN interface
116 * @KS8695_DTYPE_HPNA: This device is an HPNA interface
117 */
118enum ks8695_dtype {
119 KS8695_DTYPE_WAN,
120 KS8695_DTYPE_LAN,
121 KS8695_DTYPE_HPNA,
122};
123
124/**
125 * struct ks8695_priv - Private data for the KS8695 Ethernet
126 * @in_suspend: Flag to indicate if we're suspending/resuming
127 * @ndev: The net_device for this interface
128 * @dev: The platform device object for this interface
129 * @dtype: The type of this device
130 * @io_regs: The ioremapped registers for this interface
131 * @napi : Add support NAPI for Rx
132 * @rx_irq_name: The textual name of the RX IRQ from the platform data
133 * @tx_irq_name: The textual name of the TX IRQ from the platform data
134 * @link_irq_name: The textual name of the link IRQ from the
135 * platform data if available
136 * @rx_irq: The IRQ number for the RX IRQ
137 * @tx_irq: The IRQ number for the TX IRQ
138 * @link_irq: The IRQ number for the link IRQ if available
139 * @regs_req: The resource request for the registers region
140 * @phyiface_req: The resource request for the phy/switch region
141 * if available
142 * @phyiface_regs: The ioremapped registers for the phy/switch if available
143 * @ring_base: The base pointer of the dma coherent memory for the rings
144 * @ring_base_dma: The DMA mapped equivalent of ring_base
145 * @tx_ring: The pointer in ring_base of the TX ring
146 * @tx_ring_used: The number of slots in the TX ring which are occupied
147 * @tx_ring_next_slot: The next slot to fill in the TX ring
148 * @tx_ring_dma: The DMA mapped equivalent of tx_ring
149 * @tx_buffers: The sk_buff mappings for the TX ring
150 * @txq_lock: A lock to protect the tx_buffers tx_ring_used etc variables
151 * @rx_ring: The pointer in ring_base of the RX ring
152 * @rx_ring_dma: The DMA mapped equivalent of rx_ring
153 * @rx_buffers: The sk_buff mappings for the RX ring
154 * @next_rx_desc_read: The next RX descriptor to read from on IRQ
155 * @rx_lock: A lock to protect Rx irq function
156 * @msg_enable: The flags for which messages to emit
157 */
158struct ks8695_priv {
159 int in_suspend;
160 struct net_device *ndev;
161 struct device *dev;
162 enum ks8695_dtype dtype;
163 void __iomem *io_regs;
164
165 struct napi_struct napi;
166
167 const char *rx_irq_name, *tx_irq_name, *link_irq_name;
168 int rx_irq, tx_irq, link_irq;
169
170 struct resource *regs_req, *phyiface_req;
171 void __iomem *phyiface_regs;
172
173 void *ring_base;
174 dma_addr_t ring_base_dma;
175
176 struct tx_ring_desc *tx_ring;
177 int tx_ring_used;
178 int tx_ring_next_slot;
179 dma_addr_t tx_ring_dma;
180 struct ks8695_skbuff tx_buffers[MAX_TX_DESC];
181 spinlock_t txq_lock;
182
183 struct rx_ring_desc *rx_ring;
184 dma_addr_t rx_ring_dma;
185 struct ks8695_skbuff rx_buffers[MAX_RX_DESC];
186 int next_rx_desc_read;
187 spinlock_t rx_lock;
188
189 int msg_enable;
190};
191
192/* Register access */
193
194/**
195 * ks8695_readreg - Read from a KS8695 ethernet register
196 * @ksp: The device to read from
197 * @reg: The register to read
198 */
199static inline u32
200ks8695_readreg(struct ks8695_priv *ksp, int reg)
201{
202 return readl(ksp->io_regs + reg);
203}
204
205/**
206 * ks8695_writereg - Write to a KS8695 ethernet register
207 * @ksp: The device to write to
208 * @reg: The register to write
209 * @value: The value to write to the register
210 */
211static inline void
212ks8695_writereg(struct ks8695_priv *ksp, int reg, u32 value)
213{
214 writel(value, ksp->io_regs + reg);
215}
216
217/* Utility functions */
218
219/**
220 * ks8695_port_type - Retrieve port-type as user-friendly string
221 * @ksp: The device to return the type for
222 *
223 * Returns a string indicating which of the WAN, LAN or HPNA
224 * ports this device is likely to represent.
225 */
226static const char *
227ks8695_port_type(struct ks8695_priv *ksp)
228{
229 switch (ksp->dtype) {
230 case KS8695_DTYPE_LAN:
231 return "LAN";
232 case KS8695_DTYPE_WAN:
233 return "WAN";
234 case KS8695_DTYPE_HPNA:
235 return "HPNA";
236 }
237
238 return "UNKNOWN";
239}
240
241/**
242 * ks8695_update_mac - Update the MAC registers in the device
243 * @ksp: The device to update
244 *
245 * Updates the MAC registers in the KS8695 device from the address in the
246 * net_device structure associated with this interface.
247 */
248static void
249ks8695_update_mac(struct ks8695_priv *ksp)
250{
251 /* Update the HW with the MAC from the net_device */
252 struct net_device *ndev = ksp->ndev;
253 u32 machigh, maclow;
254
255 maclow = ((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
256 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5] << 0));
257 machigh = ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1] << 0));
258
259 ks8695_writereg(ksp, KS8695_MAL, maclow);
260 ks8695_writereg(ksp, KS8695_MAH, machigh);
261
262}
263
264/**
265 * ks8695_refill_rxbuffers - Re-fill the RX buffer ring
266 * @ksp: The device to refill
267 *
268 * Iterates the RX ring of the device looking for empty slots.
269 * For each empty slot, we allocate and map a new SKB and give it
270 * to the hardware.
271 * This can be called from interrupt context safely.
272 */
273static void
274ks8695_refill_rxbuffers(struct ks8695_priv *ksp)
275{
276 /* Run around the RX ring, filling in any missing sk_buff's */
277 int buff_n;
278
279 for (buff_n = 0; buff_n < MAX_RX_DESC; ++buff_n) {
280 if (!ksp->rx_buffers[buff_n].skb) {
281 struct sk_buff *skb = dev_alloc_skb(MAX_RXBUF_SIZE);
282 dma_addr_t mapping;
283
284 ksp->rx_buffers[buff_n].skb = skb;
285 if (skb == NULL) {
286 /* Failed to allocate one, perhaps
287 * we'll try again later.
288 */
289 break;
290 }
291
292 mapping = dma_map_single(ksp->dev, skb->data,
293 MAX_RXBUF_SIZE,
294 DMA_FROM_DEVICE);
295 if (unlikely(dma_mapping_error(ksp->dev, mapping))) {
296 /* Failed to DMA map this SKB, try later */
297 dev_kfree_skb_irq(skb);
298 ksp->rx_buffers[buff_n].skb = NULL;
299 break;
300 }
301 ksp->rx_buffers[buff_n].dma_ptr = mapping;
302 skb->dev = ksp->ndev;
303 ksp->rx_buffers[buff_n].length = MAX_RXBUF_SIZE;
304
305 /* Record this into the DMA ring */
306 ksp->rx_ring[buff_n].data_ptr = cpu_to_le32(mapping);
307 ksp->rx_ring[buff_n].length =
308 cpu_to_le32(MAX_RXBUF_SIZE);
309
310 wmb();
311
312 /* And give ownership over to the hardware */
313 ksp->rx_ring[buff_n].status = cpu_to_le32(RDES_OWN);
314 }
315 }
316}
317
318/* Maximum number of multicast addresses which the KS8695 HW supports */
319#define KS8695_NR_ADDRESSES 16
320
321/**
322 * ks8695_init_partial_multicast - Init the mcast addr registers
323 * @ksp: The device to initialise
324 * @addr: The multicast address list to use
325 * @nr_addr: The number of addresses in the list
326 *
327 * This routine is a helper for ks8695_set_multicast - it writes
328 * the additional-address registers in the KS8695 ethernet device
329 * and cleans up any others left behind.
330 */
331static void
332ks8695_init_partial_multicast(struct ks8695_priv *ksp,
333 struct net_device *ndev)
334{
335 u32 low, high;
336 int i;
337 struct netdev_hw_addr *ha;
338
339 i = 0;
340 netdev_for_each_mc_addr(ha, ndev) {
341 /* Ran out of space in chip? */
342 BUG_ON(i == KS8695_NR_ADDRESSES);
343
344 low = (ha->addr[2] << 24) | (ha->addr[3] << 16) |
345 (ha->addr[4] << 8) | (ha->addr[5]);
346 high = (ha->addr[0] << 8) | (ha->addr[1]);
347
348 ks8695_writereg(ksp, KS8695_AAL_(i), low);
349 ks8695_writereg(ksp, KS8695_AAH_(i), AAH_E | high);
350 i++;
351 }
352
353 /* Clear the remaining Additional Station Addresses */
354 for (; i < KS8695_NR_ADDRESSES; i++) {
355 ks8695_writereg(ksp, KS8695_AAL_(i), 0);
356 ks8695_writereg(ksp, KS8695_AAH_(i), 0);
357 }
358}
359
360/* Interrupt handling */
361
362/**
363 * ks8695_tx_irq - Transmit IRQ handler
364 * @irq: The IRQ which went off (ignored)
365 * @dev_id: The net_device for the interrupt
366 *
367 * Process the TX ring, clearing out any transmitted slots.
368 * Allows the net_device to pass us new packets once slots are
369 * freed.
370 */
371static irqreturn_t
372ks8695_tx_irq(int irq, void *dev_id)
373{
374 struct net_device *ndev = (struct net_device *)dev_id;
375 struct ks8695_priv *ksp = netdev_priv(ndev);
376 int buff_n;
377
378 for (buff_n = 0; buff_n < MAX_TX_DESC; ++buff_n) {
379 if (ksp->tx_buffers[buff_n].skb &&
380 !(ksp->tx_ring[buff_n].owner & cpu_to_le32(TDES_OWN))) {
381 rmb();
382 /* An SKB which is not owned by HW is present */
383 /* Update the stats for the net_device */
384 ndev->stats.tx_packets++;
385 ndev->stats.tx_bytes += ksp->tx_buffers[buff_n].length;
386
387 /* Free the packet from the ring */
388 ksp->tx_ring[buff_n].data_ptr = 0;
389
390 /* Free the sk_buff */
391 dma_unmap_single(ksp->dev,
392 ksp->tx_buffers[buff_n].dma_ptr,
393 ksp->tx_buffers[buff_n].length,
394 DMA_TO_DEVICE);
395 dev_kfree_skb_irq(ksp->tx_buffers[buff_n].skb);
396 ksp->tx_buffers[buff_n].skb = NULL;
397 ksp->tx_ring_used--;
398 }
399 }
400
401 netif_wake_queue(ndev);
402
403 return IRQ_HANDLED;
404}
405
406/**
407 * ks8695_get_rx_enable_bit - Get rx interrupt enable/status bit
408 * @ksp: Private data for the KS8695 Ethernet
409 *
410 * For KS8695 document:
411 * Interrupt Enable Register (offset 0xE204)
412 * Bit29 : WAN MAC Receive Interrupt Enable
413 * Bit16 : LAN MAC Receive Interrupt Enable
414 * Interrupt Status Register (Offset 0xF208)
415 * Bit29: WAN MAC Receive Status
416 * Bit16: LAN MAC Receive Status
417 * So, this Rx interrrupt enable/status bit number is equal
418 * as Rx IRQ number.
419 */
420static inline u32 ks8695_get_rx_enable_bit(struct ks8695_priv *ksp)
421{
422 return ksp->rx_irq;
423}
424
425/**
426 * ks8695_rx_irq - Receive IRQ handler
427 * @irq: The IRQ which went off (ignored)
428 * @dev_id: The net_device for the interrupt
429 *
430 * Inform NAPI that packet reception needs to be scheduled
431 */
432
433static irqreturn_t
434ks8695_rx_irq(int irq, void *dev_id)
435{
436 struct net_device *ndev = (struct net_device *)dev_id;
437 struct ks8695_priv *ksp = netdev_priv(ndev);
438
439 spin_lock(&ksp->rx_lock);
440
441 if (napi_schedule_prep(&ksp->napi)) {
442 unsigned long status = readl(KS8695_IRQ_VA + KS8695_INTEN);
443 unsigned long mask_bit = 1 << ks8695_get_rx_enable_bit(ksp);
444 /*disable rx interrupt*/
445 status &= ~mask_bit;
446 writel(status , KS8695_IRQ_VA + KS8695_INTEN);
447 __napi_schedule(&ksp->napi);
448 }
449
450 spin_unlock(&ksp->rx_lock);
451 return IRQ_HANDLED;
452}
453
454/**
455 * ks8695_rx - Receive packets called by NAPI poll method
456 * @ksp: Private data for the KS8695 Ethernet
457 * @budget: Number of packets allowed to process
458 */
459static int ks8695_rx(struct ks8695_priv *ksp, int budget)
460{
461 struct net_device *ndev = ksp->ndev;
462 struct sk_buff *skb;
463 int buff_n;
464 u32 flags;
465 int pktlen;
466 int received = 0;
467
468 buff_n = ksp->next_rx_desc_read;
469 while (received < budget
470 && ksp->rx_buffers[buff_n].skb
471 && (!(ksp->rx_ring[buff_n].status &
472 cpu_to_le32(RDES_OWN)))) {
473 rmb();
474 flags = le32_to_cpu(ksp->rx_ring[buff_n].status);
475
476 /* Found an SKB which we own, this means we
477 * received a packet
478 */
479 if ((flags & (RDES_FS | RDES_LS)) !=
480 (RDES_FS | RDES_LS)) {
481 /* This packet is not the first and
482 * the last segment. Therefore it is
483 * a "spanning" packet and we can't
484 * handle it
485 */
486 goto rx_failure;
487 }
488
489 if (flags & (RDES_ES | RDES_RE)) {
490 /* It's an error packet */
491 ndev->stats.rx_errors++;
492 if (flags & RDES_TL)
493 ndev->stats.rx_length_errors++;
494 if (flags & RDES_RF)
495 ndev->stats.rx_length_errors++;
496 if (flags & RDES_CE)
497 ndev->stats.rx_crc_errors++;
498 if (flags & RDES_RE)
499 ndev->stats.rx_missed_errors++;
500
501 goto rx_failure;
502 }
503
504 pktlen = flags & RDES_FLEN;
505 pktlen -= 4; /* Drop the CRC */
506
507 /* Retrieve the sk_buff */
508 skb = ksp->rx_buffers[buff_n].skb;
509
510 /* Clear it from the ring */
511 ksp->rx_buffers[buff_n].skb = NULL;
512 ksp->rx_ring[buff_n].data_ptr = 0;
513
514 /* Unmap the SKB */
515 dma_unmap_single(ksp->dev,
516 ksp->rx_buffers[buff_n].dma_ptr,
517 ksp->rx_buffers[buff_n].length,
518 DMA_FROM_DEVICE);
519
520 /* Relinquish the SKB to the network layer */
521 skb_put(skb, pktlen);
522 skb->protocol = eth_type_trans(skb, ndev);
523 netif_receive_skb(skb);
524
525 /* Record stats */
526 ndev->stats.rx_packets++;
527 ndev->stats.rx_bytes += pktlen;
528 goto rx_finished;
529
530rx_failure:
531 /* This ring entry is an error, but we can
532 * re-use the skb
533 */
534 /* Give the ring entry back to the hardware */
535 ksp->rx_ring[buff_n].status = cpu_to_le32(RDES_OWN);
536rx_finished:
537 received++;
538 buff_n = (buff_n + 1) & MAX_RX_DESC_MASK;
539 }
540
541 /* And note which RX descriptor we last did */
542 ksp->next_rx_desc_read = buff_n;
543
544 /* And refill the buffers */
545 ks8695_refill_rxbuffers(ksp);
546
547 /* Kick the RX DMA engine, in case it became suspended */
548 ks8695_writereg(ksp, KS8695_DRSC, 0);
549
550 return received;
551}
552
553
554/**
555 * ks8695_poll - Receive packet by NAPI poll method
556 * @ksp: Private data for the KS8695 Ethernet
557 * @budget: The remaining number packets for network subsystem
558 *
559 * Invoked by the network core when it requests for new
560 * packets from the driver
561 */
562static int ks8695_poll(struct napi_struct *napi, int budget)
563{
564 struct ks8695_priv *ksp = container_of(napi, struct ks8695_priv, napi);
565 unsigned long work_done;
566
567 unsigned long isr = readl(KS8695_IRQ_VA + KS8695_INTEN);
568 unsigned long mask_bit = 1 << ks8695_get_rx_enable_bit(ksp);
569
570 work_done = ks8695_rx(ksp, budget);
571
572 if (work_done < budget) {
573 unsigned long flags;
574 spin_lock_irqsave(&ksp->rx_lock, flags);
575 __napi_complete(napi);
576 /*enable rx interrupt*/
577 writel(isr | mask_bit, KS8695_IRQ_VA + KS8695_INTEN);
578 spin_unlock_irqrestore(&ksp->rx_lock, flags);
579 }
580 return work_done;
581}
582
583/**
584 * ks8695_link_irq - Link change IRQ handler
585 * @irq: The IRQ which went off (ignored)
586 * @dev_id: The net_device for the interrupt
587 *
588 * The WAN interface can generate an IRQ when the link changes,
589 * report this to the net layer and the user.
590 */
591static irqreturn_t
592ks8695_link_irq(int irq, void *dev_id)
593{
594 struct net_device *ndev = (struct net_device *)dev_id;
595 struct ks8695_priv *ksp = netdev_priv(ndev);
596 u32 ctrl;
597
598 ctrl = readl(ksp->phyiface_regs + KS8695_WMC);
599 if (ctrl & WMC_WLS) {
600 netif_carrier_on(ndev);
601 if (netif_msg_link(ksp))
602 dev_info(ksp->dev,
603 "%s: Link is now up (10%sMbps/%s-duplex)\n",
604 ndev->name,
605 (ctrl & WMC_WSS) ? "0" : "",
606 (ctrl & WMC_WDS) ? "Full" : "Half");
607 } else {
608 netif_carrier_off(ndev);
609 if (netif_msg_link(ksp))
610 dev_info(ksp->dev, "%s: Link is now down.\n",
611 ndev->name);
612 }
613
614 return IRQ_HANDLED;
615}
616
617
618/* KS8695 Device functions */
619
620/**
621 * ks8695_reset - Reset a KS8695 ethernet interface
622 * @ksp: The interface to reset
623 *
624 * Perform an engine reset of the interface and re-program it
625 * with sensible defaults.
626 */
627static void
628ks8695_reset(struct ks8695_priv *ksp)
629{
630 int reset_timeout = watchdog;
631 /* Issue the reset via the TX DMA control register */
632 ks8695_writereg(ksp, KS8695_DTXC, DTXC_TRST);
633 while (reset_timeout--) {
634 if (!(ks8695_readreg(ksp, KS8695_DTXC) & DTXC_TRST))
635 break;
636 msleep(1);
637 }
638
639 if (reset_timeout < 0) {
640 dev_crit(ksp->dev,
641 "Timeout waiting for DMA engines to reset\n");
642 /* And blithely carry on */
643 }
644
645 /* Definitely wait long enough before attempting to program
646 * the engines
647 */
648 msleep(10);
649
650 /* RX: unicast and broadcast */
651 ks8695_writereg(ksp, KS8695_DRXC, DRXC_RU | DRXC_RB);
652 /* TX: pad and add CRC */
653 ks8695_writereg(ksp, KS8695_DTXC, DTXC_TEP | DTXC_TAC);
654}
655
656/**
657 * ks8695_shutdown - Shut down a KS8695 ethernet interface
658 * @ksp: The interface to shut down
659 *
660 * This disables packet RX/TX, cleans up IRQs, drains the rings,
661 * and basically places the interface into a clean shutdown
662 * state.
663 */
664static void
665ks8695_shutdown(struct ks8695_priv *ksp)
666{
667 u32 ctrl;
668 int buff_n;
669
670 /* Disable packet transmission */
671 ctrl = ks8695_readreg(ksp, KS8695_DTXC);
672 ks8695_writereg(ksp, KS8695_DTXC, ctrl & ~DTXC_TE);
673
674 /* Disable packet reception */
675 ctrl = ks8695_readreg(ksp, KS8695_DRXC);
676 ks8695_writereg(ksp, KS8695_DRXC, ctrl & ~DRXC_RE);
677
678 /* Release the IRQs */
679 free_irq(ksp->rx_irq, ksp->ndev);
680 free_irq(ksp->tx_irq, ksp->ndev);
681 if (ksp->link_irq != -1)
682 free_irq(ksp->link_irq, ksp->ndev);
683
684 /* Throw away any pending TX packets */
685 for (buff_n = 0; buff_n < MAX_TX_DESC; ++buff_n) {
686 if (ksp->tx_buffers[buff_n].skb) {
687 /* Remove this SKB from the TX ring */
688 ksp->tx_ring[buff_n].owner = 0;
689 ksp->tx_ring[buff_n].status = 0;
690 ksp->tx_ring[buff_n].data_ptr = 0;
691
692 /* Unmap and bin this SKB */
693 dma_unmap_single(ksp->dev,
694 ksp->tx_buffers[buff_n].dma_ptr,
695 ksp->tx_buffers[buff_n].length,
696 DMA_TO_DEVICE);
697 dev_kfree_skb_irq(ksp->tx_buffers[buff_n].skb);
698 ksp->tx_buffers[buff_n].skb = NULL;
699 }
700 }
701
702 /* Purge the RX buffers */
703 for (buff_n = 0; buff_n < MAX_RX_DESC; ++buff_n) {
704 if (ksp->rx_buffers[buff_n].skb) {
705 /* Remove the SKB from the RX ring */
706 ksp->rx_ring[buff_n].status = 0;
707 ksp->rx_ring[buff_n].data_ptr = 0;
708
709 /* Unmap and bin the SKB */
710 dma_unmap_single(ksp->dev,
711 ksp->rx_buffers[buff_n].dma_ptr,
712 ksp->rx_buffers[buff_n].length,
713 DMA_FROM_DEVICE);
714 dev_kfree_skb_irq(ksp->rx_buffers[buff_n].skb);
715 ksp->rx_buffers[buff_n].skb = NULL;
716 }
717 }
718}
719
720
721/**
722 * ks8695_setup_irq - IRQ setup helper function
723 * @irq: The IRQ number to claim
724 * @irq_name: The name to give the IRQ claimant
725 * @handler: The function to call to handle the IRQ
726 * @ndev: The net_device to pass in as the dev_id argument to the handler
727 *
728 * Return 0 on success.
729 */
730static int
731ks8695_setup_irq(int irq, const char *irq_name,
732 irq_handler_t handler, struct net_device *ndev)
733{
734 int ret;
735
736 ret = request_irq(irq, handler, IRQF_SHARED, irq_name, ndev);
737
738 if (ret) {
739 dev_err(&ndev->dev, "failure to request IRQ %d\n", irq);
740 return ret;
741 }
742
743 return 0;
744}
745
746/**
747 * ks8695_init_net - Initialise a KS8695 ethernet interface
748 * @ksp: The interface to initialise
749 *
750 * This routine fills the RX ring, initialises the DMA engines,
751 * allocates the IRQs and then starts the packet TX and RX
752 * engines.
753 */
754static int
755ks8695_init_net(struct ks8695_priv *ksp)
756{
757 int ret;
758 u32 ctrl;
759
760 ks8695_refill_rxbuffers(ksp);
761
762 /* Initialise the DMA engines */
763 ks8695_writereg(ksp, KS8695_RDLB, (u32) ksp->rx_ring_dma);
764 ks8695_writereg(ksp, KS8695_TDLB, (u32) ksp->tx_ring_dma);
765
766 /* Request the IRQs */
767 ret = ks8695_setup_irq(ksp->rx_irq, ksp->rx_irq_name,
768 ks8695_rx_irq, ksp->ndev);
769 if (ret)
770 return ret;
771 ret = ks8695_setup_irq(ksp->tx_irq, ksp->tx_irq_name,
772 ks8695_tx_irq, ksp->ndev);
773 if (ret)
774 return ret;
775 if (ksp->link_irq != -1) {
776 ret = ks8695_setup_irq(ksp->link_irq, ksp->link_irq_name,
777 ks8695_link_irq, ksp->ndev);
778 if (ret)
779 return ret;
780 }
781
782 /* Set up the ring indices */
783 ksp->next_rx_desc_read = 0;
784 ksp->tx_ring_next_slot = 0;
785 ksp->tx_ring_used = 0;
786
787 /* Bring up transmission */
788 ctrl = ks8695_readreg(ksp, KS8695_DTXC);
789 /* Enable packet transmission */
790 ks8695_writereg(ksp, KS8695_DTXC, ctrl | DTXC_TE);
791
792 /* Bring up the reception */
793 ctrl = ks8695_readreg(ksp, KS8695_DRXC);
794 /* Enable packet reception */
795 ks8695_writereg(ksp, KS8695_DRXC, ctrl | DRXC_RE);
796 /* And start the DMA engine */
797 ks8695_writereg(ksp, KS8695_DRSC, 0);
798
799 /* All done */
800 return 0;
801}
802
803/**
804 * ks8695_release_device - HW resource release for KS8695 e-net
805 * @ksp: The device to be freed
806 *
807 * This unallocates io memory regions, dma-coherent regions etc
808 * which were allocated in ks8695_probe.
809 */
810static void
811ks8695_release_device(struct ks8695_priv *ksp)
812{
813 /* Unmap the registers */
814 iounmap(ksp->io_regs);
815 if (ksp->phyiface_regs)
816 iounmap(ksp->phyiface_regs);
817
818 /* And release the request */
819 release_resource(ksp->regs_req);
820 kfree(ksp->regs_req);
821 if (ksp->phyiface_req) {
822 release_resource(ksp->phyiface_req);
823 kfree(ksp->phyiface_req);
824 }
825
826 /* Free the ring buffers */
827 dma_free_coherent(ksp->dev, RING_DMA_SIZE,
828 ksp->ring_base, ksp->ring_base_dma);
829}
830
831/* Ethtool support */
832
833/**
834 * ks8695_get_msglevel - Get the messages enabled for emission
835 * @ndev: The network device to read from
836 */
837static u32
838ks8695_get_msglevel(struct net_device *ndev)
839{
840 struct ks8695_priv *ksp = netdev_priv(ndev);
841
842 return ksp->msg_enable;
843}
844
845/**
846 * ks8695_set_msglevel - Set the messages enabled for emission
847 * @ndev: The network device to configure
848 * @value: The messages to set for emission
849 */
850static void
851ks8695_set_msglevel(struct net_device *ndev, u32 value)
852{
853 struct ks8695_priv *ksp = netdev_priv(ndev);
854
855 ksp->msg_enable = value;
856}
857
858/**
859 * ks8695_wan_get_settings - Get device-specific settings.
860 * @ndev: The network device to read settings from
861 * @cmd: The ethtool structure to read into
862 */
863static int
864ks8695_wan_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
865{
866 struct ks8695_priv *ksp = netdev_priv(ndev);
867 u32 ctrl;
868
869 /* All ports on the KS8695 support these... */
870 cmd->supported = (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
871 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
872 SUPPORTED_TP | SUPPORTED_MII);
873 cmd->transceiver = XCVR_INTERNAL;
874
875 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
876 cmd->port = PORT_MII;
877 cmd->supported |= (SUPPORTED_Autoneg | SUPPORTED_Pause);
878 cmd->phy_address = 0;
879
880 ctrl = readl(ksp->phyiface_regs + KS8695_WMC);
881 if ((ctrl & WMC_WAND) == 0) {
882 /* auto-negotiation is enabled */
883 cmd->advertising |= ADVERTISED_Autoneg;
884 if (ctrl & WMC_WANA100F)
885 cmd->advertising |= ADVERTISED_100baseT_Full;
886 if (ctrl & WMC_WANA100H)
887 cmd->advertising |= ADVERTISED_100baseT_Half;
888 if (ctrl & WMC_WANA10F)
889 cmd->advertising |= ADVERTISED_10baseT_Full;
890 if (ctrl & WMC_WANA10H)
891 cmd->advertising |= ADVERTISED_10baseT_Half;
892 if (ctrl & WMC_WANAP)
893 cmd->advertising |= ADVERTISED_Pause;
894 cmd->autoneg = AUTONEG_ENABLE;
895
896 ethtool_cmd_speed_set(cmd,
897 (ctrl & WMC_WSS) ? SPEED_100 : SPEED_10);
898 cmd->duplex = (ctrl & WMC_WDS) ?
899 DUPLEX_FULL : DUPLEX_HALF;
900 } else {
901 /* auto-negotiation is disabled */
902 cmd->autoneg = AUTONEG_DISABLE;
903
904 ethtool_cmd_speed_set(cmd, ((ctrl & WMC_WANF100) ?
905 SPEED_100 : SPEED_10));
906 cmd->duplex = (ctrl & WMC_WANFF) ?
907 DUPLEX_FULL : DUPLEX_HALF;
908 }
909
910 return 0;
911}
912
913/**
914 * ks8695_wan_set_settings - Set device-specific settings.
915 * @ndev: The network device to configure
916 * @cmd: The settings to configure
917 */
918static int
919ks8695_wan_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
920{
921 struct ks8695_priv *ksp = netdev_priv(ndev);
922 u32 ctrl;
923
924 if ((cmd->speed != SPEED_10) && (cmd->speed != SPEED_100))
925 return -EINVAL;
926 if ((cmd->duplex != DUPLEX_HALF) && (cmd->duplex != DUPLEX_FULL))
927 return -EINVAL;
928 if (cmd->port != PORT_MII)
929 return -EINVAL;
930 if (cmd->transceiver != XCVR_INTERNAL)
931 return -EINVAL;
932 if ((cmd->autoneg != AUTONEG_DISABLE) &&
933 (cmd->autoneg != AUTONEG_ENABLE))
934 return -EINVAL;
935
936 if (cmd->autoneg == AUTONEG_ENABLE) {
937 if ((cmd->advertising & (ADVERTISED_10baseT_Half |
938 ADVERTISED_10baseT_Full |
939 ADVERTISED_100baseT_Half |
940 ADVERTISED_100baseT_Full)) == 0)
941 return -EINVAL;
942
943 ctrl = readl(ksp->phyiface_regs + KS8695_WMC);
944
945 ctrl &= ~(WMC_WAND | WMC_WANA100F | WMC_WANA100H |
946 WMC_WANA10F | WMC_WANA10H);
947 if (cmd->advertising & ADVERTISED_100baseT_Full)
948 ctrl |= WMC_WANA100F;
949 if (cmd->advertising & ADVERTISED_100baseT_Half)
950 ctrl |= WMC_WANA100H;
951 if (cmd->advertising & ADVERTISED_10baseT_Full)
952 ctrl |= WMC_WANA10F;
953 if (cmd->advertising & ADVERTISED_10baseT_Half)
954 ctrl |= WMC_WANA10H;
955
956 /* force a re-negotiation */
957 ctrl |= WMC_WANR;
958 writel(ctrl, ksp->phyiface_regs + KS8695_WMC);
959 } else {
960 ctrl = readl(ksp->phyiface_regs + KS8695_WMC);
961
962 /* disable auto-negotiation */
963 ctrl |= WMC_WAND;
964 ctrl &= ~(WMC_WANF100 | WMC_WANFF);
965
966 if (cmd->speed == SPEED_100)
967 ctrl |= WMC_WANF100;
968 if (cmd->duplex == DUPLEX_FULL)
969 ctrl |= WMC_WANFF;
970
971 writel(ctrl, ksp->phyiface_regs + KS8695_WMC);
972 }
973
974 return 0;
975}
976
977/**
978 * ks8695_wan_nwayreset - Restart the autonegotiation on the port.
979 * @ndev: The network device to restart autoneotiation on
980 */
981static int
982ks8695_wan_nwayreset(struct net_device *ndev)
983{
984 struct ks8695_priv *ksp = netdev_priv(ndev);
985 u32 ctrl;
986
987 ctrl = readl(ksp->phyiface_regs + KS8695_WMC);
988
989 if ((ctrl & WMC_WAND) == 0)
990 writel(ctrl | WMC_WANR,
991 ksp->phyiface_regs + KS8695_WMC);
992 else
993 /* auto-negotiation not enabled */
994 return -EINVAL;
995
996 return 0;
997}
998
999/**
1000 * ks8695_wan_get_pause - Retrieve network pause/flow-control advertising
1001 * @ndev: The device to retrieve settings from
1002 * @param: The structure to fill out with the information
1003 */
1004static void
1005ks8695_wan_get_pause(struct net_device *ndev, struct ethtool_pauseparam *param)
1006{
1007 struct ks8695_priv *ksp = netdev_priv(ndev);
1008 u32 ctrl;
1009
1010 ctrl = readl(ksp->phyiface_regs + KS8695_WMC);
1011
1012 /* advertise Pause */
1013 param->autoneg = (ctrl & WMC_WANAP);
1014
1015 /* current Rx Flow-control */
1016 ctrl = ks8695_readreg(ksp, KS8695_DRXC);
1017 param->rx_pause = (ctrl & DRXC_RFCE);
1018
1019 /* current Tx Flow-control */
1020 ctrl = ks8695_readreg(ksp, KS8695_DTXC);
1021 param->tx_pause = (ctrl & DTXC_TFCE);
1022}
1023
1024/**
1025 * ks8695_get_drvinfo - Retrieve driver information
1026 * @ndev: The network device to retrieve info about
1027 * @info: The info structure to fill out.
1028 */
1029static void
1030ks8695_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1031{
1032 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1033 strlcpy(info->version, MODULEVERSION, sizeof(info->version));
1034 strlcpy(info->bus_info, dev_name(ndev->dev.parent),
1035 sizeof(info->bus_info));
1036}
1037
1038static const struct ethtool_ops ks8695_ethtool_ops = {
1039 .get_msglevel = ks8695_get_msglevel,
1040 .set_msglevel = ks8695_set_msglevel,
1041 .get_drvinfo = ks8695_get_drvinfo,
1042};
1043
1044static const struct ethtool_ops ks8695_wan_ethtool_ops = {
1045 .get_msglevel = ks8695_get_msglevel,
1046 .set_msglevel = ks8695_set_msglevel,
1047 .get_settings = ks8695_wan_get_settings,
1048 .set_settings = ks8695_wan_set_settings,
1049 .nway_reset = ks8695_wan_nwayreset,
1050 .get_link = ethtool_op_get_link,
1051 .get_pauseparam = ks8695_wan_get_pause,
1052 .get_drvinfo = ks8695_get_drvinfo,
1053};
1054
1055/* Network device interface functions */
1056
1057/**
1058 * ks8695_set_mac - Update MAC in net dev and HW
1059 * @ndev: The network device to update
1060 * @addr: The new MAC address to set
1061 */
1062static int
1063ks8695_set_mac(struct net_device *ndev, void *addr)
1064{
1065 struct ks8695_priv *ksp = netdev_priv(ndev);
1066 struct sockaddr *address = addr;
1067
1068 if (!is_valid_ether_addr(address->sa_data))
1069 return -EADDRNOTAVAIL;
1070
1071 memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
1072
1073 ks8695_update_mac(ksp);
1074
1075 dev_dbg(ksp->dev, "%s: Updated MAC address to %pM\n",
1076 ndev->name, ndev->dev_addr);
1077
1078 return 0;
1079}
1080
1081/**
1082 * ks8695_set_multicast - Set up the multicast behaviour of the interface
1083 * @ndev: The net_device to configure
1084 *
1085 * This routine, called by the net layer, configures promiscuity
1086 * and multicast reception behaviour for the interface.
1087 */
1088static void
1089ks8695_set_multicast(struct net_device *ndev)
1090{
1091 struct ks8695_priv *ksp = netdev_priv(ndev);
1092 u32 ctrl;
1093
1094 ctrl = ks8695_readreg(ksp, KS8695_DRXC);
1095
1096 if (ndev->flags & IFF_PROMISC) {
1097 /* enable promiscuous mode */
1098 ctrl |= DRXC_RA;
1099 } else if (ndev->flags & ~IFF_PROMISC) {
1100 /* disable promiscuous mode */
1101 ctrl &= ~DRXC_RA;
1102 }
1103
1104 if (ndev->flags & IFF_ALLMULTI) {
1105 /* enable all multicast mode */
1106 ctrl |= DRXC_RM;
1107 } else if (netdev_mc_count(ndev) > KS8695_NR_ADDRESSES) {
1108 /* more specific multicast addresses than can be
1109 * handled in hardware
1110 */
1111 ctrl |= DRXC_RM;
1112 } else {
1113 /* enable specific multicasts */
1114 ctrl &= ~DRXC_RM;
1115 ks8695_init_partial_multicast(ksp, ndev);
1116 }
1117
1118 ks8695_writereg(ksp, KS8695_DRXC, ctrl);
1119}
1120
1121/**
1122 * ks8695_timeout - Handle a network tx/rx timeout.
1123 * @ndev: The net_device which timed out.
1124 *
1125 * A network transaction timed out, reset the device.
1126 */
1127static void
1128ks8695_timeout(struct net_device *ndev)
1129{
1130 struct ks8695_priv *ksp = netdev_priv(ndev);
1131
1132 netif_stop_queue(ndev);
1133 ks8695_shutdown(ksp);
1134
1135 ks8695_reset(ksp);
1136
1137 ks8695_update_mac(ksp);
1138
1139 /* We ignore the return from this since it managed to init
1140 * before it probably will be okay to init again.
1141 */
1142 ks8695_init_net(ksp);
1143
1144 /* Reconfigure promiscuity etc */
1145 ks8695_set_multicast(ndev);
1146
1147 /* And start the TX queue once more */
1148 netif_start_queue(ndev);
1149}
1150
1151/**
1152 * ks8695_start_xmit - Start a packet transmission
1153 * @skb: The packet to transmit
1154 * @ndev: The network device to send the packet on
1155 *
1156 * This routine, called by the net layer, takes ownership of the
1157 * sk_buff and adds it to the TX ring. It then kicks the TX DMA
1158 * engine to ensure transmission begins.
1159 */
1160static int
1161ks8695_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1162{
1163 struct ks8695_priv *ksp = netdev_priv(ndev);
1164 int buff_n;
1165 dma_addr_t dmap;
1166
1167 spin_lock_irq(&ksp->txq_lock);
1168
1169 if (ksp->tx_ring_used == MAX_TX_DESC) {
1170 /* Somehow we got entered when we have no room */
1171 spin_unlock_irq(&ksp->txq_lock);
1172 return NETDEV_TX_BUSY;
1173 }
1174
1175 buff_n = ksp->tx_ring_next_slot;
1176
1177 BUG_ON(ksp->tx_buffers[buff_n].skb);
1178
1179 dmap = dma_map_single(ksp->dev, skb->data, skb->len, DMA_TO_DEVICE);
1180 if (unlikely(dma_mapping_error(ksp->dev, dmap))) {
1181 /* Failed to DMA map this SKB, give it back for now */
1182 spin_unlock_irq(&ksp->txq_lock);
1183 dev_dbg(ksp->dev, "%s: Could not map DMA memory for "\
1184 "transmission, trying later\n", ndev->name);
1185 return NETDEV_TX_BUSY;
1186 }
1187
1188 ksp->tx_buffers[buff_n].dma_ptr = dmap;
1189 /* Mapped okay, store the buffer pointer and length for later */
1190 ksp->tx_buffers[buff_n].skb = skb;
1191 ksp->tx_buffers[buff_n].length = skb->len;
1192
1193 /* Fill out the TX descriptor */
1194 ksp->tx_ring[buff_n].data_ptr =
1195 cpu_to_le32(ksp->tx_buffers[buff_n].dma_ptr);
1196 ksp->tx_ring[buff_n].status =
1197 cpu_to_le32(TDES_IC | TDES_FS | TDES_LS |
1198 (skb->len & TDES_TBS));
1199
1200 wmb();
1201
1202 /* Hand it over to the hardware */
1203 ksp->tx_ring[buff_n].owner = cpu_to_le32(TDES_OWN);
1204
1205 if (++ksp->tx_ring_used == MAX_TX_DESC)
1206 netif_stop_queue(ndev);
1207
1208 /* Kick the TX DMA in case it decided to go IDLE */
1209 ks8695_writereg(ksp, KS8695_DTSC, 0);
1210
1211 /* And update the next ring slot */
1212 ksp->tx_ring_next_slot = (buff_n + 1) & MAX_TX_DESC_MASK;
1213
1214 spin_unlock_irq(&ksp->txq_lock);
1215 return NETDEV_TX_OK;
1216}
1217
1218/**
1219 * ks8695_stop - Stop (shutdown) a KS8695 ethernet interface
1220 * @ndev: The net_device to stop
1221 *
1222 * This disables the TX queue and cleans up a KS8695 ethernet
1223 * device.
1224 */
1225static int
1226ks8695_stop(struct net_device *ndev)
1227{
1228 struct ks8695_priv *ksp = netdev_priv(ndev);
1229
1230 netif_stop_queue(ndev);
1231 napi_disable(&ksp->napi);
1232
1233 ks8695_shutdown(ksp);
1234
1235 return 0;
1236}
1237
1238/**
1239 * ks8695_open - Open (bring up) a KS8695 ethernet interface
1240 * @ndev: The net_device to open
1241 *
1242 * This resets, configures the MAC, initialises the RX ring and
1243 * DMA engines and starts the TX queue for a KS8695 ethernet
1244 * device.
1245 */
1246static int
1247ks8695_open(struct net_device *ndev)
1248{
1249 struct ks8695_priv *ksp = netdev_priv(ndev);
1250 int ret;
1251
1252 if (!is_valid_ether_addr(ndev->dev_addr))
1253 return -EADDRNOTAVAIL;
1254
1255 ks8695_reset(ksp);
1256
1257 ks8695_update_mac(ksp);
1258
1259 ret = ks8695_init_net(ksp);
1260 if (ret) {
1261 ks8695_shutdown(ksp);
1262 return ret;
1263 }
1264
1265 napi_enable(&ksp->napi);
1266 netif_start_queue(ndev);
1267
1268 return 0;
1269}
1270
1271/* Platform device driver */
1272
1273/**
1274 * ks8695_init_switch - Init LAN switch to known good defaults.
1275 * @ksp: The device to initialise
1276 *
1277 * This initialises the LAN switch in the KS8695 to a known-good
1278 * set of defaults.
1279 */
1280static void __devinit
1281ks8695_init_switch(struct ks8695_priv *ksp)
1282{
1283 u32 ctrl;
1284
1285 /* Default value for SEC0 according to datasheet */
1286 ctrl = 0x40819e00;
1287
1288 /* LED0 = Speed LED1 = Link/Activity */
1289 ctrl &= ~(SEC0_LLED1S | SEC0_LLED0S);
1290 ctrl |= (LLED0S_LINK | LLED1S_LINK_ACTIVITY);
1291
1292 /* Enable Switch */
1293 ctrl |= SEC0_ENABLE;
1294
1295 writel(ctrl, ksp->phyiface_regs + KS8695_SEC0);
1296
1297 /* Defaults for SEC1 */
1298 writel(0x9400100, ksp->phyiface_regs + KS8695_SEC1);
1299}
1300
1301/**
1302 * ks8695_init_wan_phy - Initialise the WAN PHY to sensible defaults
1303 * @ksp: The device to initialise
1304 *
1305 * This initialises a KS8695's WAN phy to sensible values for
1306 * autonegotiation etc.
1307 */
1308static void __devinit
1309ks8695_init_wan_phy(struct ks8695_priv *ksp)
1310{
1311 u32 ctrl;
1312
1313 /* Support auto-negotiation */
1314 ctrl = (WMC_WANAP | WMC_WANA100F | WMC_WANA100H |
1315 WMC_WANA10F | WMC_WANA10H);
1316
1317 /* LED0 = Activity , LED1 = Link */
1318 ctrl |= (WLED0S_ACTIVITY | WLED1S_LINK);
1319
1320 /* Restart Auto-negotiation */
1321 ctrl |= WMC_WANR;
1322
1323 writel(ctrl, ksp->phyiface_regs + KS8695_WMC);
1324
1325 writel(0, ksp->phyiface_regs + KS8695_WPPM);
1326 writel(0, ksp->phyiface_regs + KS8695_PPS);
1327}
1328
1329static const struct net_device_ops ks8695_netdev_ops = {
1330 .ndo_open = ks8695_open,
1331 .ndo_stop = ks8695_stop,
1332 .ndo_start_xmit = ks8695_start_xmit,
1333 .ndo_tx_timeout = ks8695_timeout,
1334 .ndo_set_mac_address = ks8695_set_mac,
1335 .ndo_validate_addr = eth_validate_addr,
1336 .ndo_set_multicast_list = ks8695_set_multicast,
1337};
1338
1339/**
1340 * ks8695_probe - Probe and initialise a KS8695 ethernet interface
1341 * @pdev: The platform device to probe
1342 *
1343 * Initialise a KS8695 ethernet device from platform data.
1344 *
1345 * This driver requires at least one IORESOURCE_MEM for the
1346 * registers and two IORESOURCE_IRQ for the RX and TX IRQs
1347 * respectively. It can optionally take an additional
1348 * IORESOURCE_MEM for the switch or phy in the case of the lan or
1349 * wan ports, and an IORESOURCE_IRQ for the link IRQ for the wan
1350 * port.
1351 */
1352static int __devinit
1353ks8695_probe(struct platform_device *pdev)
1354{
1355 struct ks8695_priv *ksp;
1356 struct net_device *ndev;
1357 struct resource *regs_res, *phyiface_res;
1358 struct resource *rxirq_res, *txirq_res, *linkirq_res;
1359 int ret = 0;
1360 int buff_n;
1361 u32 machigh, maclow;
1362
1363 /* Initialise a net_device */
1364 ndev = alloc_etherdev(sizeof(struct ks8695_priv));
1365 if (!ndev) {
1366 dev_err(&pdev->dev, "could not allocate device.\n");
1367 return -ENOMEM;
1368 }
1369
1370 SET_NETDEV_DEV(ndev, &pdev->dev);
1371
1372 dev_dbg(&pdev->dev, "ks8695_probe() called\n");
1373
1374 /* Configure our private structure a little */
1375 ksp = netdev_priv(ndev);
1376
1377 ksp->dev = &pdev->dev;
1378 ksp->ndev = ndev;
1379 ksp->msg_enable = NETIF_MSG_LINK;
1380
1381 /* Retrieve resources */
1382 regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1383 phyiface_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1384
1385 rxirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1386 txirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1387 linkirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1388
1389 if (!(regs_res && rxirq_res && txirq_res)) {
1390 dev_err(ksp->dev, "insufficient resources\n");
1391 ret = -ENOENT;
1392 goto failure;
1393 }
1394
1395 ksp->regs_req = request_mem_region(regs_res->start,
1396 resource_size(regs_res),
1397 pdev->name);
1398
1399 if (!ksp->regs_req) {
1400 dev_err(ksp->dev, "cannot claim register space\n");
1401 ret = -EIO;
1402 goto failure;
1403 }
1404
1405 ksp->io_regs = ioremap(regs_res->start, resource_size(regs_res));
1406
1407 if (!ksp->io_regs) {
1408 dev_err(ksp->dev, "failed to ioremap registers\n");
1409 ret = -EINVAL;
1410 goto failure;
1411 }
1412
1413 if (phyiface_res) {
1414 ksp->phyiface_req =
1415 request_mem_region(phyiface_res->start,
1416 resource_size(phyiface_res),
1417 phyiface_res->name);
1418
1419 if (!ksp->phyiface_req) {
1420 dev_err(ksp->dev,
1421 "cannot claim switch register space\n");
1422 ret = -EIO;
1423 goto failure;
1424 }
1425
1426 ksp->phyiface_regs = ioremap(phyiface_res->start,
1427 resource_size(phyiface_res));
1428
1429 if (!ksp->phyiface_regs) {
1430 dev_err(ksp->dev,
1431 "failed to ioremap switch registers\n");
1432 ret = -EINVAL;
1433 goto failure;
1434 }
1435 }
1436
1437 ksp->rx_irq = rxirq_res->start;
1438 ksp->rx_irq_name = rxirq_res->name ? rxirq_res->name : "Ethernet RX";
1439 ksp->tx_irq = txirq_res->start;
1440 ksp->tx_irq_name = txirq_res->name ? txirq_res->name : "Ethernet TX";
1441 ksp->link_irq = (linkirq_res ? linkirq_res->start : -1);
1442 ksp->link_irq_name = (linkirq_res && linkirq_res->name) ?
1443 linkirq_res->name : "Ethernet Link";
1444
1445 /* driver system setup */
1446 ndev->netdev_ops = &ks8695_netdev_ops;
1447 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1448
1449 netif_napi_add(ndev, &ksp->napi, ks8695_poll, NAPI_WEIGHT);
1450
1451 /* Retrieve the default MAC addr from the chip. */
1452 /* The bootloader should have left it in there for us. */
1453
1454 machigh = ks8695_readreg(ksp, KS8695_MAH);
1455 maclow = ks8695_readreg(ksp, KS8695_MAL);
1456
1457 ndev->dev_addr[0] = (machigh >> 8) & 0xFF;
1458 ndev->dev_addr[1] = machigh & 0xFF;
1459 ndev->dev_addr[2] = (maclow >> 24) & 0xFF;
1460 ndev->dev_addr[3] = (maclow >> 16) & 0xFF;
1461 ndev->dev_addr[4] = (maclow >> 8) & 0xFF;
1462 ndev->dev_addr[5] = maclow & 0xFF;
1463
1464 if (!is_valid_ether_addr(ndev->dev_addr))
1465 dev_warn(ksp->dev, "%s: Invalid ethernet MAC address. Please "
1466 "set using ifconfig\n", ndev->name);
1467
1468 /* In order to be efficient memory-wise, we allocate both
1469 * rings in one go.
1470 */
1471 ksp->ring_base = dma_alloc_coherent(&pdev->dev, RING_DMA_SIZE,
1472 &ksp->ring_base_dma, GFP_KERNEL);
1473 if (!ksp->ring_base) {
1474 ret = -ENOMEM;
1475 goto failure;
1476 }
1477
1478 /* Specify the TX DMA ring buffer */
1479 ksp->tx_ring = ksp->ring_base;
1480 ksp->tx_ring_dma = ksp->ring_base_dma;
1481
1482 /* And initialise the queue's lock */
1483 spin_lock_init(&ksp->txq_lock);
1484 spin_lock_init(&ksp->rx_lock);
1485
1486 /* Specify the RX DMA ring buffer */
1487 ksp->rx_ring = ksp->ring_base + TX_RING_DMA_SIZE;
1488 ksp->rx_ring_dma = ksp->ring_base_dma + TX_RING_DMA_SIZE;
1489
1490 /* Zero the descriptor rings */
1491 memset(ksp->tx_ring, 0, TX_RING_DMA_SIZE);
1492 memset(ksp->rx_ring, 0, RX_RING_DMA_SIZE);
1493
1494 /* Build the rings */
1495 for (buff_n = 0; buff_n < MAX_TX_DESC; ++buff_n) {
1496 ksp->tx_ring[buff_n].next_desc =
1497 cpu_to_le32(ksp->tx_ring_dma +
1498 (sizeof(struct tx_ring_desc) *
1499 ((buff_n + 1) & MAX_TX_DESC_MASK)));
1500 }
1501
1502 for (buff_n = 0; buff_n < MAX_RX_DESC; ++buff_n) {
1503 ksp->rx_ring[buff_n].next_desc =
1504 cpu_to_le32(ksp->rx_ring_dma +
1505 (sizeof(struct rx_ring_desc) *
1506 ((buff_n + 1) & MAX_RX_DESC_MASK)));
1507 }
1508
1509 /* Initialise the port (physically) */
1510 if (ksp->phyiface_regs && ksp->link_irq == -1) {
1511 ks8695_init_switch(ksp);
1512 ksp->dtype = KS8695_DTYPE_LAN;
1513 SET_ETHTOOL_OPS(ndev, &ks8695_ethtool_ops);
1514 } else if (ksp->phyiface_regs && ksp->link_irq != -1) {
1515 ks8695_init_wan_phy(ksp);
1516 ksp->dtype = KS8695_DTYPE_WAN;
1517 SET_ETHTOOL_OPS(ndev, &ks8695_wan_ethtool_ops);
1518 } else {
1519 /* No initialisation since HPNA does not have a PHY */
1520 ksp->dtype = KS8695_DTYPE_HPNA;
1521 SET_ETHTOOL_OPS(ndev, &ks8695_ethtool_ops);
1522 }
1523
1524 /* And bring up the net_device with the net core */
1525 platform_set_drvdata(pdev, ndev);
1526 ret = register_netdev(ndev);
1527
1528 if (ret == 0) {
1529 dev_info(ksp->dev, "ks8695 ethernet (%s) MAC: %pM\n",
1530 ks8695_port_type(ksp), ndev->dev_addr);
1531 } else {
1532 /* Report the failure to register the net_device */
1533 dev_err(ksp->dev, "ks8695net: failed to register netdev.\n");
1534 goto failure;
1535 }
1536
1537 /* All is well */
1538 return 0;
1539
1540 /* Error exit path */
1541failure:
1542 ks8695_release_device(ksp);
1543 free_netdev(ndev);
1544
1545 return ret;
1546}
1547
1548/**
1549 * ks8695_drv_suspend - Suspend a KS8695 ethernet platform device.
1550 * @pdev: The device to suspend
1551 * @state: The suspend state
1552 *
1553 * This routine detaches and shuts down a KS8695 ethernet device.
1554 */
1555static int
1556ks8695_drv_suspend(struct platform_device *pdev, pm_message_t state)
1557{
1558 struct net_device *ndev = platform_get_drvdata(pdev);
1559 struct ks8695_priv *ksp = netdev_priv(ndev);
1560
1561 ksp->in_suspend = 1;
1562
1563 if (netif_running(ndev)) {
1564 netif_device_detach(ndev);
1565 ks8695_shutdown(ksp);
1566 }
1567
1568 return 0;
1569}
1570
1571/**
1572 * ks8695_drv_resume - Resume a KS8695 ethernet platform device.
1573 * @pdev: The device to resume
1574 *
1575 * This routine re-initialises and re-attaches a KS8695 ethernet
1576 * device.
1577 */
1578static int
1579ks8695_drv_resume(struct platform_device *pdev)
1580{
1581 struct net_device *ndev = platform_get_drvdata(pdev);
1582 struct ks8695_priv *ksp = netdev_priv(ndev);
1583
1584 if (netif_running(ndev)) {
1585 ks8695_reset(ksp);
1586 ks8695_init_net(ksp);
1587 ks8695_set_multicast(ndev);
1588 netif_device_attach(ndev);
1589 }
1590
1591 ksp->in_suspend = 0;
1592
1593 return 0;
1594}
1595
1596/**
1597 * ks8695_drv_remove - Remove a KS8695 net device on driver unload.
1598 * @pdev: The platform device to remove
1599 *
1600 * This unregisters and releases a KS8695 ethernet device.
1601 */
1602static int __devexit
1603ks8695_drv_remove(struct platform_device *pdev)
1604{
1605 struct net_device *ndev = platform_get_drvdata(pdev);
1606 struct ks8695_priv *ksp = netdev_priv(ndev);
1607
1608 platform_set_drvdata(pdev, NULL);
1609 netif_napi_del(&ksp->napi);
1610
1611 unregister_netdev(ndev);
1612 ks8695_release_device(ksp);
1613 free_netdev(ndev);
1614
1615 dev_dbg(&pdev->dev, "released and freed device\n");
1616 return 0;
1617}
1618
1619static struct platform_driver ks8695_driver = {
1620 .driver = {
1621 .name = MODULENAME,
1622 .owner = THIS_MODULE,
1623 },
1624 .probe = ks8695_probe,
1625 .remove = __devexit_p(ks8695_drv_remove),
1626 .suspend = ks8695_drv_suspend,
1627 .resume = ks8695_drv_resume,
1628};
1629
1630/* Module interface */
1631
1632static int __init
1633ks8695_init(void)
1634{
1635 printk(KERN_INFO "%s Ethernet driver, V%s\n",
1636 MODULENAME, MODULEVERSION);
1637
1638 return platform_driver_register(&ks8695_driver);
1639}
1640
1641static void __exit
1642ks8695_cleanup(void)
1643{
1644 platform_driver_unregister(&ks8695_driver);
1645}
1646
1647module_init(ks8695_init);
1648module_exit(ks8695_cleanup);
1649
1650MODULE_AUTHOR("Simtec Electronics");
1651MODULE_DESCRIPTION("Micrel KS8695 (Centaur) Ethernet driver");
1652MODULE_LICENSE("GPL");
1653MODULE_ALIAS("platform:" MODULENAME);
1654
1655module_param(watchdog, int, 0400);
1656MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
diff --git a/drivers/net/ethernet/micrel/ks8695net.h b/drivers/net/ethernet/micrel/ks8695net.h
new file mode 100644
index 000000000000..80eff6ea5163
--- /dev/null
+++ b/drivers/net/ethernet/micrel/ks8695net.h
@@ -0,0 +1,107 @@
1/*
2 * Micrel KS8695 (Centaur) Ethernet.
3 *
4 * Copyright 2008 Simtec Electronics
5 * Daniel Silverstone <dsilvers@simtec.co.uk>
6 * Vincent Sanders <vince@simtec.co.uk>
7 */
8
9#ifndef KS8695NET_H
10#define KS8695NET_H
11
12/* Receive descriptor flags */
13#define RDES_OWN (1 << 31) /* Ownership */
14#define RDES_FS (1 << 30) /* First Descriptor */
15#define RDES_LS (1 << 29) /* Last Descriptor */
16#define RDES_IPE (1 << 28) /* IP Checksum error */
17#define RDES_TCPE (1 << 27) /* TCP Checksum error */
18#define RDES_UDPE (1 << 26) /* UDP Checksum error */
19#define RDES_ES (1 << 25) /* Error summary */
20#define RDES_MF (1 << 24) /* Multicast Frame */
21#define RDES_RE (1 << 19) /* MII Error reported */
22#define RDES_TL (1 << 18) /* Frame too Long */
23#define RDES_RF (1 << 17) /* Runt Frame */
24#define RDES_CE (1 << 16) /* CRC error */
25#define RDES_FT (1 << 15) /* Frame Type */
26#define RDES_FLEN (0x7ff) /* Frame Length */
27
28#define RDES_RER (1 << 25) /* Receive End of Ring */
29#define RDES_RBS (0x7ff) /* Receive Buffer Size */
30
31/* Transmit descriptor flags */
32
33#define TDES_OWN (1 << 31) /* Ownership */
34
35#define TDES_IC (1 << 31) /* Interrupt on Completion */
36#define TDES_FS (1 << 30) /* First Segment */
37#define TDES_LS (1 << 29) /* Last Segment */
38#define TDES_IPCKG (1 << 28) /* IP Checksum generate */
39#define TDES_TCPCKG (1 << 27) /* TCP Checksum generate */
40#define TDES_UDPCKG (1 << 26) /* UDP Checksum generate */
41#define TDES_TER (1 << 25) /* Transmit End of Ring */
42#define TDES_TBS (0x7ff) /* Transmit Buffer Size */
43
44/*
45 * Network controller register offsets
46 */
47#define KS8695_DTXC (0x00) /* DMA Transmit Control */
48#define KS8695_DRXC (0x04) /* DMA Receive Control */
49#define KS8695_DTSC (0x08) /* DMA Transmit Start Command */
50#define KS8695_DRSC (0x0c) /* DMA Receive Start Command */
51#define KS8695_TDLB (0x10) /* Transmit Descriptor List
52 * Base Address
53 */
54#define KS8695_RDLB (0x14) /* Receive Descriptor List
55 * Base Address
56 */
57#define KS8695_MAL (0x18) /* MAC Station Address Low */
58#define KS8695_MAH (0x1c) /* MAC Station Address High */
59#define KS8695_AAL_(n) (0x80 + ((n)*8)) /* MAC Additional
60 * Station Address
61 * (0..15) Low
62 */
63#define KS8695_AAH_(n) (0x84 + ((n)*8)) /* MAC Additional
64 * Station Address
65 * (0..15) High
66 */
67
68
69/* DMA Transmit Control Register */
70#define DTXC_TRST (1 << 31) /* Soft Reset */
71#define DTXC_TBS (0x3f << 24) /* Transmit Burst Size */
72#define DTXC_TUCG (1 << 18) /* Transmit UDP
73 * Checksum Generate
74 */
75#define DTXC_TTCG (1 << 17) /* Transmit TCP
76 * Checksum Generate
77 */
78#define DTXC_TICG (1 << 16) /* Transmit IP
79 * Checksum Generate
80 */
81#define DTXC_TFCE (1 << 9) /* Transmit Flow
82 * Control Enable
83 */
84#define DTXC_TLB (1 << 8) /* Loopback mode */
85#define DTXC_TEP (1 << 2) /* Transmit Enable Padding */
86#define DTXC_TAC (1 << 1) /* Transmit Add CRC */
87#define DTXC_TE (1 << 0) /* TX Enable */
88
89/* DMA Receive Control Register */
90#define DRXC_RBS (0x3f << 24) /* Receive Burst Size */
91#define DRXC_RUCC (1 << 18) /* Receive UDP Checksum check */
92#define DRXC_RTCG (1 << 17) /* Receive TCP Checksum check */
93#define DRXC_RICG (1 << 16) /* Receive IP Checksum check */
94#define DRXC_RFCE (1 << 9) /* Receive Flow Control
95 * Enable
96 */
97#define DRXC_RB (1 << 6) /* Receive Broadcast */
98#define DRXC_RM (1 << 5) /* Receive Multicast */
99#define DRXC_RU (1 << 4) /* Receive Unicast */
100#define DRXC_RERR (1 << 3) /* Receive Error Frame */
101#define DRXC_RA (1 << 2) /* Receive All */
102#define DRXC_RE (1 << 0) /* RX Enable */
103
104/* Additional Station Address High */
105#define AAH_E (1 << 31) /* Address Enabled */
106
107#endif /* KS8695NET_H */
diff --git a/drivers/net/ethernet/micrel/ks8842.c b/drivers/net/ethernet/micrel/ks8842.c
new file mode 100644
index 000000000000..4a6ae057e3b1
--- /dev/null
+++ b/drivers/net/ethernet/micrel/ks8842.c
@@ -0,0 +1,1284 @@
1/*
2 * ks8842.c timberdale KS8842 ethernet driver
3 * Copyright (c) 2009 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * The Micrel KS8842 behind the timberdale FPGA
21 * The genuine Micrel KS8841/42 device with ISA 16/32bit bus interface
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/ks8842.h>
34#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h>
36#include <linux/scatterlist.h>
37
38#define DRV_NAME "ks8842"
39
40/* Timberdale specific Registers */
41#define REG_TIMB_RST 0x1c
42#define REG_TIMB_FIFO 0x20
43#define REG_TIMB_ISR 0x24
44#define REG_TIMB_IER 0x28
45#define REG_TIMB_IAR 0x2C
46#define REQ_TIMB_DMA_RESUME 0x30
47
48/* KS8842 registers */
49
50#define REG_SELECT_BANK 0x0e
51
52/* bank 0 registers */
53#define REG_QRFCR 0x04
54
55/* bank 2 registers */
56#define REG_MARL 0x00
57#define REG_MARM 0x02
58#define REG_MARH 0x04
59
60/* bank 3 registers */
61#define REG_GRR 0x06
62
63/* bank 16 registers */
64#define REG_TXCR 0x00
65#define REG_TXSR 0x02
66#define REG_RXCR 0x04
67#define REG_TXMIR 0x08
68#define REG_RXMIR 0x0A
69
70/* bank 17 registers */
71#define REG_TXQCR 0x00
72#define REG_RXQCR 0x02
73#define REG_TXFDPR 0x04
74#define REG_RXFDPR 0x06
75#define REG_QMU_DATA_LO 0x08
76#define REG_QMU_DATA_HI 0x0A
77
78/* bank 18 registers */
79#define REG_IER 0x00
80#define IRQ_LINK_CHANGE 0x8000
81#define IRQ_TX 0x4000
82#define IRQ_RX 0x2000
83#define IRQ_RX_OVERRUN 0x0800
84#define IRQ_TX_STOPPED 0x0200
85#define IRQ_RX_STOPPED 0x0100
86#define IRQ_RX_ERROR 0x0080
87#define ENABLED_IRQS (IRQ_LINK_CHANGE | IRQ_TX | IRQ_RX | IRQ_RX_STOPPED | \
88 IRQ_TX_STOPPED | IRQ_RX_OVERRUN | IRQ_RX_ERROR)
89/* When running via timberdale in DMA mode, the RX interrupt should be
90 enabled in the KS8842, but not in the FPGA IP, since the IP handles
91 RX DMA internally.
92 TX interrupts are not needed it is handled by the FPGA the driver is
93 notified via DMA callbacks.
94*/
95#define ENABLED_IRQS_DMA_IP (IRQ_LINK_CHANGE | IRQ_RX_STOPPED | \
96 IRQ_TX_STOPPED | IRQ_RX_OVERRUN | IRQ_RX_ERROR)
97#define ENABLED_IRQS_DMA (ENABLED_IRQS_DMA_IP | IRQ_RX)
98#define REG_ISR 0x02
99#define REG_RXSR 0x04
100#define RXSR_VALID 0x8000
101#define RXSR_BROADCAST 0x80
102#define RXSR_MULTICAST 0x40
103#define RXSR_UNICAST 0x20
104#define RXSR_FRAMETYPE 0x08
105#define RXSR_TOO_LONG 0x04
106#define RXSR_RUNT 0x02
107#define RXSR_CRC_ERROR 0x01
108#define RXSR_ERROR (RXSR_TOO_LONG | RXSR_RUNT | RXSR_CRC_ERROR)
109
110/* bank 32 registers */
111#define REG_SW_ID_AND_ENABLE 0x00
112#define REG_SGCR1 0x02
113#define REG_SGCR2 0x04
114#define REG_SGCR3 0x06
115
116/* bank 39 registers */
117#define REG_MACAR1 0x00
118#define REG_MACAR2 0x02
119#define REG_MACAR3 0x04
120
121/* bank 45 registers */
122#define REG_P1MBCR 0x00
123#define REG_P1MBSR 0x02
124
125/* bank 46 registers */
126#define REG_P2MBCR 0x00
127#define REG_P2MBSR 0x02
128
129/* bank 48 registers */
130#define REG_P1CR2 0x02
131
132/* bank 49 registers */
133#define REG_P1CR4 0x02
134#define REG_P1SR 0x04
135
136/* flags passed by platform_device for configuration */
137#define MICREL_KS884X 0x01 /* 0=Timeberdale(FPGA), 1=Micrel */
138#define KS884X_16BIT 0x02 /* 1=16bit, 0=32bit */
139
140#define DMA_BUFFER_SIZE 2048
141
142struct ks8842_tx_dma_ctl {
143 struct dma_chan *chan;
144 struct dma_async_tx_descriptor *adesc;
145 void *buf;
146 struct scatterlist sg;
147 int channel;
148};
149
150struct ks8842_rx_dma_ctl {
151 struct dma_chan *chan;
152 struct dma_async_tx_descriptor *adesc;
153 struct sk_buff *skb;
154 struct scatterlist sg;
155 struct tasklet_struct tasklet;
156 int channel;
157};
158
159#define KS8842_USE_DMA(adapter) (((adapter)->dma_tx.channel != -1) && \
160 ((adapter)->dma_rx.channel != -1))
161
162struct ks8842_adapter {
163 void __iomem *hw_addr;
164 int irq;
165 unsigned long conf_flags; /* copy of platform_device config */
166 struct tasklet_struct tasklet;
167 spinlock_t lock; /* spinlock to be interrupt safe */
168 struct work_struct timeout_work;
169 struct net_device *netdev;
170 struct device *dev;
171 struct ks8842_tx_dma_ctl dma_tx;
172 struct ks8842_rx_dma_ctl dma_rx;
173};
174
175static void ks8842_dma_rx_cb(void *data);
176static void ks8842_dma_tx_cb(void *data);
177
178static inline void ks8842_resume_dma(struct ks8842_adapter *adapter)
179{
180 iowrite32(1, adapter->hw_addr + REQ_TIMB_DMA_RESUME);
181}
182
183static inline void ks8842_select_bank(struct ks8842_adapter *adapter, u16 bank)
184{
185 iowrite16(bank, adapter->hw_addr + REG_SELECT_BANK);
186}
187
188static inline void ks8842_write8(struct ks8842_adapter *adapter, u16 bank,
189 u8 value, int offset)
190{
191 ks8842_select_bank(adapter, bank);
192 iowrite8(value, adapter->hw_addr + offset);
193}
194
195static inline void ks8842_write16(struct ks8842_adapter *adapter, u16 bank,
196 u16 value, int offset)
197{
198 ks8842_select_bank(adapter, bank);
199 iowrite16(value, adapter->hw_addr + offset);
200}
201
202static inline void ks8842_enable_bits(struct ks8842_adapter *adapter, u16 bank,
203 u16 bits, int offset)
204{
205 u16 reg;
206 ks8842_select_bank(adapter, bank);
207 reg = ioread16(adapter->hw_addr + offset);
208 reg |= bits;
209 iowrite16(reg, adapter->hw_addr + offset);
210}
211
212static inline void ks8842_clear_bits(struct ks8842_adapter *adapter, u16 bank,
213 u16 bits, int offset)
214{
215 u16 reg;
216 ks8842_select_bank(adapter, bank);
217 reg = ioread16(adapter->hw_addr + offset);
218 reg &= ~bits;
219 iowrite16(reg, adapter->hw_addr + offset);
220}
221
222static inline void ks8842_write32(struct ks8842_adapter *adapter, u16 bank,
223 u32 value, int offset)
224{
225 ks8842_select_bank(adapter, bank);
226 iowrite32(value, adapter->hw_addr + offset);
227}
228
229static inline u8 ks8842_read8(struct ks8842_adapter *adapter, u16 bank,
230 int offset)
231{
232 ks8842_select_bank(adapter, bank);
233 return ioread8(adapter->hw_addr + offset);
234}
235
236static inline u16 ks8842_read16(struct ks8842_adapter *adapter, u16 bank,
237 int offset)
238{
239 ks8842_select_bank(adapter, bank);
240 return ioread16(adapter->hw_addr + offset);
241}
242
243static inline u32 ks8842_read32(struct ks8842_adapter *adapter, u16 bank,
244 int offset)
245{
246 ks8842_select_bank(adapter, bank);
247 return ioread32(adapter->hw_addr + offset);
248}
249
250static void ks8842_reset(struct ks8842_adapter *adapter)
251{
252 if (adapter->conf_flags & MICREL_KS884X) {
253 ks8842_write16(adapter, 3, 1, REG_GRR);
254 msleep(10);
255 iowrite16(0, adapter->hw_addr + REG_GRR);
256 } else {
257 /* The KS8842 goes haywire when doing softare reset
258 * a work around in the timberdale IP is implemented to
259 * do a hardware reset instead
260 ks8842_write16(adapter, 3, 1, REG_GRR);
261 msleep(10);
262 iowrite16(0, adapter->hw_addr + REG_GRR);
263 */
264 iowrite32(0x1, adapter->hw_addr + REG_TIMB_RST);
265 msleep(20);
266 }
267}
268
269static void ks8842_update_link_status(struct net_device *netdev,
270 struct ks8842_adapter *adapter)
271{
272 /* check the status of the link */
273 if (ks8842_read16(adapter, 45, REG_P1MBSR) & 0x4) {
274 netif_carrier_on(netdev);
275 netif_wake_queue(netdev);
276 } else {
277 netif_stop_queue(netdev);
278 netif_carrier_off(netdev);
279 }
280}
281
282static void ks8842_enable_tx(struct ks8842_adapter *adapter)
283{
284 ks8842_enable_bits(adapter, 16, 0x01, REG_TXCR);
285}
286
287static void ks8842_disable_tx(struct ks8842_adapter *adapter)
288{
289 ks8842_clear_bits(adapter, 16, 0x01, REG_TXCR);
290}
291
292static void ks8842_enable_rx(struct ks8842_adapter *adapter)
293{
294 ks8842_enable_bits(adapter, 16, 0x01, REG_RXCR);
295}
296
297static void ks8842_disable_rx(struct ks8842_adapter *adapter)
298{
299 ks8842_clear_bits(adapter, 16, 0x01, REG_RXCR);
300}
301
302static void ks8842_reset_hw(struct ks8842_adapter *adapter)
303{
304 /* reset the HW */
305 ks8842_reset(adapter);
306
307 /* Enable QMU Transmit flow control / transmit padding / Transmit CRC */
308 ks8842_write16(adapter, 16, 0x000E, REG_TXCR);
309
310 /* enable the receiver, uni + multi + broadcast + flow ctrl
311 + crc strip */
312 ks8842_write16(adapter, 16, 0x8 | 0x20 | 0x40 | 0x80 | 0x400,
313 REG_RXCR);
314
315 /* TX frame pointer autoincrement */
316 ks8842_write16(adapter, 17, 0x4000, REG_TXFDPR);
317
318 /* RX frame pointer autoincrement */
319 ks8842_write16(adapter, 17, 0x4000, REG_RXFDPR);
320
321 /* RX 2 kb high watermark */
322 ks8842_write16(adapter, 0, 0x1000, REG_QRFCR);
323
324 /* aggressive back off in half duplex */
325 ks8842_enable_bits(adapter, 32, 1 << 8, REG_SGCR1);
326
327 /* enable no excessive collison drop */
328 ks8842_enable_bits(adapter, 32, 1 << 3, REG_SGCR2);
329
330 /* Enable port 1 force flow control / back pressure / transmit / recv */
331 ks8842_write16(adapter, 48, 0x1E07, REG_P1CR2);
332
333 /* restart port auto-negotiation */
334 ks8842_enable_bits(adapter, 49, 1 << 13, REG_P1CR4);
335
336 /* Enable the transmitter */
337 ks8842_enable_tx(adapter);
338
339 /* Enable the receiver */
340 ks8842_enable_rx(adapter);
341
342 /* clear all interrupts */
343 ks8842_write16(adapter, 18, 0xffff, REG_ISR);
344
345 /* enable interrupts */
346 if (KS8842_USE_DMA(adapter)) {
347 /* When running in DMA Mode the RX interrupt is not enabled in
348 timberdale because RX data is received by DMA callbacks
349 it must still be enabled in the KS8842 because it indicates
350 to timberdale when there is RX data for it's DMA FIFOs */
351 iowrite16(ENABLED_IRQS_DMA_IP, adapter->hw_addr + REG_TIMB_IER);
352 ks8842_write16(adapter, 18, ENABLED_IRQS_DMA, REG_IER);
353 } else {
354 if (!(adapter->conf_flags & MICREL_KS884X))
355 iowrite16(ENABLED_IRQS,
356 adapter->hw_addr + REG_TIMB_IER);
357 ks8842_write16(adapter, 18, ENABLED_IRQS, REG_IER);
358 }
359 /* enable the switch */
360 ks8842_write16(adapter, 32, 0x1, REG_SW_ID_AND_ENABLE);
361}
362
363static void ks8842_read_mac_addr(struct ks8842_adapter *adapter, u8 *dest)
364{
365 int i;
366 u16 mac;
367
368 for (i = 0; i < ETH_ALEN; i++)
369 dest[ETH_ALEN - i - 1] = ks8842_read8(adapter, 2, REG_MARL + i);
370
371 if (adapter->conf_flags & MICREL_KS884X) {
372 /*
373 the sequence of saving mac addr between MAC and Switch is
374 different.
375 */
376
377 mac = ks8842_read16(adapter, 2, REG_MARL);
378 ks8842_write16(adapter, 39, mac, REG_MACAR3);
379 mac = ks8842_read16(adapter, 2, REG_MARM);
380 ks8842_write16(adapter, 39, mac, REG_MACAR2);
381 mac = ks8842_read16(adapter, 2, REG_MARH);
382 ks8842_write16(adapter, 39, mac, REG_MACAR1);
383 } else {
384
385 /* make sure the switch port uses the same MAC as the QMU */
386 mac = ks8842_read16(adapter, 2, REG_MARL);
387 ks8842_write16(adapter, 39, mac, REG_MACAR1);
388 mac = ks8842_read16(adapter, 2, REG_MARM);
389 ks8842_write16(adapter, 39, mac, REG_MACAR2);
390 mac = ks8842_read16(adapter, 2, REG_MARH);
391 ks8842_write16(adapter, 39, mac, REG_MACAR3);
392 }
393}
394
395static void ks8842_write_mac_addr(struct ks8842_adapter *adapter, u8 *mac)
396{
397 unsigned long flags;
398 unsigned i;
399
400 spin_lock_irqsave(&adapter->lock, flags);
401 for (i = 0; i < ETH_ALEN; i++) {
402 ks8842_write8(adapter, 2, mac[ETH_ALEN - i - 1], REG_MARL + i);
403 if (!(adapter->conf_flags & MICREL_KS884X))
404 ks8842_write8(adapter, 39, mac[ETH_ALEN - i - 1],
405 REG_MACAR1 + i);
406 }
407
408 if (adapter->conf_flags & MICREL_KS884X) {
409 /*
410 the sequence of saving mac addr between MAC and Switch is
411 different.
412 */
413
414 u16 mac;
415
416 mac = ks8842_read16(adapter, 2, REG_MARL);
417 ks8842_write16(adapter, 39, mac, REG_MACAR3);
418 mac = ks8842_read16(adapter, 2, REG_MARM);
419 ks8842_write16(adapter, 39, mac, REG_MACAR2);
420 mac = ks8842_read16(adapter, 2, REG_MARH);
421 ks8842_write16(adapter, 39, mac, REG_MACAR1);
422 }
423 spin_unlock_irqrestore(&adapter->lock, flags);
424}
425
426static inline u16 ks8842_tx_fifo_space(struct ks8842_adapter *adapter)
427{
428 return ks8842_read16(adapter, 16, REG_TXMIR) & 0x1fff;
429}
430
431static int ks8842_tx_frame_dma(struct sk_buff *skb, struct net_device *netdev)
432{
433 struct ks8842_adapter *adapter = netdev_priv(netdev);
434 struct ks8842_tx_dma_ctl *ctl = &adapter->dma_tx;
435 u8 *buf = ctl->buf;
436
437 if (ctl->adesc) {
438 netdev_dbg(netdev, "%s: TX ongoing\n", __func__);
439 /* transfer ongoing */
440 return NETDEV_TX_BUSY;
441 }
442
443 sg_dma_len(&ctl->sg) = skb->len + sizeof(u32);
444
445 /* copy data to the TX buffer */
446 /* the control word, enable IRQ, port 1 and the length */
447 *buf++ = 0x00;
448 *buf++ = 0x01; /* Port 1 */
449 *buf++ = skb->len & 0xff;
450 *buf++ = (skb->len >> 8) & 0xff;
451 skb_copy_from_linear_data(skb, buf, skb->len);
452
453 dma_sync_single_range_for_device(adapter->dev,
454 sg_dma_address(&ctl->sg), 0, sg_dma_len(&ctl->sg),
455 DMA_TO_DEVICE);
456
457 /* make sure the length is a multiple of 4 */
458 if (sg_dma_len(&ctl->sg) % 4)
459 sg_dma_len(&ctl->sg) += 4 - sg_dma_len(&ctl->sg) % 4;
460
461 ctl->adesc = ctl->chan->device->device_prep_slave_sg(ctl->chan,
462 &ctl->sg, 1, DMA_TO_DEVICE,
463 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP);
464 if (!ctl->adesc)
465 return NETDEV_TX_BUSY;
466
467 ctl->adesc->callback_param = netdev;
468 ctl->adesc->callback = ks8842_dma_tx_cb;
469 ctl->adesc->tx_submit(ctl->adesc);
470
471 netdev->stats.tx_bytes += skb->len;
472
473 dev_kfree_skb(skb);
474
475 return NETDEV_TX_OK;
476}
477
478static int ks8842_tx_frame(struct sk_buff *skb, struct net_device *netdev)
479{
480 struct ks8842_adapter *adapter = netdev_priv(netdev);
481 int len = skb->len;
482
483 netdev_dbg(netdev, "%s: len %u head %p data %p tail %p end %p\n",
484 __func__, skb->len, skb->head, skb->data,
485 skb_tail_pointer(skb), skb_end_pointer(skb));
486
487 /* check FIFO buffer space, we need space for CRC and command bits */
488 if (ks8842_tx_fifo_space(adapter) < len + 8)
489 return NETDEV_TX_BUSY;
490
491 if (adapter->conf_flags & KS884X_16BIT) {
492 u16 *ptr16 = (u16 *)skb->data;
493 ks8842_write16(adapter, 17, 0x8000 | 0x100, REG_QMU_DATA_LO);
494 ks8842_write16(adapter, 17, (u16)len, REG_QMU_DATA_HI);
495 netdev->stats.tx_bytes += len;
496
497 /* copy buffer */
498 while (len > 0) {
499 iowrite16(*ptr16++, adapter->hw_addr + REG_QMU_DATA_LO);
500 iowrite16(*ptr16++, adapter->hw_addr + REG_QMU_DATA_HI);
501 len -= sizeof(u32);
502 }
503 } else {
504
505 u32 *ptr = (u32 *)skb->data;
506 u32 ctrl;
507 /* the control word, enable IRQ, port 1 and the length */
508 ctrl = 0x8000 | 0x100 | (len << 16);
509 ks8842_write32(adapter, 17, ctrl, REG_QMU_DATA_LO);
510
511 netdev->stats.tx_bytes += len;
512
513 /* copy buffer */
514 while (len > 0) {
515 iowrite32(*ptr, adapter->hw_addr + REG_QMU_DATA_LO);
516 len -= sizeof(u32);
517 ptr++;
518 }
519 }
520
521 /* enqueue packet */
522 ks8842_write16(adapter, 17, 1, REG_TXQCR);
523
524 dev_kfree_skb(skb);
525
526 return NETDEV_TX_OK;
527}
528
529static void ks8842_update_rx_err_counters(struct net_device *netdev, u32 status)
530{
531 netdev_dbg(netdev, "RX error, status: %x\n", status);
532
533 netdev->stats.rx_errors++;
534 if (status & RXSR_TOO_LONG)
535 netdev->stats.rx_length_errors++;
536 if (status & RXSR_CRC_ERROR)
537 netdev->stats.rx_crc_errors++;
538 if (status & RXSR_RUNT)
539 netdev->stats.rx_frame_errors++;
540}
541
542static void ks8842_update_rx_counters(struct net_device *netdev, u32 status,
543 int len)
544{
545 netdev_dbg(netdev, "RX packet, len: %d\n", len);
546
547 netdev->stats.rx_packets++;
548 netdev->stats.rx_bytes += len;
549 if (status & RXSR_MULTICAST)
550 netdev->stats.multicast++;
551}
552
553static int __ks8842_start_new_rx_dma(struct net_device *netdev)
554{
555 struct ks8842_adapter *adapter = netdev_priv(netdev);
556 struct ks8842_rx_dma_ctl *ctl = &adapter->dma_rx;
557 struct scatterlist *sg = &ctl->sg;
558 int err;
559
560 ctl->skb = netdev_alloc_skb(netdev, DMA_BUFFER_SIZE);
561 if (ctl->skb) {
562 sg_init_table(sg, 1);
563 sg_dma_address(sg) = dma_map_single(adapter->dev,
564 ctl->skb->data, DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
565 err = dma_mapping_error(adapter->dev, sg_dma_address(sg));
566 if (unlikely(err)) {
567 sg_dma_address(sg) = 0;
568 goto out;
569 }
570
571 sg_dma_len(sg) = DMA_BUFFER_SIZE;
572
573 ctl->adesc = ctl->chan->device->device_prep_slave_sg(ctl->chan,
574 sg, 1, DMA_FROM_DEVICE,
575 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP);
576
577 if (!ctl->adesc)
578 goto out;
579
580 ctl->adesc->callback_param = netdev;
581 ctl->adesc->callback = ks8842_dma_rx_cb;
582 ctl->adesc->tx_submit(ctl->adesc);
583 } else {
584 err = -ENOMEM;
585 sg_dma_address(sg) = 0;
586 goto out;
587 }
588
589 return err;
590out:
591 if (sg_dma_address(sg))
592 dma_unmap_single(adapter->dev, sg_dma_address(sg),
593 DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
594 sg_dma_address(sg) = 0;
595 if (ctl->skb)
596 dev_kfree_skb(ctl->skb);
597
598 ctl->skb = NULL;
599
600 printk(KERN_ERR DRV_NAME": Failed to start RX DMA: %d\n", err);
601 return err;
602}
603
604static void ks8842_rx_frame_dma_tasklet(unsigned long arg)
605{
606 struct net_device *netdev = (struct net_device *)arg;
607 struct ks8842_adapter *adapter = netdev_priv(netdev);
608 struct ks8842_rx_dma_ctl *ctl = &adapter->dma_rx;
609 struct sk_buff *skb = ctl->skb;
610 dma_addr_t addr = sg_dma_address(&ctl->sg);
611 u32 status;
612
613 ctl->adesc = NULL;
614
615 /* kick next transfer going */
616 __ks8842_start_new_rx_dma(netdev);
617
618 /* now handle the data we got */
619 dma_unmap_single(adapter->dev, addr, DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
620
621 status = *((u32 *)skb->data);
622
623 netdev_dbg(netdev, "%s - rx_data: status: %x\n",
624 __func__, status & 0xffff);
625
626 /* check the status */
627 if ((status & RXSR_VALID) && !(status & RXSR_ERROR)) {
628 int len = (status >> 16) & 0x7ff;
629
630 ks8842_update_rx_counters(netdev, status, len);
631
632 /* reserve 4 bytes which is the status word */
633 skb_reserve(skb, 4);
634 skb_put(skb, len);
635
636 skb->protocol = eth_type_trans(skb, netdev);
637 netif_rx(skb);
638 } else {
639 ks8842_update_rx_err_counters(netdev, status);
640 dev_kfree_skb(skb);
641 }
642}
643
644static void ks8842_rx_frame(struct net_device *netdev,
645 struct ks8842_adapter *adapter)
646{
647 u32 status;
648 int len;
649
650 if (adapter->conf_flags & KS884X_16BIT) {
651 status = ks8842_read16(adapter, 17, REG_QMU_DATA_LO);
652 len = ks8842_read16(adapter, 17, REG_QMU_DATA_HI);
653 netdev_dbg(netdev, "%s - rx_data: status: %x\n",
654 __func__, status);
655 } else {
656 status = ks8842_read32(adapter, 17, REG_QMU_DATA_LO);
657 len = (status >> 16) & 0x7ff;
658 status &= 0xffff;
659 netdev_dbg(netdev, "%s - rx_data: status: %x\n",
660 __func__, status);
661 }
662
663 /* check the status */
664 if ((status & RXSR_VALID) && !(status & RXSR_ERROR)) {
665 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev, len + 3);
666
667 if (skb) {
668
669 ks8842_update_rx_counters(netdev, status, len);
670
671 if (adapter->conf_flags & KS884X_16BIT) {
672 u16 *data16 = (u16 *)skb_put(skb, len);
673 ks8842_select_bank(adapter, 17);
674 while (len > 0) {
675 *data16++ = ioread16(adapter->hw_addr +
676 REG_QMU_DATA_LO);
677 *data16++ = ioread16(adapter->hw_addr +
678 REG_QMU_DATA_HI);
679 len -= sizeof(u32);
680 }
681 } else {
682 u32 *data = (u32 *)skb_put(skb, len);
683
684 ks8842_select_bank(adapter, 17);
685 while (len > 0) {
686 *data++ = ioread32(adapter->hw_addr +
687 REG_QMU_DATA_LO);
688 len -= sizeof(u32);
689 }
690 }
691 skb->protocol = eth_type_trans(skb, netdev);
692 netif_rx(skb);
693 } else
694 netdev->stats.rx_dropped++;
695 } else
696 ks8842_update_rx_err_counters(netdev, status);
697
698 /* set high watermark to 3K */
699 ks8842_clear_bits(adapter, 0, 1 << 12, REG_QRFCR);
700
701 /* release the frame */
702 ks8842_write16(adapter, 17, 0x01, REG_RXQCR);
703
704 /* set high watermark to 2K */
705 ks8842_enable_bits(adapter, 0, 1 << 12, REG_QRFCR);
706}
707
708void ks8842_handle_rx(struct net_device *netdev, struct ks8842_adapter *adapter)
709{
710 u16 rx_data = ks8842_read16(adapter, 16, REG_RXMIR) & 0x1fff;
711 netdev_dbg(netdev, "%s Entry - rx_data: %d\n", __func__, rx_data);
712 while (rx_data) {
713 ks8842_rx_frame(netdev, adapter);
714 rx_data = ks8842_read16(adapter, 16, REG_RXMIR) & 0x1fff;
715 }
716}
717
718void ks8842_handle_tx(struct net_device *netdev, struct ks8842_adapter *adapter)
719{
720 u16 sr = ks8842_read16(adapter, 16, REG_TXSR);
721 netdev_dbg(netdev, "%s - entry, sr: %x\n", __func__, sr);
722 netdev->stats.tx_packets++;
723 if (netif_queue_stopped(netdev))
724 netif_wake_queue(netdev);
725}
726
727void ks8842_handle_rx_overrun(struct net_device *netdev,
728 struct ks8842_adapter *adapter)
729{
730 netdev_dbg(netdev, "%s: entry\n", __func__);
731 netdev->stats.rx_errors++;
732 netdev->stats.rx_fifo_errors++;
733}
734
735void ks8842_tasklet(unsigned long arg)
736{
737 struct net_device *netdev = (struct net_device *)arg;
738 struct ks8842_adapter *adapter = netdev_priv(netdev);
739 u16 isr;
740 unsigned long flags;
741 u16 entry_bank;
742
743 /* read current bank to be able to set it back */
744 spin_lock_irqsave(&adapter->lock, flags);
745 entry_bank = ioread16(adapter->hw_addr + REG_SELECT_BANK);
746 spin_unlock_irqrestore(&adapter->lock, flags);
747
748 isr = ks8842_read16(adapter, 18, REG_ISR);
749 netdev_dbg(netdev, "%s - ISR: 0x%x\n", __func__, isr);
750
751 /* when running in DMA mode, do not ack RX interrupts, it is handled
752 internally by timberdale, otherwise it's DMA FIFO:s would stop
753 */
754 if (KS8842_USE_DMA(adapter))
755 isr &= ~IRQ_RX;
756
757 /* Ack */
758 ks8842_write16(adapter, 18, isr, REG_ISR);
759
760 if (!(adapter->conf_flags & MICREL_KS884X))
761 /* Ack in the timberdale IP as well */
762 iowrite32(0x1, adapter->hw_addr + REG_TIMB_IAR);
763
764 if (!netif_running(netdev))
765 return;
766
767 if (isr & IRQ_LINK_CHANGE)
768 ks8842_update_link_status(netdev, adapter);
769
770 /* should not get IRQ_RX when running DMA mode */
771 if (isr & (IRQ_RX | IRQ_RX_ERROR) && !KS8842_USE_DMA(adapter))
772 ks8842_handle_rx(netdev, adapter);
773
774 /* should only happen when in PIO mode */
775 if (isr & IRQ_TX)
776 ks8842_handle_tx(netdev, adapter);
777
778 if (isr & IRQ_RX_OVERRUN)
779 ks8842_handle_rx_overrun(netdev, adapter);
780
781 if (isr & IRQ_TX_STOPPED) {
782 ks8842_disable_tx(adapter);
783 ks8842_enable_tx(adapter);
784 }
785
786 if (isr & IRQ_RX_STOPPED) {
787 ks8842_disable_rx(adapter);
788 ks8842_enable_rx(adapter);
789 }
790
791 /* re-enable interrupts, put back the bank selection register */
792 spin_lock_irqsave(&adapter->lock, flags);
793 if (KS8842_USE_DMA(adapter))
794 ks8842_write16(adapter, 18, ENABLED_IRQS_DMA, REG_IER);
795 else
796 ks8842_write16(adapter, 18, ENABLED_IRQS, REG_IER);
797 iowrite16(entry_bank, adapter->hw_addr + REG_SELECT_BANK);
798
799 /* Make sure timberdale continues DMA operations, they are stopped while
800 we are handling the ks8842 because we might change bank */
801 if (KS8842_USE_DMA(adapter))
802 ks8842_resume_dma(adapter);
803
804 spin_unlock_irqrestore(&adapter->lock, flags);
805}
806
807static irqreturn_t ks8842_irq(int irq, void *devid)
808{
809 struct net_device *netdev = devid;
810 struct ks8842_adapter *adapter = netdev_priv(netdev);
811 u16 isr;
812 u16 entry_bank = ioread16(adapter->hw_addr + REG_SELECT_BANK);
813 irqreturn_t ret = IRQ_NONE;
814
815 isr = ks8842_read16(adapter, 18, REG_ISR);
816 netdev_dbg(netdev, "%s - ISR: 0x%x\n", __func__, isr);
817
818 if (isr) {
819 if (KS8842_USE_DMA(adapter))
820 /* disable all but RX IRQ, since the FPGA relies on it*/
821 ks8842_write16(adapter, 18, IRQ_RX, REG_IER);
822 else
823 /* disable IRQ */
824 ks8842_write16(adapter, 18, 0x00, REG_IER);
825
826 /* schedule tasklet */
827 tasklet_schedule(&adapter->tasklet);
828
829 ret = IRQ_HANDLED;
830 }
831
832 iowrite16(entry_bank, adapter->hw_addr + REG_SELECT_BANK);
833
834 /* After an interrupt, tell timberdale to continue DMA operations.
835 DMA is disabled while we are handling the ks8842 because we might
836 change bank */
837 ks8842_resume_dma(adapter);
838
839 return ret;
840}
841
842static void ks8842_dma_rx_cb(void *data)
843{
844 struct net_device *netdev = data;
845 struct ks8842_adapter *adapter = netdev_priv(netdev);
846
847 netdev_dbg(netdev, "RX DMA finished\n");
848 /* schedule tasklet */
849 if (adapter->dma_rx.adesc)
850 tasklet_schedule(&adapter->dma_rx.tasklet);
851}
852
853static void ks8842_dma_tx_cb(void *data)
854{
855 struct net_device *netdev = data;
856 struct ks8842_adapter *adapter = netdev_priv(netdev);
857 struct ks8842_tx_dma_ctl *ctl = &adapter->dma_tx;
858
859 netdev_dbg(netdev, "TX DMA finished\n");
860
861 if (!ctl->adesc)
862 return;
863
864 netdev->stats.tx_packets++;
865 ctl->adesc = NULL;
866
867 if (netif_queue_stopped(netdev))
868 netif_wake_queue(netdev);
869}
870
871static void ks8842_stop_dma(struct ks8842_adapter *adapter)
872{
873 struct ks8842_tx_dma_ctl *tx_ctl = &adapter->dma_tx;
874 struct ks8842_rx_dma_ctl *rx_ctl = &adapter->dma_rx;
875
876 tx_ctl->adesc = NULL;
877 if (tx_ctl->chan)
878 tx_ctl->chan->device->device_control(tx_ctl->chan,
879 DMA_TERMINATE_ALL, 0);
880
881 rx_ctl->adesc = NULL;
882 if (rx_ctl->chan)
883 rx_ctl->chan->device->device_control(rx_ctl->chan,
884 DMA_TERMINATE_ALL, 0);
885
886 if (sg_dma_address(&rx_ctl->sg))
887 dma_unmap_single(adapter->dev, sg_dma_address(&rx_ctl->sg),
888 DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
889 sg_dma_address(&rx_ctl->sg) = 0;
890
891 dev_kfree_skb(rx_ctl->skb);
892 rx_ctl->skb = NULL;
893}
894
895static void ks8842_dealloc_dma_bufs(struct ks8842_adapter *adapter)
896{
897 struct ks8842_tx_dma_ctl *tx_ctl = &adapter->dma_tx;
898 struct ks8842_rx_dma_ctl *rx_ctl = &adapter->dma_rx;
899
900 ks8842_stop_dma(adapter);
901
902 if (tx_ctl->chan)
903 dma_release_channel(tx_ctl->chan);
904 tx_ctl->chan = NULL;
905
906 if (rx_ctl->chan)
907 dma_release_channel(rx_ctl->chan);
908 rx_ctl->chan = NULL;
909
910 tasklet_kill(&rx_ctl->tasklet);
911
912 if (sg_dma_address(&tx_ctl->sg))
913 dma_unmap_single(adapter->dev, sg_dma_address(&tx_ctl->sg),
914 DMA_BUFFER_SIZE, DMA_TO_DEVICE);
915 sg_dma_address(&tx_ctl->sg) = 0;
916
917 kfree(tx_ctl->buf);
918 tx_ctl->buf = NULL;
919}
920
921static bool ks8842_dma_filter_fn(struct dma_chan *chan, void *filter_param)
922{
923 return chan->chan_id == (long)filter_param;
924}
925
926static int ks8842_alloc_dma_bufs(struct net_device *netdev)
927{
928 struct ks8842_adapter *adapter = netdev_priv(netdev);
929 struct ks8842_tx_dma_ctl *tx_ctl = &adapter->dma_tx;
930 struct ks8842_rx_dma_ctl *rx_ctl = &adapter->dma_rx;
931 int err;
932
933 dma_cap_mask_t mask;
934
935 dma_cap_zero(mask);
936 dma_cap_set(DMA_SLAVE, mask);
937 dma_cap_set(DMA_PRIVATE, mask);
938
939 sg_init_table(&tx_ctl->sg, 1);
940
941 tx_ctl->chan = dma_request_channel(mask, ks8842_dma_filter_fn,
942 (void *)(long)tx_ctl->channel);
943 if (!tx_ctl->chan) {
944 err = -ENODEV;
945 goto err;
946 }
947
948 /* allocate DMA buffer */
949 tx_ctl->buf = kmalloc(DMA_BUFFER_SIZE, GFP_KERNEL);
950 if (!tx_ctl->buf) {
951 err = -ENOMEM;
952 goto err;
953 }
954
955 sg_dma_address(&tx_ctl->sg) = dma_map_single(adapter->dev,
956 tx_ctl->buf, DMA_BUFFER_SIZE, DMA_TO_DEVICE);
957 err = dma_mapping_error(adapter->dev,
958 sg_dma_address(&tx_ctl->sg));
959 if (err) {
960 sg_dma_address(&tx_ctl->sg) = 0;
961 goto err;
962 }
963
964 rx_ctl->chan = dma_request_channel(mask, ks8842_dma_filter_fn,
965 (void *)(long)rx_ctl->channel);
966 if (!rx_ctl->chan) {
967 err = -ENODEV;
968 goto err;
969 }
970
971 tasklet_init(&rx_ctl->tasklet, ks8842_rx_frame_dma_tasklet,
972 (unsigned long)netdev);
973
974 return 0;
975err:
976 ks8842_dealloc_dma_bufs(adapter);
977 return err;
978}
979
980/* Netdevice operations */
981
982static int ks8842_open(struct net_device *netdev)
983{
984 struct ks8842_adapter *adapter = netdev_priv(netdev);
985 int err;
986
987 netdev_dbg(netdev, "%s - entry\n", __func__);
988
989 if (KS8842_USE_DMA(adapter)) {
990 err = ks8842_alloc_dma_bufs(netdev);
991
992 if (!err) {
993 /* start RX dma */
994 err = __ks8842_start_new_rx_dma(netdev);
995 if (err)
996 ks8842_dealloc_dma_bufs(adapter);
997 }
998
999 if (err) {
1000 printk(KERN_WARNING DRV_NAME
1001 ": Failed to initiate DMA, running PIO\n");
1002 ks8842_dealloc_dma_bufs(adapter);
1003 adapter->dma_rx.channel = -1;
1004 adapter->dma_tx.channel = -1;
1005 }
1006 }
1007
1008 /* reset the HW */
1009 ks8842_reset_hw(adapter);
1010
1011 ks8842_write_mac_addr(adapter, netdev->dev_addr);
1012
1013 ks8842_update_link_status(netdev, adapter);
1014
1015 err = request_irq(adapter->irq, ks8842_irq, IRQF_SHARED, DRV_NAME,
1016 netdev);
1017 if (err) {
1018 pr_err("Failed to request IRQ: %d: %d\n", adapter->irq, err);
1019 return err;
1020 }
1021
1022 return 0;
1023}
1024
1025static int ks8842_close(struct net_device *netdev)
1026{
1027 struct ks8842_adapter *adapter = netdev_priv(netdev);
1028
1029 netdev_dbg(netdev, "%s - entry\n", __func__);
1030
1031 cancel_work_sync(&adapter->timeout_work);
1032
1033 if (KS8842_USE_DMA(adapter))
1034 ks8842_dealloc_dma_bufs(adapter);
1035
1036 /* free the irq */
1037 free_irq(adapter->irq, netdev);
1038
1039 /* disable the switch */
1040 ks8842_write16(adapter, 32, 0x0, REG_SW_ID_AND_ENABLE);
1041
1042 return 0;
1043}
1044
1045static netdev_tx_t ks8842_xmit_frame(struct sk_buff *skb,
1046 struct net_device *netdev)
1047{
1048 int ret;
1049 struct ks8842_adapter *adapter = netdev_priv(netdev);
1050
1051 netdev_dbg(netdev, "%s: entry\n", __func__);
1052
1053 if (KS8842_USE_DMA(adapter)) {
1054 unsigned long flags;
1055 ret = ks8842_tx_frame_dma(skb, netdev);
1056 /* for now only allow one transfer at the time */
1057 spin_lock_irqsave(&adapter->lock, flags);
1058 if (adapter->dma_tx.adesc)
1059 netif_stop_queue(netdev);
1060 spin_unlock_irqrestore(&adapter->lock, flags);
1061 return ret;
1062 }
1063
1064 ret = ks8842_tx_frame(skb, netdev);
1065
1066 if (ks8842_tx_fifo_space(adapter) < netdev->mtu + 8)
1067 netif_stop_queue(netdev);
1068
1069 return ret;
1070}
1071
1072static int ks8842_set_mac(struct net_device *netdev, void *p)
1073{
1074 struct ks8842_adapter *adapter = netdev_priv(netdev);
1075 struct sockaddr *addr = p;
1076 char *mac = (u8 *)addr->sa_data;
1077
1078 netdev_dbg(netdev, "%s: entry\n", __func__);
1079
1080 if (!is_valid_ether_addr(addr->sa_data))
1081 return -EADDRNOTAVAIL;
1082
1083 memcpy(netdev->dev_addr, mac, netdev->addr_len);
1084
1085 ks8842_write_mac_addr(adapter, mac);
1086 return 0;
1087}
1088
1089static void ks8842_tx_timeout_work(struct work_struct *work)
1090{
1091 struct ks8842_adapter *adapter =
1092 container_of(work, struct ks8842_adapter, timeout_work);
1093 struct net_device *netdev = adapter->netdev;
1094 unsigned long flags;
1095
1096 netdev_dbg(netdev, "%s: entry\n", __func__);
1097
1098 spin_lock_irqsave(&adapter->lock, flags);
1099
1100 if (KS8842_USE_DMA(adapter))
1101 ks8842_stop_dma(adapter);
1102
1103 /* disable interrupts */
1104 ks8842_write16(adapter, 18, 0, REG_IER);
1105 ks8842_write16(adapter, 18, 0xFFFF, REG_ISR);
1106
1107 netif_stop_queue(netdev);
1108
1109 spin_unlock_irqrestore(&adapter->lock, flags);
1110
1111 ks8842_reset_hw(adapter);
1112
1113 ks8842_write_mac_addr(adapter, netdev->dev_addr);
1114
1115 ks8842_update_link_status(netdev, adapter);
1116
1117 if (KS8842_USE_DMA(adapter))
1118 __ks8842_start_new_rx_dma(netdev);
1119}
1120
1121static void ks8842_tx_timeout(struct net_device *netdev)
1122{
1123 struct ks8842_adapter *adapter = netdev_priv(netdev);
1124
1125 netdev_dbg(netdev, "%s: entry\n", __func__);
1126
1127 schedule_work(&adapter->timeout_work);
1128}
1129
1130static const struct net_device_ops ks8842_netdev_ops = {
1131 .ndo_open = ks8842_open,
1132 .ndo_stop = ks8842_close,
1133 .ndo_start_xmit = ks8842_xmit_frame,
1134 .ndo_set_mac_address = ks8842_set_mac,
1135 .ndo_tx_timeout = ks8842_tx_timeout,
1136 .ndo_validate_addr = eth_validate_addr
1137};
1138
1139static const struct ethtool_ops ks8842_ethtool_ops = {
1140 .get_link = ethtool_op_get_link,
1141};
1142
1143static int __devinit ks8842_probe(struct platform_device *pdev)
1144{
1145 int err = -ENOMEM;
1146 struct resource *iomem;
1147 struct net_device *netdev;
1148 struct ks8842_adapter *adapter;
1149 struct ks8842_platform_data *pdata = pdev->dev.platform_data;
1150 u16 id;
1151 unsigned i;
1152
1153 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154 if (!request_mem_region(iomem->start, resource_size(iomem), DRV_NAME))
1155 goto err_mem_region;
1156
1157 netdev = alloc_etherdev(sizeof(struct ks8842_adapter));
1158 if (!netdev)
1159 goto err_alloc_etherdev;
1160
1161 SET_NETDEV_DEV(netdev, &pdev->dev);
1162
1163 adapter = netdev_priv(netdev);
1164 adapter->netdev = netdev;
1165 INIT_WORK(&adapter->timeout_work, ks8842_tx_timeout_work);
1166 adapter->hw_addr = ioremap(iomem->start, resource_size(iomem));
1167 adapter->conf_flags = iomem->flags;
1168
1169 if (!adapter->hw_addr)
1170 goto err_ioremap;
1171
1172 adapter->irq = platform_get_irq(pdev, 0);
1173 if (adapter->irq < 0) {
1174 err = adapter->irq;
1175 goto err_get_irq;
1176 }
1177
1178 adapter->dev = (pdev->dev.parent) ? pdev->dev.parent : &pdev->dev;
1179
1180 /* DMA is only supported when accessed via timberdale */
1181 if (!(adapter->conf_flags & MICREL_KS884X) && pdata &&
1182 (pdata->tx_dma_channel != -1) &&
1183 (pdata->rx_dma_channel != -1)) {
1184 adapter->dma_rx.channel = pdata->rx_dma_channel;
1185 adapter->dma_tx.channel = pdata->tx_dma_channel;
1186 } else {
1187 adapter->dma_rx.channel = -1;
1188 adapter->dma_tx.channel = -1;
1189 }
1190
1191 tasklet_init(&adapter->tasklet, ks8842_tasklet, (unsigned long)netdev);
1192 spin_lock_init(&adapter->lock);
1193
1194 netdev->netdev_ops = &ks8842_netdev_ops;
1195 netdev->ethtool_ops = &ks8842_ethtool_ops;
1196
1197 /* Check if a mac address was given */
1198 i = netdev->addr_len;
1199 if (pdata) {
1200 for (i = 0; i < netdev->addr_len; i++)
1201 if (pdata->macaddr[i] != 0)
1202 break;
1203
1204 if (i < netdev->addr_len)
1205 /* an address was passed, use it */
1206 memcpy(netdev->dev_addr, pdata->macaddr,
1207 netdev->addr_len);
1208 }
1209
1210 if (i == netdev->addr_len) {
1211 ks8842_read_mac_addr(adapter, netdev->dev_addr);
1212
1213 if (!is_valid_ether_addr(netdev->dev_addr))
1214 random_ether_addr(netdev->dev_addr);
1215 }
1216
1217 id = ks8842_read16(adapter, 32, REG_SW_ID_AND_ENABLE);
1218
1219 strcpy(netdev->name, "eth%d");
1220 err = register_netdev(netdev);
1221 if (err)
1222 goto err_register;
1223
1224 platform_set_drvdata(pdev, netdev);
1225
1226 pr_info("Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1227 (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7);
1228
1229 return 0;
1230
1231err_register:
1232err_get_irq:
1233 iounmap(adapter->hw_addr);
1234err_ioremap:
1235 free_netdev(netdev);
1236err_alloc_etherdev:
1237 release_mem_region(iomem->start, resource_size(iomem));
1238err_mem_region:
1239 return err;
1240}
1241
1242static int __devexit ks8842_remove(struct platform_device *pdev)
1243{
1244 struct net_device *netdev = platform_get_drvdata(pdev);
1245 struct ks8842_adapter *adapter = netdev_priv(netdev);
1246 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1247
1248 unregister_netdev(netdev);
1249 tasklet_kill(&adapter->tasklet);
1250 iounmap(adapter->hw_addr);
1251 free_netdev(netdev);
1252 release_mem_region(iomem->start, resource_size(iomem));
1253 platform_set_drvdata(pdev, NULL);
1254 return 0;
1255}
1256
1257
1258static struct platform_driver ks8842_platform_driver = {
1259 .driver = {
1260 .name = DRV_NAME,
1261 .owner = THIS_MODULE,
1262 },
1263 .probe = ks8842_probe,
1264 .remove = ks8842_remove,
1265};
1266
1267static int __init ks8842_init(void)
1268{
1269 return platform_driver_register(&ks8842_platform_driver);
1270}
1271
1272static void __exit ks8842_exit(void)
1273{
1274 platform_driver_unregister(&ks8842_platform_driver);
1275}
1276
1277module_init(ks8842_init);
1278module_exit(ks8842_exit);
1279
1280MODULE_DESCRIPTION("Timberdale KS8842 ethernet driver");
1281MODULE_AUTHOR("Mocean Laboratories <info@mocean-labs.com>");
1282MODULE_LICENSE("GPL v2");
1283MODULE_ALIAS("platform:ks8842");
1284
diff --git a/drivers/net/ethernet/micrel/ks8851.c b/drivers/net/ethernet/micrel/ks8851.c
new file mode 100644
index 000000000000..f56743a28fc0
--- /dev/null
+++ b/drivers/net/ethernet/micrel/ks8851.c
@@ -0,0 +1,1737 @@
1/* drivers/net/ks8851.c
2 *
3 * Copyright 2009 Simtec Electronics
4 * http://www.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#define DEBUG
15
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
22#include <linux/cache.h>
23#include <linux/crc32.h>
24#include <linux/mii.h>
25
26#include <linux/spi/spi.h>
27
28#include "ks8851.h"
29
30/**
31 * struct ks8851_rxctrl - KS8851 driver rx control
32 * @mchash: Multicast hash-table data.
33 * @rxcr1: KS_RXCR1 register setting
34 * @rxcr2: KS_RXCR2 register setting
35 *
36 * Representation of the settings needs to control the receive filtering
37 * such as the multicast hash-filter and the receive register settings. This
38 * is used to make the job of working out if the receive settings change and
39 * then issuing the new settings to the worker that will send the necessary
40 * commands.
41 */
42struct ks8851_rxctrl {
43 u16 mchash[4];
44 u16 rxcr1;
45 u16 rxcr2;
46};
47
48/**
49 * union ks8851_tx_hdr - tx header data
50 * @txb: The header as bytes
51 * @txw: The header as 16bit, little-endian words
52 *
53 * A dual representation of the tx header data to allow
54 * access to individual bytes, and to allow 16bit accesses
55 * with 16bit alignment.
56 */
57union ks8851_tx_hdr {
58 u8 txb[6];
59 __le16 txw[3];
60};
61
62/**
63 * struct ks8851_net - KS8851 driver private data
64 * @netdev: The network device we're bound to
65 * @spidev: The spi device we're bound to.
66 * @lock: Lock to ensure that the device is not accessed when busy.
67 * @statelock: Lock on this structure for tx list.
68 * @mii: The MII state information for the mii calls.
69 * @rxctrl: RX settings for @rxctrl_work.
70 * @tx_work: Work queue for tx packets
71 * @irq_work: Work queue for servicing interrupts
72 * @rxctrl_work: Work queue for updating RX mode and multicast lists
73 * @txq: Queue of packets for transmission.
74 * @spi_msg1: pre-setup SPI transfer with one message, @spi_xfer1.
75 * @spi_msg2: pre-setup SPI transfer with two messages, @spi_xfer2.
76 * @txh: Space for generating packet TX header in DMA-able data
77 * @rxd: Space for receiving SPI data, in DMA-able space.
78 * @txd: Space for transmitting SPI data, in DMA-able space.
79 * @msg_enable: The message flags controlling driver output (see ethtool).
80 * @fid: Incrementing frame id tag.
81 * @rc_ier: Cached copy of KS_IER.
82 * @rc_ccr: Cached copy of KS_CCR.
83 * @rc_rxqcr: Cached copy of KS_RXQCR.
84 * @eeprom_size: Companion eeprom size in Bytes, 0 if no eeprom
85 *
86 * The @lock ensures that the chip is protected when certain operations are
87 * in progress. When the read or write packet transfer is in progress, most
88 * of the chip registers are not ccessible until the transfer is finished and
89 * the DMA has been de-asserted.
90 *
91 * The @statelock is used to protect information in the structure which may
92 * need to be accessed via several sources, such as the network driver layer
93 * or one of the work queues.
94 *
95 * We align the buffers we may use for rx/tx to ensure that if the SPI driver
96 * wants to DMA map them, it will not have any problems with data the driver
97 * modifies.
98 */
99struct ks8851_net {
100 struct net_device *netdev;
101 struct spi_device *spidev;
102 struct mutex lock;
103 spinlock_t statelock;
104
105 union ks8851_tx_hdr txh ____cacheline_aligned;
106 u8 rxd[8];
107 u8 txd[8];
108
109 u32 msg_enable ____cacheline_aligned;
110 u16 tx_space;
111 u8 fid;
112
113 u16 rc_ier;
114 u16 rc_rxqcr;
115 u16 rc_ccr;
116 u16 eeprom_size;
117
118 struct mii_if_info mii;
119 struct ks8851_rxctrl rxctrl;
120
121 struct work_struct tx_work;
122 struct work_struct irq_work;
123 struct work_struct rxctrl_work;
124
125 struct sk_buff_head txq;
126
127 struct spi_message spi_msg1;
128 struct spi_message spi_msg2;
129 struct spi_transfer spi_xfer1;
130 struct spi_transfer spi_xfer2[2];
131};
132
133static int msg_enable;
134
135/* shift for byte-enable data */
136#define BYTE_EN(_x) ((_x) << 2)
137
138/* turn register number and byte-enable mask into data for start of packet */
139#define MK_OP(_byteen, _reg) (BYTE_EN(_byteen) | (_reg) << (8+2) | (_reg) >> 6)
140
141/* SPI register read/write calls.
142 *
143 * All these calls issue SPI transactions to access the chip's registers. They
144 * all require that the necessary lock is held to prevent accesses when the
145 * chip is busy transferring packet data (RX/TX FIFO accesses).
146 */
147
148/**
149 * ks8851_wrreg16 - write 16bit register value to chip
150 * @ks: The chip state
151 * @reg: The register address
152 * @val: The value to write
153 *
154 * Issue a write to put the value @val into the register specified in @reg.
155 */
156static void ks8851_wrreg16(struct ks8851_net *ks, unsigned reg, unsigned val)
157{
158 struct spi_transfer *xfer = &ks->spi_xfer1;
159 struct spi_message *msg = &ks->spi_msg1;
160 __le16 txb[2];
161 int ret;
162
163 txb[0] = cpu_to_le16(MK_OP(reg & 2 ? 0xC : 0x03, reg) | KS_SPIOP_WR);
164 txb[1] = cpu_to_le16(val);
165
166 xfer->tx_buf = txb;
167 xfer->rx_buf = NULL;
168 xfer->len = 4;
169
170 ret = spi_sync(ks->spidev, msg);
171 if (ret < 0)
172 netdev_err(ks->netdev, "spi_sync() failed\n");
173}
174
175/**
176 * ks8851_wrreg8 - write 8bit register value to chip
177 * @ks: The chip state
178 * @reg: The register address
179 * @val: The value to write
180 *
181 * Issue a write to put the value @val into the register specified in @reg.
182 */
183static void ks8851_wrreg8(struct ks8851_net *ks, unsigned reg, unsigned val)
184{
185 struct spi_transfer *xfer = &ks->spi_xfer1;
186 struct spi_message *msg = &ks->spi_msg1;
187 __le16 txb[2];
188 int ret;
189 int bit;
190
191 bit = 1 << (reg & 3);
192
193 txb[0] = cpu_to_le16(MK_OP(bit, reg) | KS_SPIOP_WR);
194 txb[1] = val;
195
196 xfer->tx_buf = txb;
197 xfer->rx_buf = NULL;
198 xfer->len = 3;
199
200 ret = spi_sync(ks->spidev, msg);
201 if (ret < 0)
202 netdev_err(ks->netdev, "spi_sync() failed\n");
203}
204
205/**
206 * ks8851_rx_1msg - select whether to use one or two messages for spi read
207 * @ks: The device structure
208 *
209 * Return whether to generate a single message with a tx and rx buffer
210 * supplied to spi_sync(), or alternatively send the tx and rx buffers
211 * as separate messages.
212 *
213 * Depending on the hardware in use, a single message may be more efficient
214 * on interrupts or work done by the driver.
215 *
216 * This currently always returns true until we add some per-device data passed
217 * from the platform code to specify which mode is better.
218 */
219static inline bool ks8851_rx_1msg(struct ks8851_net *ks)
220{
221 return true;
222}
223
224/**
225 * ks8851_rdreg - issue read register command and return the data
226 * @ks: The device state
227 * @op: The register address and byte enables in message format.
228 * @rxb: The RX buffer to return the result into
229 * @rxl: The length of data expected.
230 *
231 * This is the low level read call that issues the necessary spi message(s)
232 * to read data from the register specified in @op.
233 */
234static void ks8851_rdreg(struct ks8851_net *ks, unsigned op,
235 u8 *rxb, unsigned rxl)
236{
237 struct spi_transfer *xfer;
238 struct spi_message *msg;
239 __le16 *txb = (__le16 *)ks->txd;
240 u8 *trx = ks->rxd;
241 int ret;
242
243 txb[0] = cpu_to_le16(op | KS_SPIOP_RD);
244
245 if (ks8851_rx_1msg(ks)) {
246 msg = &ks->spi_msg1;
247 xfer = &ks->spi_xfer1;
248
249 xfer->tx_buf = txb;
250 xfer->rx_buf = trx;
251 xfer->len = rxl + 2;
252 } else {
253 msg = &ks->spi_msg2;
254 xfer = ks->spi_xfer2;
255
256 xfer->tx_buf = txb;
257 xfer->rx_buf = NULL;
258 xfer->len = 2;
259
260 xfer++;
261 xfer->tx_buf = NULL;
262 xfer->rx_buf = trx;
263 xfer->len = rxl;
264 }
265
266 ret = spi_sync(ks->spidev, msg);
267 if (ret < 0)
268 netdev_err(ks->netdev, "read: spi_sync() failed\n");
269 else if (ks8851_rx_1msg(ks))
270 memcpy(rxb, trx + 2, rxl);
271 else
272 memcpy(rxb, trx, rxl);
273}
274
275/**
276 * ks8851_rdreg8 - read 8 bit register from device
277 * @ks: The chip information
278 * @reg: The register address
279 *
280 * Read a 8bit register from the chip, returning the result
281*/
282static unsigned ks8851_rdreg8(struct ks8851_net *ks, unsigned reg)
283{
284 u8 rxb[1];
285
286 ks8851_rdreg(ks, MK_OP(1 << (reg & 3), reg), rxb, 1);
287 return rxb[0];
288}
289
290/**
291 * ks8851_rdreg16 - read 16 bit register from device
292 * @ks: The chip information
293 * @reg: The register address
294 *
295 * Read a 16bit register from the chip, returning the result
296*/
297static unsigned ks8851_rdreg16(struct ks8851_net *ks, unsigned reg)
298{
299 __le16 rx = 0;
300
301 ks8851_rdreg(ks, MK_OP(reg & 2 ? 0xC : 0x3, reg), (u8 *)&rx, 2);
302 return le16_to_cpu(rx);
303}
304
305/**
306 * ks8851_rdreg32 - read 32 bit register from device
307 * @ks: The chip information
308 * @reg: The register address
309 *
310 * Read a 32bit register from the chip.
311 *
312 * Note, this read requires the address be aligned to 4 bytes.
313*/
314static unsigned ks8851_rdreg32(struct ks8851_net *ks, unsigned reg)
315{
316 __le32 rx = 0;
317
318 WARN_ON(reg & 3);
319
320 ks8851_rdreg(ks, MK_OP(0xf, reg), (u8 *)&rx, 4);
321 return le32_to_cpu(rx);
322}
323
324/**
325 * ks8851_soft_reset - issue one of the soft reset to the device
326 * @ks: The device state.
327 * @op: The bit(s) to set in the GRR
328 *
329 * Issue the relevant soft-reset command to the device's GRR register
330 * specified by @op.
331 *
332 * Note, the delays are in there as a caution to ensure that the reset
333 * has time to take effect and then complete. Since the datasheet does
334 * not currently specify the exact sequence, we have chosen something
335 * that seems to work with our device.
336 */
337static void ks8851_soft_reset(struct ks8851_net *ks, unsigned op)
338{
339 ks8851_wrreg16(ks, KS_GRR, op);
340 mdelay(1); /* wait a short time to effect reset */
341 ks8851_wrreg16(ks, KS_GRR, 0);
342 mdelay(1); /* wait for condition to clear */
343}
344
345/**
346 * ks8851_write_mac_addr - write mac address to device registers
347 * @dev: The network device
348 *
349 * Update the KS8851 MAC address registers from the address in @dev.
350 *
351 * This call assumes that the chip is not running, so there is no need to
352 * shutdown the RXQ process whilst setting this.
353*/
354static int ks8851_write_mac_addr(struct net_device *dev)
355{
356 struct ks8851_net *ks = netdev_priv(dev);
357 int i;
358
359 mutex_lock(&ks->lock);
360
361 for (i = 0; i < ETH_ALEN; i++)
362 ks8851_wrreg8(ks, KS_MAR(i), dev->dev_addr[i]);
363
364 mutex_unlock(&ks->lock);
365
366 return 0;
367}
368
369/**
370 * ks8851_init_mac - initialise the mac address
371 * @ks: The device structure
372 *
373 * Get or create the initial mac address for the device and then set that
374 * into the station address register. Currently we assume that the device
375 * does not have a valid mac address in it, and so we use random_ether_addr()
376 * to create a new one.
377 *
378 * In future, the driver should check to see if the device has an EEPROM
379 * attached and whether that has a valid ethernet address in it.
380 */
381static void ks8851_init_mac(struct ks8851_net *ks)
382{
383 struct net_device *dev = ks->netdev;
384
385 random_ether_addr(dev->dev_addr);
386 ks8851_write_mac_addr(dev);
387}
388
389/**
390 * ks8851_irq - device interrupt handler
391 * @irq: Interrupt number passed from the IRQ hnalder.
392 * @pw: The private word passed to register_irq(), our struct ks8851_net.
393 *
394 * Disable the interrupt from happening again until we've processed the
395 * current status by scheduling ks8851_irq_work().
396 */
397static irqreturn_t ks8851_irq(int irq, void *pw)
398{
399 struct ks8851_net *ks = pw;
400
401 disable_irq_nosync(irq);
402 schedule_work(&ks->irq_work);
403 return IRQ_HANDLED;
404}
405
406/**
407 * ks8851_rdfifo - read data from the receive fifo
408 * @ks: The device state.
409 * @buff: The buffer address
410 * @len: The length of the data to read
411 *
412 * Issue an RXQ FIFO read command and read the @len amount of data from
413 * the FIFO into the buffer specified by @buff.
414 */
415static void ks8851_rdfifo(struct ks8851_net *ks, u8 *buff, unsigned len)
416{
417 struct spi_transfer *xfer = ks->spi_xfer2;
418 struct spi_message *msg = &ks->spi_msg2;
419 u8 txb[1];
420 int ret;
421
422 netif_dbg(ks, rx_status, ks->netdev,
423 "%s: %d@%p\n", __func__, len, buff);
424
425 /* set the operation we're issuing */
426 txb[0] = KS_SPIOP_RXFIFO;
427
428 xfer->tx_buf = txb;
429 xfer->rx_buf = NULL;
430 xfer->len = 1;
431
432 xfer++;
433 xfer->rx_buf = buff;
434 xfer->tx_buf = NULL;
435 xfer->len = len;
436
437 ret = spi_sync(ks->spidev, msg);
438 if (ret < 0)
439 netdev_err(ks->netdev, "%s: spi_sync() failed\n", __func__);
440}
441
442/**
443 * ks8851_dbg_dumpkkt - dump initial packet contents to debug
444 * @ks: The device state
445 * @rxpkt: The data for the received packet
446 *
447 * Dump the initial data from the packet to dev_dbg().
448*/
449static void ks8851_dbg_dumpkkt(struct ks8851_net *ks, u8 *rxpkt)
450{
451 netdev_dbg(ks->netdev,
452 "pkt %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
453 rxpkt[4], rxpkt[5], rxpkt[6], rxpkt[7],
454 rxpkt[8], rxpkt[9], rxpkt[10], rxpkt[11],
455 rxpkt[12], rxpkt[13], rxpkt[14], rxpkt[15]);
456}
457
458/**
459 * ks8851_rx_pkts - receive packets from the host
460 * @ks: The device information.
461 *
462 * This is called from the IRQ work queue when the system detects that there
463 * are packets in the receive queue. Find out how many packets there are and
464 * read them from the FIFO.
465 */
466static void ks8851_rx_pkts(struct ks8851_net *ks)
467{
468 struct sk_buff *skb;
469 unsigned rxfc;
470 unsigned rxlen;
471 unsigned rxstat;
472 u32 rxh;
473 u8 *rxpkt;
474
475 rxfc = ks8851_rdreg8(ks, KS_RXFC);
476
477 netif_dbg(ks, rx_status, ks->netdev,
478 "%s: %d packets\n", __func__, rxfc);
479
480 /* Currently we're issuing a read per packet, but we could possibly
481 * improve the code by issuing a single read, getting the receive
482 * header, allocating the packet and then reading the packet data
483 * out in one go.
484 *
485 * This form of operation would require us to hold the SPI bus'
486 * chipselect low during the entie transaction to avoid any
487 * reset to the data stream coming from the chip.
488 */
489
490 for (; rxfc != 0; rxfc--) {
491 rxh = ks8851_rdreg32(ks, KS_RXFHSR);
492 rxstat = rxh & 0xffff;
493 rxlen = rxh >> 16;
494
495 netif_dbg(ks, rx_status, ks->netdev,
496 "rx: stat 0x%04x, len 0x%04x\n", rxstat, rxlen);
497
498 /* the length of the packet includes the 32bit CRC */
499
500 /* set dma read address */
501 ks8851_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI | 0x00);
502
503 /* start the packet dma process, and set auto-dequeue rx */
504 ks8851_wrreg16(ks, KS_RXQCR,
505 ks->rc_rxqcr | RXQCR_SDA | RXQCR_ADRFE);
506
507 if (rxlen > 4) {
508 unsigned int rxalign;
509
510 rxlen -= 4;
511 rxalign = ALIGN(rxlen, 4);
512 skb = netdev_alloc_skb_ip_align(ks->netdev, rxalign);
513 if (skb) {
514
515 /* 4 bytes of status header + 4 bytes of
516 * garbage: we put them before ethernet
517 * header, so that they are copied,
518 * but ignored.
519 */
520
521 rxpkt = skb_put(skb, rxlen) - 8;
522
523 ks8851_rdfifo(ks, rxpkt, rxalign + 8);
524
525 if (netif_msg_pktdata(ks))
526 ks8851_dbg_dumpkkt(ks, rxpkt);
527
528 skb->protocol = eth_type_trans(skb, ks->netdev);
529 netif_rx(skb);
530
531 ks->netdev->stats.rx_packets++;
532 ks->netdev->stats.rx_bytes += rxlen;
533 }
534 }
535
536 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
537 }
538}
539
540/**
541 * ks8851_irq_work - work queue handler for dealing with interrupt requests
542 * @work: The work structure that was scheduled by schedule_work()
543 *
544 * This is the handler invoked when the ks8851_irq() is called to find out
545 * what happened, as we cannot allow ourselves to sleep whilst waiting for
546 * anything other process has the chip's lock.
547 *
548 * Read the interrupt status, work out what needs to be done and then clear
549 * any of the interrupts that are not needed.
550 */
551static void ks8851_irq_work(struct work_struct *work)
552{
553 struct ks8851_net *ks = container_of(work, struct ks8851_net, irq_work);
554 unsigned status;
555 unsigned handled = 0;
556
557 mutex_lock(&ks->lock);
558
559 status = ks8851_rdreg16(ks, KS_ISR);
560
561 netif_dbg(ks, intr, ks->netdev,
562 "%s: status 0x%04x\n", __func__, status);
563
564 if (status & IRQ_LCI) {
565 /* should do something about checking link status */
566 handled |= IRQ_LCI;
567 }
568
569 if (status & IRQ_LDI) {
570 u16 pmecr = ks8851_rdreg16(ks, KS_PMECR);
571 pmecr &= ~PMECR_WKEVT_MASK;
572 ks8851_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
573
574 handled |= IRQ_LDI;
575 }
576
577 if (status & IRQ_RXPSI)
578 handled |= IRQ_RXPSI;
579
580 if (status & IRQ_TXI) {
581 handled |= IRQ_TXI;
582
583 /* no lock here, tx queue should have been stopped */
584
585 /* update our idea of how much tx space is available to the
586 * system */
587 ks->tx_space = ks8851_rdreg16(ks, KS_TXMIR);
588
589 netif_dbg(ks, intr, ks->netdev,
590 "%s: txspace %d\n", __func__, ks->tx_space);
591 }
592
593 if (status & IRQ_RXI)
594 handled |= IRQ_RXI;
595
596 if (status & IRQ_SPIBEI) {
597 dev_err(&ks->spidev->dev, "%s: spi bus error\n", __func__);
598 handled |= IRQ_SPIBEI;
599 }
600
601 ks8851_wrreg16(ks, KS_ISR, handled);
602
603 if (status & IRQ_RXI) {
604 /* the datasheet says to disable the rx interrupt during
605 * packet read-out, however we're masking the interrupt
606 * from the device so do not bother masking just the RX
607 * from the device. */
608
609 ks8851_rx_pkts(ks);
610 }
611
612 /* if something stopped the rx process, probably due to wanting
613 * to change the rx settings, then do something about restarting
614 * it. */
615 if (status & IRQ_RXPSI) {
616 struct ks8851_rxctrl *rxc = &ks->rxctrl;
617
618 /* update the multicast hash table */
619 ks8851_wrreg16(ks, KS_MAHTR0, rxc->mchash[0]);
620 ks8851_wrreg16(ks, KS_MAHTR1, rxc->mchash[1]);
621 ks8851_wrreg16(ks, KS_MAHTR2, rxc->mchash[2]);
622 ks8851_wrreg16(ks, KS_MAHTR3, rxc->mchash[3]);
623
624 ks8851_wrreg16(ks, KS_RXCR2, rxc->rxcr2);
625 ks8851_wrreg16(ks, KS_RXCR1, rxc->rxcr1);
626 }
627
628 mutex_unlock(&ks->lock);
629
630 if (status & IRQ_TXI)
631 netif_wake_queue(ks->netdev);
632
633 enable_irq(ks->netdev->irq);
634}
635
636/**
637 * calc_txlen - calculate size of message to send packet
638 * @len: Length of data
639 *
640 * Returns the size of the TXFIFO message needed to send
641 * this packet.
642 */
643static inline unsigned calc_txlen(unsigned len)
644{
645 return ALIGN(len + 4, 4);
646}
647
648/**
649 * ks8851_wrpkt - write packet to TX FIFO
650 * @ks: The device state.
651 * @txp: The sk_buff to transmit.
652 * @irq: IRQ on completion of the packet.
653 *
654 * Send the @txp to the chip. This means creating the relevant packet header
655 * specifying the length of the packet and the other information the chip
656 * needs, such as IRQ on completion. Send the header and the packet data to
657 * the device.
658 */
659static void ks8851_wrpkt(struct ks8851_net *ks, struct sk_buff *txp, bool irq)
660{
661 struct spi_transfer *xfer = ks->spi_xfer2;
662 struct spi_message *msg = &ks->spi_msg2;
663 unsigned fid = 0;
664 int ret;
665
666 netif_dbg(ks, tx_queued, ks->netdev, "%s: skb %p, %d@%p, irq %d\n",
667 __func__, txp, txp->len, txp->data, irq);
668
669 fid = ks->fid++;
670 fid &= TXFR_TXFID_MASK;
671
672 if (irq)
673 fid |= TXFR_TXIC; /* irq on completion */
674
675 /* start header at txb[1] to align txw entries */
676 ks->txh.txb[1] = KS_SPIOP_TXFIFO;
677 ks->txh.txw[1] = cpu_to_le16(fid);
678 ks->txh.txw[2] = cpu_to_le16(txp->len);
679
680 xfer->tx_buf = &ks->txh.txb[1];
681 xfer->rx_buf = NULL;
682 xfer->len = 5;
683
684 xfer++;
685 xfer->tx_buf = txp->data;
686 xfer->rx_buf = NULL;
687 xfer->len = ALIGN(txp->len, 4);
688
689 ret = spi_sync(ks->spidev, msg);
690 if (ret < 0)
691 netdev_err(ks->netdev, "%s: spi_sync() failed\n", __func__);
692}
693
694/**
695 * ks8851_done_tx - update and then free skbuff after transmitting
696 * @ks: The device state
697 * @txb: The buffer transmitted
698 */
699static void ks8851_done_tx(struct ks8851_net *ks, struct sk_buff *txb)
700{
701 struct net_device *dev = ks->netdev;
702
703 dev->stats.tx_bytes += txb->len;
704 dev->stats.tx_packets++;
705
706 dev_kfree_skb(txb);
707}
708
709/**
710 * ks8851_tx_work - process tx packet(s)
711 * @work: The work strucutre what was scheduled.
712 *
713 * This is called when a number of packets have been scheduled for
714 * transmission and need to be sent to the device.
715 */
716static void ks8851_tx_work(struct work_struct *work)
717{
718 struct ks8851_net *ks = container_of(work, struct ks8851_net, tx_work);
719 struct sk_buff *txb;
720 bool last = skb_queue_empty(&ks->txq);
721
722 mutex_lock(&ks->lock);
723
724 while (!last) {
725 txb = skb_dequeue(&ks->txq);
726 last = skb_queue_empty(&ks->txq);
727
728 if (txb != NULL) {
729 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr | RXQCR_SDA);
730 ks8851_wrpkt(ks, txb, last);
731 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
732 ks8851_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
733
734 ks8851_done_tx(ks, txb);
735 }
736 }
737
738 mutex_unlock(&ks->lock);
739}
740
741/**
742 * ks8851_set_powermode - set power mode of the device
743 * @ks: The device state
744 * @pwrmode: The power mode value to write to KS_PMECR.
745 *
746 * Change the power mode of the chip.
747 */
748static void ks8851_set_powermode(struct ks8851_net *ks, unsigned pwrmode)
749{
750 unsigned pmecr;
751
752 netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
753
754 pmecr = ks8851_rdreg16(ks, KS_PMECR);
755 pmecr &= ~PMECR_PM_MASK;
756 pmecr |= pwrmode;
757
758 ks8851_wrreg16(ks, KS_PMECR, pmecr);
759}
760
761/**
762 * ks8851_net_open - open network device
763 * @dev: The network device being opened.
764 *
765 * Called when the network device is marked active, such as a user executing
766 * 'ifconfig up' on the device.
767 */
768static int ks8851_net_open(struct net_device *dev)
769{
770 struct ks8851_net *ks = netdev_priv(dev);
771
772 /* lock the card, even if we may not actually be doing anything
773 * else at the moment */
774 mutex_lock(&ks->lock);
775
776 netif_dbg(ks, ifup, ks->netdev, "opening\n");
777
778 /* bring chip out of any power saving mode it was in */
779 ks8851_set_powermode(ks, PMECR_PM_NORMAL);
780
781 /* issue a soft reset to the RX/TX QMU to put it into a known
782 * state. */
783 ks8851_soft_reset(ks, GRR_QMU);
784
785 /* setup transmission parameters */
786
787 ks8851_wrreg16(ks, KS_TXCR, (TXCR_TXE | /* enable transmit process */
788 TXCR_TXPE | /* pad to min length */
789 TXCR_TXCRC | /* add CRC */
790 TXCR_TXFCE)); /* enable flow control */
791
792 /* auto-increment tx data, reset tx pointer */
793 ks8851_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
794
795 /* setup receiver control */
796
797 ks8851_wrreg16(ks, KS_RXCR1, (RXCR1_RXPAFMA | /* from mac filter */
798 RXCR1_RXFCE | /* enable flow control */
799 RXCR1_RXBE | /* broadcast enable */
800 RXCR1_RXUE | /* unicast enable */
801 RXCR1_RXE)); /* enable rx block */
802
803 /* transfer entire frames out in one go */
804 ks8851_wrreg16(ks, KS_RXCR2, RXCR2_SRDBL_FRAME);
805
806 /* set receive counter timeouts */
807 ks8851_wrreg16(ks, KS_RXDTTR, 1000); /* 1ms after first frame to IRQ */
808 ks8851_wrreg16(ks, KS_RXDBCTR, 4096); /* >4Kbytes in buffer to IRQ */
809 ks8851_wrreg16(ks, KS_RXFCTR, 10); /* 10 frames to IRQ */
810
811 ks->rc_rxqcr = (RXQCR_RXFCTE | /* IRQ on frame count exceeded */
812 RXQCR_RXDBCTE | /* IRQ on byte count exceeded */
813 RXQCR_RXDTTE); /* IRQ on time exceeded */
814
815 ks8851_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
816
817 /* clear then enable interrupts */
818
819#define STD_IRQ (IRQ_LCI | /* Link Change */ \
820 IRQ_TXI | /* TX done */ \
821 IRQ_RXI | /* RX done */ \
822 IRQ_SPIBEI | /* SPI bus error */ \
823 IRQ_TXPSI | /* TX process stop */ \
824 IRQ_RXPSI) /* RX process stop */
825
826 ks->rc_ier = STD_IRQ;
827 ks8851_wrreg16(ks, KS_ISR, STD_IRQ);
828 ks8851_wrreg16(ks, KS_IER, STD_IRQ);
829
830 netif_start_queue(ks->netdev);
831
832 netif_dbg(ks, ifup, ks->netdev, "network device up\n");
833
834 mutex_unlock(&ks->lock);
835 return 0;
836}
837
838/**
839 * ks8851_net_stop - close network device
840 * @dev: The device being closed.
841 *
842 * Called to close down a network device which has been active. Cancell any
843 * work, shutdown the RX and TX process and then place the chip into a low
844 * power state whilst it is not being used.
845 */
846static int ks8851_net_stop(struct net_device *dev)
847{
848 struct ks8851_net *ks = netdev_priv(dev);
849
850 netif_info(ks, ifdown, dev, "shutting down\n");
851
852 netif_stop_queue(dev);
853
854 mutex_lock(&ks->lock);
855
856 /* stop any outstanding work */
857 flush_work(&ks->irq_work);
858 flush_work(&ks->tx_work);
859 flush_work(&ks->rxctrl_work);
860
861 /* turn off the IRQs and ack any outstanding */
862 ks8851_wrreg16(ks, KS_IER, 0x0000);
863 ks8851_wrreg16(ks, KS_ISR, 0xffff);
864
865 /* shutdown RX process */
866 ks8851_wrreg16(ks, KS_RXCR1, 0x0000);
867
868 /* shutdown TX process */
869 ks8851_wrreg16(ks, KS_TXCR, 0x0000);
870
871 /* set powermode to soft power down to save power */
872 ks8851_set_powermode(ks, PMECR_PM_SOFTDOWN);
873
874 /* ensure any queued tx buffers are dumped */
875 while (!skb_queue_empty(&ks->txq)) {
876 struct sk_buff *txb = skb_dequeue(&ks->txq);
877
878 netif_dbg(ks, ifdown, ks->netdev,
879 "%s: freeing txb %p\n", __func__, txb);
880
881 dev_kfree_skb(txb);
882 }
883
884 mutex_unlock(&ks->lock);
885 return 0;
886}
887
888/**
889 * ks8851_start_xmit - transmit packet
890 * @skb: The buffer to transmit
891 * @dev: The device used to transmit the packet.
892 *
893 * Called by the network layer to transmit the @skb. Queue the packet for
894 * the device and schedule the necessary work to transmit the packet when
895 * it is free.
896 *
897 * We do this to firstly avoid sleeping with the network device locked,
898 * and secondly so we can round up more than one packet to transmit which
899 * means we can try and avoid generating too many transmit done interrupts.
900 */
901static netdev_tx_t ks8851_start_xmit(struct sk_buff *skb,
902 struct net_device *dev)
903{
904 struct ks8851_net *ks = netdev_priv(dev);
905 unsigned needed = calc_txlen(skb->len);
906 netdev_tx_t ret = NETDEV_TX_OK;
907
908 netif_dbg(ks, tx_queued, ks->netdev,
909 "%s: skb %p, %d@%p\n", __func__, skb, skb->len, skb->data);
910
911 spin_lock(&ks->statelock);
912
913 if (needed > ks->tx_space) {
914 netif_stop_queue(dev);
915 ret = NETDEV_TX_BUSY;
916 } else {
917 ks->tx_space -= needed;
918 skb_queue_tail(&ks->txq, skb);
919 }
920
921 spin_unlock(&ks->statelock);
922 schedule_work(&ks->tx_work);
923
924 return ret;
925}
926
927/**
928 * ks8851_rxctrl_work - work handler to change rx mode
929 * @work: The work structure this belongs to.
930 *
931 * Lock the device and issue the necessary changes to the receive mode from
932 * the network device layer. This is done so that we can do this without
933 * having to sleep whilst holding the network device lock.
934 *
935 * Since the recommendation from Micrel is that the RXQ is shutdown whilst the
936 * receive parameters are programmed, we issue a write to disable the RXQ and
937 * then wait for the interrupt handler to be triggered once the RXQ shutdown is
938 * complete. The interrupt handler then writes the new values into the chip.
939 */
940static void ks8851_rxctrl_work(struct work_struct *work)
941{
942 struct ks8851_net *ks = container_of(work, struct ks8851_net, rxctrl_work);
943
944 mutex_lock(&ks->lock);
945
946 /* need to shutdown RXQ before modifying filter parameters */
947 ks8851_wrreg16(ks, KS_RXCR1, 0x00);
948
949 mutex_unlock(&ks->lock);
950}
951
952static void ks8851_set_rx_mode(struct net_device *dev)
953{
954 struct ks8851_net *ks = netdev_priv(dev);
955 struct ks8851_rxctrl rxctrl;
956
957 memset(&rxctrl, 0, sizeof(rxctrl));
958
959 if (dev->flags & IFF_PROMISC) {
960 /* interface to receive everything */
961
962 rxctrl.rxcr1 = RXCR1_RXAE | RXCR1_RXINVF;
963 } else if (dev->flags & IFF_ALLMULTI) {
964 /* accept all multicast packets */
965
966 rxctrl.rxcr1 = (RXCR1_RXME | RXCR1_RXAE |
967 RXCR1_RXPAFMA | RXCR1_RXMAFMA);
968 } else if (dev->flags & IFF_MULTICAST && !netdev_mc_empty(dev)) {
969 struct netdev_hw_addr *ha;
970 u32 crc;
971
972 /* accept some multicast */
973
974 netdev_for_each_mc_addr(ha, dev) {
975 crc = ether_crc(ETH_ALEN, ha->addr);
976 crc >>= (32 - 6); /* get top six bits */
977
978 rxctrl.mchash[crc >> 4] |= (1 << (crc & 0xf));
979 }
980
981 rxctrl.rxcr1 = RXCR1_RXME | RXCR1_RXPAFMA;
982 } else {
983 /* just accept broadcast / unicast */
984 rxctrl.rxcr1 = RXCR1_RXPAFMA;
985 }
986
987 rxctrl.rxcr1 |= (RXCR1_RXUE | /* unicast enable */
988 RXCR1_RXBE | /* broadcast enable */
989 RXCR1_RXE | /* RX process enable */
990 RXCR1_RXFCE); /* enable flow control */
991
992 rxctrl.rxcr2 |= RXCR2_SRDBL_FRAME;
993
994 /* schedule work to do the actual set of the data if needed */
995
996 spin_lock(&ks->statelock);
997
998 if (memcmp(&rxctrl, &ks->rxctrl, sizeof(rxctrl)) != 0) {
999 memcpy(&ks->rxctrl, &rxctrl, sizeof(ks->rxctrl));
1000 schedule_work(&ks->rxctrl_work);
1001 }
1002
1003 spin_unlock(&ks->statelock);
1004}
1005
1006static int ks8851_set_mac_address(struct net_device *dev, void *addr)
1007{
1008 struct sockaddr *sa = addr;
1009
1010 if (netif_running(dev))
1011 return -EBUSY;
1012
1013 if (!is_valid_ether_addr(sa->sa_data))
1014 return -EADDRNOTAVAIL;
1015
1016 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1017 return ks8851_write_mac_addr(dev);
1018}
1019
1020static int ks8851_net_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1021{
1022 struct ks8851_net *ks = netdev_priv(dev);
1023
1024 if (!netif_running(dev))
1025 return -EINVAL;
1026
1027 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
1028}
1029
1030static const struct net_device_ops ks8851_netdev_ops = {
1031 .ndo_open = ks8851_net_open,
1032 .ndo_stop = ks8851_net_stop,
1033 .ndo_do_ioctl = ks8851_net_ioctl,
1034 .ndo_start_xmit = ks8851_start_xmit,
1035 .ndo_set_mac_address = ks8851_set_mac_address,
1036 .ndo_set_rx_mode = ks8851_set_rx_mode,
1037 .ndo_change_mtu = eth_change_mtu,
1038 .ndo_validate_addr = eth_validate_addr,
1039};
1040
1041/* Companion eeprom access */
1042
1043enum { /* EEPROM programming states */
1044 EEPROM_CONTROL,
1045 EEPROM_ADDRESS,
1046 EEPROM_DATA,
1047 EEPROM_COMPLETE
1048};
1049
1050/**
1051 * ks8851_eeprom_read - read a 16bits word in ks8851 companion EEPROM
1052 * @dev: The network device the PHY is on.
1053 * @addr: EEPROM address to read
1054 *
1055 * eeprom_size: used to define the data coding length. Can be changed
1056 * through debug-fs.
1057 *
1058 * Programs a read on the EEPROM using ks8851 EEPROM SW access feature.
1059 * Warning: The READ feature is not supported on ks8851 revision 0.
1060 *
1061 * Rough programming model:
1062 * - on period start: set clock high and read value on bus
1063 * - on period / 2: set clock low and program value on bus
1064 * - start on period / 2
1065 */
1066unsigned int ks8851_eeprom_read(struct net_device *dev, unsigned int addr)
1067{
1068 struct ks8851_net *ks = netdev_priv(dev);
1069 int eepcr;
1070 int ctrl = EEPROM_OP_READ;
1071 int state = EEPROM_CONTROL;
1072 int bit_count = EEPROM_OP_LEN - 1;
1073 unsigned int data = 0;
1074 int dummy;
1075 unsigned int addr_len;
1076
1077 addr_len = (ks->eeprom_size == 128) ? 6 : 8;
1078
1079 /* start transaction: chip select high, authorize write */
1080 mutex_lock(&ks->lock);
1081 eepcr = EEPCR_EESA | EEPCR_EESRWA;
1082 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1083 eepcr |= EEPCR_EECS;
1084 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1085 mutex_unlock(&ks->lock);
1086
1087 while (state != EEPROM_COMPLETE) {
1088 /* falling clock period starts... */
1089 /* set EED_IO pin for control and address */
1090 eepcr &= ~EEPCR_EEDO;
1091 switch (state) {
1092 case EEPROM_CONTROL:
1093 eepcr |= ((ctrl >> bit_count) & 1) << 2;
1094 if (bit_count-- <= 0) {
1095 bit_count = addr_len - 1;
1096 state = EEPROM_ADDRESS;
1097 }
1098 break;
1099 case EEPROM_ADDRESS:
1100 eepcr |= ((addr >> bit_count) & 1) << 2;
1101 bit_count--;
1102 break;
1103 case EEPROM_DATA:
1104 /* Change to receive mode */
1105 eepcr &= ~EEPCR_EESRWA;
1106 break;
1107 }
1108
1109 /* lower clock */
1110 eepcr &= ~EEPCR_EESCK;
1111
1112 mutex_lock(&ks->lock);
1113 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1114 mutex_unlock(&ks->lock);
1115
1116 /* waitread period / 2 */
1117 udelay(EEPROM_SK_PERIOD / 2);
1118
1119 /* rising clock period starts... */
1120
1121 /* raise clock */
1122 mutex_lock(&ks->lock);
1123 eepcr |= EEPCR_EESCK;
1124 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1125 mutex_unlock(&ks->lock);
1126
1127 /* Manage read */
1128 switch (state) {
1129 case EEPROM_ADDRESS:
1130 if (bit_count < 0) {
1131 bit_count = EEPROM_DATA_LEN - 1;
1132 state = EEPROM_DATA;
1133 }
1134 break;
1135 case EEPROM_DATA:
1136 mutex_lock(&ks->lock);
1137 dummy = ks8851_rdreg16(ks, KS_EEPCR);
1138 mutex_unlock(&ks->lock);
1139 data |= ((dummy >> EEPCR_EESB_OFFSET) & 1) << bit_count;
1140 if (bit_count-- <= 0)
1141 state = EEPROM_COMPLETE;
1142 break;
1143 }
1144
1145 /* wait period / 2 */
1146 udelay(EEPROM_SK_PERIOD / 2);
1147 }
1148
1149 /* close transaction */
1150 mutex_lock(&ks->lock);
1151 eepcr &= ~EEPCR_EECS;
1152 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1153 eepcr = 0;
1154 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1155 mutex_unlock(&ks->lock);
1156
1157 return data;
1158}
1159
1160/**
1161 * ks8851_eeprom_write - write a 16bits word in ks8851 companion EEPROM
1162 * @dev: The network device the PHY is on.
1163 * @op: operand (can be WRITE, EWEN, EWDS)
1164 * @addr: EEPROM address to write
1165 * @data: data to write
1166 *
1167 * eeprom_size: used to define the data coding length. Can be changed
1168 * through debug-fs.
1169 *
1170 * Programs a write on the EEPROM using ks8851 EEPROM SW access feature.
1171 *
1172 * Note that a write enable is required before writing data.
1173 *
1174 * Rough programming model:
1175 * - on period start: set clock high
1176 * - on period / 2: set clock low and program value on bus
1177 * - start on period / 2
1178 */
1179void ks8851_eeprom_write(struct net_device *dev, unsigned int op,
1180 unsigned int addr, unsigned int data)
1181{
1182 struct ks8851_net *ks = netdev_priv(dev);
1183 int eepcr;
1184 int state = EEPROM_CONTROL;
1185 int bit_count = EEPROM_OP_LEN - 1;
1186 unsigned int addr_len;
1187
1188 addr_len = (ks->eeprom_size == 128) ? 6 : 8;
1189
1190 switch (op) {
1191 case EEPROM_OP_EWEN:
1192 addr = 0x30;
1193 break;
1194 case EEPROM_OP_EWDS:
1195 addr = 0;
1196 break;
1197 }
1198
1199 /* start transaction: chip select high, authorize write */
1200 mutex_lock(&ks->lock);
1201 eepcr = EEPCR_EESA | EEPCR_EESRWA;
1202 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1203 eepcr |= EEPCR_EECS;
1204 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1205 mutex_unlock(&ks->lock);
1206
1207 while (state != EEPROM_COMPLETE) {
1208 /* falling clock period starts... */
1209 /* set EED_IO pin for control and address */
1210 eepcr &= ~EEPCR_EEDO;
1211 switch (state) {
1212 case EEPROM_CONTROL:
1213 eepcr |= ((op >> bit_count) & 1) << 2;
1214 if (bit_count-- <= 0) {
1215 bit_count = addr_len - 1;
1216 state = EEPROM_ADDRESS;
1217 }
1218 break;
1219 case EEPROM_ADDRESS:
1220 eepcr |= ((addr >> bit_count) & 1) << 2;
1221 if (bit_count-- <= 0) {
1222 if (op == EEPROM_OP_WRITE) {
1223 bit_count = EEPROM_DATA_LEN - 1;
1224 state = EEPROM_DATA;
1225 } else {
1226 state = EEPROM_COMPLETE;
1227 }
1228 }
1229 break;
1230 case EEPROM_DATA:
1231 eepcr |= ((data >> bit_count) & 1) << 2;
1232 if (bit_count-- <= 0)
1233 state = EEPROM_COMPLETE;
1234 break;
1235 }
1236
1237 /* lower clock */
1238 eepcr &= ~EEPCR_EESCK;
1239
1240 mutex_lock(&ks->lock);
1241 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1242 mutex_unlock(&ks->lock);
1243
1244 /* wait period / 2 */
1245 udelay(EEPROM_SK_PERIOD / 2);
1246
1247 /* rising clock period starts... */
1248
1249 /* raise clock */
1250 eepcr |= EEPCR_EESCK;
1251 mutex_lock(&ks->lock);
1252 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1253 mutex_unlock(&ks->lock);
1254
1255 /* wait period / 2 */
1256 udelay(EEPROM_SK_PERIOD / 2);
1257 }
1258
1259 /* close transaction */
1260 mutex_lock(&ks->lock);
1261 eepcr &= ~EEPCR_EECS;
1262 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1263 eepcr = 0;
1264 ks8851_wrreg16(ks, KS_EEPCR, eepcr);
1265 mutex_unlock(&ks->lock);
1266
1267}
1268
1269/* ethtool support */
1270
1271static void ks8851_get_drvinfo(struct net_device *dev,
1272 struct ethtool_drvinfo *di)
1273{
1274 strlcpy(di->driver, "KS8851", sizeof(di->driver));
1275 strlcpy(di->version, "1.00", sizeof(di->version));
1276 strlcpy(di->bus_info, dev_name(dev->dev.parent), sizeof(di->bus_info));
1277}
1278
1279static u32 ks8851_get_msglevel(struct net_device *dev)
1280{
1281 struct ks8851_net *ks = netdev_priv(dev);
1282 return ks->msg_enable;
1283}
1284
1285static void ks8851_set_msglevel(struct net_device *dev, u32 to)
1286{
1287 struct ks8851_net *ks = netdev_priv(dev);
1288 ks->msg_enable = to;
1289}
1290
1291static int ks8851_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1292{
1293 struct ks8851_net *ks = netdev_priv(dev);
1294 return mii_ethtool_gset(&ks->mii, cmd);
1295}
1296
1297static int ks8851_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1298{
1299 struct ks8851_net *ks = netdev_priv(dev);
1300 return mii_ethtool_sset(&ks->mii, cmd);
1301}
1302
1303static u32 ks8851_get_link(struct net_device *dev)
1304{
1305 struct ks8851_net *ks = netdev_priv(dev);
1306 return mii_link_ok(&ks->mii);
1307}
1308
1309static int ks8851_nway_reset(struct net_device *dev)
1310{
1311 struct ks8851_net *ks = netdev_priv(dev);
1312 return mii_nway_restart(&ks->mii);
1313}
1314
1315static int ks8851_get_eeprom_len(struct net_device *dev)
1316{
1317 struct ks8851_net *ks = netdev_priv(dev);
1318 return ks->eeprom_size;
1319}
1320
1321static int ks8851_get_eeprom(struct net_device *dev,
1322 struct ethtool_eeprom *eeprom, u8 *bytes)
1323{
1324 struct ks8851_net *ks = netdev_priv(dev);
1325 u16 *eeprom_buff;
1326 int first_word;
1327 int last_word;
1328 int ret_val = 0;
1329 u16 i;
1330
1331 if (eeprom->len == 0)
1332 return -EINVAL;
1333
1334 if (eeprom->len > ks->eeprom_size)
1335 return -EINVAL;
1336
1337 eeprom->magic = ks8851_rdreg16(ks, KS_CIDER);
1338
1339 first_word = eeprom->offset >> 1;
1340 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1341
1342 eeprom_buff = kmalloc(sizeof(u16) *
1343 (last_word - first_word + 1), GFP_KERNEL);
1344 if (!eeprom_buff)
1345 return -ENOMEM;
1346
1347 for (i = 0; i < last_word - first_word + 1; i++)
1348 eeprom_buff[i] = ks8851_eeprom_read(dev, first_word + 1);
1349
1350 /* Device's eeprom is little-endian, word addressable */
1351 for (i = 0; i < last_word - first_word + 1; i++)
1352 le16_to_cpus(&eeprom_buff[i]);
1353
1354 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
1355 kfree(eeprom_buff);
1356
1357 return ret_val;
1358}
1359
1360static int ks8851_set_eeprom(struct net_device *dev,
1361 struct ethtool_eeprom *eeprom, u8 *bytes)
1362{
1363 struct ks8851_net *ks = netdev_priv(dev);
1364 u16 *eeprom_buff;
1365 void *ptr;
1366 int max_len;
1367 int first_word;
1368 int last_word;
1369 int ret_val = 0;
1370 u16 i;
1371
1372 if (eeprom->len == 0)
1373 return -EOPNOTSUPP;
1374
1375 if (eeprom->len > ks->eeprom_size)
1376 return -EINVAL;
1377
1378 if (eeprom->magic != ks8851_rdreg16(ks, KS_CIDER))
1379 return -EFAULT;
1380
1381 first_word = eeprom->offset >> 1;
1382 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1383 max_len = (last_word - first_word + 1) * 2;
1384 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1385 if (!eeprom_buff)
1386 return -ENOMEM;
1387
1388 ptr = (void *)eeprom_buff;
1389
1390 if (eeprom->offset & 1) {
1391 /* need read/modify/write of first changed EEPROM word */
1392 /* only the second byte of the word is being modified */
1393 eeprom_buff[0] = ks8851_eeprom_read(dev, first_word);
1394 ptr++;
1395 }
1396 if ((eeprom->offset + eeprom->len) & 1)
1397 /* need read/modify/write of last changed EEPROM word */
1398 /* only the first byte of the word is being modified */
1399 eeprom_buff[last_word - first_word] =
1400 ks8851_eeprom_read(dev, last_word);
1401
1402
1403 /* Device's eeprom is little-endian, word addressable */
1404 le16_to_cpus(&eeprom_buff[0]);
1405 le16_to_cpus(&eeprom_buff[last_word - first_word]);
1406
1407 memcpy(ptr, bytes, eeprom->len);
1408
1409 for (i = 0; i < last_word - first_word + 1; i++)
1410 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
1411
1412 ks8851_eeprom_write(dev, EEPROM_OP_EWEN, 0, 0);
1413
1414 for (i = 0; i < last_word - first_word + 1; i++) {
1415 ks8851_eeprom_write(dev, EEPROM_OP_WRITE, first_word + i,
1416 eeprom_buff[i]);
1417 mdelay(EEPROM_WRITE_TIME);
1418 }
1419
1420 ks8851_eeprom_write(dev, EEPROM_OP_EWDS, 0, 0);
1421
1422 kfree(eeprom_buff);
1423 return ret_val;
1424}
1425
1426static const struct ethtool_ops ks8851_ethtool_ops = {
1427 .get_drvinfo = ks8851_get_drvinfo,
1428 .get_msglevel = ks8851_get_msglevel,
1429 .set_msglevel = ks8851_set_msglevel,
1430 .get_settings = ks8851_get_settings,
1431 .set_settings = ks8851_set_settings,
1432 .get_link = ks8851_get_link,
1433 .nway_reset = ks8851_nway_reset,
1434 .get_eeprom_len = ks8851_get_eeprom_len,
1435 .get_eeprom = ks8851_get_eeprom,
1436 .set_eeprom = ks8851_set_eeprom,
1437};
1438
1439/* MII interface controls */
1440
1441/**
1442 * ks8851_phy_reg - convert MII register into a KS8851 register
1443 * @reg: MII register number.
1444 *
1445 * Return the KS8851 register number for the corresponding MII PHY register
1446 * if possible. Return zero if the MII register has no direct mapping to the
1447 * KS8851 register set.
1448 */
1449static int ks8851_phy_reg(int reg)
1450{
1451 switch (reg) {
1452 case MII_BMCR:
1453 return KS_P1MBCR;
1454 case MII_BMSR:
1455 return KS_P1MBSR;
1456 case MII_PHYSID1:
1457 return KS_PHY1ILR;
1458 case MII_PHYSID2:
1459 return KS_PHY1IHR;
1460 case MII_ADVERTISE:
1461 return KS_P1ANAR;
1462 case MII_LPA:
1463 return KS_P1ANLPR;
1464 }
1465
1466 return 0x0;
1467}
1468
1469/**
1470 * ks8851_phy_read - MII interface PHY register read.
1471 * @dev: The network device the PHY is on.
1472 * @phy_addr: Address of PHY (ignored as we only have one)
1473 * @reg: The register to read.
1474 *
1475 * This call reads data from the PHY register specified in @reg. Since the
1476 * device does not support all the MII registers, the non-existent values
1477 * are always returned as zero.
1478 *
1479 * We return zero for unsupported registers as the MII code does not check
1480 * the value returned for any error status, and simply returns it to the
1481 * caller. The mii-tool that the driver was tested with takes any -ve error
1482 * as real PHY capabilities, thus displaying incorrect data to the user.
1483 */
1484static int ks8851_phy_read(struct net_device *dev, int phy_addr, int reg)
1485{
1486 struct ks8851_net *ks = netdev_priv(dev);
1487 int ksreg;
1488 int result;
1489
1490 ksreg = ks8851_phy_reg(reg);
1491 if (!ksreg)
1492 return 0x0; /* no error return allowed, so use zero */
1493
1494 mutex_lock(&ks->lock);
1495 result = ks8851_rdreg16(ks, ksreg);
1496 mutex_unlock(&ks->lock);
1497
1498 return result;
1499}
1500
1501static void ks8851_phy_write(struct net_device *dev,
1502 int phy, int reg, int value)
1503{
1504 struct ks8851_net *ks = netdev_priv(dev);
1505 int ksreg;
1506
1507 ksreg = ks8851_phy_reg(reg);
1508 if (ksreg) {
1509 mutex_lock(&ks->lock);
1510 ks8851_wrreg16(ks, ksreg, value);
1511 mutex_unlock(&ks->lock);
1512 }
1513}
1514
1515/**
1516 * ks8851_read_selftest - read the selftest memory info.
1517 * @ks: The device state
1518 *
1519 * Read and check the TX/RX memory selftest information.
1520 */
1521static int ks8851_read_selftest(struct ks8851_net *ks)
1522{
1523 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1524 int ret = 0;
1525 unsigned rd;
1526
1527 rd = ks8851_rdreg16(ks, KS_MBIR);
1528
1529 if ((rd & both_done) != both_done) {
1530 netdev_warn(ks->netdev, "Memory selftest not finished\n");
1531 return 0;
1532 }
1533
1534 if (rd & MBIR_TXMBFA) {
1535 netdev_err(ks->netdev, "TX memory selftest fail\n");
1536 ret |= 1;
1537 }
1538
1539 if (rd & MBIR_RXMBFA) {
1540 netdev_err(ks->netdev, "RX memory selftest fail\n");
1541 ret |= 2;
1542 }
1543
1544 return 0;
1545}
1546
1547/* driver bus management functions */
1548
1549#ifdef CONFIG_PM
1550static int ks8851_suspend(struct spi_device *spi, pm_message_t state)
1551{
1552 struct ks8851_net *ks = dev_get_drvdata(&spi->dev);
1553 struct net_device *dev = ks->netdev;
1554
1555 if (netif_running(dev)) {
1556 netif_device_detach(dev);
1557 ks8851_net_stop(dev);
1558 }
1559
1560 return 0;
1561}
1562
1563static int ks8851_resume(struct spi_device *spi)
1564{
1565 struct ks8851_net *ks = dev_get_drvdata(&spi->dev);
1566 struct net_device *dev = ks->netdev;
1567
1568 if (netif_running(dev)) {
1569 ks8851_net_open(dev);
1570 netif_device_attach(dev);
1571 }
1572
1573 return 0;
1574}
1575#else
1576#define ks8851_suspend NULL
1577#define ks8851_resume NULL
1578#endif
1579
1580static int __devinit ks8851_probe(struct spi_device *spi)
1581{
1582 struct net_device *ndev;
1583 struct ks8851_net *ks;
1584 int ret;
1585
1586 ndev = alloc_etherdev(sizeof(struct ks8851_net));
1587 if (!ndev) {
1588 dev_err(&spi->dev, "failed to alloc ethernet device\n");
1589 return -ENOMEM;
1590 }
1591
1592 spi->bits_per_word = 8;
1593
1594 ks = netdev_priv(ndev);
1595
1596 ks->netdev = ndev;
1597 ks->spidev = spi;
1598 ks->tx_space = 6144;
1599
1600 mutex_init(&ks->lock);
1601 spin_lock_init(&ks->statelock);
1602
1603 INIT_WORK(&ks->tx_work, ks8851_tx_work);
1604 INIT_WORK(&ks->irq_work, ks8851_irq_work);
1605 INIT_WORK(&ks->rxctrl_work, ks8851_rxctrl_work);
1606
1607 /* initialise pre-made spi transfer messages */
1608
1609 spi_message_init(&ks->spi_msg1);
1610 spi_message_add_tail(&ks->spi_xfer1, &ks->spi_msg1);
1611
1612 spi_message_init(&ks->spi_msg2);
1613 spi_message_add_tail(&ks->spi_xfer2[0], &ks->spi_msg2);
1614 spi_message_add_tail(&ks->spi_xfer2[1], &ks->spi_msg2);
1615
1616 /* setup mii state */
1617 ks->mii.dev = ndev;
1618 ks->mii.phy_id = 1,
1619 ks->mii.phy_id_mask = 1;
1620 ks->mii.reg_num_mask = 0xf;
1621 ks->mii.mdio_read = ks8851_phy_read;
1622 ks->mii.mdio_write = ks8851_phy_write;
1623
1624 dev_info(&spi->dev, "message enable is %d\n", msg_enable);
1625
1626 /* set the default message enable */
1627 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1628 NETIF_MSG_PROBE |
1629 NETIF_MSG_LINK));
1630
1631 skb_queue_head_init(&ks->txq);
1632
1633 SET_ETHTOOL_OPS(ndev, &ks8851_ethtool_ops);
1634 SET_NETDEV_DEV(ndev, &spi->dev);
1635
1636 dev_set_drvdata(&spi->dev, ks);
1637
1638 ndev->if_port = IF_PORT_100BASET;
1639 ndev->netdev_ops = &ks8851_netdev_ops;
1640 ndev->irq = spi->irq;
1641
1642 /* issue a global soft reset to reset the device. */
1643 ks8851_soft_reset(ks, GRR_GSR);
1644
1645 /* simple check for a valid chip being connected to the bus */
1646
1647 if ((ks8851_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1648 dev_err(&spi->dev, "failed to read device ID\n");
1649 ret = -ENODEV;
1650 goto err_id;
1651 }
1652
1653 /* cache the contents of the CCR register for EEPROM, etc. */
1654 ks->rc_ccr = ks8851_rdreg16(ks, KS_CCR);
1655
1656 if (ks->rc_ccr & CCR_EEPROM)
1657 ks->eeprom_size = 128;
1658 else
1659 ks->eeprom_size = 0;
1660
1661 ks8851_read_selftest(ks);
1662 ks8851_init_mac(ks);
1663
1664 ret = request_irq(spi->irq, ks8851_irq, IRQF_TRIGGER_LOW,
1665 ndev->name, ks);
1666 if (ret < 0) {
1667 dev_err(&spi->dev, "failed to get irq\n");
1668 goto err_irq;
1669 }
1670
1671 ret = register_netdev(ndev);
1672 if (ret) {
1673 dev_err(&spi->dev, "failed to register network device\n");
1674 goto err_netdev;
1675 }
1676
1677 netdev_info(ndev, "revision %d, MAC %pM, IRQ %d\n",
1678 CIDER_REV_GET(ks8851_rdreg16(ks, KS_CIDER)),
1679 ndev->dev_addr, ndev->irq);
1680
1681 return 0;
1682
1683
1684err_netdev:
1685 free_irq(ndev->irq, ndev);
1686
1687err_id:
1688err_irq:
1689 free_netdev(ndev);
1690 return ret;
1691}
1692
1693static int __devexit ks8851_remove(struct spi_device *spi)
1694{
1695 struct ks8851_net *priv = dev_get_drvdata(&spi->dev);
1696
1697 if (netif_msg_drv(priv))
1698 dev_info(&spi->dev, "remove\n");
1699
1700 unregister_netdev(priv->netdev);
1701 free_irq(spi->irq, priv);
1702 free_netdev(priv->netdev);
1703
1704 return 0;
1705}
1706
1707static struct spi_driver ks8851_driver = {
1708 .driver = {
1709 .name = "ks8851",
1710 .owner = THIS_MODULE,
1711 },
1712 .probe = ks8851_probe,
1713 .remove = __devexit_p(ks8851_remove),
1714 .suspend = ks8851_suspend,
1715 .resume = ks8851_resume,
1716};
1717
1718static int __init ks8851_init(void)
1719{
1720 return spi_register_driver(&ks8851_driver);
1721}
1722
1723static void __exit ks8851_exit(void)
1724{
1725 spi_unregister_driver(&ks8851_driver);
1726}
1727
1728module_init(ks8851_init);
1729module_exit(ks8851_exit);
1730
1731MODULE_DESCRIPTION("KS8851 Network driver");
1732MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1733MODULE_LICENSE("GPL");
1734
1735module_param_named(message, msg_enable, int, 0);
1736MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
1737MODULE_ALIAS("spi:ks8851");
diff --git a/drivers/net/ethernet/micrel/ks8851.h b/drivers/net/ethernet/micrel/ks8851.h
new file mode 100644
index 000000000000..537fb06e5932
--- /dev/null
+++ b/drivers/net/ethernet/micrel/ks8851.h
@@ -0,0 +1,309 @@
1/* drivers/net/ks8851.h
2 *
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * KS8851 register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#define KS_CCR 0x08
14#define CCR_EEPROM (1 << 9)
15#define CCR_SPI (1 << 8)
16#define CCR_32PIN (1 << 0)
17
18/* MAC address registers */
19#define KS_MAR(_m) 0x15 - (_m)
20#define KS_MARL 0x10
21#define KS_MARM 0x12
22#define KS_MARH 0x14
23
24#define KS_OBCR 0x20
25#define OBCR_ODS_16mA (1 << 6)
26
27#define KS_EEPCR 0x22
28#define EEPCR_EESRWA (1 << 5)
29#define EEPCR_EESA (1 << 4)
30#define EEPCR_EESB_OFFSET 3
31#define EEPCR_EESB (1 << EEPCR_EESB_OFFSET)
32#define EEPCR_EEDO (1 << 2)
33#define EEPCR_EESCK (1 << 1)
34#define EEPCR_EECS (1 << 0)
35
36#define EEPROM_OP_LEN 3 /* bits:*/
37#define EEPROM_OP_READ 0x06
38#define EEPROM_OP_EWEN 0x04
39#define EEPROM_OP_WRITE 0x05
40#define EEPROM_OP_EWDS 0x14
41
42#define EEPROM_DATA_LEN 16 /* 16 bits EEPROM */
43#define EEPROM_WRITE_TIME 4 /* wrt ack time in ms */
44#define EEPROM_SK_PERIOD 400 /* in us */
45
46#define KS_MBIR 0x24
47#define MBIR_TXMBF (1 << 12)
48#define MBIR_TXMBFA (1 << 11)
49#define MBIR_RXMBF (1 << 4)
50#define MBIR_RXMBFA (1 << 3)
51
52#define KS_GRR 0x26
53#define GRR_QMU (1 << 1)
54#define GRR_GSR (1 << 0)
55
56#define KS_WFCR 0x2A
57#define WFCR_MPRXE (1 << 7)
58#define WFCR_WF3E (1 << 3)
59#define WFCR_WF2E (1 << 2)
60#define WFCR_WF1E (1 << 1)
61#define WFCR_WF0E (1 << 0)
62
63#define KS_WF0CRC0 0x30
64#define KS_WF0CRC1 0x32
65#define KS_WF0BM0 0x34
66#define KS_WF0BM1 0x36
67#define KS_WF0BM2 0x38
68#define KS_WF0BM3 0x3A
69
70#define KS_WF1CRC0 0x40
71#define KS_WF1CRC1 0x42
72#define KS_WF1BM0 0x44
73#define KS_WF1BM1 0x46
74#define KS_WF1BM2 0x48
75#define KS_WF1BM3 0x4A
76
77#define KS_WF2CRC0 0x50
78#define KS_WF2CRC1 0x52
79#define KS_WF2BM0 0x54
80#define KS_WF2BM1 0x56
81#define KS_WF2BM2 0x58
82#define KS_WF2BM3 0x5A
83
84#define KS_WF3CRC0 0x60
85#define KS_WF3CRC1 0x62
86#define KS_WF3BM0 0x64
87#define KS_WF3BM1 0x66
88#define KS_WF3BM2 0x68
89#define KS_WF3BM3 0x6A
90
91#define KS_TXCR 0x70
92#define TXCR_TCGICMP (1 << 8)
93#define TXCR_TCGUDP (1 << 7)
94#define TXCR_TCGTCP (1 << 6)
95#define TXCR_TCGIP (1 << 5)
96#define TXCR_FTXQ (1 << 4)
97#define TXCR_TXFCE (1 << 3)
98#define TXCR_TXPE (1 << 2)
99#define TXCR_TXCRC (1 << 1)
100#define TXCR_TXE (1 << 0)
101
102#define KS_TXSR 0x72
103#define TXSR_TXLC (1 << 13)
104#define TXSR_TXMC (1 << 12)
105#define TXSR_TXFID_MASK (0x3f << 0)
106#define TXSR_TXFID_SHIFT (0)
107#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
108
109#define KS_RXCR1 0x74
110#define RXCR1_FRXQ (1 << 15)
111#define RXCR1_RXUDPFCC (1 << 14)
112#define RXCR1_RXTCPFCC (1 << 13)
113#define RXCR1_RXIPFCC (1 << 12)
114#define RXCR1_RXPAFMA (1 << 11)
115#define RXCR1_RXFCE (1 << 10)
116#define RXCR1_RXEFE (1 << 9)
117#define RXCR1_RXMAFMA (1 << 8)
118#define RXCR1_RXBE (1 << 7)
119#define RXCR1_RXME (1 << 6)
120#define RXCR1_RXUE (1 << 5)
121#define RXCR1_RXAE (1 << 4)
122#define RXCR1_RXINVF (1 << 1)
123#define RXCR1_RXE (1 << 0)
124
125#define KS_RXCR2 0x76
126#define RXCR2_SRDBL_MASK (0x7 << 5)
127#define RXCR2_SRDBL_SHIFT (5)
128#define RXCR2_SRDBL_4B (0x0 << 5)
129#define RXCR2_SRDBL_8B (0x1 << 5)
130#define RXCR2_SRDBL_16B (0x2 << 5)
131#define RXCR2_SRDBL_32B (0x3 << 5)
132#define RXCR2_SRDBL_FRAME (0x4 << 5)
133#define RXCR2_IUFFP (1 << 4)
134#define RXCR2_RXIUFCEZ (1 << 3)
135#define RXCR2_UDPLFE (1 << 2)
136#define RXCR2_RXICMPFCC (1 << 1)
137#define RXCR2_RXSAF (1 << 0)
138
139#define KS_TXMIR 0x78
140
141#define KS_RXFHSR 0x7C
142#define RXFSHR_RXFV (1 << 15)
143#define RXFSHR_RXICMPFCS (1 << 13)
144#define RXFSHR_RXIPFCS (1 << 12)
145#define RXFSHR_RXTCPFCS (1 << 11)
146#define RXFSHR_RXUDPFCS (1 << 10)
147#define RXFSHR_RXBF (1 << 7)
148#define RXFSHR_RXMF (1 << 6)
149#define RXFSHR_RXUF (1 << 5)
150#define RXFSHR_RXMR (1 << 4)
151#define RXFSHR_RXFT (1 << 3)
152#define RXFSHR_RXFTL (1 << 2)
153#define RXFSHR_RXRF (1 << 1)
154#define RXFSHR_RXCE (1 << 0)
155
156#define KS_RXFHBCR 0x7E
157#define KS_TXQCR 0x80
158#define TXQCR_AETFE (1 << 2)
159#define TXQCR_TXQMAM (1 << 1)
160#define TXQCR_METFE (1 << 0)
161
162#define KS_RXQCR 0x82
163#define RXQCR_RXDTTS (1 << 12)
164#define RXQCR_RXDBCTS (1 << 11)
165#define RXQCR_RXFCTS (1 << 10)
166#define RXQCR_RXIPHTOE (1 << 9)
167#define RXQCR_RXDTTE (1 << 7)
168#define RXQCR_RXDBCTE (1 << 6)
169#define RXQCR_RXFCTE (1 << 5)
170#define RXQCR_ADRFE (1 << 4)
171#define RXQCR_SDA (1 << 3)
172#define RXQCR_RRXEF (1 << 0)
173
174#define KS_TXFDPR 0x84
175#define TXFDPR_TXFPAI (1 << 14)
176#define TXFDPR_TXFP_MASK (0x7ff << 0)
177#define TXFDPR_TXFP_SHIFT (0)
178
179#define KS_RXFDPR 0x86
180#define RXFDPR_RXFPAI (1 << 14)
181
182#define KS_RXDTTR 0x8C
183#define KS_RXDBCTR 0x8E
184
185#define KS_IER 0x90
186#define KS_ISR 0x92
187#define IRQ_LCI (1 << 15)
188#define IRQ_TXI (1 << 14)
189#define IRQ_RXI (1 << 13)
190#define IRQ_RXOI (1 << 11)
191#define IRQ_TXPSI (1 << 9)
192#define IRQ_RXPSI (1 << 8)
193#define IRQ_TXSAI (1 << 6)
194#define IRQ_RXWFDI (1 << 5)
195#define IRQ_RXMPDI (1 << 4)
196#define IRQ_LDI (1 << 3)
197#define IRQ_EDI (1 << 2)
198#define IRQ_SPIBEI (1 << 1)
199#define IRQ_DEDI (1 << 0)
200
201#define KS_RXFCTR 0x9C
202#define KS_RXFC 0x9D
203#define RXFCTR_RXFC_MASK (0xff << 8)
204#define RXFCTR_RXFC_SHIFT (8)
205#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
206#define RXFCTR_RXFCT_MASK (0xff << 0)
207#define RXFCTR_RXFCT_SHIFT (0)
208
209#define KS_TXNTFSR 0x9E
210
211#define KS_MAHTR0 0xA0
212#define KS_MAHTR1 0xA2
213#define KS_MAHTR2 0xA4
214#define KS_MAHTR3 0xA6
215
216#define KS_FCLWR 0xB0
217#define KS_FCHWR 0xB2
218#define KS_FCOWR 0xB4
219
220#define KS_CIDER 0xC0
221#define CIDER_ID 0x8870
222#define CIDER_REV_MASK (0x7 << 1)
223#define CIDER_REV_SHIFT (1)
224#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
225
226#define KS_CGCR 0xC6
227
228#define KS_IACR 0xC8
229#define IACR_RDEN (1 << 12)
230#define IACR_TSEL_MASK (0x3 << 10)
231#define IACR_TSEL_SHIFT (10)
232#define IACR_TSEL_MIB (0x3 << 10)
233#define IACR_ADDR_MASK (0x1f << 0)
234#define IACR_ADDR_SHIFT (0)
235
236#define KS_IADLR 0xD0
237#define KS_IAHDR 0xD2
238
239#define KS_PMECR 0xD4
240#define PMECR_PME_DELAY (1 << 14)
241#define PMECR_PME_POL (1 << 12)
242#define PMECR_WOL_WAKEUP (1 << 11)
243#define PMECR_WOL_MAGICPKT (1 << 10)
244#define PMECR_WOL_LINKUP (1 << 9)
245#define PMECR_WOL_ENERGY (1 << 8)
246#define PMECR_AUTO_WAKE_EN (1 << 7)
247#define PMECR_WAKEUP_NORMAL (1 << 6)
248#define PMECR_WKEVT_MASK (0xf << 2)
249#define PMECR_WKEVT_SHIFT (2)
250#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
251#define PMECR_WKEVT_ENERGY (0x1 << 2)
252#define PMECR_WKEVT_LINK (0x2 << 2)
253#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
254#define PMECR_WKEVT_FRAME (0x8 << 2)
255#define PMECR_PM_MASK (0x3 << 0)
256#define PMECR_PM_SHIFT (0)
257#define PMECR_PM_NORMAL (0x0 << 0)
258#define PMECR_PM_ENERGY (0x1 << 0)
259#define PMECR_PM_SOFTDOWN (0x2 << 0)
260#define PMECR_PM_POWERSAVE (0x3 << 0)
261
262/* Standard MII PHY data */
263#define KS_P1MBCR 0xE4
264#define KS_P1MBSR 0xE6
265#define KS_PHY1ILR 0xE8
266#define KS_PHY1IHR 0xEA
267#define KS_P1ANAR 0xEC
268#define KS_P1ANLPR 0xEE
269
270#define KS_P1SCLMD 0xF4
271#define P1SCLMD_LEDOFF (1 << 15)
272#define P1SCLMD_TXIDS (1 << 14)
273#define P1SCLMD_RESTARTAN (1 << 13)
274#define P1SCLMD_DISAUTOMDIX (1 << 10)
275#define P1SCLMD_FORCEMDIX (1 << 9)
276#define P1SCLMD_AUTONEGEN (1 << 7)
277#define P1SCLMD_FORCE100 (1 << 6)
278#define P1SCLMD_FORCEFDX (1 << 5)
279#define P1SCLMD_ADV_FLOW (1 << 4)
280#define P1SCLMD_ADV_100BT_FDX (1 << 3)
281#define P1SCLMD_ADV_100BT_HDX (1 << 2)
282#define P1SCLMD_ADV_10BT_FDX (1 << 1)
283#define P1SCLMD_ADV_10BT_HDX (1 << 0)
284
285#define KS_P1CR 0xF6
286#define P1CR_HP_MDIX (1 << 15)
287#define P1CR_REV_POL (1 << 13)
288#define P1CR_OP_100M (1 << 10)
289#define P1CR_OP_FDX (1 << 9)
290#define P1CR_OP_MDI (1 << 7)
291#define P1CR_AN_DONE (1 << 6)
292#define P1CR_LINK_GOOD (1 << 5)
293#define P1CR_PNTR_FLOW (1 << 4)
294#define P1CR_PNTR_100BT_FDX (1 << 3)
295#define P1CR_PNTR_100BT_HDX (1 << 2)
296#define P1CR_PNTR_10BT_FDX (1 << 1)
297#define P1CR_PNTR_10BT_HDX (1 << 0)
298
299/* TX Frame control */
300
301#define TXFR_TXIC (1 << 15)
302#define TXFR_TXFID_MASK (0x3f << 0)
303#define TXFR_TXFID_SHIFT (0)
304
305/* SPI frame opcodes */
306#define KS_SPIOP_RD (0x00)
307#define KS_SPIOP_WR (0x40)
308#define KS_SPIOP_RXFIFO (0x80)
309#define KS_SPIOP_TXFIFO (0xC0)
diff --git a/drivers/net/ethernet/micrel/ks8851_mll.c b/drivers/net/ethernet/micrel/ks8851_mll.c
new file mode 100644
index 000000000000..d19c849059d8
--- /dev/null
+++ b/drivers/net/ethernet/micrel/ks8851_mll.c
@@ -0,0 +1,1680 @@
1/**
2 * drivers/net/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/**
20 * Supports:
21 * KS8851 16bit MLL chip from Micrel Inc.
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/cache.h>
33#include <linux/crc32.h>
34#include <linux/mii.h>
35#include <linux/platform_device.h>
36#include <linux/delay.h>
37#include <linux/slab.h>
38#include <asm/io.h>
39
40#define DRV_NAME "ks8851_mll"
41
42static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
43#define MAX_RECV_FRAMES 32
44#define MAX_BUF_SIZE 2048
45#define TX_BUF_SIZE 2000
46#define RX_BUF_SIZE 2000
47
48#define KS_CCR 0x08
49#define CCR_EEPROM (1 << 9)
50#define CCR_SPI (1 << 8)
51#define CCR_8BIT (1 << 7)
52#define CCR_16BIT (1 << 6)
53#define CCR_32BIT (1 << 5)
54#define CCR_SHARED (1 << 4)
55#define CCR_32PIN (1 << 0)
56
57/* MAC address registers */
58#define KS_MARL 0x10
59#define KS_MARM 0x12
60#define KS_MARH 0x14
61
62#define KS_OBCR 0x20
63#define OBCR_ODS_16MA (1 << 6)
64
65#define KS_EEPCR 0x22
66#define EEPCR_EESA (1 << 4)
67#define EEPCR_EESB (1 << 3)
68#define EEPCR_EEDO (1 << 2)
69#define EEPCR_EESCK (1 << 1)
70#define EEPCR_EECS (1 << 0)
71
72#define KS_MBIR 0x24
73#define MBIR_TXMBF (1 << 12)
74#define MBIR_TXMBFA (1 << 11)
75#define MBIR_RXMBF (1 << 4)
76#define MBIR_RXMBFA (1 << 3)
77
78#define KS_GRR 0x26
79#define GRR_QMU (1 << 1)
80#define GRR_GSR (1 << 0)
81
82#define KS_WFCR 0x2A
83#define WFCR_MPRXE (1 << 7)
84#define WFCR_WF3E (1 << 3)
85#define WFCR_WF2E (1 << 2)
86#define WFCR_WF1E (1 << 1)
87#define WFCR_WF0E (1 << 0)
88
89#define KS_WF0CRC0 0x30
90#define KS_WF0CRC1 0x32
91#define KS_WF0BM0 0x34
92#define KS_WF0BM1 0x36
93#define KS_WF0BM2 0x38
94#define KS_WF0BM3 0x3A
95
96#define KS_WF1CRC0 0x40
97#define KS_WF1CRC1 0x42
98#define KS_WF1BM0 0x44
99#define KS_WF1BM1 0x46
100#define KS_WF1BM2 0x48
101#define KS_WF1BM3 0x4A
102
103#define KS_WF2CRC0 0x50
104#define KS_WF2CRC1 0x52
105#define KS_WF2BM0 0x54
106#define KS_WF2BM1 0x56
107#define KS_WF2BM2 0x58
108#define KS_WF2BM3 0x5A
109
110#define KS_WF3CRC0 0x60
111#define KS_WF3CRC1 0x62
112#define KS_WF3BM0 0x64
113#define KS_WF3BM1 0x66
114#define KS_WF3BM2 0x68
115#define KS_WF3BM3 0x6A
116
117#define KS_TXCR 0x70
118#define TXCR_TCGICMP (1 << 8)
119#define TXCR_TCGUDP (1 << 7)
120#define TXCR_TCGTCP (1 << 6)
121#define TXCR_TCGIP (1 << 5)
122#define TXCR_FTXQ (1 << 4)
123#define TXCR_TXFCE (1 << 3)
124#define TXCR_TXPE (1 << 2)
125#define TXCR_TXCRC (1 << 1)
126#define TXCR_TXE (1 << 0)
127
128#define KS_TXSR 0x72
129#define TXSR_TXLC (1 << 13)
130#define TXSR_TXMC (1 << 12)
131#define TXSR_TXFID_MASK (0x3f << 0)
132#define TXSR_TXFID_SHIFT (0)
133#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
134
135
136#define KS_RXCR1 0x74
137#define RXCR1_FRXQ (1 << 15)
138#define RXCR1_RXUDPFCC (1 << 14)
139#define RXCR1_RXTCPFCC (1 << 13)
140#define RXCR1_RXIPFCC (1 << 12)
141#define RXCR1_RXPAFMA (1 << 11)
142#define RXCR1_RXFCE (1 << 10)
143#define RXCR1_RXEFE (1 << 9)
144#define RXCR1_RXMAFMA (1 << 8)
145#define RXCR1_RXBE (1 << 7)
146#define RXCR1_RXME (1 << 6)
147#define RXCR1_RXUE (1 << 5)
148#define RXCR1_RXAE (1 << 4)
149#define RXCR1_RXINVF (1 << 1)
150#define RXCR1_RXE (1 << 0)
151#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
152 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
153
154#define KS_RXCR2 0x76
155#define RXCR2_SRDBL_MASK (0x7 << 5)
156#define RXCR2_SRDBL_SHIFT (5)
157#define RXCR2_SRDBL_4B (0x0 << 5)
158#define RXCR2_SRDBL_8B (0x1 << 5)
159#define RXCR2_SRDBL_16B (0x2 << 5)
160#define RXCR2_SRDBL_32B (0x3 << 5)
161/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
162#define RXCR2_IUFFP (1 << 4)
163#define RXCR2_RXIUFCEZ (1 << 3)
164#define RXCR2_UDPLFE (1 << 2)
165#define RXCR2_RXICMPFCC (1 << 1)
166#define RXCR2_RXSAF (1 << 0)
167
168#define KS_TXMIR 0x78
169
170#define KS_RXFHSR 0x7C
171#define RXFSHR_RXFV (1 << 15)
172#define RXFSHR_RXICMPFCS (1 << 13)
173#define RXFSHR_RXIPFCS (1 << 12)
174#define RXFSHR_RXTCPFCS (1 << 11)
175#define RXFSHR_RXUDPFCS (1 << 10)
176#define RXFSHR_RXBF (1 << 7)
177#define RXFSHR_RXMF (1 << 6)
178#define RXFSHR_RXUF (1 << 5)
179#define RXFSHR_RXMR (1 << 4)
180#define RXFSHR_RXFT (1 << 3)
181#define RXFSHR_RXFTL (1 << 2)
182#define RXFSHR_RXRF (1 << 1)
183#define RXFSHR_RXCE (1 << 0)
184#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
185 RXFSHR_RXFTL | RXFSHR_RXMR |\
186 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
187 RXFSHR_RXTCPFCS)
188#define KS_RXFHBCR 0x7E
189#define RXFHBCR_CNT_MASK 0x0FFF
190
191#define KS_TXQCR 0x80
192#define TXQCR_AETFE (1 << 2)
193#define TXQCR_TXQMAM (1 << 1)
194#define TXQCR_METFE (1 << 0)
195
196#define KS_RXQCR 0x82
197#define RXQCR_RXDTTS (1 << 12)
198#define RXQCR_RXDBCTS (1 << 11)
199#define RXQCR_RXFCTS (1 << 10)
200#define RXQCR_RXIPHTOE (1 << 9)
201#define RXQCR_RXDTTE (1 << 7)
202#define RXQCR_RXDBCTE (1 << 6)
203#define RXQCR_RXFCTE (1 << 5)
204#define RXQCR_ADRFE (1 << 4)
205#define RXQCR_SDA (1 << 3)
206#define RXQCR_RRXEF (1 << 0)
207#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
208
209#define KS_TXFDPR 0x84
210#define TXFDPR_TXFPAI (1 << 14)
211#define TXFDPR_TXFP_MASK (0x7ff << 0)
212#define TXFDPR_TXFP_SHIFT (0)
213
214#define KS_RXFDPR 0x86
215#define RXFDPR_RXFPAI (1 << 14)
216
217#define KS_RXDTTR 0x8C
218#define KS_RXDBCTR 0x8E
219
220#define KS_IER 0x90
221#define KS_ISR 0x92
222#define IRQ_LCI (1 << 15)
223#define IRQ_TXI (1 << 14)
224#define IRQ_RXI (1 << 13)
225#define IRQ_RXOI (1 << 11)
226#define IRQ_TXPSI (1 << 9)
227#define IRQ_RXPSI (1 << 8)
228#define IRQ_TXSAI (1 << 6)
229#define IRQ_RXWFDI (1 << 5)
230#define IRQ_RXMPDI (1 << 4)
231#define IRQ_LDI (1 << 3)
232#define IRQ_EDI (1 << 2)
233#define IRQ_SPIBEI (1 << 1)
234#define IRQ_DEDI (1 << 0)
235
236#define KS_RXFCTR 0x9C
237#define RXFCTR_THRESHOLD_MASK 0x00FF
238
239#define KS_RXFC 0x9D
240#define RXFCTR_RXFC_MASK (0xff << 8)
241#define RXFCTR_RXFC_SHIFT (8)
242#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
243#define RXFCTR_RXFCT_MASK (0xff << 0)
244#define RXFCTR_RXFCT_SHIFT (0)
245
246#define KS_TXNTFSR 0x9E
247
248#define KS_MAHTR0 0xA0
249#define KS_MAHTR1 0xA2
250#define KS_MAHTR2 0xA4
251#define KS_MAHTR3 0xA6
252
253#define KS_FCLWR 0xB0
254#define KS_FCHWR 0xB2
255#define KS_FCOWR 0xB4
256
257#define KS_CIDER 0xC0
258#define CIDER_ID 0x8870
259#define CIDER_REV_MASK (0x7 << 1)
260#define CIDER_REV_SHIFT (1)
261#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
262
263#define KS_CGCR 0xC6
264#define KS_IACR 0xC8
265#define IACR_RDEN (1 << 12)
266#define IACR_TSEL_MASK (0x3 << 10)
267#define IACR_TSEL_SHIFT (10)
268#define IACR_TSEL_MIB (0x3 << 10)
269#define IACR_ADDR_MASK (0x1f << 0)
270#define IACR_ADDR_SHIFT (0)
271
272#define KS_IADLR 0xD0
273#define KS_IAHDR 0xD2
274
275#define KS_PMECR 0xD4
276#define PMECR_PME_DELAY (1 << 14)
277#define PMECR_PME_POL (1 << 12)
278#define PMECR_WOL_WAKEUP (1 << 11)
279#define PMECR_WOL_MAGICPKT (1 << 10)
280#define PMECR_WOL_LINKUP (1 << 9)
281#define PMECR_WOL_ENERGY (1 << 8)
282#define PMECR_AUTO_WAKE_EN (1 << 7)
283#define PMECR_WAKEUP_NORMAL (1 << 6)
284#define PMECR_WKEVT_MASK (0xf << 2)
285#define PMECR_WKEVT_SHIFT (2)
286#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
287#define PMECR_WKEVT_ENERGY (0x1 << 2)
288#define PMECR_WKEVT_LINK (0x2 << 2)
289#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
290#define PMECR_WKEVT_FRAME (0x8 << 2)
291#define PMECR_PM_MASK (0x3 << 0)
292#define PMECR_PM_SHIFT (0)
293#define PMECR_PM_NORMAL (0x0 << 0)
294#define PMECR_PM_ENERGY (0x1 << 0)
295#define PMECR_PM_SOFTDOWN (0x2 << 0)
296#define PMECR_PM_POWERSAVE (0x3 << 0)
297
298/* Standard MII PHY data */
299#define KS_P1MBCR 0xE4
300#define P1MBCR_FORCE_FDX (1 << 8)
301
302#define KS_P1MBSR 0xE6
303#define P1MBSR_AN_COMPLETE (1 << 5)
304#define P1MBSR_AN_CAPABLE (1 << 3)
305#define P1MBSR_LINK_UP (1 << 2)
306
307#define KS_PHY1ILR 0xE8
308#define KS_PHY1IHR 0xEA
309#define KS_P1ANAR 0xEC
310#define KS_P1ANLPR 0xEE
311
312#define KS_P1SCLMD 0xF4
313#define P1SCLMD_LEDOFF (1 << 15)
314#define P1SCLMD_TXIDS (1 << 14)
315#define P1SCLMD_RESTARTAN (1 << 13)
316#define P1SCLMD_DISAUTOMDIX (1 << 10)
317#define P1SCLMD_FORCEMDIX (1 << 9)
318#define P1SCLMD_AUTONEGEN (1 << 7)
319#define P1SCLMD_FORCE100 (1 << 6)
320#define P1SCLMD_FORCEFDX (1 << 5)
321#define P1SCLMD_ADV_FLOW (1 << 4)
322#define P1SCLMD_ADV_100BT_FDX (1 << 3)
323#define P1SCLMD_ADV_100BT_HDX (1 << 2)
324#define P1SCLMD_ADV_10BT_FDX (1 << 1)
325#define P1SCLMD_ADV_10BT_HDX (1 << 0)
326
327#define KS_P1CR 0xF6
328#define P1CR_HP_MDIX (1 << 15)
329#define P1CR_REV_POL (1 << 13)
330#define P1CR_OP_100M (1 << 10)
331#define P1CR_OP_FDX (1 << 9)
332#define P1CR_OP_MDI (1 << 7)
333#define P1CR_AN_DONE (1 << 6)
334#define P1CR_LINK_GOOD (1 << 5)
335#define P1CR_PNTR_FLOW (1 << 4)
336#define P1CR_PNTR_100BT_FDX (1 << 3)
337#define P1CR_PNTR_100BT_HDX (1 << 2)
338#define P1CR_PNTR_10BT_FDX (1 << 1)
339#define P1CR_PNTR_10BT_HDX (1 << 0)
340
341/* TX Frame control */
342
343#define TXFR_TXIC (1 << 15)
344#define TXFR_TXFID_MASK (0x3f << 0)
345#define TXFR_TXFID_SHIFT (0)
346
347#define KS_P1SR 0xF8
348#define P1SR_HP_MDIX (1 << 15)
349#define P1SR_REV_POL (1 << 13)
350#define P1SR_OP_100M (1 << 10)
351#define P1SR_OP_FDX (1 << 9)
352#define P1SR_OP_MDI (1 << 7)
353#define P1SR_AN_DONE (1 << 6)
354#define P1SR_LINK_GOOD (1 << 5)
355#define P1SR_PNTR_FLOW (1 << 4)
356#define P1SR_PNTR_100BT_FDX (1 << 3)
357#define P1SR_PNTR_100BT_HDX (1 << 2)
358#define P1SR_PNTR_10BT_FDX (1 << 1)
359#define P1SR_PNTR_10BT_HDX (1 << 0)
360
361#define ENUM_BUS_NONE 0
362#define ENUM_BUS_8BIT 1
363#define ENUM_BUS_16BIT 2
364#define ENUM_BUS_32BIT 3
365
366#define MAX_MCAST_LST 32
367#define HW_MCAST_SIZE 8
368
369/**
370 * union ks_tx_hdr - tx header data
371 * @txb: The header as bytes
372 * @txw: The header as 16bit, little-endian words
373 *
374 * A dual representation of the tx header data to allow
375 * access to individual bytes, and to allow 16bit accesses
376 * with 16bit alignment.
377 */
378union ks_tx_hdr {
379 u8 txb[4];
380 __le16 txw[2];
381};
382
383/**
384 * struct ks_net - KS8851 driver private data
385 * @net_device : The network device we're bound to
386 * @hw_addr : start address of data register.
387 * @hw_addr_cmd : start address of command register.
388 * @txh : temporaly buffer to save status/length.
389 * @lock : Lock to ensure that the device is not accessed when busy.
390 * @pdev : Pointer to platform device.
391 * @mii : The MII state information for the mii calls.
392 * @frame_head_info : frame header information for multi-pkt rx.
393 * @statelock : Lock on this structure for tx list.
394 * @msg_enable : The message flags controlling driver output (see ethtool).
395 * @frame_cnt : number of frames received.
396 * @bus_width : i/o bus width.
397 * @irq : irq number assigned to this device.
398 * @rc_rxqcr : Cached copy of KS_RXQCR.
399 * @rc_txcr : Cached copy of KS_TXCR.
400 * @rc_ier : Cached copy of KS_IER.
401 * @sharedbus : Multipex(addr and data bus) mode indicator.
402 * @cmd_reg_cache : command register cached.
403 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
404 * @promiscuous : promiscuous mode indicator.
405 * @all_mcast : mutlicast indicator.
406 * @mcast_lst_size : size of multicast list.
407 * @mcast_lst : multicast list.
408 * @mcast_bits : multicast enabed.
409 * @mac_addr : MAC address assigned to this device.
410 * @fid : frame id.
411 * @extra_byte : number of extra byte prepended rx pkt.
412 * @enabled : indicator this device works.
413 *
414 * The @lock ensures that the chip is protected when certain operations are
415 * in progress. When the read or write packet transfer is in progress, most
416 * of the chip registers are not accessible until the transfer is finished and
417 * the DMA has been de-asserted.
418 *
419 * The @statelock is used to protect information in the structure which may
420 * need to be accessed via several sources, such as the network driver layer
421 * or one of the work queues.
422 *
423 */
424
425/* Receive multiplex framer header info */
426struct type_frame_head {
427 u16 sts; /* Frame status */
428 u16 len; /* Byte count */
429};
430
431struct ks_net {
432 struct net_device *netdev;
433 void __iomem *hw_addr;
434 void __iomem *hw_addr_cmd;
435 union ks_tx_hdr txh ____cacheline_aligned;
436 struct mutex lock; /* spinlock to be interrupt safe */
437 struct platform_device *pdev;
438 struct mii_if_info mii;
439 struct type_frame_head *frame_head_info;
440 spinlock_t statelock;
441 u32 msg_enable;
442 u32 frame_cnt;
443 int bus_width;
444 int irq;
445
446 u16 rc_rxqcr;
447 u16 rc_txcr;
448 u16 rc_ier;
449 u16 sharedbus;
450 u16 cmd_reg_cache;
451 u16 cmd_reg_cache_int;
452 u16 promiscuous;
453 u16 all_mcast;
454 u16 mcast_lst_size;
455 u8 mcast_lst[MAX_MCAST_LST][ETH_ALEN];
456 u8 mcast_bits[HW_MCAST_SIZE];
457 u8 mac_addr[6];
458 u8 fid;
459 u8 extra_byte;
460 u8 enabled;
461};
462
463static int msg_enable;
464
465#define BE3 0x8000 /* Byte Enable 3 */
466#define BE2 0x4000 /* Byte Enable 2 */
467#define BE1 0x2000 /* Byte Enable 1 */
468#define BE0 0x1000 /* Byte Enable 0 */
469
470/**
471 * register read/write calls.
472 *
473 * All these calls issue transactions to access the chip's registers. They
474 * all require that the necessary lock is held to prevent accesses when the
475 * chip is busy transferring packet data (RX/TX FIFO accesses).
476 */
477
478/**
479 * ks_rdreg8 - read 8 bit register from device
480 * @ks : The chip information
481 * @offset: The register address
482 *
483 * Read a 8bit register from the chip, returning the result
484 */
485static u8 ks_rdreg8(struct ks_net *ks, int offset)
486{
487 u16 data;
488 u8 shift_bit = offset & 0x03;
489 u8 shift_data = (offset & 1) << 3;
490 ks->cmd_reg_cache = (u16) offset | (u16)(BE0 << shift_bit);
491 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
492 data = ioread16(ks->hw_addr);
493 return (u8)(data >> shift_data);
494}
495
496/**
497 * ks_rdreg16 - read 16 bit register from device
498 * @ks : The chip information
499 * @offset: The register address
500 *
501 * Read a 16bit register from the chip, returning the result
502 */
503
504static u16 ks_rdreg16(struct ks_net *ks, int offset)
505{
506 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
507 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
508 return ioread16(ks->hw_addr);
509}
510
511/**
512 * ks_wrreg8 - write 8bit register value to chip
513 * @ks: The chip information
514 * @offset: The register address
515 * @value: The value to write
516 *
517 */
518static void ks_wrreg8(struct ks_net *ks, int offset, u8 value)
519{
520 u8 shift_bit = (offset & 0x03);
521 u16 value_write = (u16)(value << ((offset & 1) << 3));
522 ks->cmd_reg_cache = (u16)offset | (BE0 << shift_bit);
523 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
524 iowrite16(value_write, ks->hw_addr);
525}
526
527/**
528 * ks_wrreg16 - write 16bit register value to chip
529 * @ks: The chip information
530 * @offset: The register address
531 * @value: The value to write
532 *
533 */
534
535static void ks_wrreg16(struct ks_net *ks, int offset, u16 value)
536{
537 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
538 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
539 iowrite16(value, ks->hw_addr);
540}
541
542/**
543 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
544 * @ks: The chip state
545 * @wptr: buffer address to save data
546 * @len: length in byte to read
547 *
548 */
549static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
550{
551 len >>= 1;
552 while (len--)
553 *wptr++ = (u16)ioread16(ks->hw_addr);
554}
555
556/**
557 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
558 * @ks: The chip information
559 * @wptr: buffer address
560 * @len: length in byte to write
561 *
562 */
563static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
564{
565 len >>= 1;
566 while (len--)
567 iowrite16(*wptr++, ks->hw_addr);
568}
569
570static void ks_disable_int(struct ks_net *ks)
571{
572 ks_wrreg16(ks, KS_IER, 0x0000);
573} /* ks_disable_int */
574
575static void ks_enable_int(struct ks_net *ks)
576{
577 ks_wrreg16(ks, KS_IER, ks->rc_ier);
578} /* ks_enable_int */
579
580/**
581 * ks_tx_fifo_space - return the available hardware buffer size.
582 * @ks: The chip information
583 *
584 */
585static inline u16 ks_tx_fifo_space(struct ks_net *ks)
586{
587 return ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
588}
589
590/**
591 * ks_save_cmd_reg - save the command register from the cache.
592 * @ks: The chip information
593 *
594 */
595static inline void ks_save_cmd_reg(struct ks_net *ks)
596{
597 /*ks8851 MLL has a bug to read back the command register.
598 * So rely on software to save the content of command register.
599 */
600 ks->cmd_reg_cache_int = ks->cmd_reg_cache;
601}
602
603/**
604 * ks_restore_cmd_reg - restore the command register from the cache and
605 * write to hardware register.
606 * @ks: The chip information
607 *
608 */
609static inline void ks_restore_cmd_reg(struct ks_net *ks)
610{
611 ks->cmd_reg_cache = ks->cmd_reg_cache_int;
612 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
613}
614
615/**
616 * ks_set_powermode - set power mode of the device
617 * @ks: The chip information
618 * @pwrmode: The power mode value to write to KS_PMECR.
619 *
620 * Change the power mode of the chip.
621 */
622static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode)
623{
624 unsigned pmecr;
625
626 netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
627
628 ks_rdreg16(ks, KS_GRR);
629 pmecr = ks_rdreg16(ks, KS_PMECR);
630 pmecr &= ~PMECR_PM_MASK;
631 pmecr |= pwrmode;
632
633 ks_wrreg16(ks, KS_PMECR, pmecr);
634}
635
636/**
637 * ks_read_config - read chip configuration of bus width.
638 * @ks: The chip information
639 *
640 */
641static void ks_read_config(struct ks_net *ks)
642{
643 u16 reg_data = 0;
644
645 /* Regardless of bus width, 8 bit read should always work.*/
646 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
647 reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8;
648
649 /* addr/data bus are multiplexed */
650 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
651
652 /* There are garbage data when reading data from QMU,
653 depending on bus-width.
654 */
655
656 if (reg_data & CCR_8BIT) {
657 ks->bus_width = ENUM_BUS_8BIT;
658 ks->extra_byte = 1;
659 } else if (reg_data & CCR_16BIT) {
660 ks->bus_width = ENUM_BUS_16BIT;
661 ks->extra_byte = 2;
662 } else {
663 ks->bus_width = ENUM_BUS_32BIT;
664 ks->extra_byte = 4;
665 }
666}
667
668/**
669 * ks_soft_reset - issue one of the soft reset to the device
670 * @ks: The device state.
671 * @op: The bit(s) to set in the GRR
672 *
673 * Issue the relevant soft-reset command to the device's GRR register
674 * specified by @op.
675 *
676 * Note, the delays are in there as a caution to ensure that the reset
677 * has time to take effect and then complete. Since the datasheet does
678 * not currently specify the exact sequence, we have chosen something
679 * that seems to work with our device.
680 */
681static void ks_soft_reset(struct ks_net *ks, unsigned op)
682{
683 /* Disable interrupt first */
684 ks_wrreg16(ks, KS_IER, 0x0000);
685 ks_wrreg16(ks, KS_GRR, op);
686 mdelay(10); /* wait a short time to effect reset */
687 ks_wrreg16(ks, KS_GRR, 0);
688 mdelay(1); /* wait for condition to clear */
689}
690
691
692void ks_enable_qmu(struct ks_net *ks)
693{
694 u16 w;
695
696 w = ks_rdreg16(ks, KS_TXCR);
697 /* Enables QMU Transmit (TXCR). */
698 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
699
700 /*
701 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
702 * Enable
703 */
704
705 w = ks_rdreg16(ks, KS_RXQCR);
706 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
707
708 /* Enables QMU Receive (RXCR1). */
709 w = ks_rdreg16(ks, KS_RXCR1);
710 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
711 ks->enabled = true;
712} /* ks_enable_qmu */
713
714static void ks_disable_qmu(struct ks_net *ks)
715{
716 u16 w;
717
718 w = ks_rdreg16(ks, KS_TXCR);
719
720 /* Disables QMU Transmit (TXCR). */
721 w &= ~TXCR_TXE;
722 ks_wrreg16(ks, KS_TXCR, w);
723
724 /* Disables QMU Receive (RXCR1). */
725 w = ks_rdreg16(ks, KS_RXCR1);
726 w &= ~RXCR1_RXE ;
727 ks_wrreg16(ks, KS_RXCR1, w);
728
729 ks->enabled = false;
730
731} /* ks_disable_qmu */
732
733/**
734 * ks_read_qmu - read 1 pkt data from the QMU.
735 * @ks: The chip information
736 * @buf: buffer address to save 1 pkt
737 * @len: Pkt length
738 * Here is the sequence to read 1 pkt:
739 * 1. set sudo DMA mode
740 * 2. read prepend data
741 * 3. read pkt data
742 * 4. reset sudo DMA Mode
743 */
744static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
745{
746 u32 r = ks->extra_byte & 0x1 ;
747 u32 w = ks->extra_byte - r;
748
749 /* 1. set sudo DMA mode */
750 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
751 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
752
753 /* 2. read prepend data */
754 /**
755 * read 4 + extra bytes and discard them.
756 * extra bytes for dummy, 2 for status, 2 for len
757 */
758
759 /* use likely(r) for 8 bit access for performance */
760 if (unlikely(r))
761 ioread8(ks->hw_addr);
762 ks_inblk(ks, buf, w + 2 + 2);
763
764 /* 3. read pkt data */
765 ks_inblk(ks, buf, ALIGN(len, 4));
766
767 /* 4. reset sudo DMA Mode */
768 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
769}
770
771/**
772 * ks_rcv - read multiple pkts data from the QMU.
773 * @ks: The chip information
774 * @netdev: The network device being opened.
775 *
776 * Read all of header information before reading pkt content.
777 * It is not allowed only port of pkts in QMU after issuing
778 * interrupt ack.
779 */
780static void ks_rcv(struct ks_net *ks, struct net_device *netdev)
781{
782 u32 i;
783 struct type_frame_head *frame_hdr = ks->frame_head_info;
784 struct sk_buff *skb;
785
786 ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
787
788 /* read all header information */
789 for (i = 0; i < ks->frame_cnt; i++) {
790 /* Checking Received packet status */
791 frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR);
792 /* Get packet len from hardware */
793 frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR);
794 frame_hdr++;
795 }
796
797 frame_hdr = ks->frame_head_info;
798 while (ks->frame_cnt--) {
799 skb = dev_alloc_skb(frame_hdr->len + 16);
800 if (likely(skb && (frame_hdr->sts & RXFSHR_RXFV) &&
801 (frame_hdr->len < RX_BUF_SIZE) && frame_hdr->len)) {
802 skb_reserve(skb, 2);
803 /* read data block including CRC 4 bytes */
804 ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len);
805 skb_put(skb, frame_hdr->len);
806 skb->protocol = eth_type_trans(skb, netdev);
807 netif_rx(skb);
808 } else {
809 pr_err("%s: err:skb alloc\n", __func__);
810 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
811 if (skb)
812 dev_kfree_skb_irq(skb);
813 }
814 frame_hdr++;
815 }
816}
817
818/**
819 * ks_update_link_status - link status update.
820 * @netdev: The network device being opened.
821 * @ks: The chip information
822 *
823 */
824
825static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks)
826{
827 /* check the status of the link */
828 u32 link_up_status;
829 if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) {
830 netif_carrier_on(netdev);
831 link_up_status = true;
832 } else {
833 netif_carrier_off(netdev);
834 link_up_status = false;
835 }
836 netif_dbg(ks, link, ks->netdev,
837 "%s: %s\n", __func__, link_up_status ? "UP" : "DOWN");
838}
839
840/**
841 * ks_irq - device interrupt handler
842 * @irq: Interrupt number passed from the IRQ hnalder.
843 * @pw: The private word passed to register_irq(), our struct ks_net.
844 *
845 * This is the handler invoked to find out what happened
846 *
847 * Read the interrupt status, work out what needs to be done and then clear
848 * any of the interrupts that are not needed.
849 */
850
851static irqreturn_t ks_irq(int irq, void *pw)
852{
853 struct net_device *netdev = pw;
854 struct ks_net *ks = netdev_priv(netdev);
855 u16 status;
856
857 /*this should be the first in IRQ handler */
858 ks_save_cmd_reg(ks);
859
860 status = ks_rdreg16(ks, KS_ISR);
861 if (unlikely(!status)) {
862 ks_restore_cmd_reg(ks);
863 return IRQ_NONE;
864 }
865
866 ks_wrreg16(ks, KS_ISR, status);
867
868 if (likely(status & IRQ_RXI))
869 ks_rcv(ks, netdev);
870
871 if (unlikely(status & IRQ_LCI))
872 ks_update_link_status(netdev, ks);
873
874 if (unlikely(status & IRQ_TXI))
875 netif_wake_queue(netdev);
876
877 if (unlikely(status & IRQ_LDI)) {
878
879 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
880 pmecr &= ~PMECR_WKEVT_MASK;
881 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
882 }
883
884 /* this should be the last in IRQ handler*/
885 ks_restore_cmd_reg(ks);
886 return IRQ_HANDLED;
887}
888
889
890/**
891 * ks_net_open - open network device
892 * @netdev: The network device being opened.
893 *
894 * Called when the network device is marked active, such as a user executing
895 * 'ifconfig up' on the device.
896 */
897static int ks_net_open(struct net_device *netdev)
898{
899 struct ks_net *ks = netdev_priv(netdev);
900 int err;
901
902#define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW)
903 /* lock the card, even if we may not actually do anything
904 * else at the moment.
905 */
906
907 netif_dbg(ks, ifup, ks->netdev, "%s - entry\n", __func__);
908
909 /* reset the HW */
910 err = request_irq(ks->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, netdev);
911
912 if (err) {
913 pr_err("Failed to request IRQ: %d: %d\n", ks->irq, err);
914 return err;
915 }
916
917 /* wake up powermode to normal mode */
918 ks_set_powermode(ks, PMECR_PM_NORMAL);
919 mdelay(1); /* wait for normal mode to take effect */
920
921 ks_wrreg16(ks, KS_ISR, 0xffff);
922 ks_enable_int(ks);
923 ks_enable_qmu(ks);
924 netif_start_queue(ks->netdev);
925
926 netif_dbg(ks, ifup, ks->netdev, "network device up\n");
927
928 return 0;
929}
930
931/**
932 * ks_net_stop - close network device
933 * @netdev: The device being closed.
934 *
935 * Called to close down a network device which has been active. Cancell any
936 * work, shutdown the RX and TX process and then place the chip into a low
937 * power state whilst it is not being used.
938 */
939static int ks_net_stop(struct net_device *netdev)
940{
941 struct ks_net *ks = netdev_priv(netdev);
942
943 netif_info(ks, ifdown, netdev, "shutting down\n");
944
945 netif_stop_queue(netdev);
946
947 mutex_lock(&ks->lock);
948
949 /* turn off the IRQs and ack any outstanding */
950 ks_wrreg16(ks, KS_IER, 0x0000);
951 ks_wrreg16(ks, KS_ISR, 0xffff);
952
953 /* shutdown RX/TX QMU */
954 ks_disable_qmu(ks);
955
956 /* set powermode to soft power down to save power */
957 ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
958 free_irq(ks->irq, netdev);
959 mutex_unlock(&ks->lock);
960 return 0;
961}
962
963
964/**
965 * ks_write_qmu - write 1 pkt data to the QMU.
966 * @ks: The chip information
967 * @pdata: buffer address to save 1 pkt
968 * @len: Pkt length in byte
969 * Here is the sequence to write 1 pkt:
970 * 1. set sudo DMA mode
971 * 2. write status/length
972 * 3. write pkt data
973 * 4. reset sudo DMA Mode
974 * 5. reset sudo DMA mode
975 * 6. Wait until pkt is out
976 */
977static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
978{
979 /* start header at txb[0] to align txw entries */
980 ks->txh.txw[0] = 0;
981 ks->txh.txw[1] = cpu_to_le16(len);
982
983 /* 1. set sudo-DMA mode */
984 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
985 /* 2. write status/lenth info */
986 ks_outblk(ks, ks->txh.txw, 4);
987 /* 3. write pkt data */
988 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
989 /* 4. reset sudo-DMA mode */
990 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
991 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
992 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
993 /* 6. wait until TXQCR_METFE is auto-cleared */
994 while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE)
995 ;
996}
997
998/**
999 * ks_start_xmit - transmit packet
1000 * @skb : The buffer to transmit
1001 * @netdev : The device used to transmit the packet.
1002 *
1003 * Called by the network layer to transmit the @skb.
1004 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
1005 * So while tx is in-progress, prevent IRQ interrupt from happenning.
1006 */
1007static int ks_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1008{
1009 int retv = NETDEV_TX_OK;
1010 struct ks_net *ks = netdev_priv(netdev);
1011
1012 disable_irq(netdev->irq);
1013 ks_disable_int(ks);
1014 spin_lock(&ks->statelock);
1015
1016 /* Extra space are required:
1017 * 4 byte for alignment, 4 for status/length, 4 for CRC
1018 */
1019
1020 if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) {
1021 ks_write_qmu(ks, skb->data, skb->len);
1022 dev_kfree_skb(skb);
1023 } else
1024 retv = NETDEV_TX_BUSY;
1025 spin_unlock(&ks->statelock);
1026 ks_enable_int(ks);
1027 enable_irq(netdev->irq);
1028 return retv;
1029}
1030
1031/**
1032 * ks_start_rx - ready to serve pkts
1033 * @ks : The chip information
1034 *
1035 */
1036static void ks_start_rx(struct ks_net *ks)
1037{
1038 u16 cntl;
1039
1040 /* Enables QMU Receive (RXCR1). */
1041 cntl = ks_rdreg16(ks, KS_RXCR1);
1042 cntl |= RXCR1_RXE ;
1043 ks_wrreg16(ks, KS_RXCR1, cntl);
1044} /* ks_start_rx */
1045
1046/**
1047 * ks_stop_rx - stop to serve pkts
1048 * @ks : The chip information
1049 *
1050 */
1051static void ks_stop_rx(struct ks_net *ks)
1052{
1053 u16 cntl;
1054
1055 /* Disables QMU Receive (RXCR1). */
1056 cntl = ks_rdreg16(ks, KS_RXCR1);
1057 cntl &= ~RXCR1_RXE ;
1058 ks_wrreg16(ks, KS_RXCR1, cntl);
1059
1060} /* ks_stop_rx */
1061
1062static unsigned long const ethernet_polynomial = 0x04c11db7U;
1063
1064static unsigned long ether_gen_crc(int length, u8 *data)
1065{
1066 long crc = -1;
1067 while (--length >= 0) {
1068 u8 current_octet = *data++;
1069 int bit;
1070
1071 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
1072 crc = (crc << 1) ^
1073 ((crc < 0) ^ (current_octet & 1) ?
1074 ethernet_polynomial : 0);
1075 }
1076 }
1077 return (unsigned long)crc;
1078} /* ether_gen_crc */
1079
1080/**
1081* ks_set_grpaddr - set multicast information
1082* @ks : The chip information
1083*/
1084
1085static void ks_set_grpaddr(struct ks_net *ks)
1086{
1087 u8 i;
1088 u32 index, position, value;
1089
1090 memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE);
1091
1092 for (i = 0; i < ks->mcast_lst_size; i++) {
1093 position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f;
1094 index = position >> 3;
1095 value = 1 << (position & 7);
1096 ks->mcast_bits[index] |= (u8)value;
1097 }
1098
1099 for (i = 0; i < HW_MCAST_SIZE; i++) {
1100 if (i & 1) {
1101 ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1),
1102 (ks->mcast_bits[i] << 8) |
1103 ks->mcast_bits[i - 1]);
1104 }
1105 }
1106} /* ks_set_grpaddr */
1107
1108/*
1109* ks_clear_mcast - clear multicast information
1110*
1111* @ks : The chip information
1112* This routine removes all mcast addresses set in the hardware.
1113*/
1114
1115static void ks_clear_mcast(struct ks_net *ks)
1116{
1117 u16 i, mcast_size;
1118 for (i = 0; i < HW_MCAST_SIZE; i++)
1119 ks->mcast_bits[i] = 0;
1120
1121 mcast_size = HW_MCAST_SIZE >> 2;
1122 for (i = 0; i < mcast_size; i++)
1123 ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0);
1124}
1125
1126static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode)
1127{
1128 u16 cntl;
1129 ks->promiscuous = promiscuous_mode;
1130 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1131 cntl = ks_rdreg16(ks, KS_RXCR1);
1132
1133 cntl &= ~RXCR1_FILTER_MASK;
1134 if (promiscuous_mode)
1135 /* Enable Promiscuous mode */
1136 cntl |= RXCR1_RXAE | RXCR1_RXINVF;
1137 else
1138 /* Disable Promiscuous mode (default normal mode) */
1139 cntl |= RXCR1_RXPAFMA;
1140
1141 ks_wrreg16(ks, KS_RXCR1, cntl);
1142
1143 if (ks->enabled)
1144 ks_start_rx(ks);
1145
1146} /* ks_set_promis */
1147
1148static void ks_set_mcast(struct ks_net *ks, u16 mcast)
1149{
1150 u16 cntl;
1151
1152 ks->all_mcast = mcast;
1153 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1154 cntl = ks_rdreg16(ks, KS_RXCR1);
1155 cntl &= ~RXCR1_FILTER_MASK;
1156 if (mcast)
1157 /* Enable "Perfect with Multicast address passed mode" */
1158 cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1159 else
1160 /**
1161 * Disable "Perfect with Multicast address passed
1162 * mode" (normal mode).
1163 */
1164 cntl |= RXCR1_RXPAFMA;
1165
1166 ks_wrreg16(ks, KS_RXCR1, cntl);
1167
1168 if (ks->enabled)
1169 ks_start_rx(ks);
1170} /* ks_set_mcast */
1171
1172static void ks_set_rx_mode(struct net_device *netdev)
1173{
1174 struct ks_net *ks = netdev_priv(netdev);
1175 struct netdev_hw_addr *ha;
1176
1177 /* Turn on/off promiscuous mode. */
1178 if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC)
1179 ks_set_promis(ks,
1180 (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC));
1181 /* Turn on/off all mcast mode. */
1182 else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)
1183 ks_set_mcast(ks,
1184 (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI));
1185 else
1186 ks_set_promis(ks, false);
1187
1188 if ((netdev->flags & IFF_MULTICAST) && netdev_mc_count(netdev)) {
1189 if (netdev_mc_count(netdev) <= MAX_MCAST_LST) {
1190 int i = 0;
1191
1192 netdev_for_each_mc_addr(ha, netdev) {
1193 if (i >= MAX_MCAST_LST)
1194 break;
1195 memcpy(ks->mcast_lst[i++], ha->addr, ETH_ALEN);
1196 }
1197 ks->mcast_lst_size = (u8)i;
1198 ks_set_grpaddr(ks);
1199 } else {
1200 /**
1201 * List too big to support so
1202 * turn on all mcast mode.
1203 */
1204 ks->mcast_lst_size = MAX_MCAST_LST;
1205 ks_set_mcast(ks, true);
1206 }
1207 } else {
1208 ks->mcast_lst_size = 0;
1209 ks_clear_mcast(ks);
1210 }
1211} /* ks_set_rx_mode */
1212
1213static void ks_set_mac(struct ks_net *ks, u8 *data)
1214{
1215 u16 *pw = (u16 *)data;
1216 u16 w, u;
1217
1218 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1219
1220 u = *pw++;
1221 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1222 ks_wrreg16(ks, KS_MARH, w);
1223
1224 u = *pw++;
1225 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1226 ks_wrreg16(ks, KS_MARM, w);
1227
1228 u = *pw;
1229 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1230 ks_wrreg16(ks, KS_MARL, w);
1231
1232 memcpy(ks->mac_addr, data, 6);
1233
1234 if (ks->enabled)
1235 ks_start_rx(ks);
1236}
1237
1238static int ks_set_mac_address(struct net_device *netdev, void *paddr)
1239{
1240 struct ks_net *ks = netdev_priv(netdev);
1241 struct sockaddr *addr = paddr;
1242 u8 *da;
1243
1244 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1245
1246 da = (u8 *)netdev->dev_addr;
1247
1248 ks_set_mac(ks, da);
1249 return 0;
1250}
1251
1252static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
1253{
1254 struct ks_net *ks = netdev_priv(netdev);
1255
1256 if (!netif_running(netdev))
1257 return -EINVAL;
1258
1259 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
1260}
1261
1262static const struct net_device_ops ks_netdev_ops = {
1263 .ndo_open = ks_net_open,
1264 .ndo_stop = ks_net_stop,
1265 .ndo_do_ioctl = ks_net_ioctl,
1266 .ndo_start_xmit = ks_start_xmit,
1267 .ndo_set_mac_address = ks_set_mac_address,
1268 .ndo_set_rx_mode = ks_set_rx_mode,
1269 .ndo_change_mtu = eth_change_mtu,
1270 .ndo_validate_addr = eth_validate_addr,
1271};
1272
1273/* ethtool support */
1274
1275static void ks_get_drvinfo(struct net_device *netdev,
1276 struct ethtool_drvinfo *di)
1277{
1278 strlcpy(di->driver, DRV_NAME, sizeof(di->driver));
1279 strlcpy(di->version, "1.00", sizeof(di->version));
1280 strlcpy(di->bus_info, dev_name(netdev->dev.parent),
1281 sizeof(di->bus_info));
1282}
1283
1284static u32 ks_get_msglevel(struct net_device *netdev)
1285{
1286 struct ks_net *ks = netdev_priv(netdev);
1287 return ks->msg_enable;
1288}
1289
1290static void ks_set_msglevel(struct net_device *netdev, u32 to)
1291{
1292 struct ks_net *ks = netdev_priv(netdev);
1293 ks->msg_enable = to;
1294}
1295
1296static int ks_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1297{
1298 struct ks_net *ks = netdev_priv(netdev);
1299 return mii_ethtool_gset(&ks->mii, cmd);
1300}
1301
1302static int ks_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1303{
1304 struct ks_net *ks = netdev_priv(netdev);
1305 return mii_ethtool_sset(&ks->mii, cmd);
1306}
1307
1308static u32 ks_get_link(struct net_device *netdev)
1309{
1310 struct ks_net *ks = netdev_priv(netdev);
1311 return mii_link_ok(&ks->mii);
1312}
1313
1314static int ks_nway_reset(struct net_device *netdev)
1315{
1316 struct ks_net *ks = netdev_priv(netdev);
1317 return mii_nway_restart(&ks->mii);
1318}
1319
1320static const struct ethtool_ops ks_ethtool_ops = {
1321 .get_drvinfo = ks_get_drvinfo,
1322 .get_msglevel = ks_get_msglevel,
1323 .set_msglevel = ks_set_msglevel,
1324 .get_settings = ks_get_settings,
1325 .set_settings = ks_set_settings,
1326 .get_link = ks_get_link,
1327 .nway_reset = ks_nway_reset,
1328};
1329
1330/* MII interface controls */
1331
1332/**
1333 * ks_phy_reg - convert MII register into a KS8851 register
1334 * @reg: MII register number.
1335 *
1336 * Return the KS8851 register number for the corresponding MII PHY register
1337 * if possible. Return zero if the MII register has no direct mapping to the
1338 * KS8851 register set.
1339 */
1340static int ks_phy_reg(int reg)
1341{
1342 switch (reg) {
1343 case MII_BMCR:
1344 return KS_P1MBCR;
1345 case MII_BMSR:
1346 return KS_P1MBSR;
1347 case MII_PHYSID1:
1348 return KS_PHY1ILR;
1349 case MII_PHYSID2:
1350 return KS_PHY1IHR;
1351 case MII_ADVERTISE:
1352 return KS_P1ANAR;
1353 case MII_LPA:
1354 return KS_P1ANLPR;
1355 }
1356
1357 return 0x0;
1358}
1359
1360/**
1361 * ks_phy_read - MII interface PHY register read.
1362 * @netdev: The network device the PHY is on.
1363 * @phy_addr: Address of PHY (ignored as we only have one)
1364 * @reg: The register to read.
1365 *
1366 * This call reads data from the PHY register specified in @reg. Since the
1367 * device does not support all the MII registers, the non-existent values
1368 * are always returned as zero.
1369 *
1370 * We return zero for unsupported registers as the MII code does not check
1371 * the value returned for any error status, and simply returns it to the
1372 * caller. The mii-tool that the driver was tested with takes any -ve error
1373 * as real PHY capabilities, thus displaying incorrect data to the user.
1374 */
1375static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg)
1376{
1377 struct ks_net *ks = netdev_priv(netdev);
1378 int ksreg;
1379 int result;
1380
1381 ksreg = ks_phy_reg(reg);
1382 if (!ksreg)
1383 return 0x0; /* no error return allowed, so use zero */
1384
1385 mutex_lock(&ks->lock);
1386 result = ks_rdreg16(ks, ksreg);
1387 mutex_unlock(&ks->lock);
1388
1389 return result;
1390}
1391
1392static void ks_phy_write(struct net_device *netdev,
1393 int phy, int reg, int value)
1394{
1395 struct ks_net *ks = netdev_priv(netdev);
1396 int ksreg;
1397
1398 ksreg = ks_phy_reg(reg);
1399 if (ksreg) {
1400 mutex_lock(&ks->lock);
1401 ks_wrreg16(ks, ksreg, value);
1402 mutex_unlock(&ks->lock);
1403 }
1404}
1405
1406/**
1407 * ks_read_selftest - read the selftest memory info.
1408 * @ks: The device state
1409 *
1410 * Read and check the TX/RX memory selftest information.
1411 */
1412static int ks_read_selftest(struct ks_net *ks)
1413{
1414 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1415 int ret = 0;
1416 unsigned rd;
1417
1418 rd = ks_rdreg16(ks, KS_MBIR);
1419
1420 if ((rd & both_done) != both_done) {
1421 netdev_warn(ks->netdev, "Memory selftest not finished\n");
1422 return 0;
1423 }
1424
1425 if (rd & MBIR_TXMBFA) {
1426 netdev_err(ks->netdev, "TX memory selftest fails\n");
1427 ret |= 1;
1428 }
1429
1430 if (rd & MBIR_RXMBFA) {
1431 netdev_err(ks->netdev, "RX memory selftest fails\n");
1432 ret |= 2;
1433 }
1434
1435 netdev_info(ks->netdev, "the selftest passes\n");
1436 return ret;
1437}
1438
1439static void ks_setup(struct ks_net *ks)
1440{
1441 u16 w;
1442
1443 /**
1444 * Configure QMU Transmit
1445 */
1446
1447 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1448 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
1449
1450 /* Setup Receive Frame Data Pointer Auto-Increment */
1451 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
1452
1453 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1454 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
1455
1456 /* Setup RxQ Command Control (RXQCR) */
1457 ks->rc_rxqcr = RXQCR_CMD_CNTL;
1458 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
1459
1460 /**
1461 * set the force mode to half duplex, default is full duplex
1462 * because if the auto-negotiation fails, most switch uses
1463 * half-duplex.
1464 */
1465
1466 w = ks_rdreg16(ks, KS_P1MBCR);
1467 w &= ~P1MBCR_FORCE_FDX;
1468 ks_wrreg16(ks, KS_P1MBCR, w);
1469
1470 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
1471 ks_wrreg16(ks, KS_TXCR, w);
1472
1473 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
1474
1475 if (ks->promiscuous) /* bPromiscuous */
1476 w |= (RXCR1_RXAE | RXCR1_RXINVF);
1477 else if (ks->all_mcast) /* Multicast address passed mode */
1478 w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1479 else /* Normal mode */
1480 w |= RXCR1_RXPAFMA;
1481
1482 ks_wrreg16(ks, KS_RXCR1, w);
1483} /*ks_setup */
1484
1485
1486static void ks_setup_int(struct ks_net *ks)
1487{
1488 ks->rc_ier = 0x00;
1489 /* Clear the interrupts status of the hardware. */
1490 ks_wrreg16(ks, KS_ISR, 0xffff);
1491
1492 /* Enables the interrupts of the hardware. */
1493 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
1494} /* ks_setup_int */
1495
1496static int ks_hw_init(struct ks_net *ks)
1497{
1498#define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1499 ks->promiscuous = 0;
1500 ks->all_mcast = 0;
1501 ks->mcast_lst_size = 0;
1502
1503 ks->frame_head_info = (struct type_frame_head *) \
1504 kmalloc(MHEADER_SIZE, GFP_KERNEL);
1505 if (!ks->frame_head_info) {
1506 pr_err("Error: Fail to allocate frame memory\n");
1507 return false;
1508 }
1509
1510 ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS);
1511 return true;
1512}
1513
1514
1515static int __devinit ks8851_probe(struct platform_device *pdev)
1516{
1517 int err = -ENOMEM;
1518 struct resource *io_d, *io_c;
1519 struct net_device *netdev;
1520 struct ks_net *ks;
1521 u16 id, data;
1522
1523 io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1524 io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1525
1526 if (!request_mem_region(io_d->start, resource_size(io_d), DRV_NAME))
1527 goto err_mem_region;
1528
1529 if (!request_mem_region(io_c->start, resource_size(io_c), DRV_NAME))
1530 goto err_mem_region1;
1531
1532 netdev = alloc_etherdev(sizeof(struct ks_net));
1533 if (!netdev)
1534 goto err_alloc_etherdev;
1535
1536 SET_NETDEV_DEV(netdev, &pdev->dev);
1537
1538 ks = netdev_priv(netdev);
1539 ks->netdev = netdev;
1540 ks->hw_addr = ioremap(io_d->start, resource_size(io_d));
1541
1542 if (!ks->hw_addr)
1543 goto err_ioremap;
1544
1545 ks->hw_addr_cmd = ioremap(io_c->start, resource_size(io_c));
1546 if (!ks->hw_addr_cmd)
1547 goto err_ioremap1;
1548
1549 ks->irq = platform_get_irq(pdev, 0);
1550
1551 if (ks->irq < 0) {
1552 err = ks->irq;
1553 goto err_get_irq;
1554 }
1555
1556 ks->pdev = pdev;
1557
1558 mutex_init(&ks->lock);
1559 spin_lock_init(&ks->statelock);
1560
1561 netdev->netdev_ops = &ks_netdev_ops;
1562 netdev->ethtool_ops = &ks_ethtool_ops;
1563
1564 /* setup mii state */
1565 ks->mii.dev = netdev;
1566 ks->mii.phy_id = 1,
1567 ks->mii.phy_id_mask = 1;
1568 ks->mii.reg_num_mask = 0xf;
1569 ks->mii.mdio_read = ks_phy_read;
1570 ks->mii.mdio_write = ks_phy_write;
1571
1572 netdev_info(netdev, "message enable is %d\n", msg_enable);
1573 /* set the default message enable */
1574 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1575 NETIF_MSG_PROBE |
1576 NETIF_MSG_LINK));
1577 ks_read_config(ks);
1578
1579 /* simple check for a valid chip being connected to the bus */
1580 if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1581 netdev_err(netdev, "failed to read device ID\n");
1582 err = -ENODEV;
1583 goto err_register;
1584 }
1585
1586 if (ks_read_selftest(ks)) {
1587 netdev_err(netdev, "failed to read device ID\n");
1588 err = -ENODEV;
1589 goto err_register;
1590 }
1591
1592 err = register_netdev(netdev);
1593 if (err)
1594 goto err_register;
1595
1596 platform_set_drvdata(pdev, netdev);
1597
1598 ks_soft_reset(ks, GRR_GSR);
1599 ks_hw_init(ks);
1600 ks_disable_qmu(ks);
1601 ks_setup(ks);
1602 ks_setup_int(ks);
1603 memcpy(netdev->dev_addr, ks->mac_addr, 6);
1604
1605 data = ks_rdreg16(ks, KS_OBCR);
1606 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
1607
1608 /**
1609 * If you want to use the default MAC addr,
1610 * comment out the 2 functions below.
1611 */
1612
1613 random_ether_addr(netdev->dev_addr);
1614 ks_set_mac(ks, netdev->dev_addr);
1615
1616 id = ks_rdreg16(ks, KS_CIDER);
1617
1618 netdev_info(netdev, "Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1619 (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7);
1620 return 0;
1621
1622err_register:
1623err_get_irq:
1624 iounmap(ks->hw_addr_cmd);
1625err_ioremap1:
1626 iounmap(ks->hw_addr);
1627err_ioremap:
1628 free_netdev(netdev);
1629err_alloc_etherdev:
1630 release_mem_region(io_c->start, resource_size(io_c));
1631err_mem_region1:
1632 release_mem_region(io_d->start, resource_size(io_d));
1633err_mem_region:
1634 return err;
1635}
1636
1637static int __devexit ks8851_remove(struct platform_device *pdev)
1638{
1639 struct net_device *netdev = platform_get_drvdata(pdev);
1640 struct ks_net *ks = netdev_priv(netdev);
1641 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1642
1643 kfree(ks->frame_head_info);
1644 unregister_netdev(netdev);
1645 iounmap(ks->hw_addr);
1646 free_netdev(netdev);
1647 release_mem_region(iomem->start, resource_size(iomem));
1648 platform_set_drvdata(pdev, NULL);
1649 return 0;
1650
1651}
1652
1653static struct platform_driver ks8851_platform_driver = {
1654 .driver = {
1655 .name = DRV_NAME,
1656 .owner = THIS_MODULE,
1657 },
1658 .probe = ks8851_probe,
1659 .remove = __devexit_p(ks8851_remove),
1660};
1661
1662static int __init ks8851_init(void)
1663{
1664 return platform_driver_register(&ks8851_platform_driver);
1665}
1666
1667static void __exit ks8851_exit(void)
1668{
1669 platform_driver_unregister(&ks8851_platform_driver);
1670}
1671
1672module_init(ks8851_init);
1673module_exit(ks8851_exit);
1674
1675MODULE_DESCRIPTION("KS8851 MLL Network driver");
1676MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1677MODULE_LICENSE("GPL");
1678module_param_named(message, msg_enable, int, 0);
1679MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
1680
diff --git a/drivers/net/ethernet/micrel/ksz884x.c b/drivers/net/ethernet/micrel/ksz884x.c
new file mode 100644
index 000000000000..27418d31a09f
--- /dev/null
+++ b/drivers/net/ethernet/micrel/ksz884x.c
@@ -0,0 +1,7289 @@
1/**
2 * drivers/net/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
3 *
4 * Copyright (c) 2009-2010 Micrel, Inc.
5 * Tristram Ha <Tristram.Ha@micrel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/ioport.h>
24#include <linux/pci.h>
25#include <linux/proc_fs.h>
26#include <linux/mii.h>
27#include <linux/platform_device.h>
28#include <linux/ethtool.h>
29#include <linux/etherdevice.h>
30#include <linux/in.h>
31#include <linux/ip.h>
32#include <linux/if_vlan.h>
33#include <linux/crc32.h>
34#include <linux/sched.h>
35#include <linux/slab.h>
36
37
38/* DMA Registers */
39
40#define KS_DMA_TX_CTRL 0x0000
41#define DMA_TX_ENABLE 0x00000001
42#define DMA_TX_CRC_ENABLE 0x00000002
43#define DMA_TX_PAD_ENABLE 0x00000004
44#define DMA_TX_LOOPBACK 0x00000100
45#define DMA_TX_FLOW_ENABLE 0x00000200
46#define DMA_TX_CSUM_IP 0x00010000
47#define DMA_TX_CSUM_TCP 0x00020000
48#define DMA_TX_CSUM_UDP 0x00040000
49#define DMA_TX_BURST_SIZE 0x3F000000
50
51#define KS_DMA_RX_CTRL 0x0004
52#define DMA_RX_ENABLE 0x00000001
53#define KS884X_DMA_RX_MULTICAST 0x00000002
54#define DMA_RX_PROMISCUOUS 0x00000004
55#define DMA_RX_ERROR 0x00000008
56#define DMA_RX_UNICAST 0x00000010
57#define DMA_RX_ALL_MULTICAST 0x00000020
58#define DMA_RX_BROADCAST 0x00000040
59#define DMA_RX_FLOW_ENABLE 0x00000200
60#define DMA_RX_CSUM_IP 0x00010000
61#define DMA_RX_CSUM_TCP 0x00020000
62#define DMA_RX_CSUM_UDP 0x00040000
63#define DMA_RX_BURST_SIZE 0x3F000000
64
65#define DMA_BURST_SHIFT 24
66#define DMA_BURST_DEFAULT 8
67
68#define KS_DMA_TX_START 0x0008
69#define KS_DMA_RX_START 0x000C
70#define DMA_START 0x00000001
71
72#define KS_DMA_TX_ADDR 0x0010
73#define KS_DMA_RX_ADDR 0x0014
74
75#define DMA_ADDR_LIST_MASK 0xFFFFFFFC
76#define DMA_ADDR_LIST_SHIFT 2
77
78/* MTR0 */
79#define KS884X_MULTICAST_0_OFFSET 0x0020
80#define KS884X_MULTICAST_1_OFFSET 0x0021
81#define KS884X_MULTICAST_2_OFFSET 0x0022
82#define KS884x_MULTICAST_3_OFFSET 0x0023
83/* MTR1 */
84#define KS884X_MULTICAST_4_OFFSET 0x0024
85#define KS884X_MULTICAST_5_OFFSET 0x0025
86#define KS884X_MULTICAST_6_OFFSET 0x0026
87#define KS884X_MULTICAST_7_OFFSET 0x0027
88
89/* Interrupt Registers */
90
91/* INTEN */
92#define KS884X_INTERRUPTS_ENABLE 0x0028
93/* INTST */
94#define KS884X_INTERRUPTS_STATUS 0x002C
95
96#define KS884X_INT_RX_STOPPED 0x02000000
97#define KS884X_INT_TX_STOPPED 0x04000000
98#define KS884X_INT_RX_OVERRUN 0x08000000
99#define KS884X_INT_TX_EMPTY 0x10000000
100#define KS884X_INT_RX 0x20000000
101#define KS884X_INT_TX 0x40000000
102#define KS884X_INT_PHY 0x80000000
103
104#define KS884X_INT_RX_MASK \
105 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
106#define KS884X_INT_TX_MASK \
107 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
108#define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
109
110/* MAC Additional Station Address */
111
112/* MAAL0 */
113#define KS_ADD_ADDR_0_LO 0x0080
114/* MAAH0 */
115#define KS_ADD_ADDR_0_HI 0x0084
116/* MAAL1 */
117#define KS_ADD_ADDR_1_LO 0x0088
118/* MAAH1 */
119#define KS_ADD_ADDR_1_HI 0x008C
120/* MAAL2 */
121#define KS_ADD_ADDR_2_LO 0x0090
122/* MAAH2 */
123#define KS_ADD_ADDR_2_HI 0x0094
124/* MAAL3 */
125#define KS_ADD_ADDR_3_LO 0x0098
126/* MAAH3 */
127#define KS_ADD_ADDR_3_HI 0x009C
128/* MAAL4 */
129#define KS_ADD_ADDR_4_LO 0x00A0
130/* MAAH4 */
131#define KS_ADD_ADDR_4_HI 0x00A4
132/* MAAL5 */
133#define KS_ADD_ADDR_5_LO 0x00A8
134/* MAAH5 */
135#define KS_ADD_ADDR_5_HI 0x00AC
136/* MAAL6 */
137#define KS_ADD_ADDR_6_LO 0x00B0
138/* MAAH6 */
139#define KS_ADD_ADDR_6_HI 0x00B4
140/* MAAL7 */
141#define KS_ADD_ADDR_7_LO 0x00B8
142/* MAAH7 */
143#define KS_ADD_ADDR_7_HI 0x00BC
144/* MAAL8 */
145#define KS_ADD_ADDR_8_LO 0x00C0
146/* MAAH8 */
147#define KS_ADD_ADDR_8_HI 0x00C4
148/* MAAL9 */
149#define KS_ADD_ADDR_9_LO 0x00C8
150/* MAAH9 */
151#define KS_ADD_ADDR_9_HI 0x00CC
152/* MAAL10 */
153#define KS_ADD_ADDR_A_LO 0x00D0
154/* MAAH10 */
155#define KS_ADD_ADDR_A_HI 0x00D4
156/* MAAL11 */
157#define KS_ADD_ADDR_B_LO 0x00D8
158/* MAAH11 */
159#define KS_ADD_ADDR_B_HI 0x00DC
160/* MAAL12 */
161#define KS_ADD_ADDR_C_LO 0x00E0
162/* MAAH12 */
163#define KS_ADD_ADDR_C_HI 0x00E4
164/* MAAL13 */
165#define KS_ADD_ADDR_D_LO 0x00E8
166/* MAAH13 */
167#define KS_ADD_ADDR_D_HI 0x00EC
168/* MAAL14 */
169#define KS_ADD_ADDR_E_LO 0x00F0
170/* MAAH14 */
171#define KS_ADD_ADDR_E_HI 0x00F4
172/* MAAL15 */
173#define KS_ADD_ADDR_F_LO 0x00F8
174/* MAAH15 */
175#define KS_ADD_ADDR_F_HI 0x00FC
176
177#define ADD_ADDR_HI_MASK 0x0000FFFF
178#define ADD_ADDR_ENABLE 0x80000000
179#define ADD_ADDR_INCR 8
180
181/* Miscellaneous Registers */
182
183/* MARL */
184#define KS884X_ADDR_0_OFFSET 0x0200
185#define KS884X_ADDR_1_OFFSET 0x0201
186/* MARM */
187#define KS884X_ADDR_2_OFFSET 0x0202
188#define KS884X_ADDR_3_OFFSET 0x0203
189/* MARH */
190#define KS884X_ADDR_4_OFFSET 0x0204
191#define KS884X_ADDR_5_OFFSET 0x0205
192
193/* OBCR */
194#define KS884X_BUS_CTRL_OFFSET 0x0210
195
196#define BUS_SPEED_125_MHZ 0x0000
197#define BUS_SPEED_62_5_MHZ 0x0001
198#define BUS_SPEED_41_66_MHZ 0x0002
199#define BUS_SPEED_25_MHZ 0x0003
200
201/* EEPCR */
202#define KS884X_EEPROM_CTRL_OFFSET 0x0212
203
204#define EEPROM_CHIP_SELECT 0x0001
205#define EEPROM_SERIAL_CLOCK 0x0002
206#define EEPROM_DATA_OUT 0x0004
207#define EEPROM_DATA_IN 0x0008
208#define EEPROM_ACCESS_ENABLE 0x0010
209
210/* MBIR */
211#define KS884X_MEM_INFO_OFFSET 0x0214
212
213#define RX_MEM_TEST_FAILED 0x0008
214#define RX_MEM_TEST_FINISHED 0x0010
215#define TX_MEM_TEST_FAILED 0x0800
216#define TX_MEM_TEST_FINISHED 0x1000
217
218/* GCR */
219#define KS884X_GLOBAL_CTRL_OFFSET 0x0216
220#define GLOBAL_SOFTWARE_RESET 0x0001
221
222#define KS8841_POWER_MANAGE_OFFSET 0x0218
223
224/* WFCR */
225#define KS8841_WOL_CTRL_OFFSET 0x021A
226#define KS8841_WOL_MAGIC_ENABLE 0x0080
227#define KS8841_WOL_FRAME3_ENABLE 0x0008
228#define KS8841_WOL_FRAME2_ENABLE 0x0004
229#define KS8841_WOL_FRAME1_ENABLE 0x0002
230#define KS8841_WOL_FRAME0_ENABLE 0x0001
231
232/* WF0 */
233#define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
234#define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
235#define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
236
237/* IACR */
238#define KS884X_IACR_P 0x04A0
239#define KS884X_IACR_OFFSET KS884X_IACR_P
240
241/* IADR1 */
242#define KS884X_IADR1_P 0x04A2
243#define KS884X_IADR2_P 0x04A4
244#define KS884X_IADR3_P 0x04A6
245#define KS884X_IADR4_P 0x04A8
246#define KS884X_IADR5_P 0x04AA
247
248#define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
249#define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
250
251#define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
252#define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
253#define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
254#define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
255#define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
256#define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
257#define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
258#define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
259#define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
260
261/* P1MBCR */
262#define KS884X_P1MBCR_P 0x04D0
263#define KS884X_P1MBSR_P 0x04D2
264#define KS884X_PHY1ILR_P 0x04D4
265#define KS884X_PHY1IHR_P 0x04D6
266#define KS884X_P1ANAR_P 0x04D8
267#define KS884X_P1ANLPR_P 0x04DA
268
269/* P2MBCR */
270#define KS884X_P2MBCR_P 0x04E0
271#define KS884X_P2MBSR_P 0x04E2
272#define KS884X_PHY2ILR_P 0x04E4
273#define KS884X_PHY2IHR_P 0x04E6
274#define KS884X_P2ANAR_P 0x04E8
275#define KS884X_P2ANLPR_P 0x04EA
276
277#define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
278#define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
279
280#define KS884X_PHY_CTRL_OFFSET 0x00
281
282/* Mode Control Register */
283#define PHY_REG_CTRL 0
284
285#define PHY_RESET 0x8000
286#define PHY_LOOPBACK 0x4000
287#define PHY_SPEED_100MBIT 0x2000
288#define PHY_AUTO_NEG_ENABLE 0x1000
289#define PHY_POWER_DOWN 0x0800
290#define PHY_MII_DISABLE 0x0400
291#define PHY_AUTO_NEG_RESTART 0x0200
292#define PHY_FULL_DUPLEX 0x0100
293#define PHY_COLLISION_TEST 0x0080
294#define PHY_HP_MDIX 0x0020
295#define PHY_FORCE_MDIX 0x0010
296#define PHY_AUTO_MDIX_DISABLE 0x0008
297#define PHY_REMOTE_FAULT_DISABLE 0x0004
298#define PHY_TRANSMIT_DISABLE 0x0002
299#define PHY_LED_DISABLE 0x0001
300
301#define KS884X_PHY_STATUS_OFFSET 0x02
302
303/* Mode Status Register */
304#define PHY_REG_STATUS 1
305
306#define PHY_100BT4_CAPABLE 0x8000
307#define PHY_100BTX_FD_CAPABLE 0x4000
308#define PHY_100BTX_CAPABLE 0x2000
309#define PHY_10BT_FD_CAPABLE 0x1000
310#define PHY_10BT_CAPABLE 0x0800
311#define PHY_MII_SUPPRESS_CAPABLE 0x0040
312#define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
313#define PHY_REMOTE_FAULT 0x0010
314#define PHY_AUTO_NEG_CAPABLE 0x0008
315#define PHY_LINK_STATUS 0x0004
316#define PHY_JABBER_DETECT 0x0002
317#define PHY_EXTENDED_CAPABILITY 0x0001
318
319#define KS884X_PHY_ID_1_OFFSET 0x04
320#define KS884X_PHY_ID_2_OFFSET 0x06
321
322/* PHY Identifier Registers */
323#define PHY_REG_ID_1 2
324#define PHY_REG_ID_2 3
325
326#define KS884X_PHY_AUTO_NEG_OFFSET 0x08
327
328/* Auto-Negotiation Advertisement Register */
329#define PHY_REG_AUTO_NEGOTIATION 4
330
331#define PHY_AUTO_NEG_NEXT_PAGE 0x8000
332#define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
333/* Not supported. */
334#define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
335#define PHY_AUTO_NEG_SYM_PAUSE 0x0400
336#define PHY_AUTO_NEG_100BT4 0x0200
337#define PHY_AUTO_NEG_100BTX_FD 0x0100
338#define PHY_AUTO_NEG_100BTX 0x0080
339#define PHY_AUTO_NEG_10BT_FD 0x0040
340#define PHY_AUTO_NEG_10BT 0x0020
341#define PHY_AUTO_NEG_SELECTOR 0x001F
342#define PHY_AUTO_NEG_802_3 0x0001
343
344#define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
345
346#define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
347
348/* Auto-Negotiation Link Partner Ability Register */
349#define PHY_REG_REMOTE_CAPABILITY 5
350
351#define PHY_REMOTE_NEXT_PAGE 0x8000
352#define PHY_REMOTE_ACKNOWLEDGE 0x4000
353#define PHY_REMOTE_REMOTE_FAULT 0x2000
354#define PHY_REMOTE_SYM_PAUSE 0x0400
355#define PHY_REMOTE_100BTX_FD 0x0100
356#define PHY_REMOTE_100BTX 0x0080
357#define PHY_REMOTE_10BT_FD 0x0040
358#define PHY_REMOTE_10BT 0x0020
359
360/* P1VCT */
361#define KS884X_P1VCT_P 0x04F0
362#define KS884X_P1PHYCTRL_P 0x04F2
363
364/* P2VCT */
365#define KS884X_P2VCT_P 0x04F4
366#define KS884X_P2PHYCTRL_P 0x04F6
367
368#define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
369#define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
370
371#define KS884X_PHY_LINK_MD_OFFSET 0x00
372
373#define PHY_START_CABLE_DIAG 0x8000
374#define PHY_CABLE_DIAG_RESULT 0x6000
375#define PHY_CABLE_STAT_NORMAL 0x0000
376#define PHY_CABLE_STAT_OPEN 0x2000
377#define PHY_CABLE_STAT_SHORT 0x4000
378#define PHY_CABLE_STAT_FAILED 0x6000
379#define PHY_CABLE_10M_SHORT 0x1000
380#define PHY_CABLE_FAULT_COUNTER 0x01FF
381
382#define KS884X_PHY_PHY_CTRL_OFFSET 0x02
383
384#define PHY_STAT_REVERSED_POLARITY 0x0020
385#define PHY_STAT_MDIX 0x0010
386#define PHY_FORCE_LINK 0x0008
387#define PHY_POWER_SAVING_DISABLE 0x0004
388#define PHY_REMOTE_LOOPBACK 0x0002
389
390/* SIDER */
391#define KS884X_SIDER_P 0x0400
392#define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
393#define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
394
395#define REG_FAMILY_ID 0x88
396
397#define REG_CHIP_ID_41 0x8810
398#define REG_CHIP_ID_42 0x8800
399
400#define KS884X_CHIP_ID_MASK_41 0xFF10
401#define KS884X_CHIP_ID_MASK 0xFFF0
402#define KS884X_CHIP_ID_SHIFT 4
403#define KS884X_REVISION_MASK 0x000E
404#define KS884X_REVISION_SHIFT 1
405#define KS8842_START 0x0001
406
407#define CHIP_IP_41_M 0x8810
408#define CHIP_IP_42_M 0x8800
409#define CHIP_IP_61_M 0x8890
410#define CHIP_IP_62_M 0x8880
411
412#define CHIP_IP_41_P 0x8850
413#define CHIP_IP_42_P 0x8840
414#define CHIP_IP_61_P 0x88D0
415#define CHIP_IP_62_P 0x88C0
416
417/* SGCR1 */
418#define KS8842_SGCR1_P 0x0402
419#define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
420
421#define SWITCH_PASS_ALL 0x8000
422#define SWITCH_TX_FLOW_CTRL 0x2000
423#define SWITCH_RX_FLOW_CTRL 0x1000
424#define SWITCH_CHECK_LENGTH 0x0800
425#define SWITCH_AGING_ENABLE 0x0400
426#define SWITCH_FAST_AGING 0x0200
427#define SWITCH_AGGR_BACKOFF 0x0100
428#define SWITCH_PASS_PAUSE 0x0008
429#define SWITCH_LINK_AUTO_AGING 0x0001
430
431/* SGCR2 */
432#define KS8842_SGCR2_P 0x0404
433#define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
434
435#define SWITCH_VLAN_ENABLE 0x8000
436#define SWITCH_IGMP_SNOOP 0x4000
437#define IPV6_MLD_SNOOP_ENABLE 0x2000
438#define IPV6_MLD_SNOOP_OPTION 0x1000
439#define PRIORITY_SCHEME_SELECT 0x0800
440#define SWITCH_MIRROR_RX_TX 0x0100
441#define UNICAST_VLAN_BOUNDARY 0x0080
442#define MULTICAST_STORM_DISABLE 0x0040
443#define SWITCH_BACK_PRESSURE 0x0020
444#define FAIR_FLOW_CTRL 0x0010
445#define NO_EXC_COLLISION_DROP 0x0008
446#define SWITCH_HUGE_PACKET 0x0004
447#define SWITCH_LEGAL_PACKET 0x0002
448#define SWITCH_BUF_RESERVE 0x0001
449
450/* SGCR3 */
451#define KS8842_SGCR3_P 0x0406
452#define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
453
454#define BROADCAST_STORM_RATE_LO 0xFF00
455#define SWITCH_REPEATER 0x0080
456#define SWITCH_HALF_DUPLEX 0x0040
457#define SWITCH_FLOW_CTRL 0x0020
458#define SWITCH_10_MBIT 0x0010
459#define SWITCH_REPLACE_NULL_VID 0x0008
460#define BROADCAST_STORM_RATE_HI 0x0007
461
462#define BROADCAST_STORM_RATE 0x07FF
463
464/* SGCR4 */
465#define KS8842_SGCR4_P 0x0408
466
467/* SGCR5 */
468#define KS8842_SGCR5_P 0x040A
469#define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
470
471#define LED_MODE 0x8200
472#define LED_SPEED_DUPLEX_ACT 0x0000
473#define LED_SPEED_DUPLEX_LINK_ACT 0x8000
474#define LED_DUPLEX_10_100 0x0200
475
476/* SGCR6 */
477#define KS8842_SGCR6_P 0x0410
478#define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
479
480#define KS8842_PRIORITY_MASK 3
481#define KS8842_PRIORITY_SHIFT 2
482
483/* SGCR7 */
484#define KS8842_SGCR7_P 0x0412
485#define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
486
487#define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
488#define SWITCH_UNK_DEF_PORT_3 0x0004
489#define SWITCH_UNK_DEF_PORT_2 0x0002
490#define SWITCH_UNK_DEF_PORT_1 0x0001
491
492/* MACAR1 */
493#define KS8842_MACAR1_P 0x0470
494#define KS8842_MACAR2_P 0x0472
495#define KS8842_MACAR3_P 0x0474
496#define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
497#define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
498#define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
499#define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
500#define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
501#define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
502
503/* TOSR1 */
504#define KS8842_TOSR1_P 0x0480
505#define KS8842_TOSR2_P 0x0482
506#define KS8842_TOSR3_P 0x0484
507#define KS8842_TOSR4_P 0x0486
508#define KS8842_TOSR5_P 0x0488
509#define KS8842_TOSR6_P 0x048A
510#define KS8842_TOSR7_P 0x0490
511#define KS8842_TOSR8_P 0x0492
512#define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
513#define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
514#define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
515#define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
516#define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
517#define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
518
519#define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
520#define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
521
522/* P1CR1 */
523#define KS8842_P1CR1_P 0x0500
524#define KS8842_P1CR2_P 0x0502
525#define KS8842_P1VIDR_P 0x0504
526#define KS8842_P1CR3_P 0x0506
527#define KS8842_P1IRCR_P 0x0508
528#define KS8842_P1ERCR_P 0x050A
529#define KS884X_P1SCSLMD_P 0x0510
530#define KS884X_P1CR4_P 0x0512
531#define KS884X_P1SR_P 0x0514
532
533/* P2CR1 */
534#define KS8842_P2CR1_P 0x0520
535#define KS8842_P2CR2_P 0x0522
536#define KS8842_P2VIDR_P 0x0524
537#define KS8842_P2CR3_P 0x0526
538#define KS8842_P2IRCR_P 0x0528
539#define KS8842_P2ERCR_P 0x052A
540#define KS884X_P2SCSLMD_P 0x0530
541#define KS884X_P2CR4_P 0x0532
542#define KS884X_P2SR_P 0x0534
543
544/* P3CR1 */
545#define KS8842_P3CR1_P 0x0540
546#define KS8842_P3CR2_P 0x0542
547#define KS8842_P3VIDR_P 0x0544
548#define KS8842_P3CR3_P 0x0546
549#define KS8842_P3IRCR_P 0x0548
550#define KS8842_P3ERCR_P 0x054A
551
552#define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
553#define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
554#define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
555
556#define PORT_CTRL_ADDR(port, addr) \
557 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
558 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
559
560#define KS8842_PORT_CTRL_1_OFFSET 0x00
561
562#define PORT_BROADCAST_STORM 0x0080
563#define PORT_DIFFSERV_ENABLE 0x0040
564#define PORT_802_1P_ENABLE 0x0020
565#define PORT_BASED_PRIORITY_MASK 0x0018
566#define PORT_BASED_PRIORITY_BASE 0x0003
567#define PORT_BASED_PRIORITY_SHIFT 3
568#define PORT_BASED_PRIORITY_0 0x0000
569#define PORT_BASED_PRIORITY_1 0x0008
570#define PORT_BASED_PRIORITY_2 0x0010
571#define PORT_BASED_PRIORITY_3 0x0018
572#define PORT_INSERT_TAG 0x0004
573#define PORT_REMOVE_TAG 0x0002
574#define PORT_PRIO_QUEUE_ENABLE 0x0001
575
576#define KS8842_PORT_CTRL_2_OFFSET 0x02
577
578#define PORT_INGRESS_VLAN_FILTER 0x4000
579#define PORT_DISCARD_NON_VID 0x2000
580#define PORT_FORCE_FLOW_CTRL 0x1000
581#define PORT_BACK_PRESSURE 0x0800
582#define PORT_TX_ENABLE 0x0400
583#define PORT_RX_ENABLE 0x0200
584#define PORT_LEARN_DISABLE 0x0100
585#define PORT_MIRROR_SNIFFER 0x0080
586#define PORT_MIRROR_RX 0x0040
587#define PORT_MIRROR_TX 0x0020
588#define PORT_USER_PRIORITY_CEILING 0x0008
589#define PORT_VLAN_MEMBERSHIP 0x0007
590
591#define KS8842_PORT_CTRL_VID_OFFSET 0x04
592
593#define PORT_DEFAULT_VID 0x0001
594
595#define KS8842_PORT_CTRL_3_OFFSET 0x06
596
597#define PORT_INGRESS_LIMIT_MODE 0x000C
598#define PORT_INGRESS_ALL 0x0000
599#define PORT_INGRESS_UNICAST 0x0004
600#define PORT_INGRESS_MULTICAST 0x0008
601#define PORT_INGRESS_BROADCAST 0x000C
602#define PORT_COUNT_IFG 0x0002
603#define PORT_COUNT_PREAMBLE 0x0001
604
605#define KS8842_PORT_IN_RATE_OFFSET 0x08
606#define KS8842_PORT_OUT_RATE_OFFSET 0x0A
607
608#define PORT_PRIORITY_RATE 0x0F
609#define PORT_PRIORITY_RATE_SHIFT 4
610
611#define KS884X_PORT_LINK_MD 0x10
612
613#define PORT_CABLE_10M_SHORT 0x8000
614#define PORT_CABLE_DIAG_RESULT 0x6000
615#define PORT_CABLE_STAT_NORMAL 0x0000
616#define PORT_CABLE_STAT_OPEN 0x2000
617#define PORT_CABLE_STAT_SHORT 0x4000
618#define PORT_CABLE_STAT_FAILED 0x6000
619#define PORT_START_CABLE_DIAG 0x1000
620#define PORT_FORCE_LINK 0x0800
621#define PORT_POWER_SAVING_DISABLE 0x0400
622#define PORT_PHY_REMOTE_LOOPBACK 0x0200
623#define PORT_CABLE_FAULT_COUNTER 0x01FF
624
625#define KS884X_PORT_CTRL_4_OFFSET 0x12
626
627#define PORT_LED_OFF 0x8000
628#define PORT_TX_DISABLE 0x4000
629#define PORT_AUTO_NEG_RESTART 0x2000
630#define PORT_REMOTE_FAULT_DISABLE 0x1000
631#define PORT_POWER_DOWN 0x0800
632#define PORT_AUTO_MDIX_DISABLE 0x0400
633#define PORT_FORCE_MDIX 0x0200
634#define PORT_LOOPBACK 0x0100
635#define PORT_AUTO_NEG_ENABLE 0x0080
636#define PORT_FORCE_100_MBIT 0x0040
637#define PORT_FORCE_FULL_DUPLEX 0x0020
638#define PORT_AUTO_NEG_SYM_PAUSE 0x0010
639#define PORT_AUTO_NEG_100BTX_FD 0x0008
640#define PORT_AUTO_NEG_100BTX 0x0004
641#define PORT_AUTO_NEG_10BT_FD 0x0002
642#define PORT_AUTO_NEG_10BT 0x0001
643
644#define KS884X_PORT_STATUS_OFFSET 0x14
645
646#define PORT_HP_MDIX 0x8000
647#define PORT_REVERSED_POLARITY 0x2000
648#define PORT_RX_FLOW_CTRL 0x0800
649#define PORT_TX_FLOW_CTRL 0x1000
650#define PORT_STATUS_SPEED_100MBIT 0x0400
651#define PORT_STATUS_FULL_DUPLEX 0x0200
652#define PORT_REMOTE_FAULT 0x0100
653#define PORT_MDIX_STATUS 0x0080
654#define PORT_AUTO_NEG_COMPLETE 0x0040
655#define PORT_STATUS_LINK_GOOD 0x0020
656#define PORT_REMOTE_SYM_PAUSE 0x0010
657#define PORT_REMOTE_100BTX_FD 0x0008
658#define PORT_REMOTE_100BTX 0x0004
659#define PORT_REMOTE_10BT_FD 0x0002
660#define PORT_REMOTE_10BT 0x0001
661
662/*
663#define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
664#define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
665#define STATIC_MAC_TABLE_VALID 00-00080000-00000000
666#define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
667#define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
668#define STATIC_MAC_TABLE_FID 00-03C00000-00000000
669*/
670
671#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
672#define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
673#define STATIC_MAC_TABLE_VALID 0x00080000
674#define STATIC_MAC_TABLE_OVERRIDE 0x00100000
675#define STATIC_MAC_TABLE_USE_FID 0x00200000
676#define STATIC_MAC_TABLE_FID 0x03C00000
677
678#define STATIC_MAC_FWD_PORTS_SHIFT 16
679#define STATIC_MAC_FID_SHIFT 22
680
681/*
682#define VLAN_TABLE_VID 00-00000000-00000FFF
683#define VLAN_TABLE_FID 00-00000000-0000F000
684#define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
685#define VLAN_TABLE_VALID 00-00000000-00080000
686*/
687
688#define VLAN_TABLE_VID 0x00000FFF
689#define VLAN_TABLE_FID 0x0000F000
690#define VLAN_TABLE_MEMBERSHIP 0x00070000
691#define VLAN_TABLE_VALID 0x00080000
692
693#define VLAN_TABLE_FID_SHIFT 12
694#define VLAN_TABLE_MEMBERSHIP_SHIFT 16
695
696/*
697#define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
698#define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
699#define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
700#define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
701#define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
702#define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
703#define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
704#define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
705*/
706
707#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
708#define DYNAMIC_MAC_TABLE_FID 0x000F0000
709#define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
710#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
711#define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
712
713#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
714#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
715#define DYNAMIC_MAC_TABLE_RESERVED 0x78
716#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
717
718#define DYNAMIC_MAC_FID_SHIFT 16
719#define DYNAMIC_MAC_SRC_PORT_SHIFT 20
720#define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
721#define DYNAMIC_MAC_ENTRIES_SHIFT 24
722#define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
723
724/*
725#define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
726#define MIB_COUNTER_VALID 00-00000000-40000000
727#define MIB_COUNTER_OVERFLOW 00-00000000-80000000
728*/
729
730#define MIB_COUNTER_VALUE 0x3FFFFFFF
731#define MIB_COUNTER_VALID 0x40000000
732#define MIB_COUNTER_OVERFLOW 0x80000000
733
734#define MIB_PACKET_DROPPED 0x0000FFFF
735
736#define KS_MIB_PACKET_DROPPED_TX_0 0x100
737#define KS_MIB_PACKET_DROPPED_TX_1 0x101
738#define KS_MIB_PACKET_DROPPED_TX 0x102
739#define KS_MIB_PACKET_DROPPED_RX_0 0x103
740#define KS_MIB_PACKET_DROPPED_RX_1 0x104
741#define KS_MIB_PACKET_DROPPED_RX 0x105
742
743/* Change default LED mode. */
744#define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
745
746#define MAC_ADDR_LEN 6
747#define MAC_ADDR_ORDER(i) (MAC_ADDR_LEN - 1 - (i))
748
749#define MAX_ETHERNET_BODY_SIZE 1500
750#define ETHERNET_HEADER_SIZE 14
751
752#define MAX_ETHERNET_PACKET_SIZE \
753 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
754
755#define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
756#define MAX_RX_BUF_SIZE (1912 + 4)
757
758#define ADDITIONAL_ENTRIES 16
759#define MAX_MULTICAST_LIST 32
760
761#define HW_MULTICAST_SIZE 8
762
763#define HW_TO_DEV_PORT(port) (port - 1)
764
765enum {
766 media_connected,
767 media_disconnected
768};
769
770enum {
771 OID_COUNTER_UNKOWN,
772
773 OID_COUNTER_FIRST,
774
775 /* total transmit errors */
776 OID_COUNTER_XMIT_ERROR,
777
778 /* total receive errors */
779 OID_COUNTER_RCV_ERROR,
780
781 OID_COUNTER_LAST
782};
783
784/*
785 * Hardware descriptor definitions
786 */
787
788#define DESC_ALIGNMENT 16
789#define BUFFER_ALIGNMENT 8
790
791#define NUM_OF_RX_DESC 64
792#define NUM_OF_TX_DESC 64
793
794#define KS_DESC_RX_FRAME_LEN 0x000007FF
795#define KS_DESC_RX_FRAME_TYPE 0x00008000
796#define KS_DESC_RX_ERROR_CRC 0x00010000
797#define KS_DESC_RX_ERROR_RUNT 0x00020000
798#define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
799#define KS_DESC_RX_ERROR_PHY 0x00080000
800#define KS884X_DESC_RX_PORT_MASK 0x00300000
801#define KS_DESC_RX_MULTICAST 0x01000000
802#define KS_DESC_RX_ERROR 0x02000000
803#define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
804#define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
805#define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
806#define KS_DESC_RX_LAST 0x20000000
807#define KS_DESC_RX_FIRST 0x40000000
808#define KS_DESC_RX_ERROR_COND \
809 (KS_DESC_RX_ERROR_CRC | \
810 KS_DESC_RX_ERROR_RUNT | \
811 KS_DESC_RX_ERROR_PHY | \
812 KS_DESC_RX_ERROR_TOO_LONG)
813
814#define KS_DESC_HW_OWNED 0x80000000
815
816#define KS_DESC_BUF_SIZE 0x000007FF
817#define KS884X_DESC_TX_PORT_MASK 0x00300000
818#define KS_DESC_END_OF_RING 0x02000000
819#define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
820#define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
821#define KS_DESC_TX_CSUM_GEN_IP 0x10000000
822#define KS_DESC_TX_LAST 0x20000000
823#define KS_DESC_TX_FIRST 0x40000000
824#define KS_DESC_TX_INTERRUPT 0x80000000
825
826#define KS_DESC_PORT_SHIFT 20
827
828#define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
829
830#define KS_DESC_TX_MASK \
831 (KS_DESC_TX_INTERRUPT | \
832 KS_DESC_TX_FIRST | \
833 KS_DESC_TX_LAST | \
834 KS_DESC_TX_CSUM_GEN_IP | \
835 KS_DESC_TX_CSUM_GEN_TCP | \
836 KS_DESC_TX_CSUM_GEN_UDP | \
837 KS_DESC_BUF_SIZE)
838
839struct ksz_desc_rx_stat {
840#ifdef __BIG_ENDIAN_BITFIELD
841 u32 hw_owned:1;
842 u32 first_desc:1;
843 u32 last_desc:1;
844 u32 csum_err_ip:1;
845 u32 csum_err_tcp:1;
846 u32 csum_err_udp:1;
847 u32 error:1;
848 u32 multicast:1;
849 u32 src_port:4;
850 u32 err_phy:1;
851 u32 err_too_long:1;
852 u32 err_runt:1;
853 u32 err_crc:1;
854 u32 frame_type:1;
855 u32 reserved1:4;
856 u32 frame_len:11;
857#else
858 u32 frame_len:11;
859 u32 reserved1:4;
860 u32 frame_type:1;
861 u32 err_crc:1;
862 u32 err_runt:1;
863 u32 err_too_long:1;
864 u32 err_phy:1;
865 u32 src_port:4;
866 u32 multicast:1;
867 u32 error:1;
868 u32 csum_err_udp:1;
869 u32 csum_err_tcp:1;
870 u32 csum_err_ip:1;
871 u32 last_desc:1;
872 u32 first_desc:1;
873 u32 hw_owned:1;
874#endif
875};
876
877struct ksz_desc_tx_stat {
878#ifdef __BIG_ENDIAN_BITFIELD
879 u32 hw_owned:1;
880 u32 reserved1:31;
881#else
882 u32 reserved1:31;
883 u32 hw_owned:1;
884#endif
885};
886
887struct ksz_desc_rx_buf {
888#ifdef __BIG_ENDIAN_BITFIELD
889 u32 reserved4:6;
890 u32 end_of_ring:1;
891 u32 reserved3:14;
892 u32 buf_size:11;
893#else
894 u32 buf_size:11;
895 u32 reserved3:14;
896 u32 end_of_ring:1;
897 u32 reserved4:6;
898#endif
899};
900
901struct ksz_desc_tx_buf {
902#ifdef __BIG_ENDIAN_BITFIELD
903 u32 intr:1;
904 u32 first_seg:1;
905 u32 last_seg:1;
906 u32 csum_gen_ip:1;
907 u32 csum_gen_tcp:1;
908 u32 csum_gen_udp:1;
909 u32 end_of_ring:1;
910 u32 reserved4:1;
911 u32 dest_port:4;
912 u32 reserved3:9;
913 u32 buf_size:11;
914#else
915 u32 buf_size:11;
916 u32 reserved3:9;
917 u32 dest_port:4;
918 u32 reserved4:1;
919 u32 end_of_ring:1;
920 u32 csum_gen_udp:1;
921 u32 csum_gen_tcp:1;
922 u32 csum_gen_ip:1;
923 u32 last_seg:1;
924 u32 first_seg:1;
925 u32 intr:1;
926#endif
927};
928
929union desc_stat {
930 struct ksz_desc_rx_stat rx;
931 struct ksz_desc_tx_stat tx;
932 u32 data;
933};
934
935union desc_buf {
936 struct ksz_desc_rx_buf rx;
937 struct ksz_desc_tx_buf tx;
938 u32 data;
939};
940
941/**
942 * struct ksz_hw_desc - Hardware descriptor data structure
943 * @ctrl: Descriptor control value.
944 * @buf: Descriptor buffer value.
945 * @addr: Physical address of memory buffer.
946 * @next: Pointer to next hardware descriptor.
947 */
948struct ksz_hw_desc {
949 union desc_stat ctrl;
950 union desc_buf buf;
951 u32 addr;
952 u32 next;
953};
954
955/**
956 * struct ksz_sw_desc - Software descriptor data structure
957 * @ctrl: Descriptor control value.
958 * @buf: Descriptor buffer value.
959 * @buf_size: Current buffers size value in hardware descriptor.
960 */
961struct ksz_sw_desc {
962 union desc_stat ctrl;
963 union desc_buf buf;
964 u32 buf_size;
965};
966
967/**
968 * struct ksz_dma_buf - OS dependent DMA buffer data structure
969 * @skb: Associated socket buffer.
970 * @dma: Associated physical DMA address.
971 * len: Actual len used.
972 */
973struct ksz_dma_buf {
974 struct sk_buff *skb;
975 dma_addr_t dma;
976 int len;
977};
978
979/**
980 * struct ksz_desc - Descriptor structure
981 * @phw: Hardware descriptor pointer to uncached physical memory.
982 * @sw: Cached memory to hold hardware descriptor values for
983 * manipulation.
984 * @dma_buf: Operating system dependent data structure to hold physical
985 * memory buffer allocation information.
986 */
987struct ksz_desc {
988 struct ksz_hw_desc *phw;
989 struct ksz_sw_desc sw;
990 struct ksz_dma_buf dma_buf;
991};
992
993#define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
994
995/**
996 * struct ksz_desc_info - Descriptor information data structure
997 * @ring: First descriptor in the ring.
998 * @cur: Current descriptor being manipulated.
999 * @ring_virt: First hardware descriptor in the ring.
1000 * @ring_phys: The physical address of the first descriptor of the ring.
1001 * @size: Size of hardware descriptor.
1002 * @alloc: Number of descriptors allocated.
1003 * @avail: Number of descriptors available for use.
1004 * @last: Index for last descriptor released to hardware.
1005 * @next: Index for next descriptor available for use.
1006 * @mask: Mask for index wrapping.
1007 */
1008struct ksz_desc_info {
1009 struct ksz_desc *ring;
1010 struct ksz_desc *cur;
1011 struct ksz_hw_desc *ring_virt;
1012 u32 ring_phys;
1013 int size;
1014 int alloc;
1015 int avail;
1016 int last;
1017 int next;
1018 int mask;
1019};
1020
1021/*
1022 * KSZ8842 switch definitions
1023 */
1024
1025enum {
1026 TABLE_STATIC_MAC = 0,
1027 TABLE_VLAN,
1028 TABLE_DYNAMIC_MAC,
1029 TABLE_MIB
1030};
1031
1032#define LEARNED_MAC_TABLE_ENTRIES 1024
1033#define STATIC_MAC_TABLE_ENTRIES 8
1034
1035/**
1036 * struct ksz_mac_table - Static MAC table data structure
1037 * @mac_addr: MAC address to filter.
1038 * @vid: VID value.
1039 * @fid: FID value.
1040 * @ports: Port membership.
1041 * @override: Override setting.
1042 * @use_fid: FID use setting.
1043 * @valid: Valid setting indicating the entry is being used.
1044 */
1045struct ksz_mac_table {
1046 u8 mac_addr[MAC_ADDR_LEN];
1047 u16 vid;
1048 u8 fid;
1049 u8 ports;
1050 u8 override:1;
1051 u8 use_fid:1;
1052 u8 valid:1;
1053};
1054
1055#define VLAN_TABLE_ENTRIES 16
1056
1057/**
1058 * struct ksz_vlan_table - VLAN table data structure
1059 * @vid: VID value.
1060 * @fid: FID value.
1061 * @member: Port membership.
1062 */
1063struct ksz_vlan_table {
1064 u16 vid;
1065 u8 fid;
1066 u8 member;
1067};
1068
1069#define DIFFSERV_ENTRIES 64
1070#define PRIO_802_1P_ENTRIES 8
1071#define PRIO_QUEUES 4
1072
1073#define SWITCH_PORT_NUM 2
1074#define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
1075#define HOST_MASK (1 << SWITCH_PORT_NUM)
1076#define PORT_MASK 7
1077
1078#define MAIN_PORT 0
1079#define OTHER_PORT 1
1080#define HOST_PORT SWITCH_PORT_NUM
1081
1082#define PORT_COUNTER_NUM 0x20
1083#define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1084
1085#define MIB_COUNTER_RX_LO_PRIORITY 0x00
1086#define MIB_COUNTER_RX_HI_PRIORITY 0x01
1087#define MIB_COUNTER_RX_UNDERSIZE 0x02
1088#define MIB_COUNTER_RX_FRAGMENT 0x03
1089#define MIB_COUNTER_RX_OVERSIZE 0x04
1090#define MIB_COUNTER_RX_JABBER 0x05
1091#define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1092#define MIB_COUNTER_RX_CRC_ERR 0x07
1093#define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1094#define MIB_COUNTER_RX_CTRL_8808 0x09
1095#define MIB_COUNTER_RX_PAUSE 0x0A
1096#define MIB_COUNTER_RX_BROADCAST 0x0B
1097#define MIB_COUNTER_RX_MULTICAST 0x0C
1098#define MIB_COUNTER_RX_UNICAST 0x0D
1099#define MIB_COUNTER_RX_OCTET_64 0x0E
1100#define MIB_COUNTER_RX_OCTET_65_127 0x0F
1101#define MIB_COUNTER_RX_OCTET_128_255 0x10
1102#define MIB_COUNTER_RX_OCTET_256_511 0x11
1103#define MIB_COUNTER_RX_OCTET_512_1023 0x12
1104#define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1105#define MIB_COUNTER_TX_LO_PRIORITY 0x14
1106#define MIB_COUNTER_TX_HI_PRIORITY 0x15
1107#define MIB_COUNTER_TX_LATE_COLLISION 0x16
1108#define MIB_COUNTER_TX_PAUSE 0x17
1109#define MIB_COUNTER_TX_BROADCAST 0x18
1110#define MIB_COUNTER_TX_MULTICAST 0x19
1111#define MIB_COUNTER_TX_UNICAST 0x1A
1112#define MIB_COUNTER_TX_DEFERRED 0x1B
1113#define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1114#define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1115#define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1116#define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1117
1118#define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1119#define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1120
1121/**
1122 * struct ksz_port_mib - Port MIB data structure
1123 * @cnt_ptr: Current pointer to MIB counter index.
1124 * @link_down: Indication the link has just gone down.
1125 * @state: Connection status of the port.
1126 * @mib_start: The starting counter index. Some ports do not start at 0.
1127 * @counter: 64-bit MIB counter value.
1128 * @dropped: Temporary buffer to remember last read packet dropped values.
1129 *
1130 * MIB counters needs to be read periodically so that counters do not get
1131 * overflowed and give incorrect values. A right balance is needed to
1132 * satisfy this condition and not waste too much CPU time.
1133 *
1134 * It is pointless to read MIB counters when the port is disconnected. The
1135 * @state provides the connection status so that MIB counters are read only
1136 * when the port is connected. The @link_down indicates the port is just
1137 * disconnected so that all MIB counters are read one last time to update the
1138 * information.
1139 */
1140struct ksz_port_mib {
1141 u8 cnt_ptr;
1142 u8 link_down;
1143 u8 state;
1144 u8 mib_start;
1145
1146 u64 counter[TOTAL_PORT_COUNTER_NUM];
1147 u32 dropped[2];
1148};
1149
1150/**
1151 * struct ksz_port_cfg - Port configuration data structure
1152 * @vid: VID value.
1153 * @member: Port membership.
1154 * @port_prio: Port priority.
1155 * @rx_rate: Receive priority rate.
1156 * @tx_rate: Transmit priority rate.
1157 * @stp_state: Current Spanning Tree Protocol state.
1158 */
1159struct ksz_port_cfg {
1160 u16 vid;
1161 u8 member;
1162 u8 port_prio;
1163 u32 rx_rate[PRIO_QUEUES];
1164 u32 tx_rate[PRIO_QUEUES];
1165 int stp_state;
1166};
1167
1168/**
1169 * struct ksz_switch - KSZ8842 switch data structure
1170 * @mac_table: MAC table entries information.
1171 * @vlan_table: VLAN table entries information.
1172 * @port_cfg: Port configuration information.
1173 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1174 * (bit7 ~ bit2) field.
1175 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1176 * Tag priority field.
1177 * @br_addr: Bridge address. Used for STP.
1178 * @other_addr: Other MAC address. Used for multiple network device mode.
1179 * @broad_per: Broadcast storm percentage.
1180 * @member: Current port membership. Used for STP.
1181 */
1182struct ksz_switch {
1183 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1184 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1185 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1186
1187 u8 diffserv[DIFFSERV_ENTRIES];
1188 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1189
1190 u8 br_addr[MAC_ADDR_LEN];
1191 u8 other_addr[MAC_ADDR_LEN];
1192
1193 u8 broad_per;
1194 u8 member;
1195};
1196
1197#define TX_RATE_UNIT 10000
1198
1199/**
1200 * struct ksz_port_info - Port information data structure
1201 * @state: Connection status of the port.
1202 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1203 * @duplex: Duplex mode.
1204 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1205 * @partner: Auto-negotiation partner setting. Used to determine link.
1206 * @port_id: Port index to access actual hardware register.
1207 * @pdev: Pointer to OS dependent network device.
1208 */
1209struct ksz_port_info {
1210 uint state;
1211 uint tx_rate;
1212 u8 duplex;
1213 u8 advertised;
1214 u8 partner;
1215 u8 port_id;
1216 void *pdev;
1217};
1218
1219#define MAX_TX_HELD_SIZE 52000
1220
1221/* Hardware features and bug fixes. */
1222#define LINK_INT_WORKING (1 << 0)
1223#define SMALL_PACKET_TX_BUG (1 << 1)
1224#define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1225#define RX_HUGE_FRAME (1 << 4)
1226#define STP_SUPPORT (1 << 8)
1227
1228/* Software overrides. */
1229#define PAUSE_FLOW_CTRL (1 << 0)
1230#define FAST_AGING (1 << 1)
1231
1232/**
1233 * struct ksz_hw - KSZ884X hardware data structure
1234 * @io: Virtual address assigned.
1235 * @ksz_switch: Pointer to KSZ8842 switch.
1236 * @port_info: Port information.
1237 * @port_mib: Port MIB information.
1238 * @dev_count: Number of network devices this hardware supports.
1239 * @dst_ports: Destination ports in switch for transmission.
1240 * @id: Hardware ID. Used for display only.
1241 * @mib_cnt: Number of MIB counters this hardware has.
1242 * @mib_port_cnt: Number of ports with MIB counters.
1243 * @tx_cfg: Cached transmit control settings.
1244 * @rx_cfg: Cached receive control settings.
1245 * @intr_mask: Current interrupt mask.
1246 * @intr_set: Current interrup set.
1247 * @intr_blocked: Interrupt blocked.
1248 * @rx_desc_info: Receive descriptor information.
1249 * @tx_desc_info: Transmit descriptor information.
1250 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1251 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1252 * @tx_size: Transmit data size. Used for TX optimization.
1253 * The maximum is defined by MAX_TX_HELD_SIZE.
1254 * @perm_addr: Permanent MAC address.
1255 * @override_addr: Overrided MAC address.
1256 * @address: Additional MAC address entries.
1257 * @addr_list_size: Additional MAC address list size.
1258 * @mac_override: Indication of MAC address overrided.
1259 * @promiscuous: Counter to keep track of promiscuous mode set.
1260 * @all_multi: Counter to keep track of all multicast mode set.
1261 * @multi_list: Multicast address entries.
1262 * @multi_bits: Cached multicast hash table settings.
1263 * @multi_list_size: Multicast address list size.
1264 * @enabled: Indication of hardware enabled.
1265 * @rx_stop: Indication of receive process stop.
1266 * @features: Hardware features to enable.
1267 * @overrides: Hardware features to override.
1268 * @parent: Pointer to parent, network device private structure.
1269 */
1270struct ksz_hw {
1271 void __iomem *io;
1272
1273 struct ksz_switch *ksz_switch;
1274 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1275 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1276 int dev_count;
1277 int dst_ports;
1278 int id;
1279 int mib_cnt;
1280 int mib_port_cnt;
1281
1282 u32 tx_cfg;
1283 u32 rx_cfg;
1284 u32 intr_mask;
1285 u32 intr_set;
1286 uint intr_blocked;
1287
1288 struct ksz_desc_info rx_desc_info;
1289 struct ksz_desc_info tx_desc_info;
1290
1291 int tx_int_cnt;
1292 int tx_int_mask;
1293 int tx_size;
1294
1295 u8 perm_addr[MAC_ADDR_LEN];
1296 u8 override_addr[MAC_ADDR_LEN];
1297 u8 address[ADDITIONAL_ENTRIES][MAC_ADDR_LEN];
1298 u8 addr_list_size;
1299 u8 mac_override;
1300 u8 promiscuous;
1301 u8 all_multi;
1302 u8 multi_list[MAX_MULTICAST_LIST][MAC_ADDR_LEN];
1303 u8 multi_bits[HW_MULTICAST_SIZE];
1304 u8 multi_list_size;
1305
1306 u8 enabled;
1307 u8 rx_stop;
1308 u8 reserved2[1];
1309
1310 uint features;
1311 uint overrides;
1312
1313 void *parent;
1314};
1315
1316enum {
1317 PHY_NO_FLOW_CTRL,
1318 PHY_FLOW_CTRL,
1319 PHY_TX_ONLY,
1320 PHY_RX_ONLY
1321};
1322
1323/**
1324 * struct ksz_port - Virtual port data structure
1325 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1326 * duplex, and 0 for auto, which normally results in full
1327 * duplex.
1328 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1329 * 0 for auto, which normally results in 100 Mbit.
1330 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1331 * force.
1332 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1333 * control, and PHY_FLOW_CTRL for flow control.
1334 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1335 * Mbit PHY.
1336 * @first_port: Index of first port this port supports.
1337 * @mib_port_cnt: Number of ports with MIB counters.
1338 * @port_cnt: Number of ports this port supports.
1339 * @counter: Port statistics counter.
1340 * @hw: Pointer to hardware structure.
1341 * @linked: Pointer to port information linked to this port.
1342 */
1343struct ksz_port {
1344 u8 duplex;
1345 u8 speed;
1346 u8 force_link;
1347 u8 flow_ctrl;
1348
1349 int first_port;
1350 int mib_port_cnt;
1351 int port_cnt;
1352 u64 counter[OID_COUNTER_LAST];
1353
1354 struct ksz_hw *hw;
1355 struct ksz_port_info *linked;
1356};
1357
1358/**
1359 * struct ksz_timer_info - Timer information data structure
1360 * @timer: Kernel timer.
1361 * @cnt: Running timer counter.
1362 * @max: Number of times to run timer; -1 for infinity.
1363 * @period: Timer period in jiffies.
1364 */
1365struct ksz_timer_info {
1366 struct timer_list timer;
1367 int cnt;
1368 int max;
1369 int period;
1370};
1371
1372/**
1373 * struct ksz_shared_mem - OS dependent shared memory data structure
1374 * @dma_addr: Physical DMA address allocated.
1375 * @alloc_size: Allocation size.
1376 * @phys: Actual physical address used.
1377 * @alloc_virt: Virtual address allocated.
1378 * @virt: Actual virtual address used.
1379 */
1380struct ksz_shared_mem {
1381 dma_addr_t dma_addr;
1382 uint alloc_size;
1383 uint phys;
1384 u8 *alloc_virt;
1385 u8 *virt;
1386};
1387
1388/**
1389 * struct ksz_counter_info - OS dependent counter information data structure
1390 * @counter: Wait queue to wakeup after counters are read.
1391 * @time: Next time in jiffies to read counter.
1392 * @read: Indication of counters read in full or not.
1393 */
1394struct ksz_counter_info {
1395 wait_queue_head_t counter;
1396 unsigned long time;
1397 int read;
1398};
1399
1400/**
1401 * struct dev_info - Network device information data structure
1402 * @dev: Pointer to network device.
1403 * @pdev: Pointer to PCI device.
1404 * @hw: Hardware structure.
1405 * @desc_pool: Physical memory used for descriptor pool.
1406 * @hwlock: Spinlock to prevent hardware from accessing.
1407 * @lock: Mutex lock to prevent device from accessing.
1408 * @dev_rcv: Receive process function used.
1409 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1410 * @skb_index: Buffer index for receiving fragments.
1411 * @skb_len: Buffer length for receiving fragments.
1412 * @mib_read: Workqueue to read MIB counters.
1413 * @mib_timer_info: Timer to read MIB counters.
1414 * @counter: Used for MIB reading.
1415 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1416 * the maximum is MAX_RX_BUF_SIZE.
1417 * @opened: Counter to keep track of device open.
1418 * @rx_tasklet: Receive processing tasklet.
1419 * @tx_tasklet: Transmit processing tasklet.
1420 * @wol_enable: Wake-on-LAN enable set by ethtool.
1421 * @wol_support: Wake-on-LAN support used by ethtool.
1422 * @pme_wait: Used for KSZ8841 power management.
1423 */
1424struct dev_info {
1425 struct net_device *dev;
1426 struct pci_dev *pdev;
1427
1428 struct ksz_hw hw;
1429 struct ksz_shared_mem desc_pool;
1430
1431 spinlock_t hwlock;
1432 struct mutex lock;
1433
1434 int (*dev_rcv)(struct dev_info *);
1435
1436 struct sk_buff *last_skb;
1437 int skb_index;
1438 int skb_len;
1439
1440 struct work_struct mib_read;
1441 struct ksz_timer_info mib_timer_info;
1442 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1443
1444 int mtu;
1445 int opened;
1446
1447 struct tasklet_struct rx_tasklet;
1448 struct tasklet_struct tx_tasklet;
1449
1450 int wol_enable;
1451 int wol_support;
1452 unsigned long pme_wait;
1453};
1454
1455/**
1456 * struct dev_priv - Network device private data structure
1457 * @adapter: Adapter device information.
1458 * @port: Port information.
1459 * @monitor_time_info: Timer to monitor ports.
1460 * @proc_sem: Semaphore for proc accessing.
1461 * @id: Device ID.
1462 * @mii_if: MII interface information.
1463 * @advertising: Temporary variable to store advertised settings.
1464 * @msg_enable: The message flags controlling driver output.
1465 * @media_state: The connection status of the device.
1466 * @multicast: The all multicast state of the device.
1467 * @promiscuous: The promiscuous state of the device.
1468 */
1469struct dev_priv {
1470 struct dev_info *adapter;
1471 struct ksz_port port;
1472 struct ksz_timer_info monitor_timer_info;
1473
1474 struct semaphore proc_sem;
1475 int id;
1476
1477 struct mii_if_info mii_if;
1478 u32 advertising;
1479
1480 u32 msg_enable;
1481 int media_state;
1482 int multicast;
1483 int promiscuous;
1484};
1485
1486#define DRV_NAME "KSZ884X PCI"
1487#define DEVICE_NAME "KSZ884x PCI"
1488#define DRV_VERSION "1.0.0"
1489#define DRV_RELDATE "Feb 8, 2010"
1490
1491static char version[] __devinitdata =
1492 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1493
1494static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1495
1496/*
1497 * Interrupt processing primary routines
1498 */
1499
1500static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1501{
1502 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1503}
1504
1505static inline void hw_dis_intr(struct ksz_hw *hw)
1506{
1507 hw->intr_blocked = hw->intr_mask;
1508 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1509 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1510}
1511
1512static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1513{
1514 hw->intr_set = interrupt;
1515 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1516}
1517
1518static inline void hw_ena_intr(struct ksz_hw *hw)
1519{
1520 hw->intr_blocked = 0;
1521 hw_set_intr(hw, hw->intr_mask);
1522}
1523
1524static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1525{
1526 hw->intr_mask &= ~(bit);
1527}
1528
1529static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1530{
1531 u32 read_intr;
1532
1533 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1534 hw->intr_set = read_intr & ~interrupt;
1535 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1536 hw_dis_intr_bit(hw, interrupt);
1537}
1538
1539/**
1540 * hw_turn_on_intr - turn on specified interrupts
1541 * @hw: The hardware instance.
1542 * @bit: The interrupt bits to be on.
1543 *
1544 * This routine turns on the specified interrupts in the interrupt mask so that
1545 * those interrupts will be enabled.
1546 */
1547static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1548{
1549 hw->intr_mask |= bit;
1550
1551 if (!hw->intr_blocked)
1552 hw_set_intr(hw, hw->intr_mask);
1553}
1554
1555static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1556{
1557 u32 read_intr;
1558
1559 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1560 hw->intr_set = read_intr | interrupt;
1561 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1562}
1563
1564static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1565{
1566 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1567 *status = *status & hw->intr_set;
1568}
1569
1570static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1571{
1572 if (interrupt)
1573 hw_ena_intr(hw);
1574}
1575
1576/**
1577 * hw_block_intr - block hardware interrupts
1578 *
1579 * This function blocks all interrupts of the hardware and returns the current
1580 * interrupt enable mask so that interrupts can be restored later.
1581 *
1582 * Return the current interrupt enable mask.
1583 */
1584static uint hw_block_intr(struct ksz_hw *hw)
1585{
1586 uint interrupt = 0;
1587
1588 if (!hw->intr_blocked) {
1589 hw_dis_intr(hw);
1590 interrupt = hw->intr_blocked;
1591 }
1592 return interrupt;
1593}
1594
1595/*
1596 * Hardware descriptor routines
1597 */
1598
1599static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1600{
1601 status.rx.hw_owned = 0;
1602 desc->phw->ctrl.data = cpu_to_le32(status.data);
1603}
1604
1605static inline void release_desc(struct ksz_desc *desc)
1606{
1607 desc->sw.ctrl.tx.hw_owned = 1;
1608 if (desc->sw.buf_size != desc->sw.buf.data) {
1609 desc->sw.buf_size = desc->sw.buf.data;
1610 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1611 }
1612 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1613}
1614
1615static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1616{
1617 *desc = &info->ring[info->last];
1618 info->last++;
1619 info->last &= info->mask;
1620 info->avail--;
1621 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1622}
1623
1624static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1625{
1626 desc->phw->addr = cpu_to_le32(addr);
1627}
1628
1629static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1630{
1631 desc->sw.buf.rx.buf_size = len;
1632}
1633
1634static inline void get_tx_pkt(struct ksz_desc_info *info,
1635 struct ksz_desc **desc)
1636{
1637 *desc = &info->ring[info->next];
1638 info->next++;
1639 info->next &= info->mask;
1640 info->avail--;
1641 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1642}
1643
1644static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1645{
1646 desc->phw->addr = cpu_to_le32(addr);
1647}
1648
1649static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1650{
1651 desc->sw.buf.tx.buf_size = len;
1652}
1653
1654/* Switch functions */
1655
1656#define TABLE_READ 0x10
1657#define TABLE_SEL_SHIFT 2
1658
1659#define HW_DELAY(hw, reg) \
1660 do { \
1661 u16 dummy; \
1662 dummy = readw(hw->io + reg); \
1663 } while (0)
1664
1665/**
1666 * sw_r_table - read 4 bytes of data from switch table
1667 * @hw: The hardware instance.
1668 * @table: The table selector.
1669 * @addr: The address of the table entry.
1670 * @data: Buffer to store the read data.
1671 *
1672 * This routine reads 4 bytes of data from the table of the switch.
1673 * Hardware interrupts are disabled to minimize corruption of read data.
1674 */
1675static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1676{
1677 u16 ctrl_addr;
1678 uint interrupt;
1679
1680 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1681
1682 interrupt = hw_block_intr(hw);
1683
1684 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1685 HW_DELAY(hw, KS884X_IACR_OFFSET);
1686 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1687
1688 hw_restore_intr(hw, interrupt);
1689}
1690
1691/**
1692 * sw_w_table_64 - write 8 bytes of data to the switch table
1693 * @hw: The hardware instance.
1694 * @table: The table selector.
1695 * @addr: The address of the table entry.
1696 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1697 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1698 *
1699 * This routine writes 8 bytes of data to the table of the switch.
1700 * Hardware interrupts are disabled to minimize corruption of written data.
1701 */
1702static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1703 u32 data_lo)
1704{
1705 u16 ctrl_addr;
1706 uint interrupt;
1707
1708 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1709
1710 interrupt = hw_block_intr(hw);
1711
1712 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1713 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1714
1715 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1716 HW_DELAY(hw, KS884X_IACR_OFFSET);
1717
1718 hw_restore_intr(hw, interrupt);
1719}
1720
1721/**
1722 * sw_w_sta_mac_table - write to the static MAC table
1723 * @hw: The hardware instance.
1724 * @addr: The address of the table entry.
1725 * @mac_addr: The MAC address.
1726 * @ports: The port members.
1727 * @override: The flag to override the port receive/transmit settings.
1728 * @valid: The flag to indicate entry is valid.
1729 * @use_fid: The flag to indicate the FID is valid.
1730 * @fid: The FID value.
1731 *
1732 * This routine writes an entry of the static MAC table of the switch. It
1733 * calls sw_w_table_64() to write the data.
1734 */
1735static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1736 u8 ports, int override, int valid, int use_fid, u8 fid)
1737{
1738 u32 data_hi;
1739 u32 data_lo;
1740
1741 data_lo = ((u32) mac_addr[2] << 24) |
1742 ((u32) mac_addr[3] << 16) |
1743 ((u32) mac_addr[4] << 8) | mac_addr[5];
1744 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1745 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1746
1747 if (override)
1748 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1749 if (use_fid) {
1750 data_hi |= STATIC_MAC_TABLE_USE_FID;
1751 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1752 }
1753 if (valid)
1754 data_hi |= STATIC_MAC_TABLE_VALID;
1755
1756 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1757}
1758
1759/**
1760 * sw_r_vlan_table - read from the VLAN table
1761 * @hw: The hardware instance.
1762 * @addr: The address of the table entry.
1763 * @vid: Buffer to store the VID.
1764 * @fid: Buffer to store the VID.
1765 * @member: Buffer to store the port membership.
1766 *
1767 * This function reads an entry of the VLAN table of the switch. It calls
1768 * sw_r_table() to get the data.
1769 *
1770 * Return 0 if the entry is valid; otherwise -1.
1771 */
1772static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1773 u8 *member)
1774{
1775 u32 data;
1776
1777 sw_r_table(hw, TABLE_VLAN, addr, &data);
1778 if (data & VLAN_TABLE_VALID) {
1779 *vid = (u16)(data & VLAN_TABLE_VID);
1780 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1781 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1782 VLAN_TABLE_MEMBERSHIP_SHIFT);
1783 return 0;
1784 }
1785 return -1;
1786}
1787
1788/**
1789 * port_r_mib_cnt - read MIB counter
1790 * @hw: The hardware instance.
1791 * @port: The port index.
1792 * @addr: The address of the counter.
1793 * @cnt: Buffer to store the counter.
1794 *
1795 * This routine reads a MIB counter of the port.
1796 * Hardware interrupts are disabled to minimize corruption of read data.
1797 */
1798static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1799{
1800 u32 data;
1801 u16 ctrl_addr;
1802 uint interrupt;
1803 int timeout;
1804
1805 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1806
1807 interrupt = hw_block_intr(hw);
1808
1809 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1810 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1811 HW_DELAY(hw, KS884X_IACR_OFFSET);
1812
1813 for (timeout = 100; timeout > 0; timeout--) {
1814 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1815
1816 if (data & MIB_COUNTER_VALID) {
1817 if (data & MIB_COUNTER_OVERFLOW)
1818 *cnt += MIB_COUNTER_VALUE + 1;
1819 *cnt += data & MIB_COUNTER_VALUE;
1820 break;
1821 }
1822 }
1823
1824 hw_restore_intr(hw, interrupt);
1825}
1826
1827/**
1828 * port_r_mib_pkt - read dropped packet counts
1829 * @hw: The hardware instance.
1830 * @port: The port index.
1831 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1832 *
1833 * This routine reads the dropped packet counts of the port.
1834 * Hardware interrupts are disabled to minimize corruption of read data.
1835 */
1836static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1837{
1838 u32 cur;
1839 u32 data;
1840 u16 ctrl_addr;
1841 uint interrupt;
1842 int index;
1843
1844 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1845 do {
1846 interrupt = hw_block_intr(hw);
1847
1848 ctrl_addr = (u16) index;
1849 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1850 << 8);
1851 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1852 HW_DELAY(hw, KS884X_IACR_OFFSET);
1853 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1854
1855 hw_restore_intr(hw, interrupt);
1856
1857 data &= MIB_PACKET_DROPPED;
1858 cur = *last;
1859 if (data != cur) {
1860 *last = data;
1861 if (data < cur)
1862 data += MIB_PACKET_DROPPED + 1;
1863 data -= cur;
1864 *cnt += data;
1865 }
1866 ++last;
1867 ++cnt;
1868 index -= KS_MIB_PACKET_DROPPED_TX -
1869 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1870 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1871}
1872
1873/**
1874 * port_r_cnt - read MIB counters periodically
1875 * @hw: The hardware instance.
1876 * @port: The port index.
1877 *
1878 * This routine is used to read the counters of the port periodically to avoid
1879 * counter overflow. The hardware should be acquired first before calling this
1880 * routine.
1881 *
1882 * Return non-zero when not all counters not read.
1883 */
1884static int port_r_cnt(struct ksz_hw *hw, int port)
1885{
1886 struct ksz_port_mib *mib = &hw->port_mib[port];
1887
1888 if (mib->mib_start < PORT_COUNTER_NUM)
1889 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1890 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1891 &mib->counter[mib->cnt_ptr]);
1892 ++mib->cnt_ptr;
1893 }
1894 if (hw->mib_cnt > PORT_COUNTER_NUM)
1895 port_r_mib_pkt(hw, port, mib->dropped,
1896 &mib->counter[PORT_COUNTER_NUM]);
1897 mib->cnt_ptr = 0;
1898 return 0;
1899}
1900
1901/**
1902 * port_init_cnt - initialize MIB counter values
1903 * @hw: The hardware instance.
1904 * @port: The port index.
1905 *
1906 * This routine is used to initialize all counters to zero if the hardware
1907 * cannot do it after reset.
1908 */
1909static void port_init_cnt(struct ksz_hw *hw, int port)
1910{
1911 struct ksz_port_mib *mib = &hw->port_mib[port];
1912
1913 mib->cnt_ptr = 0;
1914 if (mib->mib_start < PORT_COUNTER_NUM)
1915 do {
1916 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1917 &mib->counter[mib->cnt_ptr]);
1918 ++mib->cnt_ptr;
1919 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1920 if (hw->mib_cnt > PORT_COUNTER_NUM)
1921 port_r_mib_pkt(hw, port, mib->dropped,
1922 &mib->counter[PORT_COUNTER_NUM]);
1923 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1924 mib->cnt_ptr = 0;
1925}
1926
1927/*
1928 * Port functions
1929 */
1930
1931/**
1932 * port_chk - check port register bits
1933 * @hw: The hardware instance.
1934 * @port: The port index.
1935 * @offset: The offset of the port register.
1936 * @bits: The data bits to check.
1937 *
1938 * This function checks whether the specified bits of the port register are set
1939 * or not.
1940 *
1941 * Return 0 if the bits are not set.
1942 */
1943static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1944{
1945 u32 addr;
1946 u16 data;
1947
1948 PORT_CTRL_ADDR(port, addr);
1949 addr += offset;
1950 data = readw(hw->io + addr);
1951 return (data & bits) == bits;
1952}
1953
1954/**
1955 * port_cfg - set port register bits
1956 * @hw: The hardware instance.
1957 * @port: The port index.
1958 * @offset: The offset of the port register.
1959 * @bits: The data bits to set.
1960 * @set: The flag indicating whether the bits are to be set or not.
1961 *
1962 * This routine sets or resets the specified bits of the port register.
1963 */
1964static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1965 int set)
1966{
1967 u32 addr;
1968 u16 data;
1969
1970 PORT_CTRL_ADDR(port, addr);
1971 addr += offset;
1972 data = readw(hw->io + addr);
1973 if (set)
1974 data |= bits;
1975 else
1976 data &= ~bits;
1977 writew(data, hw->io + addr);
1978}
1979
1980/**
1981 * port_chk_shift - check port bit
1982 * @hw: The hardware instance.
1983 * @port: The port index.
1984 * @offset: The offset of the register.
1985 * @shift: Number of bits to shift.
1986 *
1987 * This function checks whether the specified port is set in the register or
1988 * not.
1989 *
1990 * Return 0 if the port is not set.
1991 */
1992static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1993{
1994 u16 data;
1995 u16 bit = 1 << port;
1996
1997 data = readw(hw->io + addr);
1998 data >>= shift;
1999 return (data & bit) == bit;
2000}
2001
2002/**
2003 * port_cfg_shift - set port bit
2004 * @hw: The hardware instance.
2005 * @port: The port index.
2006 * @offset: The offset of the register.
2007 * @shift: Number of bits to shift.
2008 * @set: The flag indicating whether the port is to be set or not.
2009 *
2010 * This routine sets or resets the specified port in the register.
2011 */
2012static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2013 int set)
2014{
2015 u16 data;
2016 u16 bits = 1 << port;
2017
2018 data = readw(hw->io + addr);
2019 bits <<= shift;
2020 if (set)
2021 data |= bits;
2022 else
2023 data &= ~bits;
2024 writew(data, hw->io + addr);
2025}
2026
2027/**
2028 * port_r8 - read byte from port register
2029 * @hw: The hardware instance.
2030 * @port: The port index.
2031 * @offset: The offset of the port register.
2032 * @data: Buffer to store the data.
2033 *
2034 * This routine reads a byte from the port register.
2035 */
2036static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2037{
2038 u32 addr;
2039
2040 PORT_CTRL_ADDR(port, addr);
2041 addr += offset;
2042 *data = readb(hw->io + addr);
2043}
2044
2045/**
2046 * port_r16 - read word from port register.
2047 * @hw: The hardware instance.
2048 * @port: The port index.
2049 * @offset: The offset of the port register.
2050 * @data: Buffer to store the data.
2051 *
2052 * This routine reads a word from the port register.
2053 */
2054static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2055{
2056 u32 addr;
2057
2058 PORT_CTRL_ADDR(port, addr);
2059 addr += offset;
2060 *data = readw(hw->io + addr);
2061}
2062
2063/**
2064 * port_w16 - write word to port register.
2065 * @hw: The hardware instance.
2066 * @port: The port index.
2067 * @offset: The offset of the port register.
2068 * @data: Data to write.
2069 *
2070 * This routine writes a word to the port register.
2071 */
2072static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2073{
2074 u32 addr;
2075
2076 PORT_CTRL_ADDR(port, addr);
2077 addr += offset;
2078 writew(data, hw->io + addr);
2079}
2080
2081/**
2082 * sw_chk - check switch register bits
2083 * @hw: The hardware instance.
2084 * @addr: The address of the switch register.
2085 * @bits: The data bits to check.
2086 *
2087 * This function checks whether the specified bits of the switch register are
2088 * set or not.
2089 *
2090 * Return 0 if the bits are not set.
2091 */
2092static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2093{
2094 u16 data;
2095
2096 data = readw(hw->io + addr);
2097 return (data & bits) == bits;
2098}
2099
2100/**
2101 * sw_cfg - set switch register bits
2102 * @hw: The hardware instance.
2103 * @addr: The address of the switch register.
2104 * @bits: The data bits to set.
2105 * @set: The flag indicating whether the bits are to be set or not.
2106 *
2107 * This function sets or resets the specified bits of the switch register.
2108 */
2109static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2110{
2111 u16 data;
2112
2113 data = readw(hw->io + addr);
2114 if (set)
2115 data |= bits;
2116 else
2117 data &= ~bits;
2118 writew(data, hw->io + addr);
2119}
2120
2121/* Bandwidth */
2122
2123static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2124{
2125 port_cfg(hw, p,
2126 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2127}
2128
2129static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2130{
2131 return port_chk(hw, p,
2132 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2133}
2134
2135/* Driver set switch broadcast storm protection at 10% rate. */
2136#define BROADCAST_STORM_PROTECTION_RATE 10
2137
2138/* 148,800 frames * 67 ms / 100 */
2139#define BROADCAST_STORM_VALUE 9969
2140
2141/**
2142 * sw_cfg_broad_storm - configure broadcast storm threshold
2143 * @hw: The hardware instance.
2144 * @percent: Broadcast storm threshold in percent of transmit rate.
2145 *
2146 * This routine configures the broadcast storm threshold of the switch.
2147 */
2148static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2149{
2150 u16 data;
2151 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2152
2153 if (value > BROADCAST_STORM_RATE)
2154 value = BROADCAST_STORM_RATE;
2155
2156 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2157 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2158 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2159 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2160}
2161
2162/**
2163 * sw_get_board_storm - get broadcast storm threshold
2164 * @hw: The hardware instance.
2165 * @percent: Buffer to store the broadcast storm threshold percentage.
2166 *
2167 * This routine retrieves the broadcast storm threshold of the switch.
2168 */
2169static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2170{
2171 int num;
2172 u16 data;
2173
2174 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2175 num = (data & BROADCAST_STORM_RATE_HI);
2176 num <<= 8;
2177 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2178 num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE;
2179 *percent = (u8) num;
2180}
2181
2182/**
2183 * sw_dis_broad_storm - disable broadstorm
2184 * @hw: The hardware instance.
2185 * @port: The port index.
2186 *
2187 * This routine disables the broadcast storm limit function of the switch.
2188 */
2189static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2190{
2191 port_cfg_broad_storm(hw, port, 0);
2192}
2193
2194/**
2195 * sw_ena_broad_storm - enable broadcast storm
2196 * @hw: The hardware instance.
2197 * @port: The port index.
2198 *
2199 * This routine enables the broadcast storm limit function of the switch.
2200 */
2201static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2202{
2203 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2204 port_cfg_broad_storm(hw, port, 1);
2205}
2206
2207/**
2208 * sw_init_broad_storm - initialize broadcast storm
2209 * @hw: The hardware instance.
2210 *
2211 * This routine initializes the broadcast storm limit function of the switch.
2212 */
2213static void sw_init_broad_storm(struct ksz_hw *hw)
2214{
2215 int port;
2216
2217 hw->ksz_switch->broad_per = 1;
2218 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2219 for (port = 0; port < TOTAL_PORT_NUM; port++)
2220 sw_dis_broad_storm(hw, port);
2221 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2222}
2223
2224/**
2225 * hw_cfg_broad_storm - configure broadcast storm
2226 * @hw: The hardware instance.
2227 * @percent: Broadcast storm threshold in percent of transmit rate.
2228 *
2229 * This routine configures the broadcast storm threshold of the switch.
2230 * It is called by user functions. The hardware should be acquired first.
2231 */
2232static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2233{
2234 if (percent > 100)
2235 percent = 100;
2236
2237 sw_cfg_broad_storm(hw, percent);
2238 sw_get_broad_storm(hw, &percent);
2239 hw->ksz_switch->broad_per = percent;
2240}
2241
2242/**
2243 * sw_dis_prio_rate - disable switch priority rate
2244 * @hw: The hardware instance.
2245 * @port: The port index.
2246 *
2247 * This routine disables the priority rate function of the switch.
2248 */
2249static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2250{
2251 u32 addr;
2252
2253 PORT_CTRL_ADDR(port, addr);
2254 addr += KS8842_PORT_IN_RATE_OFFSET;
2255 writel(0, hw->io + addr);
2256}
2257
2258/**
2259 * sw_init_prio_rate - initialize switch prioirty rate
2260 * @hw: The hardware instance.
2261 *
2262 * This routine initializes the priority rate function of the switch.
2263 */
2264static void sw_init_prio_rate(struct ksz_hw *hw)
2265{
2266 int port;
2267 int prio;
2268 struct ksz_switch *sw = hw->ksz_switch;
2269
2270 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2271 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2272 sw->port_cfg[port].rx_rate[prio] =
2273 sw->port_cfg[port].tx_rate[prio] = 0;
2274 }
2275 sw_dis_prio_rate(hw, port);
2276 }
2277}
2278
2279/* Communication */
2280
2281static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2282{
2283 port_cfg(hw, p,
2284 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2285}
2286
2287static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2288{
2289 port_cfg(hw, p,
2290 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2291}
2292
2293static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2294{
2295 return port_chk(hw, p,
2296 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2297}
2298
2299static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2300{
2301 return port_chk(hw, p,
2302 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2303}
2304
2305/* Spanning Tree */
2306
2307static inline void port_cfg_dis_learn(struct ksz_hw *hw, int p, int set)
2308{
2309 port_cfg(hw, p,
2310 KS8842_PORT_CTRL_2_OFFSET, PORT_LEARN_DISABLE, set);
2311}
2312
2313static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2314{
2315 port_cfg(hw, p,
2316 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2317}
2318
2319static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2320{
2321 port_cfg(hw, p,
2322 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2323}
2324
2325static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2326{
2327 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2328}
2329
2330static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2331{
2332 if (!(hw->overrides & FAST_AGING)) {
2333 sw_cfg_fast_aging(hw, 1);
2334 mdelay(1);
2335 sw_cfg_fast_aging(hw, 0);
2336 }
2337}
2338
2339/* VLAN */
2340
2341static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2342{
2343 port_cfg(hw, p,
2344 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2345}
2346
2347static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2348{
2349 port_cfg(hw, p,
2350 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2351}
2352
2353static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2354{
2355 return port_chk(hw, p,
2356 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2357}
2358
2359static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2360{
2361 return port_chk(hw, p,
2362 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2363}
2364
2365static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2366{
2367 port_cfg(hw, p,
2368 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2369}
2370
2371static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2372{
2373 port_cfg(hw, p,
2374 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2375}
2376
2377static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2378{
2379 return port_chk(hw, p,
2380 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2381}
2382
2383static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2384{
2385 return port_chk(hw, p,
2386 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2387}
2388
2389/* Mirroring */
2390
2391static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2392{
2393 port_cfg(hw, p,
2394 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2395}
2396
2397static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2398{
2399 port_cfg(hw, p,
2400 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2401}
2402
2403static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2404{
2405 port_cfg(hw, p,
2406 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2407}
2408
2409static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2410{
2411 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2412}
2413
2414static void sw_init_mirror(struct ksz_hw *hw)
2415{
2416 int port;
2417
2418 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2419 port_cfg_mirror_sniffer(hw, port, 0);
2420 port_cfg_mirror_rx(hw, port, 0);
2421 port_cfg_mirror_tx(hw, port, 0);
2422 }
2423 sw_cfg_mirror_rx_tx(hw, 0);
2424}
2425
2426static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2427{
2428 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2429 SWITCH_UNK_DEF_PORT_ENABLE, set);
2430}
2431
2432static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2433{
2434 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2435 SWITCH_UNK_DEF_PORT_ENABLE);
2436}
2437
2438static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2439{
2440 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2441}
2442
2443static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2444{
2445 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2446}
2447
2448/* Priority */
2449
2450static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2451{
2452 port_cfg(hw, p,
2453 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2454}
2455
2456static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2457{
2458 port_cfg(hw, p,
2459 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2460}
2461
2462static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2463{
2464 port_cfg(hw, p,
2465 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2466}
2467
2468static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2469{
2470 port_cfg(hw, p,
2471 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2472}
2473
2474static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2475{
2476 return port_chk(hw, p,
2477 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2478}
2479
2480static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2481{
2482 return port_chk(hw, p,
2483 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2484}
2485
2486static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2487{
2488 return port_chk(hw, p,
2489 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2490}
2491
2492static inline int port_chk_prio(struct ksz_hw *hw, int p)
2493{
2494 return port_chk(hw, p,
2495 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2496}
2497
2498/**
2499 * sw_dis_diffserv - disable switch DiffServ priority
2500 * @hw: The hardware instance.
2501 * @port: The port index.
2502 *
2503 * This routine disables the DiffServ priority function of the switch.
2504 */
2505static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2506{
2507 port_cfg_diffserv(hw, port, 0);
2508}
2509
2510/**
2511 * sw_dis_802_1p - disable switch 802.1p priority
2512 * @hw: The hardware instance.
2513 * @port: The port index.
2514 *
2515 * This routine disables the 802.1p priority function of the switch.
2516 */
2517static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2518{
2519 port_cfg_802_1p(hw, port, 0);
2520}
2521
2522/**
2523 * sw_cfg_replace_null_vid -
2524 * @hw: The hardware instance.
2525 * @set: The flag to disable or enable.
2526 *
2527 */
2528static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2529{
2530 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2531}
2532
2533/**
2534 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2535 * @hw: The hardware instance.
2536 * @port: The port index.
2537 * @set: The flag to disable or enable.
2538 *
2539 * This routine enables the 802.1p priority re-mapping function of the switch.
2540 * That allows 802.1p priority field to be replaced with the port's default
2541 * tag's priority value if the ingress packet's 802.1p priority has a higher
2542 * priority than port's default tag's priority.
2543 */
2544static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2545{
2546 port_cfg_replace_vid(hw, port, set);
2547}
2548
2549/**
2550 * sw_cfg_port_based - configure switch port based priority
2551 * @hw: The hardware instance.
2552 * @port: The port index.
2553 * @prio: The priority to set.
2554 *
2555 * This routine configures the port based priority of the switch.
2556 */
2557static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2558{
2559 u16 data;
2560
2561 if (prio > PORT_BASED_PRIORITY_BASE)
2562 prio = PORT_BASED_PRIORITY_BASE;
2563
2564 hw->ksz_switch->port_cfg[port].port_prio = prio;
2565
2566 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2567 data &= ~PORT_BASED_PRIORITY_MASK;
2568 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2569 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2570}
2571
2572/**
2573 * sw_dis_multi_queue - disable transmit multiple queues
2574 * @hw: The hardware instance.
2575 * @port: The port index.
2576 *
2577 * This routine disables the transmit multiple queues selection of the switch
2578 * port. Only single transmit queue on the port.
2579 */
2580static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2581{
2582 port_cfg_prio(hw, port, 0);
2583}
2584
2585/**
2586 * sw_init_prio - initialize switch priority
2587 * @hw: The hardware instance.
2588 *
2589 * This routine initializes the switch QoS priority functions.
2590 */
2591static void sw_init_prio(struct ksz_hw *hw)
2592{
2593 int port;
2594 int tos;
2595 struct ksz_switch *sw = hw->ksz_switch;
2596
2597 /*
2598 * Init all the 802.1p tag priority value to be assigned to different
2599 * priority queue.
2600 */
2601 sw->p_802_1p[0] = 0;
2602 sw->p_802_1p[1] = 0;
2603 sw->p_802_1p[2] = 1;
2604 sw->p_802_1p[3] = 1;
2605 sw->p_802_1p[4] = 2;
2606 sw->p_802_1p[5] = 2;
2607 sw->p_802_1p[6] = 3;
2608 sw->p_802_1p[7] = 3;
2609
2610 /*
2611 * Init all the DiffServ priority value to be assigned to priority
2612 * queue 0.
2613 */
2614 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2615 sw->diffserv[tos] = 0;
2616
2617 /* All QoS functions disabled. */
2618 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2619 sw_dis_multi_queue(hw, port);
2620 sw_dis_diffserv(hw, port);
2621 sw_dis_802_1p(hw, port);
2622 sw_cfg_replace_vid(hw, port, 0);
2623
2624 sw->port_cfg[port].port_prio = 0;
2625 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2626 }
2627 sw_cfg_replace_null_vid(hw, 0);
2628}
2629
2630/**
2631 * port_get_def_vid - get port default VID.
2632 * @hw: The hardware instance.
2633 * @port: The port index.
2634 * @vid: Buffer to store the VID.
2635 *
2636 * This routine retrieves the default VID of the port.
2637 */
2638static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2639{
2640 u32 addr;
2641
2642 PORT_CTRL_ADDR(port, addr);
2643 addr += KS8842_PORT_CTRL_VID_OFFSET;
2644 *vid = readw(hw->io + addr);
2645}
2646
2647/**
2648 * sw_init_vlan - initialize switch VLAN
2649 * @hw: The hardware instance.
2650 *
2651 * This routine initializes the VLAN function of the switch.
2652 */
2653static void sw_init_vlan(struct ksz_hw *hw)
2654{
2655 int port;
2656 int entry;
2657 struct ksz_switch *sw = hw->ksz_switch;
2658
2659 /* Read 16 VLAN entries from device's VLAN table. */
2660 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2661 sw_r_vlan_table(hw, entry,
2662 &sw->vlan_table[entry].vid,
2663 &sw->vlan_table[entry].fid,
2664 &sw->vlan_table[entry].member);
2665 }
2666
2667 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2668 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2669 sw->port_cfg[port].member = PORT_MASK;
2670 }
2671}
2672
2673/**
2674 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2675 * @hw: The hardware instance.
2676 * @port: The port index.
2677 * @member: The port-based VLAN membership.
2678 *
2679 * This routine configures the port-based VLAN membership of the port.
2680 */
2681static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2682{
2683 u32 addr;
2684 u8 data;
2685
2686 PORT_CTRL_ADDR(port, addr);
2687 addr += KS8842_PORT_CTRL_2_OFFSET;
2688
2689 data = readb(hw->io + addr);
2690 data &= ~PORT_VLAN_MEMBERSHIP;
2691 data |= (member & PORT_MASK);
2692 writeb(data, hw->io + addr);
2693
2694 hw->ksz_switch->port_cfg[port].member = member;
2695}
2696
2697/**
2698 * sw_get_addr - get the switch MAC address.
2699 * @hw: The hardware instance.
2700 * @mac_addr: Buffer to store the MAC address.
2701 *
2702 * This function retrieves the MAC address of the switch.
2703 */
2704static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2705{
2706 int i;
2707
2708 for (i = 0; i < 6; i += 2) {
2709 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2710 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2711 }
2712}
2713
2714/**
2715 * sw_set_addr - configure switch MAC address
2716 * @hw: The hardware instance.
2717 * @mac_addr: The MAC address.
2718 *
2719 * This function configures the MAC address of the switch.
2720 */
2721static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2722{
2723 int i;
2724
2725 for (i = 0; i < 6; i += 2) {
2726 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2727 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2728 }
2729}
2730
2731/**
2732 * sw_set_global_ctrl - set switch global control
2733 * @hw: The hardware instance.
2734 *
2735 * This routine sets the global control of the switch function.
2736 */
2737static void sw_set_global_ctrl(struct ksz_hw *hw)
2738{
2739 u16 data;
2740
2741 /* Enable switch MII flow control. */
2742 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2743 data |= SWITCH_FLOW_CTRL;
2744 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2745
2746 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2747
2748 /* Enable aggressive back off algorithm in half duplex mode. */
2749 data |= SWITCH_AGGR_BACKOFF;
2750
2751 /* Enable automatic fast aging when link changed detected. */
2752 data |= SWITCH_AGING_ENABLE;
2753 data |= SWITCH_LINK_AUTO_AGING;
2754
2755 if (hw->overrides & FAST_AGING)
2756 data |= SWITCH_FAST_AGING;
2757 else
2758 data &= ~SWITCH_FAST_AGING;
2759 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2760
2761 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2762
2763 /* Enable no excessive collision drop. */
2764 data |= NO_EXC_COLLISION_DROP;
2765 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2766}
2767
2768enum {
2769 STP_STATE_DISABLED = 0,
2770 STP_STATE_LISTENING,
2771 STP_STATE_LEARNING,
2772 STP_STATE_FORWARDING,
2773 STP_STATE_BLOCKED,
2774 STP_STATE_SIMPLE
2775};
2776
2777/**
2778 * port_set_stp_state - configure port spanning tree state
2779 * @hw: The hardware instance.
2780 * @port: The port index.
2781 * @state: The spanning tree state.
2782 *
2783 * This routine configures the spanning tree state of the port.
2784 */
2785static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2786{
2787 u16 data;
2788
2789 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2790 switch (state) {
2791 case STP_STATE_DISABLED:
2792 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2793 data |= PORT_LEARN_DISABLE;
2794 break;
2795 case STP_STATE_LISTENING:
2796/*
2797 * No need to turn on transmit because of port direct mode.
2798 * Turning on receive is required if static MAC table is not setup.
2799 */
2800 data &= ~PORT_TX_ENABLE;
2801 data |= PORT_RX_ENABLE;
2802 data |= PORT_LEARN_DISABLE;
2803 break;
2804 case STP_STATE_LEARNING:
2805 data &= ~PORT_TX_ENABLE;
2806 data |= PORT_RX_ENABLE;
2807 data &= ~PORT_LEARN_DISABLE;
2808 break;
2809 case STP_STATE_FORWARDING:
2810 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2811 data &= ~PORT_LEARN_DISABLE;
2812 break;
2813 case STP_STATE_BLOCKED:
2814/*
2815 * Need to setup static MAC table with override to keep receiving BPDU
2816 * messages. See sw_init_stp routine.
2817 */
2818 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2819 data |= PORT_LEARN_DISABLE;
2820 break;
2821 case STP_STATE_SIMPLE:
2822 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2823 data |= PORT_LEARN_DISABLE;
2824 break;
2825 }
2826 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2827 hw->ksz_switch->port_cfg[port].stp_state = state;
2828}
2829
2830#define STP_ENTRY 0
2831#define BROADCAST_ENTRY 1
2832#define BRIDGE_ADDR_ENTRY 2
2833#define IPV6_ADDR_ENTRY 3
2834
2835/**
2836 * sw_clr_sta_mac_table - clear static MAC table
2837 * @hw: The hardware instance.
2838 *
2839 * This routine clears the static MAC table.
2840 */
2841static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2842{
2843 struct ksz_mac_table *entry;
2844 int i;
2845
2846 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2847 entry = &hw->ksz_switch->mac_table[i];
2848 sw_w_sta_mac_table(hw, i,
2849 entry->mac_addr, entry->ports,
2850 entry->override, 0,
2851 entry->use_fid, entry->fid);
2852 }
2853}
2854
2855/**
2856 * sw_init_stp - initialize switch spanning tree support
2857 * @hw: The hardware instance.
2858 *
2859 * This routine initializes the spanning tree support of the switch.
2860 */
2861static void sw_init_stp(struct ksz_hw *hw)
2862{
2863 struct ksz_mac_table *entry;
2864
2865 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2866 entry->mac_addr[0] = 0x01;
2867 entry->mac_addr[1] = 0x80;
2868 entry->mac_addr[2] = 0xC2;
2869 entry->mac_addr[3] = 0x00;
2870 entry->mac_addr[4] = 0x00;
2871 entry->mac_addr[5] = 0x00;
2872 entry->ports = HOST_MASK;
2873 entry->override = 1;
2874 entry->valid = 1;
2875 sw_w_sta_mac_table(hw, STP_ENTRY,
2876 entry->mac_addr, entry->ports,
2877 entry->override, entry->valid,
2878 entry->use_fid, entry->fid);
2879}
2880
2881/**
2882 * sw_block_addr - block certain packets from the host port
2883 * @hw: The hardware instance.
2884 *
2885 * This routine blocks certain packets from reaching to the host port.
2886 */
2887static void sw_block_addr(struct ksz_hw *hw)
2888{
2889 struct ksz_mac_table *entry;
2890 int i;
2891
2892 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2893 entry = &hw->ksz_switch->mac_table[i];
2894 entry->valid = 0;
2895 sw_w_sta_mac_table(hw, i,
2896 entry->mac_addr, entry->ports,
2897 entry->override, entry->valid,
2898 entry->use_fid, entry->fid);
2899 }
2900}
2901
2902#define PHY_LINK_SUPPORT \
2903 (PHY_AUTO_NEG_ASYM_PAUSE | \
2904 PHY_AUTO_NEG_SYM_PAUSE | \
2905 PHY_AUTO_NEG_100BT4 | \
2906 PHY_AUTO_NEG_100BTX_FD | \
2907 PHY_AUTO_NEG_100BTX | \
2908 PHY_AUTO_NEG_10BT_FD | \
2909 PHY_AUTO_NEG_10BT)
2910
2911static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2912{
2913 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2914}
2915
2916static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2917{
2918 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2919}
2920
2921static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2922{
2923 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2924}
2925
2926static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2927{
2928 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2929}
2930
2931static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2932{
2933 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2934}
2935
2936static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2937{
2938 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2939}
2940
2941static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2942{
2943 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2944}
2945
2946static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2947{
2948 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2949}
2950
2951static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2952{
2953 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2954}
2955
2956static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2957{
2958 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2959}
2960
2961static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2962{
2963 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2964}
2965
2966static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2967{
2968 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2969}
2970
2971/**
2972 * hw_r_phy - read data from PHY register
2973 * @hw: The hardware instance.
2974 * @port: Port to read.
2975 * @reg: PHY register to read.
2976 * @val: Buffer to store the read data.
2977 *
2978 * This routine reads data from the PHY register.
2979 */
2980static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2981{
2982 int phy;
2983
2984 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2985 *val = readw(hw->io + phy);
2986}
2987
2988/**
2989 * port_w_phy - write data to PHY register
2990 * @hw: The hardware instance.
2991 * @port: Port to write.
2992 * @reg: PHY register to write.
2993 * @val: Word data to write.
2994 *
2995 * This routine writes data to the PHY register.
2996 */
2997static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2998{
2999 int phy;
3000
3001 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
3002 writew(val, hw->io + phy);
3003}
3004
3005/*
3006 * EEPROM access functions
3007 */
3008
3009#define AT93C_CODE 0
3010#define AT93C_WR_OFF 0x00
3011#define AT93C_WR_ALL 0x10
3012#define AT93C_ER_ALL 0x20
3013#define AT93C_WR_ON 0x30
3014
3015#define AT93C_WRITE 1
3016#define AT93C_READ 2
3017#define AT93C_ERASE 3
3018
3019#define EEPROM_DELAY 4
3020
3021static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3022{
3023 u16 data;
3024
3025 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3026 data &= ~gpio;
3027 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3028}
3029
3030static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3031{
3032 u16 data;
3033
3034 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3035 data |= gpio;
3036 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3037}
3038
3039static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3040{
3041 u16 data;
3042
3043 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3044 return (u8)(data & gpio);
3045}
3046
3047static void eeprom_clk(struct ksz_hw *hw)
3048{
3049 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3050 udelay(EEPROM_DELAY);
3051 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3052 udelay(EEPROM_DELAY);
3053}
3054
3055static u16 spi_r(struct ksz_hw *hw)
3056{
3057 int i;
3058 u16 temp = 0;
3059
3060 for (i = 15; i >= 0; i--) {
3061 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3062 udelay(EEPROM_DELAY);
3063
3064 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3065
3066 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3067 udelay(EEPROM_DELAY);
3068 }
3069 return temp;
3070}
3071
3072static void spi_w(struct ksz_hw *hw, u16 data)
3073{
3074 int i;
3075
3076 for (i = 15; i >= 0; i--) {
3077 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3078 drop_gpio(hw, EEPROM_DATA_OUT);
3079 eeprom_clk(hw);
3080 }
3081}
3082
3083static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3084{
3085 int i;
3086
3087 /* Initial start bit */
3088 raise_gpio(hw, EEPROM_DATA_OUT);
3089 eeprom_clk(hw);
3090
3091 /* AT93C operation */
3092 for (i = 1; i >= 0; i--) {
3093 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3094 drop_gpio(hw, EEPROM_DATA_OUT);
3095 eeprom_clk(hw);
3096 }
3097
3098 /* Address location */
3099 for (i = 5; i >= 0; i--) {
3100 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3101 drop_gpio(hw, EEPROM_DATA_OUT);
3102 eeprom_clk(hw);
3103 }
3104}
3105
3106#define EEPROM_DATA_RESERVED 0
3107#define EEPROM_DATA_MAC_ADDR_0 1
3108#define EEPROM_DATA_MAC_ADDR_1 2
3109#define EEPROM_DATA_MAC_ADDR_2 3
3110#define EEPROM_DATA_SUBSYS_ID 4
3111#define EEPROM_DATA_SUBSYS_VEN_ID 5
3112#define EEPROM_DATA_PM_CAP 6
3113
3114/* User defined EEPROM data */
3115#define EEPROM_DATA_OTHER_MAC_ADDR 9
3116
3117/**
3118 * eeprom_read - read from AT93C46 EEPROM
3119 * @hw: The hardware instance.
3120 * @reg: The register offset.
3121 *
3122 * This function reads a word from the AT93C46 EEPROM.
3123 *
3124 * Return the data value.
3125 */
3126static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3127{
3128 u16 data;
3129
3130 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3131
3132 spi_reg(hw, AT93C_READ, reg);
3133 data = spi_r(hw);
3134
3135 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3136
3137 return data;
3138}
3139
3140/**
3141 * eeprom_write - write to AT93C46 EEPROM
3142 * @hw: The hardware instance.
3143 * @reg: The register offset.
3144 * @data: The data value.
3145 *
3146 * This procedure writes a word to the AT93C46 EEPROM.
3147 */
3148static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3149{
3150 int timeout;
3151
3152 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3153
3154 /* Enable write. */
3155 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3156 drop_gpio(hw, EEPROM_CHIP_SELECT);
3157 udelay(1);
3158
3159 /* Erase the register. */
3160 raise_gpio(hw, EEPROM_CHIP_SELECT);
3161 spi_reg(hw, AT93C_ERASE, reg);
3162 drop_gpio(hw, EEPROM_CHIP_SELECT);
3163 udelay(1);
3164
3165 /* Check operation complete. */
3166 raise_gpio(hw, EEPROM_CHIP_SELECT);
3167 timeout = 8;
3168 mdelay(2);
3169 do {
3170 mdelay(1);
3171 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3172 drop_gpio(hw, EEPROM_CHIP_SELECT);
3173 udelay(1);
3174
3175 /* Write the register. */
3176 raise_gpio(hw, EEPROM_CHIP_SELECT);
3177 spi_reg(hw, AT93C_WRITE, reg);
3178 spi_w(hw, data);
3179 drop_gpio(hw, EEPROM_CHIP_SELECT);
3180 udelay(1);
3181
3182 /* Check operation complete. */
3183 raise_gpio(hw, EEPROM_CHIP_SELECT);
3184 timeout = 8;
3185 mdelay(2);
3186 do {
3187 mdelay(1);
3188 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3189 drop_gpio(hw, EEPROM_CHIP_SELECT);
3190 udelay(1);
3191
3192 /* Disable write. */
3193 raise_gpio(hw, EEPROM_CHIP_SELECT);
3194 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3195
3196 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3197}
3198
3199/*
3200 * Link detection routines
3201 */
3202
3203static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3204{
3205 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3206 switch (port->flow_ctrl) {
3207 case PHY_FLOW_CTRL:
3208 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3209 break;
3210 /* Not supported. */
3211 case PHY_TX_ONLY:
3212 case PHY_RX_ONLY:
3213 default:
3214 break;
3215 }
3216 return ctrl;
3217}
3218
3219static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3220{
3221 u32 rx_cfg;
3222 u32 tx_cfg;
3223
3224 rx_cfg = hw->rx_cfg;
3225 tx_cfg = hw->tx_cfg;
3226 if (rx)
3227 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3228 else
3229 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3230 if (tx)
3231 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3232 else
3233 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3234 if (hw->enabled) {
3235 if (rx_cfg != hw->rx_cfg)
3236 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3237 if (tx_cfg != hw->tx_cfg)
3238 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3239 }
3240}
3241
3242static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3243 u16 local, u16 remote)
3244{
3245 int rx;
3246 int tx;
3247
3248 if (hw->overrides & PAUSE_FLOW_CTRL)
3249 return;
3250
3251 rx = tx = 0;
3252 if (port->force_link)
3253 rx = tx = 1;
3254 if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
3255 if (local & PHY_AUTO_NEG_SYM_PAUSE) {
3256 rx = tx = 1;
3257 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
3258 (local & PHY_AUTO_NEG_PAUSE) ==
3259 PHY_AUTO_NEG_ASYM_PAUSE) {
3260 tx = 1;
3261 }
3262 } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
3263 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
3264 rx = 1;
3265 }
3266 if (!hw->ksz_switch)
3267 set_flow_ctrl(hw, rx, tx);
3268}
3269
3270static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3271 struct ksz_port_info *info, u16 link_status)
3272{
3273 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3274 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3275 u32 cfg = hw->tx_cfg;
3276
3277 /* Disable flow control in the half duplex mode. */
3278 if (1 == info->duplex)
3279 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3280 if (hw->enabled && cfg != hw->tx_cfg)
3281 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3282 }
3283}
3284
3285/**
3286 * port_get_link_speed - get current link status
3287 * @port: The port instance.
3288 *
3289 * This routine reads PHY registers to determine the current link status of the
3290 * switch ports.
3291 */
3292static void port_get_link_speed(struct ksz_port *port)
3293{
3294 uint interrupt;
3295 struct ksz_port_info *info;
3296 struct ksz_port_info *linked = NULL;
3297 struct ksz_hw *hw = port->hw;
3298 u16 data;
3299 u16 status;
3300 u8 local;
3301 u8 remote;
3302 int i;
3303 int p;
3304 int change = 0;
3305
3306 interrupt = hw_block_intr(hw);
3307
3308 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3309 info = &hw->port_info[p];
3310 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3311 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3312
3313 /*
3314 * Link status is changing all the time even when there is no
3315 * cable connection!
3316 */
3317 remote = status & (PORT_AUTO_NEG_COMPLETE |
3318 PORT_STATUS_LINK_GOOD);
3319 local = (u8) data;
3320
3321 /* No change to status. */
3322 if (local == info->advertised && remote == info->partner)
3323 continue;
3324
3325 info->advertised = local;
3326 info->partner = remote;
3327 if (status & PORT_STATUS_LINK_GOOD) {
3328
3329 /* Remember the first linked port. */
3330 if (!linked)
3331 linked = info;
3332
3333 info->tx_rate = 10 * TX_RATE_UNIT;
3334 if (status & PORT_STATUS_SPEED_100MBIT)
3335 info->tx_rate = 100 * TX_RATE_UNIT;
3336
3337 info->duplex = 1;
3338 if (status & PORT_STATUS_FULL_DUPLEX)
3339 info->duplex = 2;
3340
3341 if (media_connected != info->state) {
3342 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3343 &data);
3344 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3345 &status);
3346 determine_flow_ctrl(hw, port, data, status);
3347 if (hw->ksz_switch) {
3348 port_cfg_back_pressure(hw, p,
3349 (1 == info->duplex));
3350 }
3351 change |= 1 << i;
3352 port_cfg_change(hw, port, info, status);
3353 }
3354 info->state = media_connected;
3355 } else {
3356 if (media_disconnected != info->state) {
3357 change |= 1 << i;
3358
3359 /* Indicate the link just goes down. */
3360 hw->port_mib[p].link_down = 1;
3361 }
3362 info->state = media_disconnected;
3363 }
3364 hw->port_mib[p].state = (u8) info->state;
3365 }
3366
3367 if (linked && media_disconnected == port->linked->state)
3368 port->linked = linked;
3369
3370 hw_restore_intr(hw, interrupt);
3371}
3372
3373#define PHY_RESET_TIMEOUT 10
3374
3375/**
3376 * port_set_link_speed - set port speed
3377 * @port: The port instance.
3378 *
3379 * This routine sets the link speed of the switch ports.
3380 */
3381static void port_set_link_speed(struct ksz_port *port)
3382{
3383 struct ksz_port_info *info;
3384 struct ksz_hw *hw = port->hw;
3385 u16 data;
3386 u16 cfg;
3387 u8 status;
3388 int i;
3389 int p;
3390
3391 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3392 info = &hw->port_info[p];
3393
3394 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3395 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3396
3397 cfg = 0;
3398 if (status & PORT_STATUS_LINK_GOOD)
3399 cfg = data;
3400
3401 data |= PORT_AUTO_NEG_ENABLE;
3402 data = advertised_flow_ctrl(port, data);
3403
3404 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3405 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3406
3407 /* Check if manual configuration is specified by the user. */
3408 if (port->speed || port->duplex) {
3409 if (10 == port->speed)
3410 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3411 PORT_AUTO_NEG_100BTX);
3412 else if (100 == port->speed)
3413 data &= ~(PORT_AUTO_NEG_10BT_FD |
3414 PORT_AUTO_NEG_10BT);
3415 if (1 == port->duplex)
3416 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3417 PORT_AUTO_NEG_10BT_FD);
3418 else if (2 == port->duplex)
3419 data &= ~(PORT_AUTO_NEG_100BTX |
3420 PORT_AUTO_NEG_10BT);
3421 }
3422 if (data != cfg) {
3423 data |= PORT_AUTO_NEG_RESTART;
3424 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3425 }
3426 }
3427}
3428
3429/**
3430 * port_force_link_speed - force port speed
3431 * @port: The port instance.
3432 *
3433 * This routine forces the link speed of the switch ports.
3434 */
3435static void port_force_link_speed(struct ksz_port *port)
3436{
3437 struct ksz_hw *hw = port->hw;
3438 u16 data;
3439 int i;
3440 int phy;
3441 int p;
3442
3443 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3444 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3445 hw_r_phy_ctrl(hw, phy, &data);
3446
3447 data &= ~PHY_AUTO_NEG_ENABLE;
3448
3449 if (10 == port->speed)
3450 data &= ~PHY_SPEED_100MBIT;
3451 else if (100 == port->speed)
3452 data |= PHY_SPEED_100MBIT;
3453 if (1 == port->duplex)
3454 data &= ~PHY_FULL_DUPLEX;
3455 else if (2 == port->duplex)
3456 data |= PHY_FULL_DUPLEX;
3457 hw_w_phy_ctrl(hw, phy, data);
3458 }
3459}
3460
3461static void port_set_power_saving(struct ksz_port *port, int enable)
3462{
3463 struct ksz_hw *hw = port->hw;
3464 int i;
3465 int p;
3466
3467 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3468 port_cfg(hw, p,
3469 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3470}
3471
3472/*
3473 * KSZ8841 power management functions
3474 */
3475
3476/**
3477 * hw_chk_wol_pme_status - check PMEN pin
3478 * @hw: The hardware instance.
3479 *
3480 * This function is used to check PMEN pin is asserted.
3481 *
3482 * Return 1 if PMEN pin is asserted; otherwise, 0.
3483 */
3484static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3485{
3486 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3487 struct pci_dev *pdev = hw_priv->pdev;
3488 u16 data;
3489
3490 if (!pdev->pm_cap)
3491 return 0;
3492 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3493 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3494}
3495
3496/**
3497 * hw_clr_wol_pme_status - clear PMEN pin
3498 * @hw: The hardware instance.
3499 *
3500 * This routine is used to clear PME_Status to deassert PMEN pin.
3501 */
3502static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3503{
3504 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3505 struct pci_dev *pdev = hw_priv->pdev;
3506 u16 data;
3507
3508 if (!pdev->pm_cap)
3509 return;
3510
3511 /* Clear PME_Status to deassert PMEN pin. */
3512 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3513 data |= PCI_PM_CTRL_PME_STATUS;
3514 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3515}
3516
3517/**
3518 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3519 * @hw: The hardware instance.
3520 * @set: The flag indicating whether to enable or disable.
3521 *
3522 * This routine is used to enable or disable Wake-on-LAN.
3523 */
3524static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3525{
3526 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3527 struct pci_dev *pdev = hw_priv->pdev;
3528 u16 data;
3529
3530 if (!pdev->pm_cap)
3531 return;
3532 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3533 data &= ~PCI_PM_CTRL_STATE_MASK;
3534 if (set)
3535 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3536 else
3537 data &= ~PCI_PM_CTRL_PME_ENABLE;
3538 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3539}
3540
3541/**
3542 * hw_cfg_wol - configure Wake-on-LAN features
3543 * @hw: The hardware instance.
3544 * @frame: The pattern frame bit.
3545 * @set: The flag indicating whether to enable or disable.
3546 *
3547 * This routine is used to enable or disable certain Wake-on-LAN features.
3548 */
3549static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3550{
3551 u16 data;
3552
3553 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3554 if (set)
3555 data |= frame;
3556 else
3557 data &= ~frame;
3558 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3559}
3560
3561/**
3562 * hw_set_wol_frame - program Wake-on-LAN pattern
3563 * @hw: The hardware instance.
3564 * @i: The frame index.
3565 * @mask_size: The size of the mask.
3566 * @mask: Mask to ignore certain bytes in the pattern.
3567 * @frame_size: The size of the frame.
3568 * @pattern: The frame data.
3569 *
3570 * This routine is used to program Wake-on-LAN pattern.
3571 */
3572static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3573 const u8 *mask, uint frame_size, const u8 *pattern)
3574{
3575 int bits;
3576 int from;
3577 int len;
3578 int to;
3579 u32 crc;
3580 u8 data[64];
3581 u8 val = 0;
3582
3583 if (frame_size > mask_size * 8)
3584 frame_size = mask_size * 8;
3585 if (frame_size > 64)
3586 frame_size = 64;
3587
3588 i *= 0x10;
3589 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3590 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3591
3592 bits = len = from = to = 0;
3593 do {
3594 if (bits) {
3595 if ((val & 1))
3596 data[to++] = pattern[from];
3597 val >>= 1;
3598 ++from;
3599 --bits;
3600 } else {
3601 val = mask[len];
3602 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3603 + len);
3604 ++len;
3605 if (val)
3606 bits = 8;
3607 else
3608 from += 8;
3609 }
3610 } while (from < (int) frame_size);
3611 if (val) {
3612 bits = mask[len - 1];
3613 val <<= (from % 8);
3614 bits &= ~val;
3615 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3616 1);
3617 }
3618 crc = ether_crc(to, data);
3619 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3620}
3621
3622/**
3623 * hw_add_wol_arp - add ARP pattern
3624 * @hw: The hardware instance.
3625 * @ip_addr: The IPv4 address assigned to the device.
3626 *
3627 * This routine is used to add ARP pattern for waking up the host.
3628 */
3629static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3630{
3631 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3632 u8 pattern[42] = {
3633 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3634 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3635 0x08, 0x06,
3636 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3637 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3638 0x00, 0x00, 0x00, 0x00,
3639 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3640 0x00, 0x00, 0x00, 0x00 };
3641
3642 memcpy(&pattern[38], ip_addr, 4);
3643 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3644}
3645
3646/**
3647 * hw_add_wol_bcast - add broadcast pattern
3648 * @hw: The hardware instance.
3649 *
3650 * This routine is used to add broadcast pattern for waking up the host.
3651 */
3652static void hw_add_wol_bcast(struct ksz_hw *hw)
3653{
3654 static const u8 mask[] = { 0x3F };
3655 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3656
3657 hw_set_wol_frame(hw, 2, 1, mask, MAC_ADDR_LEN, pattern);
3658}
3659
3660/**
3661 * hw_add_wol_mcast - add multicast pattern
3662 * @hw: The hardware instance.
3663 *
3664 * This routine is used to add multicast pattern for waking up the host.
3665 *
3666 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3667 * by IPv6 ping command. Note that multicast packets are filtred through the
3668 * multicast hash table, so not all multicast packets can wake up the host.
3669 */
3670static void hw_add_wol_mcast(struct ksz_hw *hw)
3671{
3672 static const u8 mask[] = { 0x3F };
3673 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3674
3675 memcpy(&pattern[3], &hw->override_addr[3], 3);
3676 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3677}
3678
3679/**
3680 * hw_add_wol_ucast - add unicast pattern
3681 * @hw: The hardware instance.
3682 *
3683 * This routine is used to add unicast pattern to wakeup the host.
3684 *
3685 * It is assumed the unicast packet is directed to the device, as the hardware
3686 * can only receive them in normal case.
3687 */
3688static void hw_add_wol_ucast(struct ksz_hw *hw)
3689{
3690 static const u8 mask[] = { 0x3F };
3691
3692 hw_set_wol_frame(hw, 0, 1, mask, MAC_ADDR_LEN, hw->override_addr);
3693}
3694
3695/**
3696 * hw_enable_wol - enable Wake-on-LAN
3697 * @hw: The hardware instance.
3698 * @wol_enable: The Wake-on-LAN settings.
3699 * @net_addr: The IPv4 address assigned to the device.
3700 *
3701 * This routine is used to enable Wake-on-LAN depending on driver settings.
3702 */
3703static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3704{
3705 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3706 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3707 hw_add_wol_ucast(hw);
3708 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3709 hw_add_wol_mcast(hw);
3710 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3711 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3712 hw_add_wol_arp(hw, net_addr);
3713}
3714
3715/**
3716 * hw_init - check driver is correct for the hardware
3717 * @hw: The hardware instance.
3718 *
3719 * This function checks the hardware is correct for this driver and sets the
3720 * hardware up for proper initialization.
3721 *
3722 * Return number of ports or 0 if not right.
3723 */
3724static int hw_init(struct ksz_hw *hw)
3725{
3726 int rc = 0;
3727 u16 data;
3728 u16 revision;
3729
3730 /* Set bus speed to 125MHz. */
3731 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3732
3733 /* Check KSZ884x chip ID. */
3734 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3735
3736 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3737 data &= KS884X_CHIP_ID_MASK_41;
3738 if (REG_CHIP_ID_41 == data)
3739 rc = 1;
3740 else if (REG_CHIP_ID_42 == data)
3741 rc = 2;
3742 else
3743 return 0;
3744
3745 /* Setup hardware features or bug workarounds. */
3746 if (revision <= 1) {
3747 hw->features |= SMALL_PACKET_TX_BUG;
3748 if (1 == rc)
3749 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3750 }
3751 return rc;
3752}
3753
3754/**
3755 * hw_reset - reset the hardware
3756 * @hw: The hardware instance.
3757 *
3758 * This routine resets the hardware.
3759 */
3760static void hw_reset(struct ksz_hw *hw)
3761{
3762 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3763
3764 /* Wait for device to reset. */
3765 mdelay(10);
3766
3767 /* Write 0 to clear device reset. */
3768 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3769}
3770
3771/**
3772 * hw_setup - setup the hardware
3773 * @hw: The hardware instance.
3774 *
3775 * This routine setup the hardware for proper operation.
3776 */
3777static void hw_setup(struct ksz_hw *hw)
3778{
3779#if SET_DEFAULT_LED
3780 u16 data;
3781
3782 /* Change default LED mode. */
3783 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3784 data &= ~LED_MODE;
3785 data |= SET_DEFAULT_LED;
3786 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3787#endif
3788
3789 /* Setup transmit control. */
3790 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3791 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3792
3793 /* Setup receive control. */
3794 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3795 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3796 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3797
3798 /* Hardware cannot handle UDP packet in IP fragments. */
3799 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3800
3801 if (hw->all_multi)
3802 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3803 if (hw->promiscuous)
3804 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3805}
3806
3807/**
3808 * hw_setup_intr - setup interrupt mask
3809 * @hw: The hardware instance.
3810 *
3811 * This routine setup the interrupt mask for proper operation.
3812 */
3813static void hw_setup_intr(struct ksz_hw *hw)
3814{
3815 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3816}
3817
3818static void ksz_check_desc_num(struct ksz_desc_info *info)
3819{
3820#define MIN_DESC_SHIFT 2
3821
3822 int alloc = info->alloc;
3823 int shift;
3824
3825 shift = 0;
3826 while (!(alloc & 1)) {
3827 shift++;
3828 alloc >>= 1;
3829 }
3830 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3831 pr_alert("Hardware descriptor numbers not right!\n");
3832 while (alloc) {
3833 shift++;
3834 alloc >>= 1;
3835 }
3836 if (shift < MIN_DESC_SHIFT)
3837 shift = MIN_DESC_SHIFT;
3838 alloc = 1 << shift;
3839 info->alloc = alloc;
3840 }
3841 info->mask = info->alloc - 1;
3842}
3843
3844static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3845{
3846 int i;
3847 u32 phys = desc_info->ring_phys;
3848 struct ksz_hw_desc *desc = desc_info->ring_virt;
3849 struct ksz_desc *cur = desc_info->ring;
3850 struct ksz_desc *previous = NULL;
3851
3852 for (i = 0; i < desc_info->alloc; i++) {
3853 cur->phw = desc++;
3854 phys += desc_info->size;
3855 previous = cur++;
3856 previous->phw->next = cpu_to_le32(phys);
3857 }
3858 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3859 previous->sw.buf.rx.end_of_ring = 1;
3860 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3861
3862 desc_info->avail = desc_info->alloc;
3863 desc_info->last = desc_info->next = 0;
3864
3865 desc_info->cur = desc_info->ring;
3866}
3867
3868/**
3869 * hw_set_desc_base - set descriptor base addresses
3870 * @hw: The hardware instance.
3871 * @tx_addr: The transmit descriptor base.
3872 * @rx_addr: The receive descriptor base.
3873 *
3874 * This routine programs the descriptor base addresses after reset.
3875 */
3876static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3877{
3878 /* Set base address of Tx/Rx descriptors. */
3879 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3880 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3881}
3882
3883static void hw_reset_pkts(struct ksz_desc_info *info)
3884{
3885 info->cur = info->ring;
3886 info->avail = info->alloc;
3887 info->last = info->next = 0;
3888}
3889
3890static inline void hw_resume_rx(struct ksz_hw *hw)
3891{
3892 writel(DMA_START, hw->io + KS_DMA_RX_START);
3893}
3894
3895/**
3896 * hw_start_rx - start receiving
3897 * @hw: The hardware instance.
3898 *
3899 * This routine starts the receive function of the hardware.
3900 */
3901static void hw_start_rx(struct ksz_hw *hw)
3902{
3903 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3904
3905 /* Notify when the receive stops. */
3906 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3907
3908 writel(DMA_START, hw->io + KS_DMA_RX_START);
3909 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3910 hw->rx_stop++;
3911
3912 /* Variable overflows. */
3913 if (0 == hw->rx_stop)
3914 hw->rx_stop = 2;
3915}
3916
3917/*
3918 * hw_stop_rx - stop receiving
3919 * @hw: The hardware instance.
3920 *
3921 * This routine stops the receive function of the hardware.
3922 */
3923static void hw_stop_rx(struct ksz_hw *hw)
3924{
3925 hw->rx_stop = 0;
3926 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3927 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3928}
3929
3930/**
3931 * hw_start_tx - start transmitting
3932 * @hw: The hardware instance.
3933 *
3934 * This routine starts the transmit function of the hardware.
3935 */
3936static void hw_start_tx(struct ksz_hw *hw)
3937{
3938 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3939}
3940
3941/**
3942 * hw_stop_tx - stop transmitting
3943 * @hw: The hardware instance.
3944 *
3945 * This routine stops the transmit function of the hardware.
3946 */
3947static void hw_stop_tx(struct ksz_hw *hw)
3948{
3949 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3950}
3951
3952/**
3953 * hw_disable - disable hardware
3954 * @hw: The hardware instance.
3955 *
3956 * This routine disables the hardware.
3957 */
3958static void hw_disable(struct ksz_hw *hw)
3959{
3960 hw_stop_rx(hw);
3961 hw_stop_tx(hw);
3962 hw->enabled = 0;
3963}
3964
3965/**
3966 * hw_enable - enable hardware
3967 * @hw: The hardware instance.
3968 *
3969 * This routine enables the hardware.
3970 */
3971static void hw_enable(struct ksz_hw *hw)
3972{
3973 hw_start_tx(hw);
3974 hw_start_rx(hw);
3975 hw->enabled = 1;
3976}
3977
3978/**
3979 * hw_alloc_pkt - allocate enough descriptors for transmission
3980 * @hw: The hardware instance.
3981 * @length: The length of the packet.
3982 * @physical: Number of descriptors required.
3983 *
3984 * This function allocates descriptors for transmission.
3985 *
3986 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3987 */
3988static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3989{
3990 /* Always leave one descriptor free. */
3991 if (hw->tx_desc_info.avail <= 1)
3992 return 0;
3993
3994 /* Allocate a descriptor for transmission and mark it current. */
3995 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3996 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3997
3998 /* Keep track of number of transmit descriptors used so far. */
3999 ++hw->tx_int_cnt;
4000 hw->tx_size += length;
4001
4002 /* Cannot hold on too much data. */
4003 if (hw->tx_size >= MAX_TX_HELD_SIZE)
4004 hw->tx_int_cnt = hw->tx_int_mask + 1;
4005
4006 if (physical > hw->tx_desc_info.avail)
4007 return 1;
4008
4009 return hw->tx_desc_info.avail;
4010}
4011
4012/**
4013 * hw_send_pkt - mark packet for transmission
4014 * @hw: The hardware instance.
4015 *
4016 * This routine marks the packet for transmission in PCI version.
4017 */
4018static void hw_send_pkt(struct ksz_hw *hw)
4019{
4020 struct ksz_desc *cur = hw->tx_desc_info.cur;
4021
4022 cur->sw.buf.tx.last_seg = 1;
4023
4024 /* Interrupt only after specified number of descriptors used. */
4025 if (hw->tx_int_cnt > hw->tx_int_mask) {
4026 cur->sw.buf.tx.intr = 1;
4027 hw->tx_int_cnt = 0;
4028 hw->tx_size = 0;
4029 }
4030
4031 /* KSZ8842 supports port directed transmission. */
4032 cur->sw.buf.tx.dest_port = hw->dst_ports;
4033
4034 release_desc(cur);
4035
4036 writel(0, hw->io + KS_DMA_TX_START);
4037}
4038
4039static int empty_addr(u8 *addr)
4040{
4041 u32 *addr1 = (u32 *) addr;
4042 u16 *addr2 = (u16 *) &addr[4];
4043
4044 return 0 == *addr1 && 0 == *addr2;
4045}
4046
4047/**
4048 * hw_set_addr - set MAC address
4049 * @hw: The hardware instance.
4050 *
4051 * This routine programs the MAC address of the hardware when the address is
4052 * overrided.
4053 */
4054static void hw_set_addr(struct ksz_hw *hw)
4055{
4056 int i;
4057
4058 for (i = 0; i < MAC_ADDR_LEN; i++)
4059 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4060 hw->io + KS884X_ADDR_0_OFFSET + i);
4061
4062 sw_set_addr(hw, hw->override_addr);
4063}
4064
4065/**
4066 * hw_read_addr - read MAC address
4067 * @hw: The hardware instance.
4068 *
4069 * This routine retrieves the MAC address of the hardware.
4070 */
4071static void hw_read_addr(struct ksz_hw *hw)
4072{
4073 int i;
4074
4075 for (i = 0; i < MAC_ADDR_LEN; i++)
4076 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4077 KS884X_ADDR_0_OFFSET + i);
4078
4079 if (!hw->mac_override) {
4080 memcpy(hw->override_addr, hw->perm_addr, MAC_ADDR_LEN);
4081 if (empty_addr(hw->override_addr)) {
4082 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS,
4083 MAC_ADDR_LEN);
4084 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4085 MAC_ADDR_LEN);
4086 hw->override_addr[5] += hw->id;
4087 hw_set_addr(hw);
4088 }
4089 }
4090}
4091
4092static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4093{
4094 int i;
4095 u32 mac_addr_lo;
4096 u32 mac_addr_hi;
4097
4098 mac_addr_hi = 0;
4099 for (i = 0; i < 2; i++) {
4100 mac_addr_hi <<= 8;
4101 mac_addr_hi |= mac_addr[i];
4102 }
4103 mac_addr_hi |= ADD_ADDR_ENABLE;
4104 mac_addr_lo = 0;
4105 for (i = 2; i < 6; i++) {
4106 mac_addr_lo <<= 8;
4107 mac_addr_lo |= mac_addr[i];
4108 }
4109 index *= ADD_ADDR_INCR;
4110
4111 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4112 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4113}
4114
4115static void hw_set_add_addr(struct ksz_hw *hw)
4116{
4117 int i;
4118
4119 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4120 if (empty_addr(hw->address[i]))
4121 writel(0, hw->io + ADD_ADDR_INCR * i +
4122 KS_ADD_ADDR_0_HI);
4123 else
4124 hw_ena_add_addr(hw, i, hw->address[i]);
4125 }
4126}
4127
4128static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4129{
4130 int i;
4131 int j = ADDITIONAL_ENTRIES;
4132
4133 if (!memcmp(hw->override_addr, mac_addr, MAC_ADDR_LEN))
4134 return 0;
4135 for (i = 0; i < hw->addr_list_size; i++) {
4136 if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN))
4137 return 0;
4138 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4139 j = i;
4140 }
4141 if (j < ADDITIONAL_ENTRIES) {
4142 memcpy(hw->address[j], mac_addr, MAC_ADDR_LEN);
4143 hw_ena_add_addr(hw, j, hw->address[j]);
4144 return 0;
4145 }
4146 return -1;
4147}
4148
4149static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4150{
4151 int i;
4152
4153 for (i = 0; i < hw->addr_list_size; i++) {
4154 if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN)) {
4155 memset(hw->address[i], 0, MAC_ADDR_LEN);
4156 writel(0, hw->io + ADD_ADDR_INCR * i +
4157 KS_ADD_ADDR_0_HI);
4158 return 0;
4159 }
4160 }
4161 return -1;
4162}
4163
4164/**
4165 * hw_clr_multicast - clear multicast addresses
4166 * @hw: The hardware instance.
4167 *
4168 * This routine removes all multicast addresses set in the hardware.
4169 */
4170static void hw_clr_multicast(struct ksz_hw *hw)
4171{
4172 int i;
4173
4174 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4175 hw->multi_bits[i] = 0;
4176
4177 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4178 }
4179}
4180
4181/**
4182 * hw_set_grp_addr - set multicast addresses
4183 * @hw: The hardware instance.
4184 *
4185 * This routine programs multicast addresses for the hardware to accept those
4186 * addresses.
4187 */
4188static void hw_set_grp_addr(struct ksz_hw *hw)
4189{
4190 int i;
4191 int index;
4192 int position;
4193 int value;
4194
4195 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4196
4197 for (i = 0; i < hw->multi_list_size; i++) {
4198 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4199 index = position >> 3;
4200 value = 1 << (position & 7);
4201 hw->multi_bits[index] |= (u8) value;
4202 }
4203
4204 for (i = 0; i < HW_MULTICAST_SIZE; i++)
4205 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4206 i);
4207}
4208
4209/**
4210 * hw_set_multicast - enable or disable all multicast receiving
4211 * @hw: The hardware instance.
4212 * @multicast: To turn on or off the all multicast feature.
4213 *
4214 * This routine enables/disables the hardware to accept all multicast packets.
4215 */
4216static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4217{
4218 /* Stop receiving for reconfiguration. */
4219 hw_stop_rx(hw);
4220
4221 if (multicast)
4222 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4223 else
4224 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4225
4226 if (hw->enabled)
4227 hw_start_rx(hw);
4228}
4229
4230/**
4231 * hw_set_promiscuous - enable or disable promiscuous receiving
4232 * @hw: The hardware instance.
4233 * @prom: To turn on or off the promiscuous feature.
4234 *
4235 * This routine enables/disables the hardware to accept all packets.
4236 */
4237static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4238{
4239 /* Stop receiving for reconfiguration. */
4240 hw_stop_rx(hw);
4241
4242 if (prom)
4243 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4244 else
4245 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4246
4247 if (hw->enabled)
4248 hw_start_rx(hw);
4249}
4250
4251/**
4252 * sw_enable - enable the switch
4253 * @hw: The hardware instance.
4254 * @enable: The flag to enable or disable the switch
4255 *
4256 * This routine is used to enable/disable the switch in KSZ8842.
4257 */
4258static void sw_enable(struct ksz_hw *hw, int enable)
4259{
4260 int port;
4261
4262 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4263 if (hw->dev_count > 1) {
4264 /* Set port-base vlan membership with host port. */
4265 sw_cfg_port_base_vlan(hw, port,
4266 HOST_MASK | (1 << port));
4267 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4268 } else {
4269 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4270 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4271 }
4272 }
4273 if (hw->dev_count > 1)
4274 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4275 else
4276 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4277
4278 if (enable)
4279 enable = KS8842_START;
4280 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4281}
4282
4283/**
4284 * sw_setup - setup the switch
4285 * @hw: The hardware instance.
4286 *
4287 * This routine setup the hardware switch engine for default operation.
4288 */
4289static void sw_setup(struct ksz_hw *hw)
4290{
4291 int port;
4292
4293 sw_set_global_ctrl(hw);
4294
4295 /* Enable switch broadcast storm protection at 10% percent rate. */
4296 sw_init_broad_storm(hw);
4297 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4298 for (port = 0; port < SWITCH_PORT_NUM; port++)
4299 sw_ena_broad_storm(hw, port);
4300
4301 sw_init_prio(hw);
4302
4303 sw_init_mirror(hw);
4304
4305 sw_init_prio_rate(hw);
4306
4307 sw_init_vlan(hw);
4308
4309 if (hw->features & STP_SUPPORT)
4310 sw_init_stp(hw);
4311 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4312 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4313 hw->overrides |= PAUSE_FLOW_CTRL;
4314 sw_enable(hw, 1);
4315}
4316
4317/**
4318 * ksz_start_timer - start kernel timer
4319 * @info: Kernel timer information.
4320 * @time: The time tick.
4321 *
4322 * This routine starts the kernel timer after the specified time tick.
4323 */
4324static void ksz_start_timer(struct ksz_timer_info *info, int time)
4325{
4326 info->cnt = 0;
4327 info->timer.expires = jiffies + time;
4328 add_timer(&info->timer);
4329
4330 /* infinity */
4331 info->max = -1;
4332}
4333
4334/**
4335 * ksz_stop_timer - stop kernel timer
4336 * @info: Kernel timer information.
4337 *
4338 * This routine stops the kernel timer.
4339 */
4340static void ksz_stop_timer(struct ksz_timer_info *info)
4341{
4342 if (info->max) {
4343 info->max = 0;
4344 del_timer_sync(&info->timer);
4345 }
4346}
4347
4348static void ksz_init_timer(struct ksz_timer_info *info, int period,
4349 void (*function)(unsigned long), void *data)
4350{
4351 info->max = 0;
4352 info->period = period;
4353 init_timer(&info->timer);
4354 info->timer.function = function;
4355 info->timer.data = (unsigned long) data;
4356}
4357
4358static void ksz_update_timer(struct ksz_timer_info *info)
4359{
4360 ++info->cnt;
4361 if (info->max > 0) {
4362 if (info->cnt < info->max) {
4363 info->timer.expires = jiffies + info->period;
4364 add_timer(&info->timer);
4365 } else
4366 info->max = 0;
4367 } else if (info->max < 0) {
4368 info->timer.expires = jiffies + info->period;
4369 add_timer(&info->timer);
4370 }
4371}
4372
4373/**
4374 * ksz_alloc_soft_desc - allocate software descriptors
4375 * @desc_info: Descriptor information structure.
4376 * @transmit: Indication that descriptors are for transmit.
4377 *
4378 * This local function allocates software descriptors for manipulation in
4379 * memory.
4380 *
4381 * Return 0 if successful.
4382 */
4383static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4384{
4385 desc_info->ring = kmalloc(sizeof(struct ksz_desc) * desc_info->alloc,
4386 GFP_KERNEL);
4387 if (!desc_info->ring)
4388 return 1;
4389 memset((void *) desc_info->ring, 0,
4390 sizeof(struct ksz_desc) * desc_info->alloc);
4391 hw_init_desc(desc_info, transmit);
4392 return 0;
4393}
4394
4395/**
4396 * ksz_alloc_desc - allocate hardware descriptors
4397 * @adapter: Adapter information structure.
4398 *
4399 * This local function allocates hardware descriptors for receiving and
4400 * transmitting.
4401 *
4402 * Return 0 if successful.
4403 */
4404static int ksz_alloc_desc(struct dev_info *adapter)
4405{
4406 struct ksz_hw *hw = &adapter->hw;
4407 int offset;
4408
4409 /* Allocate memory for RX & TX descriptors. */
4410 adapter->desc_pool.alloc_size =
4411 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4412 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4413 DESC_ALIGNMENT;
4414
4415 adapter->desc_pool.alloc_virt =
4416 pci_alloc_consistent(
4417 adapter->pdev, adapter->desc_pool.alloc_size,
4418 &adapter->desc_pool.dma_addr);
4419 if (adapter->desc_pool.alloc_virt == NULL) {
4420 adapter->desc_pool.alloc_size = 0;
4421 return 1;
4422 }
4423 memset(adapter->desc_pool.alloc_virt, 0, adapter->desc_pool.alloc_size);
4424
4425 /* Align to the next cache line boundary. */
4426 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4427 (DESC_ALIGNMENT -
4428 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4429 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4430 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4431
4432 /* Allocate receive/transmit descriptors. */
4433 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4434 adapter->desc_pool.virt;
4435 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4436 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4437 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4438 (adapter->desc_pool.virt + offset);
4439 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4440
4441 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4442 return 1;
4443 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4444 return 1;
4445
4446 return 0;
4447}
4448
4449/**
4450 * free_dma_buf - release DMA buffer resources
4451 * @adapter: Adapter information structure.
4452 *
4453 * This routine is just a helper function to release the DMA buffer resources.
4454 */
4455static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4456 int direction)
4457{
4458 pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction);
4459 dev_kfree_skb(dma_buf->skb);
4460 dma_buf->skb = NULL;
4461 dma_buf->dma = 0;
4462}
4463
4464/**
4465 * ksz_init_rx_buffers - initialize receive descriptors
4466 * @adapter: Adapter information structure.
4467 *
4468 * This routine initializes DMA buffers for receiving.
4469 */
4470static void ksz_init_rx_buffers(struct dev_info *adapter)
4471{
4472 int i;
4473 struct ksz_desc *desc;
4474 struct ksz_dma_buf *dma_buf;
4475 struct ksz_hw *hw = &adapter->hw;
4476 struct ksz_desc_info *info = &hw->rx_desc_info;
4477
4478 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4479 get_rx_pkt(info, &desc);
4480
4481 dma_buf = DMA_BUFFER(desc);
4482 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4483 free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE);
4484 dma_buf->len = adapter->mtu;
4485 if (!dma_buf->skb)
4486 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4487 if (dma_buf->skb && !dma_buf->dma) {
4488 dma_buf->skb->dev = adapter->dev;
4489 dma_buf->dma = pci_map_single(
4490 adapter->pdev,
4491 skb_tail_pointer(dma_buf->skb),
4492 dma_buf->len,
4493 PCI_DMA_FROMDEVICE);
4494 }
4495
4496 /* Set descriptor. */
4497 set_rx_buf(desc, dma_buf->dma);
4498 set_rx_len(desc, dma_buf->len);
4499 release_desc(desc);
4500 }
4501}
4502
4503/**
4504 * ksz_alloc_mem - allocate memory for hardware descriptors
4505 * @adapter: Adapter information structure.
4506 *
4507 * This function allocates memory for use by hardware descriptors for receiving
4508 * and transmitting.
4509 *
4510 * Return 0 if successful.
4511 */
4512static int ksz_alloc_mem(struct dev_info *adapter)
4513{
4514 struct ksz_hw *hw = &adapter->hw;
4515
4516 /* Determine the number of receive and transmit descriptors. */
4517 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4518 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4519
4520 /* Determine how many descriptors to skip transmit interrupt. */
4521 hw->tx_int_cnt = 0;
4522 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4523 if (hw->tx_int_mask > 8)
4524 hw->tx_int_mask = 8;
4525 while (hw->tx_int_mask) {
4526 hw->tx_int_cnt++;
4527 hw->tx_int_mask >>= 1;
4528 }
4529 if (hw->tx_int_cnt) {
4530 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4531 hw->tx_int_cnt = 0;
4532 }
4533
4534 /* Determine the descriptor size. */
4535 hw->rx_desc_info.size =
4536 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4537 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4538 hw->tx_desc_info.size =
4539 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4540 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4541 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4542 pr_alert("Hardware descriptor size not right!\n");
4543 ksz_check_desc_num(&hw->rx_desc_info);
4544 ksz_check_desc_num(&hw->tx_desc_info);
4545
4546 /* Allocate descriptors. */
4547 if (ksz_alloc_desc(adapter))
4548 return 1;
4549
4550 return 0;
4551}
4552
4553/**
4554 * ksz_free_desc - free software and hardware descriptors
4555 * @adapter: Adapter information structure.
4556 *
4557 * This local routine frees the software and hardware descriptors allocated by
4558 * ksz_alloc_desc().
4559 */
4560static void ksz_free_desc(struct dev_info *adapter)
4561{
4562 struct ksz_hw *hw = &adapter->hw;
4563
4564 /* Reset descriptor. */
4565 hw->rx_desc_info.ring_virt = NULL;
4566 hw->tx_desc_info.ring_virt = NULL;
4567 hw->rx_desc_info.ring_phys = 0;
4568 hw->tx_desc_info.ring_phys = 0;
4569
4570 /* Free memory. */
4571 if (adapter->desc_pool.alloc_virt)
4572 pci_free_consistent(
4573 adapter->pdev,
4574 adapter->desc_pool.alloc_size,
4575 adapter->desc_pool.alloc_virt,
4576 adapter->desc_pool.dma_addr);
4577
4578 /* Reset resource pool. */
4579 adapter->desc_pool.alloc_size = 0;
4580 adapter->desc_pool.alloc_virt = NULL;
4581
4582 kfree(hw->rx_desc_info.ring);
4583 hw->rx_desc_info.ring = NULL;
4584 kfree(hw->tx_desc_info.ring);
4585 hw->tx_desc_info.ring = NULL;
4586}
4587
4588/**
4589 * ksz_free_buffers - free buffers used in the descriptors
4590 * @adapter: Adapter information structure.
4591 * @desc_info: Descriptor information structure.
4592 *
4593 * This local routine frees buffers used in the DMA buffers.
4594 */
4595static void ksz_free_buffers(struct dev_info *adapter,
4596 struct ksz_desc_info *desc_info, int direction)
4597{
4598 int i;
4599 struct ksz_dma_buf *dma_buf;
4600 struct ksz_desc *desc = desc_info->ring;
4601
4602 for (i = 0; i < desc_info->alloc; i++) {
4603 dma_buf = DMA_BUFFER(desc);
4604 if (dma_buf->skb)
4605 free_dma_buf(adapter, dma_buf, direction);
4606 desc++;
4607 }
4608}
4609
4610/**
4611 * ksz_free_mem - free all resources used by descriptors
4612 * @adapter: Adapter information structure.
4613 *
4614 * This local routine frees all the resources allocated by ksz_alloc_mem().
4615 */
4616static void ksz_free_mem(struct dev_info *adapter)
4617{
4618 /* Free transmit buffers. */
4619 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4620 PCI_DMA_TODEVICE);
4621
4622 /* Free receive buffers. */
4623 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4624 PCI_DMA_FROMDEVICE);
4625
4626 /* Free descriptors. */
4627 ksz_free_desc(adapter);
4628}
4629
4630static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4631 u64 *counter)
4632{
4633 int i;
4634 int mib;
4635 int port;
4636 struct ksz_port_mib *port_mib;
4637
4638 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4639 for (i = 0, port = first; i < cnt; i++, port++) {
4640 port_mib = &hw->port_mib[port];
4641 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4642 counter[mib] += port_mib->counter[mib];
4643 }
4644}
4645
4646/**
4647 * send_packet - send packet
4648 * @skb: Socket buffer.
4649 * @dev: Network device.
4650 *
4651 * This routine is used to send a packet out to the network.
4652 */
4653static void send_packet(struct sk_buff *skb, struct net_device *dev)
4654{
4655 struct ksz_desc *desc;
4656 struct ksz_desc *first;
4657 struct dev_priv *priv = netdev_priv(dev);
4658 struct dev_info *hw_priv = priv->adapter;
4659 struct ksz_hw *hw = &hw_priv->hw;
4660 struct ksz_desc_info *info = &hw->tx_desc_info;
4661 struct ksz_dma_buf *dma_buf;
4662 int len;
4663 int last_frag = skb_shinfo(skb)->nr_frags;
4664
4665 /*
4666 * KSZ8842 with multiple device interfaces needs to be told which port
4667 * to send.
4668 */
4669 if (hw->dev_count > 1)
4670 hw->dst_ports = 1 << priv->port.first_port;
4671
4672 /* Hardware will pad the length to 60. */
4673 len = skb->len;
4674
4675 /* Remember the very first descriptor. */
4676 first = info->cur;
4677 desc = first;
4678
4679 dma_buf = DMA_BUFFER(desc);
4680 if (last_frag) {
4681 int frag;
4682 skb_frag_t *this_frag;
4683
4684 dma_buf->len = skb_headlen(skb);
4685
4686 dma_buf->dma = pci_map_single(
4687 hw_priv->pdev, skb->data, dma_buf->len,
4688 PCI_DMA_TODEVICE);
4689 set_tx_buf(desc, dma_buf->dma);
4690 set_tx_len(desc, dma_buf->len);
4691
4692 frag = 0;
4693 do {
4694 this_frag = &skb_shinfo(skb)->frags[frag];
4695
4696 /* Get a new descriptor. */
4697 get_tx_pkt(info, &desc);
4698
4699 /* Keep track of descriptors used so far. */
4700 ++hw->tx_int_cnt;
4701
4702 dma_buf = DMA_BUFFER(desc);
4703 dma_buf->len = this_frag->size;
4704
4705 dma_buf->dma = pci_map_single(
4706 hw_priv->pdev,
4707 page_address(this_frag->page) +
4708 this_frag->page_offset,
4709 dma_buf->len,
4710 PCI_DMA_TODEVICE);
4711 set_tx_buf(desc, dma_buf->dma);
4712 set_tx_len(desc, dma_buf->len);
4713
4714 frag++;
4715 if (frag == last_frag)
4716 break;
4717
4718 /* Do not release the last descriptor here. */
4719 release_desc(desc);
4720 } while (1);
4721
4722 /* current points to the last descriptor. */
4723 info->cur = desc;
4724
4725 /* Release the first descriptor. */
4726 release_desc(first);
4727 } else {
4728 dma_buf->len = len;
4729
4730 dma_buf->dma = pci_map_single(
4731 hw_priv->pdev, skb->data, dma_buf->len,
4732 PCI_DMA_TODEVICE);
4733 set_tx_buf(desc, dma_buf->dma);
4734 set_tx_len(desc, dma_buf->len);
4735 }
4736
4737 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4738 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4739 (desc)->sw.buf.tx.csum_gen_udp = 1;
4740 }
4741
4742 /*
4743 * The last descriptor holds the packet so that it can be returned to
4744 * network subsystem after all descriptors are transmitted.
4745 */
4746 dma_buf->skb = skb;
4747
4748 hw_send_pkt(hw);
4749
4750 /* Update transmit statistics. */
4751 dev->stats.tx_packets++;
4752 dev->stats.tx_bytes += len;
4753}
4754
4755/**
4756 * transmit_cleanup - clean up transmit descriptors
4757 * @dev: Network device.
4758 *
4759 * This routine is called to clean up the transmitted buffers.
4760 */
4761static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4762{
4763 int last;
4764 union desc_stat status;
4765 struct ksz_hw *hw = &hw_priv->hw;
4766 struct ksz_desc_info *info = &hw->tx_desc_info;
4767 struct ksz_desc *desc;
4768 struct ksz_dma_buf *dma_buf;
4769 struct net_device *dev = NULL;
4770
4771 spin_lock(&hw_priv->hwlock);
4772 last = info->last;
4773
4774 while (info->avail < info->alloc) {
4775 /* Get next descriptor which is not hardware owned. */
4776 desc = &info->ring[last];
4777 status.data = le32_to_cpu(desc->phw->ctrl.data);
4778 if (status.tx.hw_owned) {
4779 if (normal)
4780 break;
4781 else
4782 reset_desc(desc, status);
4783 }
4784
4785 dma_buf = DMA_BUFFER(desc);
4786 pci_unmap_single(
4787 hw_priv->pdev, dma_buf->dma, dma_buf->len,
4788 PCI_DMA_TODEVICE);
4789
4790 /* This descriptor contains the last buffer in the packet. */
4791 if (dma_buf->skb) {
4792 dev = dma_buf->skb->dev;
4793
4794 /* Release the packet back to network subsystem. */
4795 dev_kfree_skb_irq(dma_buf->skb);
4796 dma_buf->skb = NULL;
4797 }
4798
4799 /* Free the transmitted descriptor. */
4800 last++;
4801 last &= info->mask;
4802 info->avail++;
4803 }
4804 info->last = last;
4805 spin_unlock(&hw_priv->hwlock);
4806
4807 /* Notify the network subsystem that the packet has been sent. */
4808 if (dev)
4809 dev->trans_start = jiffies;
4810}
4811
4812/**
4813 * transmit_done - transmit done processing
4814 * @dev: Network device.
4815 *
4816 * This routine is called when the transmit interrupt is triggered, indicating
4817 * either a packet is sent successfully or there are transmit errors.
4818 */
4819static void tx_done(struct dev_info *hw_priv)
4820{
4821 struct ksz_hw *hw = &hw_priv->hw;
4822 int port;
4823
4824 transmit_cleanup(hw_priv, 1);
4825
4826 for (port = 0; port < hw->dev_count; port++) {
4827 struct net_device *dev = hw->port_info[port].pdev;
4828
4829 if (netif_running(dev) && netif_queue_stopped(dev))
4830 netif_wake_queue(dev);
4831 }
4832}
4833
4834static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4835{
4836 skb->dev = old->dev;
4837 skb->protocol = old->protocol;
4838 skb->ip_summed = old->ip_summed;
4839 skb->csum = old->csum;
4840 skb_set_network_header(skb, ETH_HLEN);
4841
4842 dev_kfree_skb(old);
4843}
4844
4845/**
4846 * netdev_tx - send out packet
4847 * @skb: Socket buffer.
4848 * @dev: Network device.
4849 *
4850 * This function is used by the upper network layer to send out a packet.
4851 *
4852 * Return 0 if successful; otherwise an error code indicating failure.
4853 */
4854static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4855{
4856 struct dev_priv *priv = netdev_priv(dev);
4857 struct dev_info *hw_priv = priv->adapter;
4858 struct ksz_hw *hw = &hw_priv->hw;
4859 int left;
4860 int num = 1;
4861 int rc = 0;
4862
4863 if (hw->features & SMALL_PACKET_TX_BUG) {
4864 struct sk_buff *org_skb = skb;
4865
4866 if (skb->len <= 48) {
4867 if (skb_end_pointer(skb) - skb->data >= 50) {
4868 memset(&skb->data[skb->len], 0, 50 - skb->len);
4869 skb->len = 50;
4870 } else {
4871 skb = dev_alloc_skb(50);
4872 if (!skb)
4873 return NETDEV_TX_BUSY;
4874 memcpy(skb->data, org_skb->data, org_skb->len);
4875 memset(&skb->data[org_skb->len], 0,
4876 50 - org_skb->len);
4877 skb->len = 50;
4878 copy_old_skb(org_skb, skb);
4879 }
4880 }
4881 }
4882
4883 spin_lock_irq(&hw_priv->hwlock);
4884
4885 num = skb_shinfo(skb)->nr_frags + 1;
4886 left = hw_alloc_pkt(hw, skb->len, num);
4887 if (left) {
4888 if (left < num ||
4889 ((CHECKSUM_PARTIAL == skb->ip_summed) &&
4890 (ETH_P_IPV6 == htons(skb->protocol)))) {
4891 struct sk_buff *org_skb = skb;
4892
4893 skb = dev_alloc_skb(org_skb->len);
4894 if (!skb) {
4895 rc = NETDEV_TX_BUSY;
4896 goto unlock;
4897 }
4898 skb_copy_and_csum_dev(org_skb, skb->data);
4899 org_skb->ip_summed = CHECKSUM_NONE;
4900 skb->len = org_skb->len;
4901 copy_old_skb(org_skb, skb);
4902 }
4903 send_packet(skb, dev);
4904 if (left <= num)
4905 netif_stop_queue(dev);
4906 } else {
4907 /* Stop the transmit queue until packet is allocated. */
4908 netif_stop_queue(dev);
4909 rc = NETDEV_TX_BUSY;
4910 }
4911unlock:
4912 spin_unlock_irq(&hw_priv->hwlock);
4913
4914 return rc;
4915}
4916
4917/**
4918 * netdev_tx_timeout - transmit timeout processing
4919 * @dev: Network device.
4920 *
4921 * This routine is called when the transmit timer expires. That indicates the
4922 * hardware is not running correctly because transmit interrupts are not
4923 * triggered to free up resources so that the transmit routine can continue
4924 * sending out packets. The hardware is reset to correct the problem.
4925 */
4926static void netdev_tx_timeout(struct net_device *dev)
4927{
4928 static unsigned long last_reset;
4929
4930 struct dev_priv *priv = netdev_priv(dev);
4931 struct dev_info *hw_priv = priv->adapter;
4932 struct ksz_hw *hw = &hw_priv->hw;
4933 int port;
4934
4935 if (hw->dev_count > 1) {
4936 /*
4937 * Only reset the hardware if time between calls is long
4938 * enough.
4939 */
4940 if (jiffies - last_reset <= dev->watchdog_timeo)
4941 hw_priv = NULL;
4942 }
4943
4944 last_reset = jiffies;
4945 if (hw_priv) {
4946 hw_dis_intr(hw);
4947 hw_disable(hw);
4948
4949 transmit_cleanup(hw_priv, 0);
4950 hw_reset_pkts(&hw->rx_desc_info);
4951 hw_reset_pkts(&hw->tx_desc_info);
4952 ksz_init_rx_buffers(hw_priv);
4953
4954 hw_reset(hw);
4955
4956 hw_set_desc_base(hw,
4957 hw->tx_desc_info.ring_phys,
4958 hw->rx_desc_info.ring_phys);
4959 hw_set_addr(hw);
4960 if (hw->all_multi)
4961 hw_set_multicast(hw, hw->all_multi);
4962 else if (hw->multi_list_size)
4963 hw_set_grp_addr(hw);
4964
4965 if (hw->dev_count > 1) {
4966 hw_set_add_addr(hw);
4967 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4968 struct net_device *port_dev;
4969
4970 port_set_stp_state(hw, port,
4971 STP_STATE_DISABLED);
4972
4973 port_dev = hw->port_info[port].pdev;
4974 if (netif_running(port_dev))
4975 port_set_stp_state(hw, port,
4976 STP_STATE_SIMPLE);
4977 }
4978 }
4979
4980 hw_enable(hw);
4981 hw_ena_intr(hw);
4982 }
4983
4984 dev->trans_start = jiffies;
4985 netif_wake_queue(dev);
4986}
4987
4988static inline void csum_verified(struct sk_buff *skb)
4989{
4990 unsigned short protocol;
4991 struct iphdr *iph;
4992
4993 protocol = skb->protocol;
4994 skb_reset_network_header(skb);
4995 iph = (struct iphdr *) skb_network_header(skb);
4996 if (protocol == htons(ETH_P_8021Q)) {
4997 protocol = iph->tot_len;
4998 skb_set_network_header(skb, VLAN_HLEN);
4999 iph = (struct iphdr *) skb_network_header(skb);
5000 }
5001 if (protocol == htons(ETH_P_IP)) {
5002 if (iph->protocol == IPPROTO_TCP)
5003 skb->ip_summed = CHECKSUM_UNNECESSARY;
5004 }
5005}
5006
5007static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
5008 struct ksz_desc *desc, union desc_stat status)
5009{
5010 int packet_len;
5011 struct dev_priv *priv = netdev_priv(dev);
5012 struct dev_info *hw_priv = priv->adapter;
5013 struct ksz_dma_buf *dma_buf;
5014 struct sk_buff *skb;
5015 int rx_status;
5016
5017 /* Received length includes 4-byte CRC. */
5018 packet_len = status.rx.frame_len - 4;
5019
5020 dma_buf = DMA_BUFFER(desc);
5021 pci_dma_sync_single_for_cpu(
5022 hw_priv->pdev, dma_buf->dma, packet_len + 4,
5023 PCI_DMA_FROMDEVICE);
5024
5025 do {
5026 /* skb->data != skb->head */
5027 skb = dev_alloc_skb(packet_len + 2);
5028 if (!skb) {
5029 dev->stats.rx_dropped++;
5030 return -ENOMEM;
5031 }
5032
5033 /*
5034 * Align socket buffer in 4-byte boundary for better
5035 * performance.
5036 */
5037 skb_reserve(skb, 2);
5038
5039 memcpy(skb_put(skb, packet_len),
5040 dma_buf->skb->data, packet_len);
5041 } while (0);
5042
5043 skb->protocol = eth_type_trans(skb, dev);
5044
5045 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5046 csum_verified(skb);
5047
5048 /* Update receive statistics. */
5049 dev->stats.rx_packets++;
5050 dev->stats.rx_bytes += packet_len;
5051
5052 /* Notify upper layer for received packet. */
5053 rx_status = netif_rx(skb);
5054
5055 return 0;
5056}
5057
5058static int dev_rcv_packets(struct dev_info *hw_priv)
5059{
5060 int next;
5061 union desc_stat status;
5062 struct ksz_hw *hw = &hw_priv->hw;
5063 struct net_device *dev = hw->port_info[0].pdev;
5064 struct ksz_desc_info *info = &hw->rx_desc_info;
5065 int left = info->alloc;
5066 struct ksz_desc *desc;
5067 int received = 0;
5068
5069 next = info->next;
5070 while (left--) {
5071 /* Get next descriptor which is not hardware owned. */
5072 desc = &info->ring[next];
5073 status.data = le32_to_cpu(desc->phw->ctrl.data);
5074 if (status.rx.hw_owned)
5075 break;
5076
5077 /* Status valid only when last descriptor bit is set. */
5078 if (status.rx.last_desc && status.rx.first_desc) {
5079 if (rx_proc(dev, hw, desc, status))
5080 goto release_packet;
5081 received++;
5082 }
5083
5084release_packet:
5085 release_desc(desc);
5086 next++;
5087 next &= info->mask;
5088 }
5089 info->next = next;
5090
5091 return received;
5092}
5093
5094static int port_rcv_packets(struct dev_info *hw_priv)
5095{
5096 int next;
5097 union desc_stat status;
5098 struct ksz_hw *hw = &hw_priv->hw;
5099 struct net_device *dev = hw->port_info[0].pdev;
5100 struct ksz_desc_info *info = &hw->rx_desc_info;
5101 int left = info->alloc;
5102 struct ksz_desc *desc;
5103 int received = 0;
5104
5105 next = info->next;
5106 while (left--) {
5107 /* Get next descriptor which is not hardware owned. */
5108 desc = &info->ring[next];
5109 status.data = le32_to_cpu(desc->phw->ctrl.data);
5110 if (status.rx.hw_owned)
5111 break;
5112
5113 if (hw->dev_count > 1) {
5114 /* Get received port number. */
5115 int p = HW_TO_DEV_PORT(status.rx.src_port);
5116
5117 dev = hw->port_info[p].pdev;
5118 if (!netif_running(dev))
5119 goto release_packet;
5120 }
5121
5122 /* Status valid only when last descriptor bit is set. */
5123 if (status.rx.last_desc && status.rx.first_desc) {
5124 if (rx_proc(dev, hw, desc, status))
5125 goto release_packet;
5126 received++;
5127 }
5128
5129release_packet:
5130 release_desc(desc);
5131 next++;
5132 next &= info->mask;
5133 }
5134 info->next = next;
5135
5136 return received;
5137}
5138
5139static int dev_rcv_special(struct dev_info *hw_priv)
5140{
5141 int next;
5142 union desc_stat status;
5143 struct ksz_hw *hw = &hw_priv->hw;
5144 struct net_device *dev = hw->port_info[0].pdev;
5145 struct ksz_desc_info *info = &hw->rx_desc_info;
5146 int left = info->alloc;
5147 struct ksz_desc *desc;
5148 int received = 0;
5149
5150 next = info->next;
5151 while (left--) {
5152 /* Get next descriptor which is not hardware owned. */
5153 desc = &info->ring[next];
5154 status.data = le32_to_cpu(desc->phw->ctrl.data);
5155 if (status.rx.hw_owned)
5156 break;
5157
5158 if (hw->dev_count > 1) {
5159 /* Get received port number. */
5160 int p = HW_TO_DEV_PORT(status.rx.src_port);
5161
5162 dev = hw->port_info[p].pdev;
5163 if (!netif_running(dev))
5164 goto release_packet;
5165 }
5166
5167 /* Status valid only when last descriptor bit is set. */
5168 if (status.rx.last_desc && status.rx.first_desc) {
5169 /*
5170 * Receive without error. With receive errors
5171 * disabled, packets with receive errors will be
5172 * dropped, so no need to check the error bit.
5173 */
5174 if (!status.rx.error || (status.data &
5175 KS_DESC_RX_ERROR_COND) ==
5176 KS_DESC_RX_ERROR_TOO_LONG) {
5177 if (rx_proc(dev, hw, desc, status))
5178 goto release_packet;
5179 received++;
5180 } else {
5181 struct dev_priv *priv = netdev_priv(dev);
5182
5183 /* Update receive error statistics. */
5184 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5185 }
5186 }
5187
5188release_packet:
5189 release_desc(desc);
5190 next++;
5191 next &= info->mask;
5192 }
5193 info->next = next;
5194
5195 return received;
5196}
5197
5198static void rx_proc_task(unsigned long data)
5199{
5200 struct dev_info *hw_priv = (struct dev_info *) data;
5201 struct ksz_hw *hw = &hw_priv->hw;
5202
5203 if (!hw->enabled)
5204 return;
5205 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5206
5207 /* In case receive process is suspended because of overrun. */
5208 hw_resume_rx(hw);
5209
5210 /* tasklets are interruptible. */
5211 spin_lock_irq(&hw_priv->hwlock);
5212 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5213 spin_unlock_irq(&hw_priv->hwlock);
5214 } else {
5215 hw_ack_intr(hw, KS884X_INT_RX);
5216 tasklet_schedule(&hw_priv->rx_tasklet);
5217 }
5218}
5219
5220static void tx_proc_task(unsigned long data)
5221{
5222 struct dev_info *hw_priv = (struct dev_info *) data;
5223 struct ksz_hw *hw = &hw_priv->hw;
5224
5225 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5226
5227 tx_done(hw_priv);
5228
5229 /* tasklets are interruptible. */
5230 spin_lock_irq(&hw_priv->hwlock);
5231 hw_turn_on_intr(hw, KS884X_INT_TX);
5232 spin_unlock_irq(&hw_priv->hwlock);
5233}
5234
5235static inline void handle_rx_stop(struct ksz_hw *hw)
5236{
5237 /* Receive just has been stopped. */
5238 if (0 == hw->rx_stop)
5239 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5240 else if (hw->rx_stop > 1) {
5241 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5242 hw_start_rx(hw);
5243 } else {
5244 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5245 hw->rx_stop = 0;
5246 }
5247 } else
5248 /* Receive just has been started. */
5249 hw->rx_stop++;
5250}
5251
5252/**
5253 * netdev_intr - interrupt handling
5254 * @irq: Interrupt number.
5255 * @dev_id: Network device.
5256 *
5257 * This function is called by upper network layer to signal interrupt.
5258 *
5259 * Return IRQ_HANDLED if interrupt is handled.
5260 */
5261static irqreturn_t netdev_intr(int irq, void *dev_id)
5262{
5263 uint int_enable = 0;
5264 struct net_device *dev = (struct net_device *) dev_id;
5265 struct dev_priv *priv = netdev_priv(dev);
5266 struct dev_info *hw_priv = priv->adapter;
5267 struct ksz_hw *hw = &hw_priv->hw;
5268
5269 hw_read_intr(hw, &int_enable);
5270
5271 /* Not our interrupt! */
5272 if (!int_enable)
5273 return IRQ_NONE;
5274
5275 do {
5276 hw_ack_intr(hw, int_enable);
5277 int_enable &= hw->intr_mask;
5278
5279 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5280 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5281 tasklet_schedule(&hw_priv->tx_tasklet);
5282 }
5283
5284 if (likely(int_enable & KS884X_INT_RX)) {
5285 hw_dis_intr_bit(hw, KS884X_INT_RX);
5286 tasklet_schedule(&hw_priv->rx_tasklet);
5287 }
5288
5289 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5290 dev->stats.rx_fifo_errors++;
5291 hw_resume_rx(hw);
5292 }
5293
5294 if (unlikely(int_enable & KS884X_INT_PHY)) {
5295 struct ksz_port *port = &priv->port;
5296
5297 hw->features |= LINK_INT_WORKING;
5298 port_get_link_speed(port);
5299 }
5300
5301 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5302 handle_rx_stop(hw);
5303 break;
5304 }
5305
5306 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5307 u32 data;
5308
5309 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5310 pr_info("Tx stopped\n");
5311 data = readl(hw->io + KS_DMA_TX_CTRL);
5312 if (!(data & DMA_TX_ENABLE))
5313 pr_info("Tx disabled\n");
5314 break;
5315 }
5316 } while (0);
5317
5318 hw_ena_intr(hw);
5319
5320 return IRQ_HANDLED;
5321}
5322
5323/*
5324 * Linux network device functions
5325 */
5326
5327static unsigned long next_jiffies;
5328
5329#ifdef CONFIG_NET_POLL_CONTROLLER
5330static void netdev_netpoll(struct net_device *dev)
5331{
5332 struct dev_priv *priv = netdev_priv(dev);
5333 struct dev_info *hw_priv = priv->adapter;
5334
5335 hw_dis_intr(&hw_priv->hw);
5336 netdev_intr(dev->irq, dev);
5337}
5338#endif
5339
5340static void bridge_change(struct ksz_hw *hw)
5341{
5342 int port;
5343 u8 member;
5344 struct ksz_switch *sw = hw->ksz_switch;
5345
5346 /* No ports in forwarding state. */
5347 if (!sw->member) {
5348 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5349 sw_block_addr(hw);
5350 }
5351 for (port = 0; port < SWITCH_PORT_NUM; port++) {
5352 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5353 member = HOST_MASK | sw->member;
5354 else
5355 member = HOST_MASK | (1 << port);
5356 if (member != sw->port_cfg[port].member)
5357 sw_cfg_port_base_vlan(hw, port, member);
5358 }
5359}
5360
5361/**
5362 * netdev_close - close network device
5363 * @dev: Network device.
5364 *
5365 * This function process the close operation of network device. This is caused
5366 * by the user command "ifconfig ethX down."
5367 *
5368 * Return 0 if successful; otherwise an error code indicating failure.
5369 */
5370static int netdev_close(struct net_device *dev)
5371{
5372 struct dev_priv *priv = netdev_priv(dev);
5373 struct dev_info *hw_priv = priv->adapter;
5374 struct ksz_port *port = &priv->port;
5375 struct ksz_hw *hw = &hw_priv->hw;
5376 int pi;
5377
5378 netif_stop_queue(dev);
5379
5380 ksz_stop_timer(&priv->monitor_timer_info);
5381
5382 /* Need to shut the port manually in multiple device interfaces mode. */
5383 if (hw->dev_count > 1) {
5384 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5385
5386 /* Port is closed. Need to change bridge setting. */
5387 if (hw->features & STP_SUPPORT) {
5388 pi = 1 << port->first_port;
5389 if (hw->ksz_switch->member & pi) {
5390 hw->ksz_switch->member &= ~pi;
5391 bridge_change(hw);
5392 }
5393 }
5394 }
5395 if (port->first_port > 0)
5396 hw_del_addr(hw, dev->dev_addr);
5397 if (!hw_priv->wol_enable)
5398 port_set_power_saving(port, true);
5399
5400 if (priv->multicast)
5401 --hw->all_multi;
5402 if (priv->promiscuous)
5403 --hw->promiscuous;
5404
5405 hw_priv->opened--;
5406 if (!(hw_priv->opened)) {
5407 ksz_stop_timer(&hw_priv->mib_timer_info);
5408 flush_work(&hw_priv->mib_read);
5409
5410 hw_dis_intr(hw);
5411 hw_disable(hw);
5412 hw_clr_multicast(hw);
5413
5414 /* Delay for receive task to stop scheduling itself. */
5415 msleep(2000 / HZ);
5416
5417 tasklet_disable(&hw_priv->rx_tasklet);
5418 tasklet_disable(&hw_priv->tx_tasklet);
5419 free_irq(dev->irq, hw_priv->dev);
5420
5421 transmit_cleanup(hw_priv, 0);
5422 hw_reset_pkts(&hw->rx_desc_info);
5423 hw_reset_pkts(&hw->tx_desc_info);
5424
5425 /* Clean out static MAC table when the switch is shutdown. */
5426 if (hw->features & STP_SUPPORT)
5427 sw_clr_sta_mac_table(hw);
5428 }
5429
5430 return 0;
5431}
5432
5433static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5434{
5435 if (hw->ksz_switch) {
5436 u32 data;
5437
5438 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5439 if (hw->features & RX_HUGE_FRAME)
5440 data |= SWITCH_HUGE_PACKET;
5441 else
5442 data &= ~SWITCH_HUGE_PACKET;
5443 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5444 }
5445 if (hw->features & RX_HUGE_FRAME) {
5446 hw->rx_cfg |= DMA_RX_ERROR;
5447 hw_priv->dev_rcv = dev_rcv_special;
5448 } else {
5449 hw->rx_cfg &= ~DMA_RX_ERROR;
5450 if (hw->dev_count > 1)
5451 hw_priv->dev_rcv = port_rcv_packets;
5452 else
5453 hw_priv->dev_rcv = dev_rcv_packets;
5454 }
5455}
5456
5457static int prepare_hardware(struct net_device *dev)
5458{
5459 struct dev_priv *priv = netdev_priv(dev);
5460 struct dev_info *hw_priv = priv->adapter;
5461 struct ksz_hw *hw = &hw_priv->hw;
5462 int rc = 0;
5463
5464 /* Remember the network device that requests interrupts. */
5465 hw_priv->dev = dev;
5466 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5467 if (rc)
5468 return rc;
5469 tasklet_enable(&hw_priv->rx_tasklet);
5470 tasklet_enable(&hw_priv->tx_tasklet);
5471
5472 hw->promiscuous = 0;
5473 hw->all_multi = 0;
5474 hw->multi_list_size = 0;
5475
5476 hw_reset(hw);
5477
5478 hw_set_desc_base(hw,
5479 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5480 hw_set_addr(hw);
5481 hw_cfg_huge_frame(hw_priv, hw);
5482 ksz_init_rx_buffers(hw_priv);
5483 return 0;
5484}
5485
5486static void set_media_state(struct net_device *dev, int media_state)
5487{
5488 struct dev_priv *priv = netdev_priv(dev);
5489
5490 if (media_state == priv->media_state)
5491 netif_carrier_on(dev);
5492 else
5493 netif_carrier_off(dev);
5494 netif_info(priv, link, dev, "link %s\n",
5495 media_state == priv->media_state ? "on" : "off");
5496}
5497
5498/**
5499 * netdev_open - open network device
5500 * @dev: Network device.
5501 *
5502 * This function process the open operation of network device. This is caused
5503 * by the user command "ifconfig ethX up."
5504 *
5505 * Return 0 if successful; otherwise an error code indicating failure.
5506 */
5507static int netdev_open(struct net_device *dev)
5508{
5509 struct dev_priv *priv = netdev_priv(dev);
5510 struct dev_info *hw_priv = priv->adapter;
5511 struct ksz_hw *hw = &hw_priv->hw;
5512 struct ksz_port *port = &priv->port;
5513 int i;
5514 int p;
5515 int rc = 0;
5516
5517 priv->multicast = 0;
5518 priv->promiscuous = 0;
5519
5520 /* Reset device statistics. */
5521 memset(&dev->stats, 0, sizeof(struct net_device_stats));
5522 memset((void *) port->counter, 0,
5523 (sizeof(u64) * OID_COUNTER_LAST));
5524
5525 if (!(hw_priv->opened)) {
5526 rc = prepare_hardware(dev);
5527 if (rc)
5528 return rc;
5529 for (i = 0; i < hw->mib_port_cnt; i++) {
5530 if (next_jiffies < jiffies)
5531 next_jiffies = jiffies + HZ * 2;
5532 else
5533 next_jiffies += HZ * 1;
5534 hw_priv->counter[i].time = next_jiffies;
5535 hw->port_mib[i].state = media_disconnected;
5536 port_init_cnt(hw, i);
5537 }
5538 if (hw->ksz_switch)
5539 hw->port_mib[HOST_PORT].state = media_connected;
5540 else {
5541 hw_add_wol_bcast(hw);
5542 hw_cfg_wol_pme(hw, 0);
5543 hw_clr_wol_pme_status(&hw_priv->hw);
5544 }
5545 }
5546 port_set_power_saving(port, false);
5547
5548 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5549 /*
5550 * Initialize to invalid value so that link detection
5551 * is done.
5552 */
5553 hw->port_info[p].partner = 0xFF;
5554 hw->port_info[p].state = media_disconnected;
5555 }
5556
5557 /* Need to open the port in multiple device interfaces mode. */
5558 if (hw->dev_count > 1) {
5559 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5560 if (port->first_port > 0)
5561 hw_add_addr(hw, dev->dev_addr);
5562 }
5563
5564 port_get_link_speed(port);
5565 if (port->force_link)
5566 port_force_link_speed(port);
5567 else
5568 port_set_link_speed(port);
5569
5570 if (!(hw_priv->opened)) {
5571 hw_setup_intr(hw);
5572 hw_enable(hw);
5573 hw_ena_intr(hw);
5574
5575 if (hw->mib_port_cnt)
5576 ksz_start_timer(&hw_priv->mib_timer_info,
5577 hw_priv->mib_timer_info.period);
5578 }
5579
5580 hw_priv->opened++;
5581
5582 ksz_start_timer(&priv->monitor_timer_info,
5583 priv->monitor_timer_info.period);
5584
5585 priv->media_state = port->linked->state;
5586
5587 set_media_state(dev, media_connected);
5588 netif_start_queue(dev);
5589
5590 return 0;
5591}
5592
5593/* RX errors = rx_errors */
5594/* RX dropped = rx_dropped */
5595/* RX overruns = rx_fifo_errors */
5596/* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5597/* TX errors = tx_errors */
5598/* TX dropped = tx_dropped */
5599/* TX overruns = tx_fifo_errors */
5600/* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5601/* collisions = collisions */
5602
5603/**
5604 * netdev_query_statistics - query network device statistics
5605 * @dev: Network device.
5606 *
5607 * This function returns the statistics of the network device. The device
5608 * needs not be opened.
5609 *
5610 * Return network device statistics.
5611 */
5612static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5613{
5614 struct dev_priv *priv = netdev_priv(dev);
5615 struct ksz_port *port = &priv->port;
5616 struct ksz_hw *hw = &priv->adapter->hw;
5617 struct ksz_port_mib *mib;
5618 int i;
5619 int p;
5620
5621 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5622 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5623
5624 /* Reset to zero to add count later. */
5625 dev->stats.multicast = 0;
5626 dev->stats.collisions = 0;
5627 dev->stats.rx_length_errors = 0;
5628 dev->stats.rx_crc_errors = 0;
5629 dev->stats.rx_frame_errors = 0;
5630 dev->stats.tx_window_errors = 0;
5631
5632 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5633 mib = &hw->port_mib[p];
5634
5635 dev->stats.multicast += (unsigned long)
5636 mib->counter[MIB_COUNTER_RX_MULTICAST];
5637
5638 dev->stats.collisions += (unsigned long)
5639 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5640
5641 dev->stats.rx_length_errors += (unsigned long)(
5642 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5643 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5644 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5645 mib->counter[MIB_COUNTER_RX_JABBER]);
5646 dev->stats.rx_crc_errors += (unsigned long)
5647 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5648 dev->stats.rx_frame_errors += (unsigned long)(
5649 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5650 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5651
5652 dev->stats.tx_window_errors += (unsigned long)
5653 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5654 }
5655
5656 return &dev->stats;
5657}
5658
5659/**
5660 * netdev_set_mac_address - set network device MAC address
5661 * @dev: Network device.
5662 * @addr: Buffer of MAC address.
5663 *
5664 * This function is used to set the MAC address of the network device.
5665 *
5666 * Return 0 to indicate success.
5667 */
5668static int netdev_set_mac_address(struct net_device *dev, void *addr)
5669{
5670 struct dev_priv *priv = netdev_priv(dev);
5671 struct dev_info *hw_priv = priv->adapter;
5672 struct ksz_hw *hw = &hw_priv->hw;
5673 struct sockaddr *mac = addr;
5674 uint interrupt;
5675
5676 if (priv->port.first_port > 0)
5677 hw_del_addr(hw, dev->dev_addr);
5678 else {
5679 hw->mac_override = 1;
5680 memcpy(hw->override_addr, mac->sa_data, MAC_ADDR_LEN);
5681 }
5682
5683 memcpy(dev->dev_addr, mac->sa_data, MAX_ADDR_LEN);
5684
5685 interrupt = hw_block_intr(hw);
5686
5687 if (priv->port.first_port > 0)
5688 hw_add_addr(hw, dev->dev_addr);
5689 else
5690 hw_set_addr(hw);
5691 hw_restore_intr(hw, interrupt);
5692
5693 return 0;
5694}
5695
5696static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5697 struct ksz_hw *hw, int promiscuous)
5698{
5699 if (promiscuous != priv->promiscuous) {
5700 u8 prev_state = hw->promiscuous;
5701
5702 if (promiscuous)
5703 ++hw->promiscuous;
5704 else
5705 --hw->promiscuous;
5706 priv->promiscuous = promiscuous;
5707
5708 /* Turn on/off promiscuous mode. */
5709 if (hw->promiscuous <= 1 && prev_state <= 1)
5710 hw_set_promiscuous(hw, hw->promiscuous);
5711
5712 /*
5713 * Port is not in promiscuous mode, meaning it is released
5714 * from the bridge.
5715 */
5716 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5717 (dev->priv_flags & IFF_BRIDGE_PORT)) {
5718 struct ksz_switch *sw = hw->ksz_switch;
5719 int port = priv->port.first_port;
5720
5721 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5722 port = 1 << port;
5723 if (sw->member & port) {
5724 sw->member &= ~port;
5725 bridge_change(hw);
5726 }
5727 }
5728 }
5729}
5730
5731static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5732 int multicast)
5733{
5734 if (multicast != priv->multicast) {
5735 u8 all_multi = hw->all_multi;
5736
5737 if (multicast)
5738 ++hw->all_multi;
5739 else
5740 --hw->all_multi;
5741 priv->multicast = multicast;
5742
5743 /* Turn on/off all multicast mode. */
5744 if (hw->all_multi <= 1 && all_multi <= 1)
5745 hw_set_multicast(hw, hw->all_multi);
5746 }
5747}
5748
5749/**
5750 * netdev_set_rx_mode
5751 * @dev: Network device.
5752 *
5753 * This routine is used to set multicast addresses or put the network device
5754 * into promiscuous mode.
5755 */
5756static void netdev_set_rx_mode(struct net_device *dev)
5757{
5758 struct dev_priv *priv = netdev_priv(dev);
5759 struct dev_info *hw_priv = priv->adapter;
5760 struct ksz_hw *hw = &hw_priv->hw;
5761 struct netdev_hw_addr *ha;
5762 int multicast = (dev->flags & IFF_ALLMULTI);
5763
5764 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5765
5766 if (hw_priv->hw.dev_count > 1)
5767 multicast |= (dev->flags & IFF_MULTICAST);
5768 dev_set_multicast(priv, hw, multicast);
5769
5770 /* Cannot use different hashes in multiple device interfaces mode. */
5771 if (hw_priv->hw.dev_count > 1)
5772 return;
5773
5774 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5775 int i = 0;
5776
5777 /* List too big to support so turn on all multicast mode. */
5778 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5779 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5780 hw->multi_list_size = MAX_MULTICAST_LIST;
5781 ++hw->all_multi;
5782 hw_set_multicast(hw, hw->all_multi);
5783 }
5784 return;
5785 }
5786
5787 netdev_for_each_mc_addr(ha, dev) {
5788 if (i >= MAX_MULTICAST_LIST)
5789 break;
5790 memcpy(hw->multi_list[i++], ha->addr, MAC_ADDR_LEN);
5791 }
5792 hw->multi_list_size = (u8) i;
5793 hw_set_grp_addr(hw);
5794 } else {
5795 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5796 --hw->all_multi;
5797 hw_set_multicast(hw, hw->all_multi);
5798 }
5799 hw->multi_list_size = 0;
5800 hw_clr_multicast(hw);
5801 }
5802}
5803
5804static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5805{
5806 struct dev_priv *priv = netdev_priv(dev);
5807 struct dev_info *hw_priv = priv->adapter;
5808 struct ksz_hw *hw = &hw_priv->hw;
5809 int hw_mtu;
5810
5811 if (netif_running(dev))
5812 return -EBUSY;
5813
5814 /* Cannot use different MTU in multiple device interfaces mode. */
5815 if (hw->dev_count > 1)
5816 if (dev != hw_priv->dev)
5817 return 0;
5818 if (new_mtu < 60)
5819 return -EINVAL;
5820
5821 if (dev->mtu != new_mtu) {
5822 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5823 if (hw_mtu > MAX_RX_BUF_SIZE)
5824 return -EINVAL;
5825 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5826 hw->features |= RX_HUGE_FRAME;
5827 hw_mtu = MAX_RX_BUF_SIZE;
5828 } else {
5829 hw->features &= ~RX_HUGE_FRAME;
5830 hw_mtu = REGULAR_RX_BUF_SIZE;
5831 }
5832 hw_mtu = (hw_mtu + 3) & ~3;
5833 hw_priv->mtu = hw_mtu;
5834 dev->mtu = new_mtu;
5835 }
5836 return 0;
5837}
5838
5839/**
5840 * netdev_ioctl - I/O control processing
5841 * @dev: Network device.
5842 * @ifr: Interface request structure.
5843 * @cmd: I/O control code.
5844 *
5845 * This function is used to process I/O control calls.
5846 *
5847 * Return 0 to indicate success.
5848 */
5849static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5850{
5851 struct dev_priv *priv = netdev_priv(dev);
5852 struct dev_info *hw_priv = priv->adapter;
5853 struct ksz_hw *hw = &hw_priv->hw;
5854 struct ksz_port *port = &priv->port;
5855 int rc;
5856 int result = 0;
5857 struct mii_ioctl_data *data = if_mii(ifr);
5858
5859 if (down_interruptible(&priv->proc_sem))
5860 return -ERESTARTSYS;
5861
5862 /* assume success */
5863 rc = 0;
5864 switch (cmd) {
5865 /* Get address of MII PHY in use. */
5866 case SIOCGMIIPHY:
5867 data->phy_id = priv->id;
5868
5869 /* Fallthrough... */
5870
5871 /* Read MII PHY register. */
5872 case SIOCGMIIREG:
5873 if (data->phy_id != priv->id || data->reg_num >= 6)
5874 result = -EIO;
5875 else
5876 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5877 &data->val_out);
5878 break;
5879
5880 /* Write MII PHY register. */
5881 case SIOCSMIIREG:
5882 if (!capable(CAP_NET_ADMIN))
5883 result = -EPERM;
5884 else if (data->phy_id != priv->id || data->reg_num >= 6)
5885 result = -EIO;
5886 else
5887 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5888 data->val_in);
5889 break;
5890
5891 default:
5892 result = -EOPNOTSUPP;
5893 }
5894
5895 up(&priv->proc_sem);
5896
5897 return result;
5898}
5899
5900/*
5901 * MII support
5902 */
5903
5904/**
5905 * mdio_read - read PHY register
5906 * @dev: Network device.
5907 * @phy_id: The PHY id.
5908 * @reg_num: The register number.
5909 *
5910 * This function returns the PHY register value.
5911 *
5912 * Return the register value.
5913 */
5914static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5915{
5916 struct dev_priv *priv = netdev_priv(dev);
5917 struct ksz_port *port = &priv->port;
5918 struct ksz_hw *hw = port->hw;
5919 u16 val_out;
5920
5921 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5922 return val_out;
5923}
5924
5925/**
5926 * mdio_write - set PHY register
5927 * @dev: Network device.
5928 * @phy_id: The PHY id.
5929 * @reg_num: The register number.
5930 * @val: The register value.
5931 *
5932 * This procedure sets the PHY register value.
5933 */
5934static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5935{
5936 struct dev_priv *priv = netdev_priv(dev);
5937 struct ksz_port *port = &priv->port;
5938 struct ksz_hw *hw = port->hw;
5939 int i;
5940 int pi;
5941
5942 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5943 hw_w_phy(hw, pi, reg_num << 1, val);
5944}
5945
5946/*
5947 * ethtool support
5948 */
5949
5950#define EEPROM_SIZE 0x40
5951
5952static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5953
5954#define ADVERTISED_ALL \
5955 (ADVERTISED_10baseT_Half | \
5956 ADVERTISED_10baseT_Full | \
5957 ADVERTISED_100baseT_Half | \
5958 ADVERTISED_100baseT_Full)
5959
5960/* These functions use the MII functions in mii.c. */
5961
5962/**
5963 * netdev_get_settings - get network device settings
5964 * @dev: Network device.
5965 * @cmd: Ethtool command.
5966 *
5967 * This function queries the PHY and returns its state in the ethtool command.
5968 *
5969 * Return 0 if successful; otherwise an error code.
5970 */
5971static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5972{
5973 struct dev_priv *priv = netdev_priv(dev);
5974 struct dev_info *hw_priv = priv->adapter;
5975
5976 mutex_lock(&hw_priv->lock);
5977 mii_ethtool_gset(&priv->mii_if, cmd);
5978 cmd->advertising |= SUPPORTED_TP;
5979 mutex_unlock(&hw_priv->lock);
5980
5981 /* Save advertised settings for workaround in next function. */
5982 priv->advertising = cmd->advertising;
5983 return 0;
5984}
5985
5986/**
5987 * netdev_set_settings - set network device settings
5988 * @dev: Network device.
5989 * @cmd: Ethtool command.
5990 *
5991 * This function sets the PHY according to the ethtool command.
5992 *
5993 * Return 0 if successful; otherwise an error code.
5994 */
5995static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5996{
5997 struct dev_priv *priv = netdev_priv(dev);
5998 struct dev_info *hw_priv = priv->adapter;
5999 struct ksz_port *port = &priv->port;
6000 u32 speed = ethtool_cmd_speed(cmd);
6001 int rc;
6002
6003 /*
6004 * ethtool utility does not change advertised setting if auto
6005 * negotiation is not specified explicitly.
6006 */
6007 if (cmd->autoneg && priv->advertising == cmd->advertising) {
6008 cmd->advertising |= ADVERTISED_ALL;
6009 if (10 == speed)
6010 cmd->advertising &=
6011 ~(ADVERTISED_100baseT_Full |
6012 ADVERTISED_100baseT_Half);
6013 else if (100 == speed)
6014 cmd->advertising &=
6015 ~(ADVERTISED_10baseT_Full |
6016 ADVERTISED_10baseT_Half);
6017 if (0 == cmd->duplex)
6018 cmd->advertising &=
6019 ~(ADVERTISED_100baseT_Full |
6020 ADVERTISED_10baseT_Full);
6021 else if (1 == cmd->duplex)
6022 cmd->advertising &=
6023 ~(ADVERTISED_100baseT_Half |
6024 ADVERTISED_10baseT_Half);
6025 }
6026 mutex_lock(&hw_priv->lock);
6027 if (cmd->autoneg &&
6028 (cmd->advertising & ADVERTISED_ALL) ==
6029 ADVERTISED_ALL) {
6030 port->duplex = 0;
6031 port->speed = 0;
6032 port->force_link = 0;
6033 } else {
6034 port->duplex = cmd->duplex + 1;
6035 if (1000 != speed)
6036 port->speed = speed;
6037 if (cmd->autoneg)
6038 port->force_link = 0;
6039 else
6040 port->force_link = 1;
6041 }
6042 rc = mii_ethtool_sset(&priv->mii_if, cmd);
6043 mutex_unlock(&hw_priv->lock);
6044 return rc;
6045}
6046
6047/**
6048 * netdev_nway_reset - restart auto-negotiation
6049 * @dev: Network device.
6050 *
6051 * This function restarts the PHY for auto-negotiation.
6052 *
6053 * Return 0 if successful; otherwise an error code.
6054 */
6055static int netdev_nway_reset(struct net_device *dev)
6056{
6057 struct dev_priv *priv = netdev_priv(dev);
6058 struct dev_info *hw_priv = priv->adapter;
6059 int rc;
6060
6061 mutex_lock(&hw_priv->lock);
6062 rc = mii_nway_restart(&priv->mii_if);
6063 mutex_unlock(&hw_priv->lock);
6064 return rc;
6065}
6066
6067/**
6068 * netdev_get_link - get network device link status
6069 * @dev: Network device.
6070 *
6071 * This function gets the link status from the PHY.
6072 *
6073 * Return true if PHY is linked and false otherwise.
6074 */
6075static u32 netdev_get_link(struct net_device *dev)
6076{
6077 struct dev_priv *priv = netdev_priv(dev);
6078 int rc;
6079
6080 rc = mii_link_ok(&priv->mii_if);
6081 return rc;
6082}
6083
6084/**
6085 * netdev_get_drvinfo - get network driver information
6086 * @dev: Network device.
6087 * @info: Ethtool driver info data structure.
6088 *
6089 * This procedure returns the driver information.
6090 */
6091static void netdev_get_drvinfo(struct net_device *dev,
6092 struct ethtool_drvinfo *info)
6093{
6094 struct dev_priv *priv = netdev_priv(dev);
6095 struct dev_info *hw_priv = priv->adapter;
6096
6097 strcpy(info->driver, DRV_NAME);
6098 strcpy(info->version, DRV_VERSION);
6099 strcpy(info->bus_info, pci_name(hw_priv->pdev));
6100}
6101
6102/**
6103 * netdev_get_regs_len - get length of register dump
6104 * @dev: Network device.
6105 *
6106 * This function returns the length of the register dump.
6107 *
6108 * Return length of the register dump.
6109 */
6110static struct hw_regs {
6111 int start;
6112 int end;
6113} hw_regs_range[] = {
6114 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
6115 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
6116 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6117 { KS884X_SIDER_P, KS8842_SGCR7_P },
6118 { KS8842_MACAR1_P, KS8842_TOSR8_P },
6119 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
6120 { 0, 0 }
6121};
6122
6123static int netdev_get_regs_len(struct net_device *dev)
6124{
6125 struct hw_regs *range = hw_regs_range;
6126 int regs_len = 0x10 * sizeof(u32);
6127
6128 while (range->end > range->start) {
6129 regs_len += (range->end - range->start + 3) / 4 * 4;
6130 range++;
6131 }
6132 return regs_len;
6133}
6134
6135/**
6136 * netdev_get_regs - get register dump
6137 * @dev: Network device.
6138 * @regs: Ethtool registers data structure.
6139 * @ptr: Buffer to store the register values.
6140 *
6141 * This procedure dumps the register values in the provided buffer.
6142 */
6143static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6144 void *ptr)
6145{
6146 struct dev_priv *priv = netdev_priv(dev);
6147 struct dev_info *hw_priv = priv->adapter;
6148 struct ksz_hw *hw = &hw_priv->hw;
6149 int *buf = (int *) ptr;
6150 struct hw_regs *range = hw_regs_range;
6151 int len;
6152
6153 mutex_lock(&hw_priv->lock);
6154 regs->version = 0;
6155 for (len = 0; len < 0x40; len += 4) {
6156 pci_read_config_dword(hw_priv->pdev, len, buf);
6157 buf++;
6158 }
6159 while (range->end > range->start) {
6160 for (len = range->start; len < range->end; len += 4) {
6161 *buf = readl(hw->io + len);
6162 buf++;
6163 }
6164 range++;
6165 }
6166 mutex_unlock(&hw_priv->lock);
6167}
6168
6169#define WOL_SUPPORT \
6170 (WAKE_PHY | WAKE_MAGIC | \
6171 WAKE_UCAST | WAKE_MCAST | \
6172 WAKE_BCAST | WAKE_ARP)
6173
6174/**
6175 * netdev_get_wol - get Wake-on-LAN support
6176 * @dev: Network device.
6177 * @wol: Ethtool Wake-on-LAN data structure.
6178 *
6179 * This procedure returns Wake-on-LAN support.
6180 */
6181static void netdev_get_wol(struct net_device *dev,
6182 struct ethtool_wolinfo *wol)
6183{
6184 struct dev_priv *priv = netdev_priv(dev);
6185 struct dev_info *hw_priv = priv->adapter;
6186
6187 wol->supported = hw_priv->wol_support;
6188 wol->wolopts = hw_priv->wol_enable;
6189 memset(&wol->sopass, 0, sizeof(wol->sopass));
6190}
6191
6192/**
6193 * netdev_set_wol - set Wake-on-LAN support
6194 * @dev: Network device.
6195 * @wol: Ethtool Wake-on-LAN data structure.
6196 *
6197 * This function sets Wake-on-LAN support.
6198 *
6199 * Return 0 if successful; otherwise an error code.
6200 */
6201static int netdev_set_wol(struct net_device *dev,
6202 struct ethtool_wolinfo *wol)
6203{
6204 struct dev_priv *priv = netdev_priv(dev);
6205 struct dev_info *hw_priv = priv->adapter;
6206
6207 /* Need to find a way to retrieve the device IP address. */
6208 static const u8 net_addr[] = { 192, 168, 1, 1 };
6209
6210 if (wol->wolopts & ~hw_priv->wol_support)
6211 return -EINVAL;
6212
6213 hw_priv->wol_enable = wol->wolopts;
6214
6215 /* Link wakeup cannot really be disabled. */
6216 if (wol->wolopts)
6217 hw_priv->wol_enable |= WAKE_PHY;
6218 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6219 return 0;
6220}
6221
6222/**
6223 * netdev_get_msglevel - get debug message level
6224 * @dev: Network device.
6225 *
6226 * This function returns current debug message level.
6227 *
6228 * Return current debug message flags.
6229 */
6230static u32 netdev_get_msglevel(struct net_device *dev)
6231{
6232 struct dev_priv *priv = netdev_priv(dev);
6233
6234 return priv->msg_enable;
6235}
6236
6237/**
6238 * netdev_set_msglevel - set debug message level
6239 * @dev: Network device.
6240 * @value: Debug message flags.
6241 *
6242 * This procedure sets debug message level.
6243 */
6244static void netdev_set_msglevel(struct net_device *dev, u32 value)
6245{
6246 struct dev_priv *priv = netdev_priv(dev);
6247
6248 priv->msg_enable = value;
6249}
6250
6251/**
6252 * netdev_get_eeprom_len - get EEPROM length
6253 * @dev: Network device.
6254 *
6255 * This function returns the length of the EEPROM.
6256 *
6257 * Return length of the EEPROM.
6258 */
6259static int netdev_get_eeprom_len(struct net_device *dev)
6260{
6261 return EEPROM_SIZE * 2;
6262}
6263
6264/**
6265 * netdev_get_eeprom - get EEPROM data
6266 * @dev: Network device.
6267 * @eeprom: Ethtool EEPROM data structure.
6268 * @data: Buffer to store the EEPROM data.
6269 *
6270 * This function dumps the EEPROM data in the provided buffer.
6271 *
6272 * Return 0 if successful; otherwise an error code.
6273 */
6274#define EEPROM_MAGIC 0x10A18842
6275
6276static int netdev_get_eeprom(struct net_device *dev,
6277 struct ethtool_eeprom *eeprom, u8 *data)
6278{
6279 struct dev_priv *priv = netdev_priv(dev);
6280 struct dev_info *hw_priv = priv->adapter;
6281 u8 *eeprom_byte = (u8 *) eeprom_data;
6282 int i;
6283 int len;
6284
6285 len = (eeprom->offset + eeprom->len + 1) / 2;
6286 for (i = eeprom->offset / 2; i < len; i++)
6287 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6288 eeprom->magic = EEPROM_MAGIC;
6289 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6290
6291 return 0;
6292}
6293
6294/**
6295 * netdev_set_eeprom - write EEPROM data
6296 * @dev: Network device.
6297 * @eeprom: Ethtool EEPROM data structure.
6298 * @data: Data buffer.
6299 *
6300 * This function modifies the EEPROM data one byte at a time.
6301 *
6302 * Return 0 if successful; otherwise an error code.
6303 */
6304static int netdev_set_eeprom(struct net_device *dev,
6305 struct ethtool_eeprom *eeprom, u8 *data)
6306{
6307 struct dev_priv *priv = netdev_priv(dev);
6308 struct dev_info *hw_priv = priv->adapter;
6309 u16 eeprom_word[EEPROM_SIZE];
6310 u8 *eeprom_byte = (u8 *) eeprom_word;
6311 int i;
6312 int len;
6313
6314 if (eeprom->magic != EEPROM_MAGIC)
6315 return -EINVAL;
6316
6317 len = (eeprom->offset + eeprom->len + 1) / 2;
6318 for (i = eeprom->offset / 2; i < len; i++)
6319 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6320 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6321 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6322 for (i = 0; i < EEPROM_SIZE; i++)
6323 if (eeprom_word[i] != eeprom_data[i]) {
6324 eeprom_data[i] = eeprom_word[i];
6325 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6326 }
6327
6328 return 0;
6329}
6330
6331/**
6332 * netdev_get_pauseparam - get flow control parameters
6333 * @dev: Network device.
6334 * @pause: Ethtool PAUSE settings data structure.
6335 *
6336 * This procedure returns the PAUSE control flow settings.
6337 */
6338static void netdev_get_pauseparam(struct net_device *dev,
6339 struct ethtool_pauseparam *pause)
6340{
6341 struct dev_priv *priv = netdev_priv(dev);
6342 struct dev_info *hw_priv = priv->adapter;
6343 struct ksz_hw *hw = &hw_priv->hw;
6344
6345 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6346 if (!hw->ksz_switch) {
6347 pause->rx_pause =
6348 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6349 pause->tx_pause =
6350 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6351 } else {
6352 pause->rx_pause =
6353 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6354 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6355 pause->tx_pause =
6356 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6357 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6358 }
6359}
6360
6361/**
6362 * netdev_set_pauseparam - set flow control parameters
6363 * @dev: Network device.
6364 * @pause: Ethtool PAUSE settings data structure.
6365 *
6366 * This function sets the PAUSE control flow settings.
6367 * Not implemented yet.
6368 *
6369 * Return 0 if successful; otherwise an error code.
6370 */
6371static int netdev_set_pauseparam(struct net_device *dev,
6372 struct ethtool_pauseparam *pause)
6373{
6374 struct dev_priv *priv = netdev_priv(dev);
6375 struct dev_info *hw_priv = priv->adapter;
6376 struct ksz_hw *hw = &hw_priv->hw;
6377 struct ksz_port *port = &priv->port;
6378
6379 mutex_lock(&hw_priv->lock);
6380 if (pause->autoneg) {
6381 if (!pause->rx_pause && !pause->tx_pause)
6382 port->flow_ctrl = PHY_NO_FLOW_CTRL;
6383 else
6384 port->flow_ctrl = PHY_FLOW_CTRL;
6385 hw->overrides &= ~PAUSE_FLOW_CTRL;
6386 port->force_link = 0;
6387 if (hw->ksz_switch) {
6388 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6389 SWITCH_RX_FLOW_CTRL, 1);
6390 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6391 SWITCH_TX_FLOW_CTRL, 1);
6392 }
6393 port_set_link_speed(port);
6394 } else {
6395 hw->overrides |= PAUSE_FLOW_CTRL;
6396 if (hw->ksz_switch) {
6397 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6398 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6399 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6400 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6401 } else
6402 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6403 }
6404 mutex_unlock(&hw_priv->lock);
6405
6406 return 0;
6407}
6408
6409/**
6410 * netdev_get_ringparam - get tx/rx ring parameters
6411 * @dev: Network device.
6412 * @pause: Ethtool RING settings data structure.
6413 *
6414 * This procedure returns the TX/RX ring settings.
6415 */
6416static void netdev_get_ringparam(struct net_device *dev,
6417 struct ethtool_ringparam *ring)
6418{
6419 struct dev_priv *priv = netdev_priv(dev);
6420 struct dev_info *hw_priv = priv->adapter;
6421 struct ksz_hw *hw = &hw_priv->hw;
6422
6423 ring->tx_max_pending = (1 << 9);
6424 ring->tx_pending = hw->tx_desc_info.alloc;
6425 ring->rx_max_pending = (1 << 9);
6426 ring->rx_pending = hw->rx_desc_info.alloc;
6427}
6428
6429#define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6430
6431static struct {
6432 char string[ETH_GSTRING_LEN];
6433} ethtool_stats_keys[STATS_LEN] = {
6434 { "rx_lo_priority_octets" },
6435 { "rx_hi_priority_octets" },
6436 { "rx_undersize_packets" },
6437 { "rx_fragments" },
6438 { "rx_oversize_packets" },
6439 { "rx_jabbers" },
6440 { "rx_symbol_errors" },
6441 { "rx_crc_errors" },
6442 { "rx_align_errors" },
6443 { "rx_mac_ctrl_packets" },
6444 { "rx_pause_packets" },
6445 { "rx_bcast_packets" },
6446 { "rx_mcast_packets" },
6447 { "rx_ucast_packets" },
6448 { "rx_64_or_less_octet_packets" },
6449 { "rx_65_to_127_octet_packets" },
6450 { "rx_128_to_255_octet_packets" },
6451 { "rx_256_to_511_octet_packets" },
6452 { "rx_512_to_1023_octet_packets" },
6453 { "rx_1024_to_1522_octet_packets" },
6454
6455 { "tx_lo_priority_octets" },
6456 { "tx_hi_priority_octets" },
6457 { "tx_late_collisions" },
6458 { "tx_pause_packets" },
6459 { "tx_bcast_packets" },
6460 { "tx_mcast_packets" },
6461 { "tx_ucast_packets" },
6462 { "tx_deferred" },
6463 { "tx_total_collisions" },
6464 { "tx_excessive_collisions" },
6465 { "tx_single_collisions" },
6466 { "tx_mult_collisions" },
6467
6468 { "rx_discards" },
6469 { "tx_discards" },
6470};
6471
6472/**
6473 * netdev_get_strings - get statistics identity strings
6474 * @dev: Network device.
6475 * @stringset: String set identifier.
6476 * @buf: Buffer to store the strings.
6477 *
6478 * This procedure returns the strings used to identify the statistics.
6479 */
6480static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6481{
6482 struct dev_priv *priv = netdev_priv(dev);
6483 struct dev_info *hw_priv = priv->adapter;
6484 struct ksz_hw *hw = &hw_priv->hw;
6485
6486 if (ETH_SS_STATS == stringset)
6487 memcpy(buf, &ethtool_stats_keys,
6488 ETH_GSTRING_LEN * hw->mib_cnt);
6489}
6490
6491/**
6492 * netdev_get_sset_count - get statistics size
6493 * @dev: Network device.
6494 * @sset: The statistics set number.
6495 *
6496 * This function returns the size of the statistics to be reported.
6497 *
6498 * Return size of the statistics to be reported.
6499 */
6500static int netdev_get_sset_count(struct net_device *dev, int sset)
6501{
6502 struct dev_priv *priv = netdev_priv(dev);
6503 struct dev_info *hw_priv = priv->adapter;
6504 struct ksz_hw *hw = &hw_priv->hw;
6505
6506 switch (sset) {
6507 case ETH_SS_STATS:
6508 return hw->mib_cnt;
6509 default:
6510 return -EOPNOTSUPP;
6511 }
6512}
6513
6514/**
6515 * netdev_get_ethtool_stats - get network device statistics
6516 * @dev: Network device.
6517 * @stats: Ethtool statistics data structure.
6518 * @data: Buffer to store the statistics.
6519 *
6520 * This procedure returns the statistics.
6521 */
6522static void netdev_get_ethtool_stats(struct net_device *dev,
6523 struct ethtool_stats *stats, u64 *data)
6524{
6525 struct dev_priv *priv = netdev_priv(dev);
6526 struct dev_info *hw_priv = priv->adapter;
6527 struct ksz_hw *hw = &hw_priv->hw;
6528 struct ksz_port *port = &priv->port;
6529 int n_stats = stats->n_stats;
6530 int i;
6531 int n;
6532 int p;
6533 int rc;
6534 u64 counter[TOTAL_PORT_COUNTER_NUM];
6535
6536 mutex_lock(&hw_priv->lock);
6537 n = SWITCH_PORT_NUM;
6538 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6539 if (media_connected == hw->port_mib[p].state) {
6540 hw_priv->counter[p].read = 1;
6541
6542 /* Remember first port that requests read. */
6543 if (n == SWITCH_PORT_NUM)
6544 n = p;
6545 }
6546 }
6547 mutex_unlock(&hw_priv->lock);
6548
6549 if (n < SWITCH_PORT_NUM)
6550 schedule_work(&hw_priv->mib_read);
6551
6552 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6553 p = n;
6554 rc = wait_event_interruptible_timeout(
6555 hw_priv->counter[p].counter,
6556 2 == hw_priv->counter[p].read,
6557 HZ * 1);
6558 } else
6559 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6560 if (0 == i) {
6561 rc = wait_event_interruptible_timeout(
6562 hw_priv->counter[p].counter,
6563 2 == hw_priv->counter[p].read,
6564 HZ * 2);
6565 } else if (hw->port_mib[p].cnt_ptr) {
6566 rc = wait_event_interruptible_timeout(
6567 hw_priv->counter[p].counter,
6568 2 == hw_priv->counter[p].read,
6569 HZ * 1);
6570 }
6571 }
6572
6573 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6574 n = hw->mib_cnt;
6575 if (n > n_stats)
6576 n = n_stats;
6577 n_stats -= n;
6578 for (i = 0; i < n; i++)
6579 *data++ = counter[i];
6580}
6581
6582/**
6583 * netdev_set_features - set receive checksum support
6584 * @dev: Network device.
6585 * @features: New device features (offloads).
6586 *
6587 * This function sets receive checksum support setting.
6588 *
6589 * Return 0 if successful; otherwise an error code.
6590 */
6591static int netdev_set_features(struct net_device *dev, u32 features)
6592{
6593 struct dev_priv *priv = netdev_priv(dev);
6594 struct dev_info *hw_priv = priv->adapter;
6595 struct ksz_hw *hw = &hw_priv->hw;
6596
6597 mutex_lock(&hw_priv->lock);
6598
6599 /* see note in hw_setup() */
6600 if (features & NETIF_F_RXCSUM)
6601 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6602 else
6603 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6604
6605 if (hw->enabled)
6606 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6607
6608 mutex_unlock(&hw_priv->lock);
6609
6610 return 0;
6611}
6612
6613static struct ethtool_ops netdev_ethtool_ops = {
6614 .get_settings = netdev_get_settings,
6615 .set_settings = netdev_set_settings,
6616 .nway_reset = netdev_nway_reset,
6617 .get_link = netdev_get_link,
6618 .get_drvinfo = netdev_get_drvinfo,
6619 .get_regs_len = netdev_get_regs_len,
6620 .get_regs = netdev_get_regs,
6621 .get_wol = netdev_get_wol,
6622 .set_wol = netdev_set_wol,
6623 .get_msglevel = netdev_get_msglevel,
6624 .set_msglevel = netdev_set_msglevel,
6625 .get_eeprom_len = netdev_get_eeprom_len,
6626 .get_eeprom = netdev_get_eeprom,
6627 .set_eeprom = netdev_set_eeprom,
6628 .get_pauseparam = netdev_get_pauseparam,
6629 .set_pauseparam = netdev_set_pauseparam,
6630 .get_ringparam = netdev_get_ringparam,
6631 .get_strings = netdev_get_strings,
6632 .get_sset_count = netdev_get_sset_count,
6633 .get_ethtool_stats = netdev_get_ethtool_stats,
6634};
6635
6636/*
6637 * Hardware monitoring
6638 */
6639
6640static void update_link(struct net_device *dev, struct dev_priv *priv,
6641 struct ksz_port *port)
6642{
6643 if (priv->media_state != port->linked->state) {
6644 priv->media_state = port->linked->state;
6645 if (netif_running(dev))
6646 set_media_state(dev, media_connected);
6647 }
6648}
6649
6650static void mib_read_work(struct work_struct *work)
6651{
6652 struct dev_info *hw_priv =
6653 container_of(work, struct dev_info, mib_read);
6654 struct ksz_hw *hw = &hw_priv->hw;
6655 struct ksz_port_mib *mib;
6656 int i;
6657
6658 next_jiffies = jiffies;
6659 for (i = 0; i < hw->mib_port_cnt; i++) {
6660 mib = &hw->port_mib[i];
6661
6662 /* Reading MIB counters or requested to read. */
6663 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6664
6665 /* Need to process receive interrupt. */
6666 if (port_r_cnt(hw, i))
6667 break;
6668 hw_priv->counter[i].read = 0;
6669
6670 /* Finish reading counters. */
6671 if (0 == mib->cnt_ptr) {
6672 hw_priv->counter[i].read = 2;
6673 wake_up_interruptible(
6674 &hw_priv->counter[i].counter);
6675 }
6676 } else if (jiffies >= hw_priv->counter[i].time) {
6677 /* Only read MIB counters when the port is connected. */
6678 if (media_connected == mib->state)
6679 hw_priv->counter[i].read = 1;
6680 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6681 hw_priv->counter[i].time = next_jiffies;
6682
6683 /* Port is just disconnected. */
6684 } else if (mib->link_down) {
6685 mib->link_down = 0;
6686
6687 /* Read counters one last time after link is lost. */
6688 hw_priv->counter[i].read = 1;
6689 }
6690 }
6691}
6692
6693static void mib_monitor(unsigned long ptr)
6694{
6695 struct dev_info *hw_priv = (struct dev_info *) ptr;
6696
6697 mib_read_work(&hw_priv->mib_read);
6698
6699 /* This is used to verify Wake-on-LAN is working. */
6700 if (hw_priv->pme_wait) {
6701 if (hw_priv->pme_wait <= jiffies) {
6702 hw_clr_wol_pme_status(&hw_priv->hw);
6703 hw_priv->pme_wait = 0;
6704 }
6705 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6706
6707 /* PME is asserted. Wait 2 seconds to clear it. */
6708 hw_priv->pme_wait = jiffies + HZ * 2;
6709 }
6710
6711 ksz_update_timer(&hw_priv->mib_timer_info);
6712}
6713
6714/**
6715 * dev_monitor - periodic monitoring
6716 * @ptr: Network device pointer.
6717 *
6718 * This routine is run in a kernel timer to monitor the network device.
6719 */
6720static void dev_monitor(unsigned long ptr)
6721{
6722 struct net_device *dev = (struct net_device *) ptr;
6723 struct dev_priv *priv = netdev_priv(dev);
6724 struct dev_info *hw_priv = priv->adapter;
6725 struct ksz_hw *hw = &hw_priv->hw;
6726 struct ksz_port *port = &priv->port;
6727
6728 if (!(hw->features & LINK_INT_WORKING))
6729 port_get_link_speed(port);
6730 update_link(dev, priv, port);
6731
6732 ksz_update_timer(&priv->monitor_timer_info);
6733}
6734
6735/*
6736 * Linux network device interface functions
6737 */
6738
6739/* Driver exported variables */
6740
6741static int msg_enable;
6742
6743static char *macaddr = ":";
6744static char *mac1addr = ":";
6745
6746/*
6747 * This enables multiple network device mode for KSZ8842, which contains a
6748 * switch with two physical ports. Some users like to take control of the
6749 * ports for running Spanning Tree Protocol. The driver will create an
6750 * additional eth? device for the other port.
6751 *
6752 * Some limitations are the network devices cannot have different MTU and
6753 * multicast hash tables.
6754 */
6755static int multi_dev;
6756
6757/*
6758 * As most users select multiple network device mode to use Spanning Tree
6759 * Protocol, this enables a feature in which most unicast and multicast packets
6760 * are forwarded inside the switch and not passed to the host. Only packets
6761 * that need the host's attention are passed to it. This prevents the host
6762 * wasting CPU time to examine each and every incoming packets and do the
6763 * forwarding itself.
6764 *
6765 * As the hack requires the private bridge header, the driver cannot compile
6766 * with just the kernel headers.
6767 *
6768 * Enabling STP support also turns on multiple network device mode.
6769 */
6770static int stp;
6771
6772/*
6773 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6774 * needs that. However, fast aging is used to flush the dynamic MAC table when
6775 * STP suport is enabled.
6776 */
6777static int fast_aging;
6778
6779/**
6780 * netdev_init - initialize network device.
6781 * @dev: Network device.
6782 *
6783 * This function initializes the network device.
6784 *
6785 * Return 0 if successful; otherwise an error code indicating failure.
6786 */
6787static int __init netdev_init(struct net_device *dev)
6788{
6789 struct dev_priv *priv = netdev_priv(dev);
6790
6791 /* 500 ms timeout */
6792 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6793 dev_monitor, dev);
6794
6795 /* 500 ms timeout */
6796 dev->watchdog_timeo = HZ / 2;
6797
6798 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6799
6800 /*
6801 * Hardware does not really support IPv6 checksum generation, but
6802 * driver actually runs faster with this on.
6803 */
6804 dev->hw_features |= NETIF_F_IPV6_CSUM;
6805
6806 dev->features |= dev->hw_features;
6807
6808 sema_init(&priv->proc_sem, 1);
6809
6810 priv->mii_if.phy_id_mask = 0x1;
6811 priv->mii_if.reg_num_mask = 0x7;
6812 priv->mii_if.dev = dev;
6813 priv->mii_if.mdio_read = mdio_read;
6814 priv->mii_if.mdio_write = mdio_write;
6815 priv->mii_if.phy_id = priv->port.first_port + 1;
6816
6817 priv->msg_enable = netif_msg_init(msg_enable,
6818 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6819
6820 return 0;
6821}
6822
6823static const struct net_device_ops netdev_ops = {
6824 .ndo_init = netdev_init,
6825 .ndo_open = netdev_open,
6826 .ndo_stop = netdev_close,
6827 .ndo_get_stats = netdev_query_statistics,
6828 .ndo_start_xmit = netdev_tx,
6829 .ndo_tx_timeout = netdev_tx_timeout,
6830 .ndo_change_mtu = netdev_change_mtu,
6831 .ndo_set_features = netdev_set_features,
6832 .ndo_set_mac_address = netdev_set_mac_address,
6833 .ndo_validate_addr = eth_validate_addr,
6834 .ndo_do_ioctl = netdev_ioctl,
6835 .ndo_set_rx_mode = netdev_set_rx_mode,
6836#ifdef CONFIG_NET_POLL_CONTROLLER
6837 .ndo_poll_controller = netdev_netpoll,
6838#endif
6839};
6840
6841static void netdev_free(struct net_device *dev)
6842{
6843 if (dev->watchdog_timeo)
6844 unregister_netdev(dev);
6845
6846 free_netdev(dev);
6847}
6848
6849struct platform_info {
6850 struct dev_info dev_info;
6851 struct net_device *netdev[SWITCH_PORT_NUM];
6852};
6853
6854static int net_device_present;
6855
6856static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6857{
6858 int i;
6859 int j;
6860 int got_num;
6861 int num;
6862
6863 i = j = num = got_num = 0;
6864 while (j < MAC_ADDR_LEN) {
6865 if (macaddr[i]) {
6866 int digit;
6867
6868 got_num = 1;
6869 digit = hex_to_bin(macaddr[i]);
6870 if (digit >= 0)
6871 num = num * 16 + digit;
6872 else if (':' == macaddr[i])
6873 got_num = 2;
6874 else
6875 break;
6876 } else if (got_num)
6877 got_num = 2;
6878 else
6879 break;
6880 if (2 == got_num) {
6881 if (MAIN_PORT == port) {
6882 hw_priv->hw.override_addr[j++] = (u8) num;
6883 hw_priv->hw.override_addr[5] +=
6884 hw_priv->hw.id;
6885 } else {
6886 hw_priv->hw.ksz_switch->other_addr[j++] =
6887 (u8) num;
6888 hw_priv->hw.ksz_switch->other_addr[5] +=
6889 hw_priv->hw.id;
6890 }
6891 num = got_num = 0;
6892 }
6893 i++;
6894 }
6895 if (MAC_ADDR_LEN == j) {
6896 if (MAIN_PORT == port)
6897 hw_priv->hw.mac_override = 1;
6898 }
6899}
6900
6901#define KS884X_DMA_MASK (~0x0UL)
6902
6903static void read_other_addr(struct ksz_hw *hw)
6904{
6905 int i;
6906 u16 data[3];
6907 struct ksz_switch *sw = hw->ksz_switch;
6908
6909 for (i = 0; i < 3; i++)
6910 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6911 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6912 sw->other_addr[5] = (u8) data[0];
6913 sw->other_addr[4] = (u8)(data[0] >> 8);
6914 sw->other_addr[3] = (u8) data[1];
6915 sw->other_addr[2] = (u8)(data[1] >> 8);
6916 sw->other_addr[1] = (u8) data[2];
6917 sw->other_addr[0] = (u8)(data[2] >> 8);
6918 }
6919}
6920
6921#ifndef PCI_VENDOR_ID_MICREL_KS
6922#define PCI_VENDOR_ID_MICREL_KS 0x16c6
6923#endif
6924
6925static int __devinit pcidev_init(struct pci_dev *pdev,
6926 const struct pci_device_id *id)
6927{
6928 struct net_device *dev;
6929 struct dev_priv *priv;
6930 struct dev_info *hw_priv;
6931 struct ksz_hw *hw;
6932 struct platform_info *info;
6933 struct ksz_port *port;
6934 unsigned long reg_base;
6935 unsigned long reg_len;
6936 int cnt;
6937 int i;
6938 int mib_port_count;
6939 int pi;
6940 int port_count;
6941 int result;
6942 char banner[sizeof(version)];
6943 struct ksz_switch *sw = NULL;
6944
6945 result = pci_enable_device(pdev);
6946 if (result)
6947 return result;
6948
6949 result = -ENODEV;
6950
6951 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
6952 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
6953 return result;
6954
6955 reg_base = pci_resource_start(pdev, 0);
6956 reg_len = pci_resource_len(pdev, 0);
6957 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6958 return result;
6959
6960 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6961 return result;
6962 pci_set_master(pdev);
6963
6964 result = -ENOMEM;
6965
6966 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6967 if (!info)
6968 goto pcidev_init_dev_err;
6969
6970 hw_priv = &info->dev_info;
6971 hw_priv->pdev = pdev;
6972
6973 hw = &hw_priv->hw;
6974
6975 hw->io = ioremap(reg_base, reg_len);
6976 if (!hw->io)
6977 goto pcidev_init_io_err;
6978
6979 cnt = hw_init(hw);
6980 if (!cnt) {
6981 if (msg_enable & NETIF_MSG_PROBE)
6982 pr_alert("chip not detected\n");
6983 result = -ENODEV;
6984 goto pcidev_init_alloc_err;
6985 }
6986
6987 snprintf(banner, sizeof(banner), "%s", version);
6988 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
6989 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6990 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6991
6992 /* Assume device is KSZ8841. */
6993 hw->dev_count = 1;
6994 port_count = 1;
6995 mib_port_count = 1;
6996 hw->addr_list_size = 0;
6997 hw->mib_cnt = PORT_COUNTER_NUM;
6998 hw->mib_port_cnt = 1;
6999
7000 /* KSZ8842 has a switch with multiple ports. */
7001 if (2 == cnt) {
7002 if (fast_aging)
7003 hw->overrides |= FAST_AGING;
7004
7005 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
7006
7007 /* Multiple network device interfaces are required. */
7008 if (multi_dev) {
7009 hw->dev_count = SWITCH_PORT_NUM;
7010 hw->addr_list_size = SWITCH_PORT_NUM - 1;
7011 }
7012
7013 /* Single network device has multiple ports. */
7014 if (1 == hw->dev_count) {
7015 port_count = SWITCH_PORT_NUM;
7016 mib_port_count = SWITCH_PORT_NUM;
7017 }
7018 hw->mib_port_cnt = TOTAL_PORT_NUM;
7019 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7020 if (!hw->ksz_switch)
7021 goto pcidev_init_alloc_err;
7022
7023 sw = hw->ksz_switch;
7024 }
7025 for (i = 0; i < hw->mib_port_cnt; i++)
7026 hw->port_mib[i].mib_start = 0;
7027
7028 hw->parent = hw_priv;
7029
7030 /* Default MTU is 1500. */
7031 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
7032
7033 if (ksz_alloc_mem(hw_priv))
7034 goto pcidev_init_mem_err;
7035
7036 hw_priv->hw.id = net_device_present;
7037
7038 spin_lock_init(&hw_priv->hwlock);
7039 mutex_init(&hw_priv->lock);
7040
7041 /* tasklet is enabled. */
7042 tasklet_init(&hw_priv->rx_tasklet, rx_proc_task,
7043 (unsigned long) hw_priv);
7044 tasklet_init(&hw_priv->tx_tasklet, tx_proc_task,
7045 (unsigned long) hw_priv);
7046
7047 /* tasklet_enable will decrement the atomic counter. */
7048 tasklet_disable(&hw_priv->rx_tasklet);
7049 tasklet_disable(&hw_priv->tx_tasklet);
7050
7051 for (i = 0; i < TOTAL_PORT_NUM; i++)
7052 init_waitqueue_head(&hw_priv->counter[i].counter);
7053
7054 if (macaddr[0] != ':')
7055 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
7056
7057 /* Read MAC address and initialize override address if not overrided. */
7058 hw_read_addr(hw);
7059
7060 /* Multiple device interfaces mode requires a second MAC address. */
7061 if (hw->dev_count > 1) {
7062 memcpy(sw->other_addr, hw->override_addr, MAC_ADDR_LEN);
7063 read_other_addr(hw);
7064 if (mac1addr[0] != ':')
7065 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
7066 }
7067
7068 hw_setup(hw);
7069 if (hw->ksz_switch)
7070 sw_setup(hw);
7071 else {
7072 hw_priv->wol_support = WOL_SUPPORT;
7073 hw_priv->wol_enable = 0;
7074 }
7075
7076 INIT_WORK(&hw_priv->mib_read, mib_read_work);
7077
7078 /* 500 ms timeout */
7079 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
7080 mib_monitor, hw_priv);
7081
7082 for (i = 0; i < hw->dev_count; i++) {
7083 dev = alloc_etherdev(sizeof(struct dev_priv));
7084 if (!dev)
7085 goto pcidev_init_reg_err;
7086 info->netdev[i] = dev;
7087
7088 priv = netdev_priv(dev);
7089 priv->adapter = hw_priv;
7090 priv->id = net_device_present++;
7091
7092 port = &priv->port;
7093 port->port_cnt = port_count;
7094 port->mib_port_cnt = mib_port_count;
7095 port->first_port = i;
7096 port->flow_ctrl = PHY_FLOW_CTRL;
7097
7098 port->hw = hw;
7099 port->linked = &hw->port_info[port->first_port];
7100
7101 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7102 hw->port_info[pi].port_id = pi;
7103 hw->port_info[pi].pdev = dev;
7104 hw->port_info[pi].state = media_disconnected;
7105 }
7106
7107 dev->mem_start = (unsigned long) hw->io;
7108 dev->mem_end = dev->mem_start + reg_len - 1;
7109 dev->irq = pdev->irq;
7110 if (MAIN_PORT == i)
7111 memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7112 MAC_ADDR_LEN);
7113 else {
7114 memcpy(dev->dev_addr, sw->other_addr,
7115 MAC_ADDR_LEN);
7116 if (!memcmp(sw->other_addr, hw->override_addr,
7117 MAC_ADDR_LEN))
7118 dev->dev_addr[5] += port->first_port;
7119 }
7120
7121 dev->netdev_ops = &netdev_ops;
7122 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7123 if (register_netdev(dev))
7124 goto pcidev_init_reg_err;
7125 port_set_power_saving(port, true);
7126 }
7127
7128 pci_dev_get(hw_priv->pdev);
7129 pci_set_drvdata(pdev, info);
7130 return 0;
7131
7132pcidev_init_reg_err:
7133 for (i = 0; i < hw->dev_count; i++) {
7134 if (info->netdev[i]) {
7135 netdev_free(info->netdev[i]);
7136 info->netdev[i] = NULL;
7137 }
7138 }
7139
7140pcidev_init_mem_err:
7141 ksz_free_mem(hw_priv);
7142 kfree(hw->ksz_switch);
7143
7144pcidev_init_alloc_err:
7145 iounmap(hw->io);
7146
7147pcidev_init_io_err:
7148 kfree(info);
7149
7150pcidev_init_dev_err:
7151 release_mem_region(reg_base, reg_len);
7152
7153 return result;
7154}
7155
7156static void pcidev_exit(struct pci_dev *pdev)
7157{
7158 int i;
7159 struct platform_info *info = pci_get_drvdata(pdev);
7160 struct dev_info *hw_priv = &info->dev_info;
7161
7162 pci_set_drvdata(pdev, NULL);
7163
7164 release_mem_region(pci_resource_start(pdev, 0),
7165 pci_resource_len(pdev, 0));
7166 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7167 if (info->netdev[i])
7168 netdev_free(info->netdev[i]);
7169 }
7170 if (hw_priv->hw.io)
7171 iounmap(hw_priv->hw.io);
7172 ksz_free_mem(hw_priv);
7173 kfree(hw_priv->hw.ksz_switch);
7174 pci_dev_put(hw_priv->pdev);
7175 kfree(info);
7176}
7177
7178#ifdef CONFIG_PM
7179static int pcidev_resume(struct pci_dev *pdev)
7180{
7181 int i;
7182 struct platform_info *info = pci_get_drvdata(pdev);
7183 struct dev_info *hw_priv = &info->dev_info;
7184 struct ksz_hw *hw = &hw_priv->hw;
7185
7186 pci_set_power_state(pdev, PCI_D0);
7187 pci_restore_state(pdev);
7188 pci_enable_wake(pdev, PCI_D0, 0);
7189
7190 if (hw_priv->wol_enable)
7191 hw_cfg_wol_pme(hw, 0);
7192 for (i = 0; i < hw->dev_count; i++) {
7193 if (info->netdev[i]) {
7194 struct net_device *dev = info->netdev[i];
7195
7196 if (netif_running(dev)) {
7197 netdev_open(dev);
7198 netif_device_attach(dev);
7199 }
7200 }
7201 }
7202 return 0;
7203}
7204
7205static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
7206{
7207 int i;
7208 struct platform_info *info = pci_get_drvdata(pdev);
7209 struct dev_info *hw_priv = &info->dev_info;
7210 struct ksz_hw *hw = &hw_priv->hw;
7211
7212 /* Need to find a way to retrieve the device IP address. */
7213 static const u8 net_addr[] = { 192, 168, 1, 1 };
7214
7215 for (i = 0; i < hw->dev_count; i++) {
7216 if (info->netdev[i]) {
7217 struct net_device *dev = info->netdev[i];
7218
7219 if (netif_running(dev)) {
7220 netif_device_detach(dev);
7221 netdev_close(dev);
7222 }
7223 }
7224 }
7225 if (hw_priv->wol_enable) {
7226 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7227 hw_cfg_wol_pme(hw, 1);
7228 }
7229
7230 pci_save_state(pdev);
7231 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
7232 pci_set_power_state(pdev, pci_choose_state(pdev, state));
7233 return 0;
7234}
7235#endif
7236
7237static char pcidev_name[] = "ksz884xp";
7238
7239static struct pci_device_id pcidev_table[] = {
7240 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7242 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7244 { 0 }
7245};
7246
7247MODULE_DEVICE_TABLE(pci, pcidev_table);
7248
7249static struct pci_driver pci_device_driver = {
7250#ifdef CONFIG_PM
7251 .suspend = pcidev_suspend,
7252 .resume = pcidev_resume,
7253#endif
7254 .name = pcidev_name,
7255 .id_table = pcidev_table,
7256 .probe = pcidev_init,
7257 .remove = pcidev_exit
7258};
7259
7260static int __init ksz884x_init_module(void)
7261{
7262 return pci_register_driver(&pci_device_driver);
7263}
7264
7265static void __exit ksz884x_cleanup_module(void)
7266{
7267 pci_unregister_driver(&pci_device_driver);
7268}
7269
7270module_init(ksz884x_init_module);
7271module_exit(ksz884x_cleanup_module);
7272
7273MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7274MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7275MODULE_LICENSE("GPL");
7276
7277module_param_named(message, msg_enable, int, 0);
7278MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7279
7280module_param(macaddr, charp, 0);
7281module_param(mac1addr, charp, 0);
7282module_param(fast_aging, int, 0);
7283module_param(multi_dev, int, 0);
7284module_param(stp, int, 0);
7285MODULE_PARM_DESC(macaddr, "MAC address");
7286MODULE_PARM_DESC(mac1addr, "Second MAC address");
7287MODULE_PARM_DESC(fast_aging, "Fast aging");
7288MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7289MODULE_PARM_DESC(stp, "STP support");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 23:55:39 -0500