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-rw-r--r--drivers/net/ethernet/Kconfig1
-rw-r--r--drivers/net/ethernet/Makefile1
-rw-r--r--drivers/net/ethernet/microchip/Kconfig37
-rw-r--r--drivers/net/ethernet/microchip/Makefile5
-rw-r--r--drivers/net/ethernet/microchip/enc28j60.c1667
-rw-r--r--drivers/net/ethernet/microchip/enc28j60_hw.h309
6 files changed, 2020 insertions, 0 deletions
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 32561c71040d..0cec25cbf36b 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -78,6 +78,7 @@ config LANTIQ_ETOP
78source "drivers/net/ethernet/marvell/Kconfig" 78source "drivers/net/ethernet/marvell/Kconfig"
79source "drivers/net/ethernet/mellanox/Kconfig" 79source "drivers/net/ethernet/mellanox/Kconfig"
80source "drivers/net/ethernet/micrel/Kconfig" 80source "drivers/net/ethernet/micrel/Kconfig"
81source "drivers/net/ethernet/microchip/Kconfig"
81 82
82config MIPS_SIM_NET 83config MIPS_SIM_NET
83 tristate "MIPS simulator Network device" 84 tristate "MIPS simulator Network device"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 94f1be8e822b..ebe8aee3f839 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
36obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ 36obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
37obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ 37obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
38obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ 38obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
39obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/
39obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o 40obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
40obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/ 41obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/
41obj-$(CONFIG_FEALNX) += fealnx.o 42obj-$(CONFIG_FEALNX) += fealnx.o
diff --git a/drivers/net/ethernet/microchip/Kconfig b/drivers/net/ethernet/microchip/Kconfig
new file mode 100644
index 000000000000..53b0b04935a3
--- /dev/null
+++ b/drivers/net/ethernet/microchip/Kconfig
@@ -0,0 +1,37 @@
1#
2# Microchip network device configuration
3#
4
5config NET_VENDOR_MICROCHIP
6 bool "Microchip devices"
7 depends on SPI && EXPERIMENTAL
8 ---help---
9 If you have a network (Ethernet) card belonging to this class, say Y
10 and read the Ethernet-HOWTO, available from
11 <http://www.tldp.org/docs.html#howto>.
12
13 Note that the answer to this question doesn't directly affect the
14 kernel: saying N will just cause the configurator to skip all
15 the questions about Microchip cards. If you say Y, you will be asked
16 for your specific card in the following questions.
17
18if NET_VENDOR_MICROCHIP
19
20config ENC28J60
21 tristate "ENC28J60 support"
22 depends on SPI && EXPERIMENTAL
23 select CRC32
24 ---help---
25 Support for the Microchip EN28J60 ethernet chip.
26
27 To compile this driver as a module, choose M here. The module will be
28 called enc28j60.
29
30config ENC28J60_WRITEVERIFY
31 bool "Enable write verify"
32 depends on ENC28J60
33 ---help---
34 Enable the verify after the buffer write useful for debugging purpose.
35 If unsure, say N.
36
37endif # NET_VENDOR_MICROCHIP
diff --git a/drivers/net/ethernet/microchip/Makefile b/drivers/net/ethernet/microchip/Makefile
new file mode 100644
index 000000000000..573d4292b9ea
--- /dev/null
+++ b/drivers/net/ethernet/microchip/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Microchip network device drivers.
3#
4
5obj-$(CONFIG_ENC28J60) += enc28j60.o
diff --git a/drivers/net/ethernet/microchip/enc28j60.c b/drivers/net/ethernet/microchip/enc28j60.c
new file mode 100644
index 000000000000..2837ce209cd7
--- /dev/null
+++ b/drivers/net/ethernet/microchip/enc28j60.c
@@ -0,0 +1,1667 @@
1/*
2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
3 *
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/string.h>
22#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/tcp.h>
28#include <linux/skbuff.h>
29#include <linux/delay.h>
30#include <linux/spi/spi.h>
31
32#include "enc28j60_hw.h"
33
34#define DRV_NAME "enc28j60"
35#define DRV_VERSION "1.01"
36
37#define SPI_OPLEN 1
38
39#define ENC28J60_MSG_DEFAULT \
40 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
41
42/* Buffer size required for the largest SPI transfer (i.e., reading a
43 * frame). */
44#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
45
46#define TX_TIMEOUT (4 * HZ)
47
48/* Max TX retries in case of collision as suggested by errata datasheet */
49#define MAX_TX_RETRYCOUNT 16
50
51enum {
52 RXFILTER_NORMAL,
53 RXFILTER_MULTI,
54 RXFILTER_PROMISC
55};
56
57/* Driver local data */
58struct enc28j60_net {
59 struct net_device *netdev;
60 struct spi_device *spi;
61 struct mutex lock;
62 struct sk_buff *tx_skb;
63 struct work_struct tx_work;
64 struct work_struct irq_work;
65 struct work_struct setrx_work;
66 struct work_struct restart_work;
67 u8 bank; /* current register bank selected */
68 u16 next_pk_ptr; /* next packet pointer within FIFO */
69 u16 max_pk_counter; /* statistics: max packet counter */
70 u16 tx_retry_count;
71 bool hw_enable;
72 bool full_duplex;
73 int rxfilter;
74 u32 msg_enable;
75 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
76};
77
78/* use ethtool to change the level for any given device */
79static struct {
80 u32 msg_enable;
81} debug = { -1 };
82
83/*
84 * SPI read buffer
85 * wait for the SPI transfer and copy received data to destination
86 */
87static int
88spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
89{
90 u8 *rx_buf = priv->spi_transfer_buf + 4;
91 u8 *tx_buf = priv->spi_transfer_buf;
92 struct spi_transfer t = {
93 .tx_buf = tx_buf,
94 .rx_buf = rx_buf,
95 .len = SPI_OPLEN + len,
96 };
97 struct spi_message msg;
98 int ret;
99
100 tx_buf[0] = ENC28J60_READ_BUF_MEM;
101 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
102
103 spi_message_init(&msg);
104 spi_message_add_tail(&t, &msg);
105 ret = spi_sync(priv->spi, &msg);
106 if (ret == 0) {
107 memcpy(data, &rx_buf[SPI_OPLEN], len);
108 ret = msg.status;
109 }
110 if (ret && netif_msg_drv(priv))
111 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
112 __func__, ret);
113
114 return ret;
115}
116
117/*
118 * SPI write buffer
119 */
120static int spi_write_buf(struct enc28j60_net *priv, int len,
121 const u8 *data)
122{
123 int ret;
124
125 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
126 ret = -EINVAL;
127 else {
128 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
129 memcpy(&priv->spi_transfer_buf[1], data, len);
130 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
131 if (ret && netif_msg_drv(priv))
132 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
133 __func__, ret);
134 }
135 return ret;
136}
137
138/*
139 * basic SPI read operation
140 */
141static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
142 u8 addr)
143{
144 u8 tx_buf[2];
145 u8 rx_buf[4];
146 u8 val = 0;
147 int ret;
148 int slen = SPI_OPLEN;
149
150 /* do dummy read if needed */
151 if (addr & SPRD_MASK)
152 slen++;
153
154 tx_buf[0] = op | (addr & ADDR_MASK);
155 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
156 if (ret)
157 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
158 __func__, ret);
159 else
160 val = rx_buf[slen - 1];
161
162 return val;
163}
164
165/*
166 * basic SPI write operation
167 */
168static int spi_write_op(struct enc28j60_net *priv, u8 op,
169 u8 addr, u8 val)
170{
171 int ret;
172
173 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
174 priv->spi_transfer_buf[1] = val;
175 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
176 if (ret && netif_msg_drv(priv))
177 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
178 __func__, ret);
179 return ret;
180}
181
182static void enc28j60_soft_reset(struct enc28j60_net *priv)
183{
184 if (netif_msg_hw(priv))
185 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
186
187 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
188 /* Errata workaround #1, CLKRDY check is unreliable,
189 * delay at least 1 mS instead */
190 udelay(2000);
191}
192
193/*
194 * select the current register bank if necessary
195 */
196static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
197{
198 u8 b = (addr & BANK_MASK) >> 5;
199
200 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
201 * are present in all banks, no need to switch bank
202 */
203 if (addr >= EIE && addr <= ECON1)
204 return;
205
206 /* Clear or set each bank selection bit as needed */
207 if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
208 if (b & ECON1_BSEL0)
209 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
210 ECON1_BSEL0);
211 else
212 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
213 ECON1_BSEL0);
214 }
215 if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
216 if (b & ECON1_BSEL1)
217 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
218 ECON1_BSEL1);
219 else
220 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
221 ECON1_BSEL1);
222 }
223 priv->bank = b;
224}
225
226/*
227 * Register access routines through the SPI bus.
228 * Every register access comes in two flavours:
229 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
230 * atomically more than one register
231 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
232 *
233 * Some registers can be accessed through the bit field clear and
234 * bit field set to avoid a read modify write cycle.
235 */
236
237/*
238 * Register bit field Set
239 */
240static void nolock_reg_bfset(struct enc28j60_net *priv,
241 u8 addr, u8 mask)
242{
243 enc28j60_set_bank(priv, addr);
244 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
245}
246
247static void locked_reg_bfset(struct enc28j60_net *priv,
248 u8 addr, u8 mask)
249{
250 mutex_lock(&priv->lock);
251 nolock_reg_bfset(priv, addr, mask);
252 mutex_unlock(&priv->lock);
253}
254
255/*
256 * Register bit field Clear
257 */
258static void nolock_reg_bfclr(struct enc28j60_net *priv,
259 u8 addr, u8 mask)
260{
261 enc28j60_set_bank(priv, addr);
262 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
263}
264
265static void locked_reg_bfclr(struct enc28j60_net *priv,
266 u8 addr, u8 mask)
267{
268 mutex_lock(&priv->lock);
269 nolock_reg_bfclr(priv, addr, mask);
270 mutex_unlock(&priv->lock);
271}
272
273/*
274 * Register byte read
275 */
276static int nolock_regb_read(struct enc28j60_net *priv,
277 u8 address)
278{
279 enc28j60_set_bank(priv, address);
280 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
281}
282
283static int locked_regb_read(struct enc28j60_net *priv,
284 u8 address)
285{
286 int ret;
287
288 mutex_lock(&priv->lock);
289 ret = nolock_regb_read(priv, address);
290 mutex_unlock(&priv->lock);
291
292 return ret;
293}
294
295/*
296 * Register word read
297 */
298static int nolock_regw_read(struct enc28j60_net *priv,
299 u8 address)
300{
301 int rl, rh;
302
303 enc28j60_set_bank(priv, address);
304 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
305 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
306
307 return (rh << 8) | rl;
308}
309
310static int locked_regw_read(struct enc28j60_net *priv,
311 u8 address)
312{
313 int ret;
314
315 mutex_lock(&priv->lock);
316 ret = nolock_regw_read(priv, address);
317 mutex_unlock(&priv->lock);
318
319 return ret;
320}
321
322/*
323 * Register byte write
324 */
325static void nolock_regb_write(struct enc28j60_net *priv,
326 u8 address, u8 data)
327{
328 enc28j60_set_bank(priv, address);
329 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
330}
331
332static void locked_regb_write(struct enc28j60_net *priv,
333 u8 address, u8 data)
334{
335 mutex_lock(&priv->lock);
336 nolock_regb_write(priv, address, data);
337 mutex_unlock(&priv->lock);
338}
339
340/*
341 * Register word write
342 */
343static void nolock_regw_write(struct enc28j60_net *priv,
344 u8 address, u16 data)
345{
346 enc28j60_set_bank(priv, address);
347 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
348 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
349 (u8) (data >> 8));
350}
351
352static void locked_regw_write(struct enc28j60_net *priv,
353 u8 address, u16 data)
354{
355 mutex_lock(&priv->lock);
356 nolock_regw_write(priv, address, data);
357 mutex_unlock(&priv->lock);
358}
359
360/*
361 * Buffer memory read
362 * Select the starting address and execute a SPI buffer read
363 */
364static void enc28j60_mem_read(struct enc28j60_net *priv,
365 u16 addr, int len, u8 *data)
366{
367 mutex_lock(&priv->lock);
368 nolock_regw_write(priv, ERDPTL, addr);
369#ifdef CONFIG_ENC28J60_WRITEVERIFY
370 if (netif_msg_drv(priv)) {
371 u16 reg;
372 reg = nolock_regw_read(priv, ERDPTL);
373 if (reg != addr)
374 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
375 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
376 }
377#endif
378 spi_read_buf(priv, len, data);
379 mutex_unlock(&priv->lock);
380}
381
382/*
383 * Write packet to enc28j60 TX buffer memory
384 */
385static void
386enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
387{
388 mutex_lock(&priv->lock);
389 /* Set the write pointer to start of transmit buffer area */
390 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
391#ifdef CONFIG_ENC28J60_WRITEVERIFY
392 if (netif_msg_drv(priv)) {
393 u16 reg;
394 reg = nolock_regw_read(priv, EWRPTL);
395 if (reg != TXSTART_INIT)
396 printk(KERN_DEBUG DRV_NAME
397 ": %s() ERWPT:0x%04x != 0x%04x\n",
398 __func__, reg, TXSTART_INIT);
399 }
400#endif
401 /* Set the TXND pointer to correspond to the packet size given */
402 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
403 /* write per-packet control byte */
404 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
405 if (netif_msg_hw(priv))
406 printk(KERN_DEBUG DRV_NAME
407 ": %s() after control byte ERWPT:0x%04x\n",
408 __func__, nolock_regw_read(priv, EWRPTL));
409 /* copy the packet into the transmit buffer */
410 spi_write_buf(priv, len, data);
411 if (netif_msg_hw(priv))
412 printk(KERN_DEBUG DRV_NAME
413 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
414 __func__, nolock_regw_read(priv, EWRPTL), len);
415 mutex_unlock(&priv->lock);
416}
417
418static unsigned long msec20_to_jiffies;
419
420static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
421{
422 unsigned long timeout = jiffies + msec20_to_jiffies;
423
424 /* 20 msec timeout read */
425 while ((nolock_regb_read(priv, reg) & mask) != val) {
426 if (time_after(jiffies, timeout)) {
427 if (netif_msg_drv(priv))
428 dev_dbg(&priv->spi->dev,
429 "reg %02x ready timeout!\n", reg);
430 return -ETIMEDOUT;
431 }
432 cpu_relax();
433 }
434 return 0;
435}
436
437/*
438 * Wait until the PHY operation is complete.
439 */
440static int wait_phy_ready(struct enc28j60_net *priv)
441{
442 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
443}
444
445/*
446 * PHY register read
447 * PHY registers are not accessed directly, but through the MII
448 */
449static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
450{
451 u16 ret;
452
453 mutex_lock(&priv->lock);
454 /* set the PHY register address */
455 nolock_regb_write(priv, MIREGADR, address);
456 /* start the register read operation */
457 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
458 /* wait until the PHY read completes */
459 wait_phy_ready(priv);
460 /* quit reading */
461 nolock_regb_write(priv, MICMD, 0x00);
462 /* return the data */
463 ret = nolock_regw_read(priv, MIRDL);
464 mutex_unlock(&priv->lock);
465
466 return ret;
467}
468
469static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
470{
471 int ret;
472
473 mutex_lock(&priv->lock);
474 /* set the PHY register address */
475 nolock_regb_write(priv, MIREGADR, address);
476 /* write the PHY data */
477 nolock_regw_write(priv, MIWRL, data);
478 /* wait until the PHY write completes and return */
479 ret = wait_phy_ready(priv);
480 mutex_unlock(&priv->lock);
481
482 return ret;
483}
484
485/*
486 * Program the hardware MAC address from dev->dev_addr.
487 */
488static int enc28j60_set_hw_macaddr(struct net_device *ndev)
489{
490 int ret;
491 struct enc28j60_net *priv = netdev_priv(ndev);
492
493 mutex_lock(&priv->lock);
494 if (!priv->hw_enable) {
495 if (netif_msg_drv(priv))
496 printk(KERN_INFO DRV_NAME
497 ": %s: Setting MAC address to %pM\n",
498 ndev->name, ndev->dev_addr);
499 /* NOTE: MAC address in ENC28J60 is byte-backward */
500 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
501 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
502 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
503 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
504 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
505 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
506 ret = 0;
507 } else {
508 if (netif_msg_drv(priv))
509 printk(KERN_DEBUG DRV_NAME
510 ": %s() Hardware must be disabled to set "
511 "Mac address\n", __func__);
512 ret = -EBUSY;
513 }
514 mutex_unlock(&priv->lock);
515 return ret;
516}
517
518/*
519 * Store the new hardware address in dev->dev_addr, and update the MAC.
520 */
521static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
522{
523 struct sockaddr *address = addr;
524
525 if (netif_running(dev))
526 return -EBUSY;
527 if (!is_valid_ether_addr(address->sa_data))
528 return -EADDRNOTAVAIL;
529
530 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
531 return enc28j60_set_hw_macaddr(dev);
532}
533
534/*
535 * Debug routine to dump useful register contents
536 */
537static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
538{
539 mutex_lock(&priv->lock);
540 printk(KERN_DEBUG DRV_NAME " %s\n"
541 "HwRevID: 0x%02x\n"
542 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
543 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
544 "MAC : MACON1 MACON3 MACON4\n"
545 " 0x%02x 0x%02x 0x%02x\n"
546 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
547 " 0x%04x 0x%04x 0x%04x 0x%04x "
548 "0x%02x 0x%02x 0x%04x\n"
549 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
550 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
551 msg, nolock_regb_read(priv, EREVID),
552 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
553 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
554 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
555 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
556 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
557 nolock_regw_read(priv, ERXWRPTL),
558 nolock_regw_read(priv, ERXRDPTL),
559 nolock_regb_read(priv, ERXFCON),
560 nolock_regb_read(priv, EPKTCNT),
561 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
562 nolock_regw_read(priv, ETXNDL),
563 nolock_regb_read(priv, MACLCON1),
564 nolock_regb_read(priv, MACLCON2),
565 nolock_regb_read(priv, MAPHSUP));
566 mutex_unlock(&priv->lock);
567}
568
569/*
570 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
571 */
572static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
573{
574 u16 erxrdpt;
575
576 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
577 erxrdpt = end;
578 else
579 erxrdpt = next_packet_ptr - 1;
580
581 return erxrdpt;
582}
583
584/*
585 * Calculate wrap around when reading beyond the end of the RX buffer
586 */
587static u16 rx_packet_start(u16 ptr)
588{
589 if (ptr + RSV_SIZE > RXEND_INIT)
590 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
591 else
592 return ptr + RSV_SIZE;
593}
594
595static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
596{
597 u16 erxrdpt;
598
599 if (start > 0x1FFF || end > 0x1FFF || start > end) {
600 if (netif_msg_drv(priv))
601 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
602 "bad parameters!\n", __func__, start, end);
603 return;
604 }
605 /* set receive buffer start + end */
606 priv->next_pk_ptr = start;
607 nolock_regw_write(priv, ERXSTL, start);
608 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
609 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
610 nolock_regw_write(priv, ERXNDL, end);
611}
612
613static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
614{
615 if (start > 0x1FFF || end > 0x1FFF || start > end) {
616 if (netif_msg_drv(priv))
617 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
618 "bad parameters!\n", __func__, start, end);
619 return;
620 }
621 /* set transmit buffer start + end */
622 nolock_regw_write(priv, ETXSTL, start);
623 nolock_regw_write(priv, ETXNDL, end);
624}
625
626/*
627 * Low power mode shrinks power consumption about 100x, so we'd like
628 * the chip to be in that mode whenever it's inactive. (However, we
629 * can't stay in lowpower mode during suspend with WOL active.)
630 */
631static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
632{
633 if (netif_msg_drv(priv))
634 dev_dbg(&priv->spi->dev, "%s power...\n",
635 is_low ? "low" : "high");
636
637 mutex_lock(&priv->lock);
638 if (is_low) {
639 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
640 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
641 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
642 /* ECON2_VRPS was set during initialization */
643 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
644 } else {
645 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
646 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
647 /* caller sets ECON1_RXEN */
648 }
649 mutex_unlock(&priv->lock);
650}
651
652static int enc28j60_hw_init(struct enc28j60_net *priv)
653{
654 u8 reg;
655
656 if (netif_msg_drv(priv))
657 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
658 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
659
660 mutex_lock(&priv->lock);
661 /* first reset the chip */
662 enc28j60_soft_reset(priv);
663 /* Clear ECON1 */
664 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
665 priv->bank = 0;
666 priv->hw_enable = false;
667 priv->tx_retry_count = 0;
668 priv->max_pk_counter = 0;
669 priv->rxfilter = RXFILTER_NORMAL;
670 /* enable address auto increment and voltage regulator powersave */
671 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
672
673 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
674 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
675 mutex_unlock(&priv->lock);
676
677 /*
678 * Check the RevID.
679 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
680 * damaged
681 */
682 reg = locked_regb_read(priv, EREVID);
683 if (netif_msg_drv(priv))
684 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
685 if (reg == 0x00 || reg == 0xff) {
686 if (netif_msg_drv(priv))
687 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
688 __func__, reg);
689 return 0;
690 }
691
692 /* default filter mode: (unicast OR broadcast) AND crc valid */
693 locked_regb_write(priv, ERXFCON,
694 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
695
696 /* enable MAC receive */
697 locked_regb_write(priv, MACON1,
698 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
699 /* enable automatic padding and CRC operations */
700 if (priv->full_duplex) {
701 locked_regb_write(priv, MACON3,
702 MACON3_PADCFG0 | MACON3_TXCRCEN |
703 MACON3_FRMLNEN | MACON3_FULDPX);
704 /* set inter-frame gap (non-back-to-back) */
705 locked_regb_write(priv, MAIPGL, 0x12);
706 /* set inter-frame gap (back-to-back) */
707 locked_regb_write(priv, MABBIPG, 0x15);
708 } else {
709 locked_regb_write(priv, MACON3,
710 MACON3_PADCFG0 | MACON3_TXCRCEN |
711 MACON3_FRMLNEN);
712 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
713 /* set inter-frame gap (non-back-to-back) */
714 locked_regw_write(priv, MAIPGL, 0x0C12);
715 /* set inter-frame gap (back-to-back) */
716 locked_regb_write(priv, MABBIPG, 0x12);
717 }
718 /*
719 * MACLCON1 (default)
720 * MACLCON2 (default)
721 * Set the maximum packet size which the controller will accept
722 */
723 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
724
725 /* Configure LEDs */
726 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
727 return 0;
728
729 if (priv->full_duplex) {
730 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
731 return 0;
732 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
733 return 0;
734 } else {
735 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
736 return 0;
737 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
738 return 0;
739 }
740 if (netif_msg_hw(priv))
741 enc28j60_dump_regs(priv, "Hw initialized.");
742
743 return 1;
744}
745
746static void enc28j60_hw_enable(struct enc28j60_net *priv)
747{
748 /* enable interrupts */
749 if (netif_msg_hw(priv))
750 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
751 __func__);
752
753 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
754
755 mutex_lock(&priv->lock);
756 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
757 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
758 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
759 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
760
761 /* enable receive logic */
762 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
763 priv->hw_enable = true;
764 mutex_unlock(&priv->lock);
765}
766
767static void enc28j60_hw_disable(struct enc28j60_net *priv)
768{
769 mutex_lock(&priv->lock);
770 /* disable interrutps and packet reception */
771 nolock_regb_write(priv, EIE, 0x00);
772 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
773 priv->hw_enable = false;
774 mutex_unlock(&priv->lock);
775}
776
777static int
778enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
779{
780 struct enc28j60_net *priv = netdev_priv(ndev);
781 int ret = 0;
782
783 if (!priv->hw_enable) {
784 /* link is in low power mode now; duplex setting
785 * will take effect on next enc28j60_hw_init().
786 */
787 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
788 priv->full_duplex = (duplex == DUPLEX_FULL);
789 else {
790 if (netif_msg_link(priv))
791 dev_warn(&ndev->dev,
792 "unsupported link setting\n");
793 ret = -EOPNOTSUPP;
794 }
795 } else {
796 if (netif_msg_link(priv))
797 dev_warn(&ndev->dev, "Warning: hw must be disabled "
798 "to set link mode\n");
799 ret = -EBUSY;
800 }
801 return ret;
802}
803
804/*
805 * Read the Transmit Status Vector
806 */
807static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
808{
809 int endptr;
810
811 endptr = locked_regw_read(priv, ETXNDL);
812 if (netif_msg_hw(priv))
813 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
814 endptr + 1);
815 enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
816}
817
818static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
819 u8 tsv[TSV_SIZE])
820{
821 u16 tmp1, tmp2;
822
823 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
824 tmp1 = tsv[1];
825 tmp1 <<= 8;
826 tmp1 |= tsv[0];
827
828 tmp2 = tsv[5];
829 tmp2 <<= 8;
830 tmp2 |= tsv[4];
831
832 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
833 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
834 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
835 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
836 TSV_GETBIT(tsv, TSV_TXCRCERROR),
837 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
838 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
839 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
840 "PacketDefer: %d, ExDefer: %d\n",
841 TSV_GETBIT(tsv, TSV_TXMULTICAST),
842 TSV_GETBIT(tsv, TSV_TXBROADCAST),
843 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
844 TSV_GETBIT(tsv, TSV_TXEXDEFER));
845 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
846 "Giant: %d, Underrun: %d\n",
847 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
848 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
849 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
850 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
851 "BackPressApp: %d, VLanTagFrame: %d\n",
852 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
853 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
854 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
855 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
856}
857
858/*
859 * Receive Status vector
860 */
861static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
862 u16 pk_ptr, int len, u16 sts)
863{
864 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
865 msg, pk_ptr);
866 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
867 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
868 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
869 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
870 RSV_GETBIT(sts, RSV_CRCERROR),
871 RSV_GETBIT(sts, RSV_LENCHECKERR),
872 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
873 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
874 "LongDropEvent: %d, CarrierEvent: %d\n",
875 RSV_GETBIT(sts, RSV_RXMULTICAST),
876 RSV_GETBIT(sts, RSV_RXBROADCAST),
877 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
878 RSV_GETBIT(sts, RSV_CARRIEREV));
879 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
880 " UnknownOp: %d, VLanTagFrame: %d\n",
881 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
882 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
883 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
884 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
885}
886
887static void dump_packet(const char *msg, int len, const char *data)
888{
889 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
890 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
891 data, len, true);
892}
893
894/*
895 * Hardware receive function.
896 * Read the buffer memory, update the FIFO pointer to free the buffer,
897 * check the status vector and decrement the packet counter.
898 */
899static void enc28j60_hw_rx(struct net_device *ndev)
900{
901 struct enc28j60_net *priv = netdev_priv(ndev);
902 struct sk_buff *skb = NULL;
903 u16 erxrdpt, next_packet, rxstat;
904 u8 rsv[RSV_SIZE];
905 int len;
906
907 if (netif_msg_rx_status(priv))
908 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
909 priv->next_pk_ptr);
910
911 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
912 if (netif_msg_rx_err(priv))
913 dev_err(&ndev->dev,
914 "%s() Invalid packet address!! 0x%04x\n",
915 __func__, priv->next_pk_ptr);
916 /* packet address corrupted: reset RX logic */
917 mutex_lock(&priv->lock);
918 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
919 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
920 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
921 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
922 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
923 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
924 mutex_unlock(&priv->lock);
925 ndev->stats.rx_errors++;
926 return;
927 }
928 /* Read next packet pointer and rx status vector */
929 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
930
931 next_packet = rsv[1];
932 next_packet <<= 8;
933 next_packet |= rsv[0];
934
935 len = rsv[3];
936 len <<= 8;
937 len |= rsv[2];
938
939 rxstat = rsv[5];
940 rxstat <<= 8;
941 rxstat |= rsv[4];
942
943 if (netif_msg_rx_status(priv))
944 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
945
946 if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
947 if (netif_msg_rx_err(priv))
948 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
949 ndev->stats.rx_errors++;
950 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
951 ndev->stats.rx_crc_errors++;
952 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
953 ndev->stats.rx_frame_errors++;
954 if (len > MAX_FRAMELEN)
955 ndev->stats.rx_over_errors++;
956 } else {
957 skb = dev_alloc_skb(len + NET_IP_ALIGN);
958 if (!skb) {
959 if (netif_msg_rx_err(priv))
960 dev_err(&ndev->dev,
961 "out of memory for Rx'd frame\n");
962 ndev->stats.rx_dropped++;
963 } else {
964 skb->dev = ndev;
965 skb_reserve(skb, NET_IP_ALIGN);
966 /* copy the packet from the receive buffer */
967 enc28j60_mem_read(priv,
968 rx_packet_start(priv->next_pk_ptr),
969 len, skb_put(skb, len));
970 if (netif_msg_pktdata(priv))
971 dump_packet(__func__, skb->len, skb->data);
972 skb->protocol = eth_type_trans(skb, ndev);
973 /* update statistics */
974 ndev->stats.rx_packets++;
975 ndev->stats.rx_bytes += len;
976 netif_rx_ni(skb);
977 }
978 }
979 /*
980 * Move the RX read pointer to the start of the next
981 * received packet.
982 * This frees the memory we just read out
983 */
984 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
985 if (netif_msg_hw(priv))
986 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
987 __func__, erxrdpt);
988
989 mutex_lock(&priv->lock);
990 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
991#ifdef CONFIG_ENC28J60_WRITEVERIFY
992 if (netif_msg_drv(priv)) {
993 u16 reg;
994 reg = nolock_regw_read(priv, ERXRDPTL);
995 if (reg != erxrdpt)
996 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
997 "error (0x%04x - 0x%04x)\n", __func__,
998 reg, erxrdpt);
999 }
1000#endif
1001 priv->next_pk_ptr = next_packet;
1002 /* we are done with this packet, decrement the packet counter */
1003 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1004 mutex_unlock(&priv->lock);
1005}
1006
1007/*
1008 * Calculate free space in RxFIFO
1009 */
1010static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1011{
1012 int epkcnt, erxst, erxnd, erxwr, erxrd;
1013 int free_space;
1014
1015 mutex_lock(&priv->lock);
1016 epkcnt = nolock_regb_read(priv, EPKTCNT);
1017 if (epkcnt >= 255)
1018 free_space = -1;
1019 else {
1020 erxst = nolock_regw_read(priv, ERXSTL);
1021 erxnd = nolock_regw_read(priv, ERXNDL);
1022 erxwr = nolock_regw_read(priv, ERXWRPTL);
1023 erxrd = nolock_regw_read(priv, ERXRDPTL);
1024
1025 if (erxwr > erxrd)
1026 free_space = (erxnd - erxst) - (erxwr - erxrd);
1027 else if (erxwr == erxrd)
1028 free_space = (erxnd - erxst);
1029 else
1030 free_space = erxrd - erxwr - 1;
1031 }
1032 mutex_unlock(&priv->lock);
1033 if (netif_msg_rx_status(priv))
1034 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
1035 __func__, free_space);
1036 return free_space;
1037}
1038
1039/*
1040 * Access the PHY to determine link status
1041 */
1042static void enc28j60_check_link_status(struct net_device *ndev)
1043{
1044 struct enc28j60_net *priv = netdev_priv(ndev);
1045 u16 reg;
1046 int duplex;
1047
1048 reg = enc28j60_phy_read(priv, PHSTAT2);
1049 if (netif_msg_hw(priv))
1050 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1051 "PHSTAT2: %04x\n", __func__,
1052 enc28j60_phy_read(priv, PHSTAT1), reg);
1053 duplex = reg & PHSTAT2_DPXSTAT;
1054
1055 if (reg & PHSTAT2_LSTAT) {
1056 netif_carrier_on(ndev);
1057 if (netif_msg_ifup(priv))
1058 dev_info(&ndev->dev, "link up - %s\n",
1059 duplex ? "Full duplex" : "Half duplex");
1060 } else {
1061 if (netif_msg_ifdown(priv))
1062 dev_info(&ndev->dev, "link down\n");
1063 netif_carrier_off(ndev);
1064 }
1065}
1066
1067static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1068{
1069 struct enc28j60_net *priv = netdev_priv(ndev);
1070
1071 if (err)
1072 ndev->stats.tx_errors++;
1073 else
1074 ndev->stats.tx_packets++;
1075
1076 if (priv->tx_skb) {
1077 if (!err)
1078 ndev->stats.tx_bytes += priv->tx_skb->len;
1079 dev_kfree_skb(priv->tx_skb);
1080 priv->tx_skb = NULL;
1081 }
1082 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1083 netif_wake_queue(ndev);
1084}
1085
1086/*
1087 * RX handler
1088 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1089 * check EPKTCNT is the suggested workaround.
1090 * We don't need to clear interrupt flag, automatically done when
1091 * enc28j60_hw_rx() decrements the packet counter.
1092 * Returns how many packet processed.
1093 */
1094static int enc28j60_rx_interrupt(struct net_device *ndev)
1095{
1096 struct enc28j60_net *priv = netdev_priv(ndev);
1097 int pk_counter, ret;
1098
1099 pk_counter = locked_regb_read(priv, EPKTCNT);
1100 if (pk_counter && netif_msg_intr(priv))
1101 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1102 if (pk_counter > priv->max_pk_counter) {
1103 /* update statistics */
1104 priv->max_pk_counter = pk_counter;
1105 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1106 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1107 priv->max_pk_counter);
1108 }
1109 ret = pk_counter;
1110 while (pk_counter-- > 0)
1111 enc28j60_hw_rx(ndev);
1112
1113 return ret;
1114}
1115
1116static void enc28j60_irq_work_handler(struct work_struct *work)
1117{
1118 struct enc28j60_net *priv =
1119 container_of(work, struct enc28j60_net, irq_work);
1120 struct net_device *ndev = priv->netdev;
1121 int intflags, loop;
1122
1123 if (netif_msg_intr(priv))
1124 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1125 /* disable further interrupts */
1126 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1127
1128 do {
1129 loop = 0;
1130 intflags = locked_regb_read(priv, EIR);
1131 /* DMA interrupt handler (not currently used) */
1132 if ((intflags & EIR_DMAIF) != 0) {
1133 loop++;
1134 if (netif_msg_intr(priv))
1135 printk(KERN_DEBUG DRV_NAME
1136 ": intDMA(%d)\n", loop);
1137 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1138 }
1139 /* LINK changed handler */
1140 if ((intflags & EIR_LINKIF) != 0) {
1141 loop++;
1142 if (netif_msg_intr(priv))
1143 printk(KERN_DEBUG DRV_NAME
1144 ": intLINK(%d)\n", loop);
1145 enc28j60_check_link_status(ndev);
1146 /* read PHIR to clear the flag */
1147 enc28j60_phy_read(priv, PHIR);
1148 }
1149 /* TX complete handler */
1150 if ((intflags & EIR_TXIF) != 0) {
1151 bool err = false;
1152 loop++;
1153 if (netif_msg_intr(priv))
1154 printk(KERN_DEBUG DRV_NAME
1155 ": intTX(%d)\n", loop);
1156 priv->tx_retry_count = 0;
1157 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1158 if (netif_msg_tx_err(priv))
1159 dev_err(&ndev->dev,
1160 "Tx Error (aborted)\n");
1161 err = true;
1162 }
1163 if (netif_msg_tx_done(priv)) {
1164 u8 tsv[TSV_SIZE];
1165 enc28j60_read_tsv(priv, tsv);
1166 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1167 }
1168 enc28j60_tx_clear(ndev, err);
1169 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1170 }
1171 /* TX Error handler */
1172 if ((intflags & EIR_TXERIF) != 0) {
1173 u8 tsv[TSV_SIZE];
1174
1175 loop++;
1176 if (netif_msg_intr(priv))
1177 printk(KERN_DEBUG DRV_NAME
1178 ": intTXErr(%d)\n", loop);
1179 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1180 enc28j60_read_tsv(priv, tsv);
1181 if (netif_msg_tx_err(priv))
1182 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1183 /* Reset TX logic */
1184 mutex_lock(&priv->lock);
1185 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1186 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1187 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1188 mutex_unlock(&priv->lock);
1189 /* Transmit Late collision check for retransmit */
1190 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1191 if (netif_msg_tx_err(priv))
1192 printk(KERN_DEBUG DRV_NAME
1193 ": LateCollision TXErr (%d)\n",
1194 priv->tx_retry_count);
1195 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1196 locked_reg_bfset(priv, ECON1,
1197 ECON1_TXRTS);
1198 else
1199 enc28j60_tx_clear(ndev, true);
1200 } else
1201 enc28j60_tx_clear(ndev, true);
1202 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1203 }
1204 /* RX Error handler */
1205 if ((intflags & EIR_RXERIF) != 0) {
1206 loop++;
1207 if (netif_msg_intr(priv))
1208 printk(KERN_DEBUG DRV_NAME
1209 ": intRXErr(%d)\n", loop);
1210 /* Check free FIFO space to flag RX overrun */
1211 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1212 if (netif_msg_rx_err(priv))
1213 printk(KERN_DEBUG DRV_NAME
1214 ": RX Overrun\n");
1215 ndev->stats.rx_dropped++;
1216 }
1217 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1218 }
1219 /* RX handler */
1220 if (enc28j60_rx_interrupt(ndev))
1221 loop++;
1222 } while (loop);
1223
1224 /* re-enable interrupts */
1225 locked_reg_bfset(priv, EIE, EIE_INTIE);
1226 if (netif_msg_intr(priv))
1227 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
1228}
1229
1230/*
1231 * Hardware transmit function.
1232 * Fill the buffer memory and send the contents of the transmit buffer
1233 * onto the network
1234 */
1235static void enc28j60_hw_tx(struct enc28j60_net *priv)
1236{
1237 if (netif_msg_tx_queued(priv))
1238 printk(KERN_DEBUG DRV_NAME
1239 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1240
1241 if (netif_msg_pktdata(priv))
1242 dump_packet(__func__,
1243 priv->tx_skb->len, priv->tx_skb->data);
1244 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1245
1246#ifdef CONFIG_ENC28J60_WRITEVERIFY
1247 /* readback and verify written data */
1248 if (netif_msg_drv(priv)) {
1249 int test_len, k;
1250 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1251 int okflag;
1252
1253 test_len = priv->tx_skb->len;
1254 if (test_len > sizeof(test_buf))
1255 test_len = sizeof(test_buf);
1256
1257 /* + 1 to skip control byte */
1258 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1259 okflag = 1;
1260 for (k = 0; k < test_len; k++) {
1261 if (priv->tx_skb->data[k] != test_buf[k]) {
1262 printk(KERN_DEBUG DRV_NAME
1263 ": Error, %d location differ: "
1264 "0x%02x-0x%02x\n", k,
1265 priv->tx_skb->data[k], test_buf[k]);
1266 okflag = 0;
1267 }
1268 }
1269 if (!okflag)
1270 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1271 "verify ERROR!\n");
1272 }
1273#endif
1274 /* set TX request flag */
1275 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1276}
1277
1278static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1279 struct net_device *dev)
1280{
1281 struct enc28j60_net *priv = netdev_priv(dev);
1282
1283 if (netif_msg_tx_queued(priv))
1284 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1285
1286 /* If some error occurs while trying to transmit this
1287 * packet, you should return '1' from this function.
1288 * In such a case you _may not_ do anything to the
1289 * SKB, it is still owned by the network queueing
1290 * layer when an error is returned. This means you
1291 * may not modify any SKB fields, you may not free
1292 * the SKB, etc.
1293 */
1294 netif_stop_queue(dev);
1295
1296 /* Remember the skb for deferred processing */
1297 priv->tx_skb = skb;
1298 schedule_work(&priv->tx_work);
1299
1300 return NETDEV_TX_OK;
1301}
1302
1303static void enc28j60_tx_work_handler(struct work_struct *work)
1304{
1305 struct enc28j60_net *priv =
1306 container_of(work, struct enc28j60_net, tx_work);
1307
1308 /* actual delivery of data */
1309 enc28j60_hw_tx(priv);
1310}
1311
1312static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1313{
1314 struct enc28j60_net *priv = dev_id;
1315
1316 /*
1317 * Can't do anything in interrupt context because we need to
1318 * block (spi_sync() is blocking) so fire of the interrupt
1319 * handling workqueue.
1320 * Remember that we access enc28j60 registers through SPI bus
1321 * via spi_sync() call.
1322 */
1323 schedule_work(&priv->irq_work);
1324
1325 return IRQ_HANDLED;
1326}
1327
1328static void enc28j60_tx_timeout(struct net_device *ndev)
1329{
1330 struct enc28j60_net *priv = netdev_priv(ndev);
1331
1332 if (netif_msg_timer(priv))
1333 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1334
1335 ndev->stats.tx_errors++;
1336 /* can't restart safely under softirq */
1337 schedule_work(&priv->restart_work);
1338}
1339
1340/*
1341 * Open/initialize the board. This is called (in the current kernel)
1342 * sometime after booting when the 'ifconfig' program is run.
1343 *
1344 * This routine should set everything up anew at each open, even
1345 * registers that "should" only need to be set once at boot, so that
1346 * there is non-reboot way to recover if something goes wrong.
1347 */
1348static int enc28j60_net_open(struct net_device *dev)
1349{
1350 struct enc28j60_net *priv = netdev_priv(dev);
1351
1352 if (netif_msg_drv(priv))
1353 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1354
1355 if (!is_valid_ether_addr(dev->dev_addr)) {
1356 if (netif_msg_ifup(priv))
1357 dev_err(&dev->dev, "invalid MAC address %pM\n",
1358 dev->dev_addr);
1359 return -EADDRNOTAVAIL;
1360 }
1361 /* Reset the hardware here (and take it out of low power mode) */
1362 enc28j60_lowpower(priv, false);
1363 enc28j60_hw_disable(priv);
1364 if (!enc28j60_hw_init(priv)) {
1365 if (netif_msg_ifup(priv))
1366 dev_err(&dev->dev, "hw_reset() failed\n");
1367 return -EINVAL;
1368 }
1369 /* Update the MAC address (in case user has changed it) */
1370 enc28j60_set_hw_macaddr(dev);
1371 /* Enable interrupts */
1372 enc28j60_hw_enable(priv);
1373 /* check link status */
1374 enc28j60_check_link_status(dev);
1375 /* We are now ready to accept transmit requests from
1376 * the queueing layer of the networking.
1377 */
1378 netif_start_queue(dev);
1379
1380 return 0;
1381}
1382
1383/* The inverse routine to net_open(). */
1384static int enc28j60_net_close(struct net_device *dev)
1385{
1386 struct enc28j60_net *priv = netdev_priv(dev);
1387
1388 if (netif_msg_drv(priv))
1389 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1390
1391 enc28j60_hw_disable(priv);
1392 enc28j60_lowpower(priv, true);
1393 netif_stop_queue(dev);
1394
1395 return 0;
1396}
1397
1398/*
1399 * Set or clear the multicast filter for this adapter
1400 * num_addrs == -1 Promiscuous mode, receive all packets
1401 * num_addrs == 0 Normal mode, filter out multicast packets
1402 * num_addrs > 0 Multicast mode, receive normal and MC packets
1403 */
1404static void enc28j60_set_multicast_list(struct net_device *dev)
1405{
1406 struct enc28j60_net *priv = netdev_priv(dev);
1407 int oldfilter = priv->rxfilter;
1408
1409 if (dev->flags & IFF_PROMISC) {
1410 if (netif_msg_link(priv))
1411 dev_info(&dev->dev, "promiscuous mode\n");
1412 priv->rxfilter = RXFILTER_PROMISC;
1413 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1414 if (netif_msg_link(priv))
1415 dev_info(&dev->dev, "%smulticast mode\n",
1416 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1417 priv->rxfilter = RXFILTER_MULTI;
1418 } else {
1419 if (netif_msg_link(priv))
1420 dev_info(&dev->dev, "normal mode\n");
1421 priv->rxfilter = RXFILTER_NORMAL;
1422 }
1423
1424 if (oldfilter != priv->rxfilter)
1425 schedule_work(&priv->setrx_work);
1426}
1427
1428static void enc28j60_setrx_work_handler(struct work_struct *work)
1429{
1430 struct enc28j60_net *priv =
1431 container_of(work, struct enc28j60_net, setrx_work);
1432
1433 if (priv->rxfilter == RXFILTER_PROMISC) {
1434 if (netif_msg_drv(priv))
1435 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1436 locked_regb_write(priv, ERXFCON, 0x00);
1437 } else if (priv->rxfilter == RXFILTER_MULTI) {
1438 if (netif_msg_drv(priv))
1439 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1440 locked_regb_write(priv, ERXFCON,
1441 ERXFCON_UCEN | ERXFCON_CRCEN |
1442 ERXFCON_BCEN | ERXFCON_MCEN);
1443 } else {
1444 if (netif_msg_drv(priv))
1445 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1446 locked_regb_write(priv, ERXFCON,
1447 ERXFCON_UCEN | ERXFCON_CRCEN |
1448 ERXFCON_BCEN);
1449 }
1450}
1451
1452static void enc28j60_restart_work_handler(struct work_struct *work)
1453{
1454 struct enc28j60_net *priv =
1455 container_of(work, struct enc28j60_net, restart_work);
1456 struct net_device *ndev = priv->netdev;
1457 int ret;
1458
1459 rtnl_lock();
1460 if (netif_running(ndev)) {
1461 enc28j60_net_close(ndev);
1462 ret = enc28j60_net_open(ndev);
1463 if (unlikely(ret)) {
1464 dev_info(&ndev->dev, " could not restart %d\n", ret);
1465 dev_close(ndev);
1466 }
1467 }
1468 rtnl_unlock();
1469}
1470
1471/* ......................... ETHTOOL SUPPORT ........................... */
1472
1473static void
1474enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1475{
1476 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1477 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1478 strlcpy(info->bus_info,
1479 dev_name(dev->dev.parent), sizeof(info->bus_info));
1480}
1481
1482static int
1483enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1484{
1485 struct enc28j60_net *priv = netdev_priv(dev);
1486
1487 cmd->transceiver = XCVR_INTERNAL;
1488 cmd->supported = SUPPORTED_10baseT_Half
1489 | SUPPORTED_10baseT_Full
1490 | SUPPORTED_TP;
1491 ethtool_cmd_speed_set(cmd, SPEED_10);
1492 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1493 cmd->port = PORT_TP;
1494 cmd->autoneg = AUTONEG_DISABLE;
1495
1496 return 0;
1497}
1498
1499static int
1500enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1501{
1502 return enc28j60_setlink(dev, cmd->autoneg,
1503 ethtool_cmd_speed(cmd), cmd->duplex);
1504}
1505
1506static u32 enc28j60_get_msglevel(struct net_device *dev)
1507{
1508 struct enc28j60_net *priv = netdev_priv(dev);
1509 return priv->msg_enable;
1510}
1511
1512static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1513{
1514 struct enc28j60_net *priv = netdev_priv(dev);
1515 priv->msg_enable = val;
1516}
1517
1518static const struct ethtool_ops enc28j60_ethtool_ops = {
1519 .get_settings = enc28j60_get_settings,
1520 .set_settings = enc28j60_set_settings,
1521 .get_drvinfo = enc28j60_get_drvinfo,
1522 .get_msglevel = enc28j60_get_msglevel,
1523 .set_msglevel = enc28j60_set_msglevel,
1524};
1525
1526static int enc28j60_chipset_init(struct net_device *dev)
1527{
1528 struct enc28j60_net *priv = netdev_priv(dev);
1529
1530 return enc28j60_hw_init(priv);
1531}
1532
1533static const struct net_device_ops enc28j60_netdev_ops = {
1534 .ndo_open = enc28j60_net_open,
1535 .ndo_stop = enc28j60_net_close,
1536 .ndo_start_xmit = enc28j60_send_packet,
1537 .ndo_set_multicast_list = enc28j60_set_multicast_list,
1538 .ndo_set_mac_address = enc28j60_set_mac_address,
1539 .ndo_tx_timeout = enc28j60_tx_timeout,
1540 .ndo_change_mtu = eth_change_mtu,
1541 .ndo_validate_addr = eth_validate_addr,
1542};
1543
1544static int __devinit enc28j60_probe(struct spi_device *spi)
1545{
1546 struct net_device *dev;
1547 struct enc28j60_net *priv;
1548 int ret = 0;
1549
1550 if (netif_msg_drv(&debug))
1551 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1552 DRV_VERSION);
1553
1554 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1555 if (!dev) {
1556 if (netif_msg_drv(&debug))
1557 dev_err(&spi->dev, DRV_NAME
1558 ": unable to alloc new ethernet\n");
1559 ret = -ENOMEM;
1560 goto error_alloc;
1561 }
1562 priv = netdev_priv(dev);
1563
1564 priv->netdev = dev; /* priv to netdev reference */
1565 priv->spi = spi; /* priv to spi reference */
1566 priv->msg_enable = netif_msg_init(debug.msg_enable,
1567 ENC28J60_MSG_DEFAULT);
1568 mutex_init(&priv->lock);
1569 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1570 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1571 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1572 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1573 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */
1574 SET_NETDEV_DEV(dev, &spi->dev);
1575
1576 if (!enc28j60_chipset_init(dev)) {
1577 if (netif_msg_probe(priv))
1578 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1579 ret = -EIO;
1580 goto error_irq;
1581 }
1582 random_ether_addr(dev->dev_addr);
1583 enc28j60_set_hw_macaddr(dev);
1584
1585 /* Board setup must set the relevant edge trigger type;
1586 * level triggers won't currently work.
1587 */
1588 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1589 if (ret < 0) {
1590 if (netif_msg_probe(priv))
1591 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1592 "(ret = %d)\n", spi->irq, ret);
1593 goto error_irq;
1594 }
1595
1596 dev->if_port = IF_PORT_10BASET;
1597 dev->irq = spi->irq;
1598 dev->netdev_ops = &enc28j60_netdev_ops;
1599 dev->watchdog_timeo = TX_TIMEOUT;
1600 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1601
1602 enc28j60_lowpower(priv, true);
1603
1604 ret = register_netdev(dev);
1605 if (ret) {
1606 if (netif_msg_probe(priv))
1607 dev_err(&spi->dev, "register netdev " DRV_NAME
1608 " failed (ret = %d)\n", ret);
1609 goto error_register;
1610 }
1611 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1612
1613 return 0;
1614
1615error_register:
1616 free_irq(spi->irq, priv);
1617error_irq:
1618 free_netdev(dev);
1619error_alloc:
1620 return ret;
1621}
1622
1623static int __devexit enc28j60_remove(struct spi_device *spi)
1624{
1625 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1626
1627 if (netif_msg_drv(priv))
1628 printk(KERN_DEBUG DRV_NAME ": remove\n");
1629
1630 unregister_netdev(priv->netdev);
1631 free_irq(spi->irq, priv);
1632 free_netdev(priv->netdev);
1633
1634 return 0;
1635}
1636
1637static struct spi_driver enc28j60_driver = {
1638 .driver = {
1639 .name = DRV_NAME,
1640 .owner = THIS_MODULE,
1641 },
1642 .probe = enc28j60_probe,
1643 .remove = __devexit_p(enc28j60_remove),
1644};
1645
1646static int __init enc28j60_init(void)
1647{
1648 msec20_to_jiffies = msecs_to_jiffies(20);
1649
1650 return spi_register_driver(&enc28j60_driver);
1651}
1652
1653module_init(enc28j60_init);
1654
1655static void __exit enc28j60_exit(void)
1656{
1657 spi_unregister_driver(&enc28j60_driver);
1658}
1659
1660module_exit(enc28j60_exit);
1661
1662MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1663MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1664MODULE_LICENSE("GPL");
1665module_param_named(debug, debug.msg_enable, int, 0);
1666MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
1667MODULE_ALIAS("spi:" DRV_NAME);
diff --git a/drivers/net/ethernet/microchip/enc28j60_hw.h b/drivers/net/ethernet/microchip/enc28j60_hw.h
new file mode 100644
index 000000000000..25b41de49f0e
--- /dev/null
+++ b/drivers/net/ethernet/microchip/enc28j60_hw.h
@@ -0,0 +1,309 @@
1/*
2 * enc28j60_hw.h: EDTP FrameThrower style enc28j60 registers
3 *
4 * $Id: enc28j60_hw.h,v 1.9 2007/12/14 11:59:16 claudio Exp $
5 */
6
7#ifndef _ENC28J60_HW_H
8#define _ENC28J60_HW_H
9
10/*
11 * ENC28J60 Control Registers
12 * Control register definitions are a combination of address,
13 * bank number, and Ethernet/MAC/PHY indicator bits.
14 * - Register address (bits 0-4)
15 * - Bank number (bits 5-6)
16 * - MAC/MII indicator (bit 7)
17 */
18#define ADDR_MASK 0x1F
19#define BANK_MASK 0x60
20#define SPRD_MASK 0x80
21/* All-bank registers */
22#define EIE 0x1B
23#define EIR 0x1C
24#define ESTAT 0x1D
25#define ECON2 0x1E
26#define ECON1 0x1F
27/* Bank 0 registers */
28#define ERDPTL (0x00|0x00)
29#define ERDPTH (0x01|0x00)
30#define EWRPTL (0x02|0x00)
31#define EWRPTH (0x03|0x00)
32#define ETXSTL (0x04|0x00)
33#define ETXSTH (0x05|0x00)
34#define ETXNDL (0x06|0x00)
35#define ETXNDH (0x07|0x00)
36#define ERXSTL (0x08|0x00)
37#define ERXSTH (0x09|0x00)
38#define ERXNDL (0x0A|0x00)
39#define ERXNDH (0x0B|0x00)
40#define ERXRDPTL (0x0C|0x00)
41#define ERXRDPTH (0x0D|0x00)
42#define ERXWRPTL (0x0E|0x00)
43#define ERXWRPTH (0x0F|0x00)
44#define EDMASTL (0x10|0x00)
45#define EDMASTH (0x11|0x00)
46#define EDMANDL (0x12|0x00)
47#define EDMANDH (0x13|0x00)
48#define EDMADSTL (0x14|0x00)
49#define EDMADSTH (0x15|0x00)
50#define EDMACSL (0x16|0x00)
51#define EDMACSH (0x17|0x00)
52/* Bank 1 registers */
53#define EHT0 (0x00|0x20)
54#define EHT1 (0x01|0x20)
55#define EHT2 (0x02|0x20)
56#define EHT3 (0x03|0x20)
57#define EHT4 (0x04|0x20)
58#define EHT5 (0x05|0x20)
59#define EHT6 (0x06|0x20)
60#define EHT7 (0x07|0x20)
61#define EPMM0 (0x08|0x20)
62#define EPMM1 (0x09|0x20)
63#define EPMM2 (0x0A|0x20)
64#define EPMM3 (0x0B|0x20)
65#define EPMM4 (0x0C|0x20)
66#define EPMM5 (0x0D|0x20)
67#define EPMM6 (0x0E|0x20)
68#define EPMM7 (0x0F|0x20)
69#define EPMCSL (0x10|0x20)
70#define EPMCSH (0x11|0x20)
71#define EPMOL (0x14|0x20)
72#define EPMOH (0x15|0x20)
73#define EWOLIE (0x16|0x20)
74#define EWOLIR (0x17|0x20)
75#define ERXFCON (0x18|0x20)
76#define EPKTCNT (0x19|0x20)
77/* Bank 2 registers */
78#define MACON1 (0x00|0x40|SPRD_MASK)
79/* #define MACON2 (0x01|0x40|SPRD_MASK) */
80#define MACON3 (0x02|0x40|SPRD_MASK)
81#define MACON4 (0x03|0x40|SPRD_MASK)
82#define MABBIPG (0x04|0x40|SPRD_MASK)
83#define MAIPGL (0x06|0x40|SPRD_MASK)
84#define MAIPGH (0x07|0x40|SPRD_MASK)
85#define MACLCON1 (0x08|0x40|SPRD_MASK)
86#define MACLCON2 (0x09|0x40|SPRD_MASK)
87#define MAMXFLL (0x0A|0x40|SPRD_MASK)
88#define MAMXFLH (0x0B|0x40|SPRD_MASK)
89#define MAPHSUP (0x0D|0x40|SPRD_MASK)
90#define MICON (0x11|0x40|SPRD_MASK)
91#define MICMD (0x12|0x40|SPRD_MASK)
92#define MIREGADR (0x14|0x40|SPRD_MASK)
93#define MIWRL (0x16|0x40|SPRD_MASK)
94#define MIWRH (0x17|0x40|SPRD_MASK)
95#define MIRDL (0x18|0x40|SPRD_MASK)
96#define MIRDH (0x19|0x40|SPRD_MASK)
97/* Bank 3 registers */
98#define MAADR1 (0x00|0x60|SPRD_MASK)
99#define MAADR0 (0x01|0x60|SPRD_MASK)
100#define MAADR3 (0x02|0x60|SPRD_MASK)
101#define MAADR2 (0x03|0x60|SPRD_MASK)
102#define MAADR5 (0x04|0x60|SPRD_MASK)
103#define MAADR4 (0x05|0x60|SPRD_MASK)
104#define EBSTSD (0x06|0x60)
105#define EBSTCON (0x07|0x60)
106#define EBSTCSL (0x08|0x60)
107#define EBSTCSH (0x09|0x60)
108#define MISTAT (0x0A|0x60|SPRD_MASK)
109#define EREVID (0x12|0x60)
110#define ECOCON (0x15|0x60)
111#define EFLOCON (0x17|0x60)
112#define EPAUSL (0x18|0x60)
113#define EPAUSH (0x19|0x60)
114/* PHY registers */
115#define PHCON1 0x00
116#define PHSTAT1 0x01
117#define PHHID1 0x02
118#define PHHID2 0x03
119#define PHCON2 0x10
120#define PHSTAT2 0x11
121#define PHIE 0x12
122#define PHIR 0x13
123#define PHLCON 0x14
124
125/* ENC28J60 EIE Register Bit Definitions */
126#define EIE_INTIE 0x80
127#define EIE_PKTIE 0x40
128#define EIE_DMAIE 0x20
129#define EIE_LINKIE 0x10
130#define EIE_TXIE 0x08
131/* #define EIE_WOLIE 0x04 (reserved) */
132#define EIE_TXERIE 0x02
133#define EIE_RXERIE 0x01
134/* ENC28J60 EIR Register Bit Definitions */
135#define EIR_PKTIF 0x40
136#define EIR_DMAIF 0x20
137#define EIR_LINKIF 0x10
138#define EIR_TXIF 0x08
139/* #define EIR_WOLIF 0x04 (reserved) */
140#define EIR_TXERIF 0x02
141#define EIR_RXERIF 0x01
142/* ENC28J60 ESTAT Register Bit Definitions */
143#define ESTAT_INT 0x80
144#define ESTAT_LATECOL 0x10
145#define ESTAT_RXBUSY 0x04
146#define ESTAT_TXABRT 0x02
147#define ESTAT_CLKRDY 0x01
148/* ENC28J60 ECON2 Register Bit Definitions */
149#define ECON2_AUTOINC 0x80
150#define ECON2_PKTDEC 0x40
151#define ECON2_PWRSV 0x20
152#define ECON2_VRPS 0x08
153/* ENC28J60 ECON1 Register Bit Definitions */
154#define ECON1_TXRST 0x80
155#define ECON1_RXRST 0x40
156#define ECON1_DMAST 0x20
157#define ECON1_CSUMEN 0x10
158#define ECON1_TXRTS 0x08
159#define ECON1_RXEN 0x04
160#define ECON1_BSEL1 0x02
161#define ECON1_BSEL0 0x01
162/* ENC28J60 MACON1 Register Bit Definitions */
163#define MACON1_LOOPBK 0x10
164#define MACON1_TXPAUS 0x08
165#define MACON1_RXPAUS 0x04
166#define MACON1_PASSALL 0x02
167#define MACON1_MARXEN 0x01
168/* ENC28J60 MACON2 Register Bit Definitions */
169#define MACON2_MARST 0x80
170#define MACON2_RNDRST 0x40
171#define MACON2_MARXRST 0x08
172#define MACON2_RFUNRST 0x04
173#define MACON2_MATXRST 0x02
174#define MACON2_TFUNRST 0x01
175/* ENC28J60 MACON3 Register Bit Definitions */
176#define MACON3_PADCFG2 0x80
177#define MACON3_PADCFG1 0x40
178#define MACON3_PADCFG0 0x20
179#define MACON3_TXCRCEN 0x10
180#define MACON3_PHDRLEN 0x08
181#define MACON3_HFRMLEN 0x04
182#define MACON3_FRMLNEN 0x02
183#define MACON3_FULDPX 0x01
184/* ENC28J60 MICMD Register Bit Definitions */
185#define MICMD_MIISCAN 0x02
186#define MICMD_MIIRD 0x01
187/* ENC28J60 MISTAT Register Bit Definitions */
188#define MISTAT_NVALID 0x04
189#define MISTAT_SCAN 0x02
190#define MISTAT_BUSY 0x01
191/* ENC28J60 ERXFCON Register Bit Definitions */
192#define ERXFCON_UCEN 0x80
193#define ERXFCON_ANDOR 0x40
194#define ERXFCON_CRCEN 0x20
195#define ERXFCON_PMEN 0x10
196#define ERXFCON_MPEN 0x08
197#define ERXFCON_HTEN 0x04
198#define ERXFCON_MCEN 0x02
199#define ERXFCON_BCEN 0x01
200
201/* ENC28J60 PHY PHCON1 Register Bit Definitions */
202#define PHCON1_PRST 0x8000
203#define PHCON1_PLOOPBK 0x4000
204#define PHCON1_PPWRSV 0x0800
205#define PHCON1_PDPXMD 0x0100
206/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
207#define PHSTAT1_PFDPX 0x1000
208#define PHSTAT1_PHDPX 0x0800
209#define PHSTAT1_LLSTAT 0x0004
210#define PHSTAT1_JBSTAT 0x0002
211/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
212#define PHSTAT2_TXSTAT (1 << 13)
213#define PHSTAT2_RXSTAT (1 << 12)
214#define PHSTAT2_COLSTAT (1 << 11)
215#define PHSTAT2_LSTAT (1 << 10)
216#define PHSTAT2_DPXSTAT (1 << 9)
217#define PHSTAT2_PLRITY (1 << 5)
218/* ENC28J60 PHY PHCON2 Register Bit Definitions */
219#define PHCON2_FRCLINK 0x4000
220#define PHCON2_TXDIS 0x2000
221#define PHCON2_JABBER 0x0400
222#define PHCON2_HDLDIS 0x0100
223/* ENC28J60 PHY PHIE Register Bit Definitions */
224#define PHIE_PLNKIE (1 << 4)
225#define PHIE_PGEIE (1 << 1)
226/* ENC28J60 PHY PHIR Register Bit Definitions */
227#define PHIR_PLNKIF (1 << 4)
228#define PHIR_PGEIF (1 << 1)
229
230/* ENC28J60 Packet Control Byte Bit Definitions */
231#define PKTCTRL_PHUGEEN 0x08
232#define PKTCTRL_PPADEN 0x04
233#define PKTCTRL_PCRCEN 0x02
234#define PKTCTRL_POVERRIDE 0x01
235
236/* ENC28J60 Transmit Status Vector */
237#define TSV_TXBYTECNT 0
238#define TSV_TXCOLLISIONCNT 16
239#define TSV_TXCRCERROR 20
240#define TSV_TXLENCHKERROR 21
241#define TSV_TXLENOUTOFRANGE 22
242#define TSV_TXDONE 23
243#define TSV_TXMULTICAST 24
244#define TSV_TXBROADCAST 25
245#define TSV_TXPACKETDEFER 26
246#define TSV_TXEXDEFER 27
247#define TSV_TXEXCOLLISION 28
248#define TSV_TXLATECOLLISION 29
249#define TSV_TXGIANT 30
250#define TSV_TXUNDERRUN 31
251#define TSV_TOTBYTETXONWIRE 32
252#define TSV_TXCONTROLFRAME 48
253#define TSV_TXPAUSEFRAME 49
254#define TSV_BACKPRESSUREAPP 50
255#define TSV_TXVLANTAGFRAME 51
256
257#define TSV_SIZE 7
258#define TSV_BYTEOF(x) ((x) / 8)
259#define TSV_BITMASK(x) (1 << ((x) % 8))
260#define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
261
262/* ENC28J60 Receive Status Vector */
263#define RSV_RXLONGEVDROPEV 16
264#define RSV_CARRIEREV 18
265#define RSV_CRCERROR 20
266#define RSV_LENCHECKERR 21
267#define RSV_LENOUTOFRANGE 22
268#define RSV_RXOK 23
269#define RSV_RXMULTICAST 24
270#define RSV_RXBROADCAST 25
271#define RSV_DRIBBLENIBBLE 26
272#define RSV_RXCONTROLFRAME 27
273#define RSV_RXPAUSEFRAME 28
274#define RSV_RXUNKNOWNOPCODE 29
275#define RSV_RXTYPEVLAN 30
276
277#define RSV_SIZE 6
278#define RSV_BITMASK(x) (1 << ((x) - 16))
279#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
280
281
282/* SPI operation codes */
283#define ENC28J60_READ_CTRL_REG 0x00
284#define ENC28J60_READ_BUF_MEM 0x3A
285#define ENC28J60_WRITE_CTRL_REG 0x40
286#define ENC28J60_WRITE_BUF_MEM 0x7A
287#define ENC28J60_BIT_FIELD_SET 0x80
288#define ENC28J60_BIT_FIELD_CLR 0xA0
289#define ENC28J60_SOFT_RESET 0xFF
290
291
292/* buffer boundaries applied to internal 8K ram
293 * entire available packet buffer space is allocated.
294 * Give TX buffer space for one full ethernet frame (~1500 bytes)
295 * receive buffer gets the rest */
296#define TXSTART_INIT 0x1A00
297#define TXEND_INIT 0x1FFF
298
299/* Put RX buffer at 0 as suggested by the Errata datasheet */
300#define RXSTART_INIT 0x0000
301#define RXEND_INIT 0x19FF
302
303/* maximum ethernet frame length */
304#define MAX_FRAMELEN 1518
305
306/* Preferred half duplex: LEDA: Link status LEDB: Rx/Tx activity */
307#define ENC28J60_LAMPS_MODE 0x3476
308
309#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 23:32:45 -0500