diff options
Diffstat (limited to 'drivers/net/ethernet/xilinx')
-rw-r--r-- | drivers/net/ethernet/xilinx/ll_temac_main.c | 2 | ||||
-rw-r--r-- | drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 2 | ||||
-rw-r--r-- | drivers/net/ethernet/xilinx/xilinx_emaclite.c | 51 |
3 files changed, 15 insertions, 40 deletions
diff --git a/drivers/net/ethernet/xilinx/ll_temac_main.c b/drivers/net/ethernet/xilinx/ll_temac_main.c index 1f2364126323..2166e879a096 100644 --- a/drivers/net/ethernet/xilinx/ll_temac_main.c +++ b/drivers/net/ethernet/xilinx/ll_temac_main.c | |||
@@ -1017,7 +1017,7 @@ static int temac_of_probe(struct platform_device *op) | |||
1017 | platform_set_drvdata(op, ndev); | 1017 | platform_set_drvdata(op, ndev); |
1018 | SET_NETDEV_DEV(ndev, &op->dev); | 1018 | SET_NETDEV_DEV(ndev, &op->dev); |
1019 | ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ | 1019 | ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ |
1020 | ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST; | 1020 | ndev->features = NETIF_F_SG; |
1021 | ndev->netdev_ops = &temac_netdev_ops; | 1021 | ndev->netdev_ops = &temac_netdev_ops; |
1022 | ndev->ethtool_ops = &temac_ethtool_ops; | 1022 | ndev->ethtool_ops = &temac_ethtool_ops; |
1023 | #if 0 | 1023 | #if 0 |
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index b2ff038d6d20..f9293da19e26 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c | |||
@@ -1486,7 +1486,7 @@ static int axienet_of_probe(struct platform_device *op) | |||
1486 | 1486 | ||
1487 | SET_NETDEV_DEV(ndev, &op->dev); | 1487 | SET_NETDEV_DEV(ndev, &op->dev); |
1488 | ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ | 1488 | ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ |
1489 | ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST; | 1489 | ndev->features = NETIF_F_SG; |
1490 | ndev->netdev_ops = &axienet_netdev_ops; | 1490 | ndev->netdev_ops = &axienet_netdev_ops; |
1491 | ndev->ethtool_ops = &axienet_ethtool_ops; | 1491 | ndev->ethtool_ops = &axienet_ethtool_ops; |
1492 | 1492 | ||
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index 74234a51c851..fefb8cd5eb65 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c | |||
@@ -163,26 +163,9 @@ static void xemaclite_enable_interrupts(struct net_local *drvdata) | |||
163 | __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK, | 163 | __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK, |
164 | drvdata->base_addr + XEL_TSR_OFFSET); | 164 | drvdata->base_addr + XEL_TSR_OFFSET); |
165 | 165 | ||
166 | /* Enable the Tx interrupts for the second Buffer if | ||
167 | * configured in HW */ | ||
168 | if (drvdata->tx_ping_pong != 0) { | ||
169 | reg_data = __raw_readl(drvdata->base_addr + | ||
170 | XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); | ||
171 | __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK, | ||
172 | drvdata->base_addr + XEL_BUFFER_OFFSET + | ||
173 | XEL_TSR_OFFSET); | ||
174 | } | ||
175 | |||
176 | /* Enable the Rx interrupts for the first buffer */ | 166 | /* Enable the Rx interrupts for the first buffer */ |
177 | __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); | 167 | __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); |
178 | 168 | ||
179 | /* Enable the Rx interrupts for the second Buffer if | ||
180 | * configured in HW */ | ||
181 | if (drvdata->rx_ping_pong != 0) { | ||
182 | __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + | ||
183 | XEL_BUFFER_OFFSET + XEL_RSR_OFFSET); | ||
184 | } | ||
185 | |||
186 | /* Enable the Global Interrupt Enable */ | 169 | /* Enable the Global Interrupt Enable */ |
187 | __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); | 170 | __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); |
188 | } | 171 | } |
@@ -206,31 +189,10 @@ static void xemaclite_disable_interrupts(struct net_local *drvdata) | |||
206 | __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), | 189 | __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), |
207 | drvdata->base_addr + XEL_TSR_OFFSET); | 190 | drvdata->base_addr + XEL_TSR_OFFSET); |
208 | 191 | ||
209 | /* Disable the Tx interrupts for the second Buffer | ||
210 | * if configured in HW */ | ||
211 | if (drvdata->tx_ping_pong != 0) { | ||
212 | reg_data = __raw_readl(drvdata->base_addr + XEL_BUFFER_OFFSET + | ||
213 | XEL_TSR_OFFSET); | ||
214 | __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), | ||
215 | drvdata->base_addr + XEL_BUFFER_OFFSET + | ||
216 | XEL_TSR_OFFSET); | ||
217 | } | ||
218 | |||
219 | /* Disable the Rx interrupts for the first buffer */ | 192 | /* Disable the Rx interrupts for the first buffer */ |
220 | reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET); | 193 | reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET); |
221 | __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), | 194 | __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), |
222 | drvdata->base_addr + XEL_RSR_OFFSET); | 195 | drvdata->base_addr + XEL_RSR_OFFSET); |
223 | |||
224 | /* Disable the Rx interrupts for the second buffer | ||
225 | * if configured in HW */ | ||
226 | if (drvdata->rx_ping_pong != 0) { | ||
227 | |||
228 | reg_data = __raw_readl(drvdata->base_addr + XEL_BUFFER_OFFSET + | ||
229 | XEL_RSR_OFFSET); | ||
230 | __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), | ||
231 | drvdata->base_addr + XEL_BUFFER_OFFSET + | ||
232 | XEL_RSR_OFFSET); | ||
233 | } | ||
234 | } | 196 | } |
235 | 197 | ||
236 | /** | 198 | /** |
@@ -258,6 +220,13 @@ static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, | |||
258 | *to_u16_ptr++ = *from_u16_ptr++; | 220 | *to_u16_ptr++ = *from_u16_ptr++; |
259 | *to_u16_ptr++ = *from_u16_ptr++; | 221 | *to_u16_ptr++ = *from_u16_ptr++; |
260 | 222 | ||
223 | /* This barrier resolves occasional issues seen around | ||
224 | * cases where the data is not properly flushed out | ||
225 | * from the processor store buffers to the destination | ||
226 | * memory locations. | ||
227 | */ | ||
228 | wmb(); | ||
229 | |||
261 | /* Output a word */ | 230 | /* Output a word */ |
262 | *to_u32_ptr++ = align_buffer; | 231 | *to_u32_ptr++ = align_buffer; |
263 | } | 232 | } |
@@ -273,6 +242,12 @@ static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, | |||
273 | for (; length > 0; length--) | 242 | for (; length > 0; length--) |
274 | *to_u8_ptr++ = *from_u8_ptr++; | 243 | *to_u8_ptr++ = *from_u8_ptr++; |
275 | 244 | ||
245 | /* This barrier resolves occasional issues seen around | ||
246 | * cases where the data is not properly flushed out | ||
247 | * from the processor store buffers to the destination | ||
248 | * memory locations. | ||
249 | */ | ||
250 | wmb(); | ||
276 | *to_u32_ptr = align_buffer; | 251 | *to_u32_ptr = align_buffer; |
277 | } | 252 | } |
278 | } | 253 | } |