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-rw-r--r--drivers/net/ethernet/stmicro/stmmac/Kconfig11
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/Makefile1
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/chain_mode.c2
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/common.h20
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c330
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/ring_mode.c9
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac.h3
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_main.c93
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c5
9 files changed, 410 insertions, 64 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index e2f202e3932f..f2d7c702c77f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -37,6 +37,17 @@ config DWMAC_SUNXI
37 stmmac device driver. This driver is used for A20/A31 37 stmmac device driver. This driver is used for A20/A31
38 GMAC ethernet controller. 38 GMAC ethernet controller.
39 39
40config DWMAC_STI
41 bool "STi GMAC support"
42 depends on STMMAC_PLATFORM && ARCH_STI
43 default y
44 ---help---
45 Support for ethernet controller on STi SOCs.
46
47 This selects STi SoC glue layer support for the stmmac
48 device driver. This driver is used on for the STi series
49 SOCs GMAC ethernet controller.
50
40config STMMAC_PCI 51config STMMAC_PCI
41 bool "STMMAC PCI bus support" 52 bool "STMMAC PCI bus support"
42 depends on STMMAC_ETH && PCI 53 depends on STMMAC_ETH && PCI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index ecadecea79b2..dcef28775dad 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_STMMAC_ETH) += stmmac.o
2stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o 2stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
3stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o 3stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
4stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o 4stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
5stmmac-$(CONFIG_DWMAC_STI) += dwmac-sti.o
5stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \ 6stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
6 chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \ 7 chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
7 dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \ 8 dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
diff --git a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
index 72d282bf33a5..c553f6b5a913 100644
--- a/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
+++ b/drivers/net/ethernet/stmicro/stmmac/chain_mode.c
@@ -151,7 +151,7 @@ static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p)
151 sizeof(struct dma_desc))); 151 sizeof(struct dma_desc)));
152} 152}
153 153
154const struct stmmac_chain_mode_ops chain_mode_ops = { 154const struct stmmac_mode_ops chain_mode_ops = {
155 .init = stmmac_init_dma_chain, 155 .init = stmmac_init_dma_chain,
156 .is_jumbo_frm = stmmac_is_jumbo_frm, 156 .is_jumbo_frm = stmmac_is_jumbo_frm,
157 .jumbo_frm = stmmac_jumbo_frm, 157 .jumbo_frm = stmmac_jumbo_frm,
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 7834a3993946..74610f3aca9e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -419,20 +419,13 @@ struct mii_regs {
419 unsigned int data; /* MII Data */ 419 unsigned int data; /* MII Data */
420}; 420};
421 421
422struct stmmac_ring_mode_ops { 422struct stmmac_mode_ops {
423 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
424 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
425 void (*refill_desc3) (void *priv, struct dma_desc *p);
426 void (*init_desc3) (struct dma_desc *p);
427 void (*clean_desc3) (void *priv, struct dma_desc *p);
428 int (*set_16kib_bfsize) (int mtu);
429};
430
431struct stmmac_chain_mode_ops {
432 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size, 423 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
433 unsigned int extend_desc); 424 unsigned int extend_desc);
434 unsigned int (*is_jumbo_frm) (int len, int ehn_desc); 425 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
435 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum); 426 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
427 int (*set_16kib_bfsize)(int mtu);
428 void (*init_desc3)(struct dma_desc *p);
436 void (*refill_desc3) (void *priv, struct dma_desc *p); 429 void (*refill_desc3) (void *priv, struct dma_desc *p);
437 void (*clean_desc3) (void *priv, struct dma_desc *p); 430 void (*clean_desc3) (void *priv, struct dma_desc *p);
438}; 431};
@@ -441,8 +434,7 @@ struct mac_device_info {
441 const struct stmmac_ops *mac; 434 const struct stmmac_ops *mac;
442 const struct stmmac_desc_ops *desc; 435 const struct stmmac_desc_ops *desc;
443 const struct stmmac_dma_ops *dma; 436 const struct stmmac_dma_ops *dma;
444 const struct stmmac_ring_mode_ops *ring; 437 const struct stmmac_mode_ops *mode;
445 const struct stmmac_chain_mode_ops *chain;
446 const struct stmmac_hwtimestamp *ptp; 438 const struct stmmac_hwtimestamp *ptp;
447 struct mii_regs mii; /* MII register Addresses */ 439 struct mii_regs mii; /* MII register Addresses */
448 struct mac_link link; 440 struct mac_link link;
@@ -460,7 +452,7 @@ void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
460void stmmac_set_mac(void __iomem *ioaddr, bool enable); 452void stmmac_set_mac(void __iomem *ioaddr, bool enable);
461 453
462void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 454void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
463extern const struct stmmac_ring_mode_ops ring_mode_ops; 455extern const struct stmmac_mode_ops ring_mode_ops;
464extern const struct stmmac_chain_mode_ops chain_mode_ops; 456extern const struct stmmac_mode_ops chain_mode_ops;
465 457
466#endif /* __COMMON_H__ */ 458#endif /* __COMMON_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
new file mode 100644
index 000000000000..552bbc17863c
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -0,0 +1,330 @@
1/**
2 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
3 *
4 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
5 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/platform_device.h>
17#include <linux/stmmac.h>
18#include <linux/phy.h>
19#include <linux/mfd/syscon.h>
20#include <linux/regmap.h>
21#include <linux/clk.h>
22#include <linux/of.h>
23#include <linux/of_net.h>
24
25/**
26 * STi GMAC glue logic.
27 * --------------------
28 *
29 * _
30 * | \
31 * --------|0 \ ETH_SEL_INTERNAL_NOTEXT_PHYCLK
32 * phyclk | |___________________________________________
33 * | | | (phyclk-in)
34 * --------|1 / |
35 * int-clk |_ / |
36 * | _
37 * | | \
38 * |_______|1 \ ETH_SEL_TX_RETIME_CLK
39 * | |___________________________
40 * | | (tx-retime-clk)
41 * _______|0 /
42 * | |_ /
43 * _ |
44 * | \ |
45 * --------|0 \ |
46 * clk_125 | |__|
47 * | | ETH_SEL_TXCLK_NOT_CLK125
48 * --------|1 /
49 * txclk |_ /
50 *
51 *
52 * ETH_SEL_INTERNAL_NOTEXT_PHYCLK is valid only for RMII where PHY can
53 * generate 50MHz clock or MAC can generate it.
54 * This bit is configured by "st,ext-phyclk" property.
55 *
56 * ETH_SEL_TXCLK_NOT_CLK125 is only valid for gigabit modes, where the 125Mhz
57 * clock either comes from clk-125 pin or txclk pin. This configuration is
58 * totally driven by the board wiring. This bit is configured by
59 * "st,tx-retime-src" property.
60 *
61 * TXCLK configuration is different for different phy interface modes
62 * and changes according to link speed in modes like RGMII.
63 *
64 * Below table summarizes the clock requirement and clock sources for
65 * supported phy interface modes with link speeds.
66 * ________________________________________________
67 *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link |
68 * ------------------------------------------------
69 *| MII | n/a | 25Mhz |
70 *| | | txclk |
71 * ------------------------------------------------
72 *| GMII | 125Mhz | 25Mhz |
73 *| | clk-125/txclk | txclk |
74 * ------------------------------------------------
75 *| RGMII | 125Mhz | 25Mhz |
76 *| | clk-125/txclk | clkgen |
77 * ------------------------------------------------
78 *| RMII | n/a | 25Mhz |
79 *| | |clkgen/phyclk-in |
80 * ------------------------------------------------
81 *
82 * TX lines are always retimed with a clk, which can vary depending
83 * on the board configuration. Below is the table of these bits
84 * in eth configuration register depending on source of retime clk.
85 *
86 *---------------------------------------------------------------
87 * src | tx_rt_clk | int_not_ext_phyclk | txclk_n_clk125|
88 *---------------------------------------------------------------
89 * txclk | 0 | n/a | 1 |
90 *---------------------------------------------------------------
91 * ck_125| 0 | n/a | 0 |
92 *---------------------------------------------------------------
93 * phyclk| 1 | 0 | n/a |
94 *---------------------------------------------------------------
95 * clkgen| 1 | 1 | n/a |
96 *---------------------------------------------------------------
97 */
98
99 /* Register definition */
100
101 /* 3 bits [8:6]
102 * [6:6] ETH_SEL_TXCLK_NOT_CLK125
103 * [7:7] ETH_SEL_INTERNAL_NOTEXT_PHYCLK
104 * [8:8] ETH_SEL_TX_RETIME_CLK
105 *
106 */
107
108#define TX_RETIME_SRC_MASK GENMASK(8, 6)
109#define ETH_SEL_TX_RETIME_CLK BIT(8)
110#define ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7)
111#define ETH_SEL_TXCLK_NOT_CLK125 BIT(6)
112
113#define ENMII_MASK GENMASK(5, 5)
114#define ENMII BIT(5)
115
116/**
117 * 3 bits [4:2]
118 * 000-GMII/MII
119 * 001-RGMII
120 * 010-SGMII
121 * 100-RMII
122*/
123#define MII_PHY_SEL_MASK GENMASK(4, 2)
124#define ETH_PHY_SEL_RMII BIT(4)
125#define ETH_PHY_SEL_SGMII BIT(3)
126#define ETH_PHY_SEL_RGMII BIT(2)
127#define ETH_PHY_SEL_GMII 0x0
128#define ETH_PHY_SEL_MII 0x0
129
130#define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \
131 iface == PHY_INTERFACE_MODE_RGMII_ID || \
132 iface == PHY_INTERFACE_MODE_RGMII_RXID || \
133 iface == PHY_INTERFACE_MODE_RGMII_TXID)
134
135#define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \
136 iface == PHY_INTERFACE_MODE_GMII)
137
138struct sti_dwmac {
139 int interface;
140 bool ext_phyclk;
141 bool is_tx_retime_src_clk_125;
142 struct clk *clk;
143 int reg;
144 struct device *dev;
145 struct regmap *regmap;
146};
147
148static u32 phy_intf_sels[] = {
149 [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII,
150 [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII,
151 [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII,
152 [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII,
153 [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII,
154 [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII,
155};
156
157enum {
158 TX_RETIME_SRC_NA = 0,
159 TX_RETIME_SRC_TXCLK = 1,
160 TX_RETIME_SRC_CLK_125,
161 TX_RETIME_SRC_PHYCLK,
162 TX_RETIME_SRC_CLKGEN,
163};
164
165static const char *const tx_retime_srcs[] = {
166 [TX_RETIME_SRC_NA] = "",
167 [TX_RETIME_SRC_TXCLK] = "txclk",
168 [TX_RETIME_SRC_CLK_125] = "clk_125",
169 [TX_RETIME_SRC_PHYCLK] = "phyclk",
170 [TX_RETIME_SRC_CLKGEN] = "clkgen",
171};
172
173static u32 tx_retime_val[] = {
174 [TX_RETIME_SRC_TXCLK] = ETH_SEL_TXCLK_NOT_CLK125,
175 [TX_RETIME_SRC_CLK_125] = 0x0,
176 [TX_RETIME_SRC_PHYCLK] = ETH_SEL_TX_RETIME_CLK,
177 [TX_RETIME_SRC_CLKGEN] = ETH_SEL_TX_RETIME_CLK |
178 ETH_SEL_INTERNAL_NOTEXT_PHYCLK,
179};
180
181static void setup_retime_src(struct sti_dwmac *dwmac, u32 spd)
182{
183 u32 src = 0, freq = 0;
184
185 if (spd == SPEED_100) {
186 if (dwmac->interface == PHY_INTERFACE_MODE_MII ||
187 dwmac->interface == PHY_INTERFACE_MODE_GMII) {
188 src = TX_RETIME_SRC_TXCLK;
189 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) {
190 if (dwmac->ext_phyclk) {
191 src = TX_RETIME_SRC_PHYCLK;
192 } else {
193 src = TX_RETIME_SRC_CLKGEN;
194 freq = 50000000;
195 }
196
197 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) {
198 src = TX_RETIME_SRC_CLKGEN;
199 freq = 25000000;
200 }
201
202 if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk)
203 clk_set_rate(dwmac->clk, freq);
204
205 } else if (spd == SPEED_1000) {
206 if (dwmac->is_tx_retime_src_clk_125)
207 src = TX_RETIME_SRC_CLK_125;
208 else
209 src = TX_RETIME_SRC_TXCLK;
210 }
211
212 regmap_update_bits(dwmac->regmap, dwmac->reg,
213 TX_RETIME_SRC_MASK, tx_retime_val[src]);
214}
215
216static void sti_dwmac_exit(struct platform_device *pdev, void *priv)
217{
218 struct sti_dwmac *dwmac = priv;
219
220 if (dwmac->clk)
221 clk_disable_unprepare(dwmac->clk);
222}
223
224static void sti_fix_mac_speed(void *priv, unsigned int spd)
225{
226 struct sti_dwmac *dwmac = priv;
227
228 setup_retime_src(dwmac, spd);
229
230 return;
231}
232
233static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
234 struct platform_device *pdev)
235{
236 struct resource *res;
237 struct device *dev = &pdev->dev;
238 struct device_node *np = dev->of_node;
239 struct regmap *regmap;
240 int err;
241
242 if (!np)
243 return -EINVAL;
244
245 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-ethconf");
246 if (!res)
247 return -ENODATA;
248
249 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
250 if (IS_ERR(regmap))
251 return PTR_ERR(regmap);
252
253 dwmac->dev = dev;
254 dwmac->interface = of_get_phy_mode(np);
255 dwmac->regmap = regmap;
256 dwmac->reg = res->start;
257 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
258 dwmac->is_tx_retime_src_clk_125 = false;
259
260 if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) {
261 const char *rs;
262
263 err = of_property_read_string(np, "st,tx-retime-src", &rs);
264 if (err < 0) {
265 dev_err(dev, "st,tx-retime-src not specified\n");
266 return err;
267 }
268
269 if (!strcasecmp(rs, "clk_125"))
270 dwmac->is_tx_retime_src_clk_125 = true;
271 }
272
273 dwmac->clk = devm_clk_get(dev, "sti-ethclk");
274
275 if (IS_ERR(dwmac->clk))
276 dwmac->clk = NULL;
277
278 return 0;
279}
280
281static int sti_dwmac_init(struct platform_device *pdev, void *priv)
282{
283 struct sti_dwmac *dwmac = priv;
284 struct regmap *regmap = dwmac->regmap;
285 int iface = dwmac->interface;
286 u32 reg = dwmac->reg;
287 u32 val, spd;
288
289 if (dwmac->clk)
290 clk_prepare_enable(dwmac->clk);
291
292 regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]);
293
294 val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII;
295 regmap_update_bits(regmap, reg, ENMII_MASK, val);
296
297 if (IS_PHY_IF_MODE_GBIT(iface))
298 spd = SPEED_1000;
299 else
300 spd = SPEED_100;
301
302 setup_retime_src(dwmac, spd);
303
304 return 0;
305}
306
307static void *sti_dwmac_setup(struct platform_device *pdev)
308{
309 struct sti_dwmac *dwmac;
310 int ret;
311
312 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
313 if (!dwmac)
314 return ERR_PTR(-ENOMEM);
315
316 ret = sti_dwmac_parse_data(dwmac, pdev);
317 if (ret) {
318 dev_err(&pdev->dev, "Unable to parse OF data\n");
319 return ERR_PTR(ret);
320 }
321
322 return dwmac;
323}
324
325const struct stmmac_of_data sti_gmac_data = {
326 .fix_mac_speed = sti_fix_mac_speed,
327 .setup = sti_dwmac_setup,
328 .init = sti_dwmac_init,
329 .exit = sti_dwmac_exit,
330};
diff --git a/drivers/net/ethernet/stmicro/stmmac/ring_mode.c b/drivers/net/ethernet/stmicro/stmmac/ring_mode.c
index a96c7c2f5f3f..650a4be6bce5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/ring_mode.c
+++ b/drivers/net/ethernet/stmicro/stmmac/ring_mode.c
@@ -100,10 +100,9 @@ static void stmmac_refill_desc3(void *priv_ptr, struct dma_desc *p)
100{ 100{
101 struct stmmac_priv *priv = (struct stmmac_priv *)priv_ptr; 101 struct stmmac_priv *priv = (struct stmmac_priv *)priv_ptr;
102 102
103 if (unlikely(priv->plat->has_gmac)) 103 /* Fill DES3 in case of RING mode */
104 /* Fill DES3 in case of RING mode */ 104 if (priv->dma_buf_sz >= BUF_SIZE_8KiB)
105 if (priv->dma_buf_sz >= BUF_SIZE_8KiB) 105 p->des3 = p->des2 + BUF_SIZE_8KiB;
106 p->des3 = p->des2 + BUF_SIZE_8KiB;
107} 106}
108 107
109/* In ring mode we need to fill the desc3 because it is used as buffer */ 108/* In ring mode we need to fill the desc3 because it is used as buffer */
@@ -126,7 +125,7 @@ static int stmmac_set_16kib_bfsize(int mtu)
126 return ret; 125 return ret;
127} 126}
128 127
129const struct stmmac_ring_mode_ops ring_mode_ops = { 128const struct stmmac_mode_ops ring_mode_ops = {
130 .is_jumbo_frm = stmmac_is_jumbo_frm, 129 .is_jumbo_frm = stmmac_is_jumbo_frm,
131 .jumbo_frm = stmmac_jumbo_frm, 130 .jumbo_frm = stmmac_jumbo_frm,
132 .refill_desc3 = stmmac_refill_desc3, 131 .refill_desc3 = stmmac_refill_desc3,
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index d9af26ed58ee..f9e60d7918c4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -133,6 +133,9 @@ bool stmmac_eee_init(struct stmmac_priv *priv);
133#ifdef CONFIG_DWMAC_SUNXI 133#ifdef CONFIG_DWMAC_SUNXI
134extern const struct stmmac_of_data sun7i_gmac_data; 134extern const struct stmmac_of_data sun7i_gmac_data;
135#endif 135#endif
136#ifdef CONFIG_DWMAC_STI
137extern const struct stmmac_of_data sti_gmac_data;
138#endif
136extern struct platform_driver stmmac_pltfr_driver; 139extern struct platform_driver stmmac_pltfr_driver;
137static inline int stmmac_register_platform(void) 140static inline int stmmac_register_platform(void)
138{ 141{
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index a2e7d2c96e36..8543e1cfd55e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -92,8 +92,8 @@ static int tc = TC_DEFAULT;
92module_param(tc, int, S_IRUGO | S_IWUSR); 92module_param(tc, int, S_IRUGO | S_IWUSR);
93MODULE_PARM_DESC(tc, "DMA threshold control value"); 93MODULE_PARM_DESC(tc, "DMA threshold control value");
94 94
95#define DMA_BUFFER_SIZE BUF_SIZE_4KiB 95#define DEFAULT_BUFSIZE 1536
96static int buf_sz = DMA_BUFFER_SIZE; 96static int buf_sz = DEFAULT_BUFSIZE;
97module_param(buf_sz, int, S_IRUGO | S_IWUSR); 97module_param(buf_sz, int, S_IRUGO | S_IWUSR);
98MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 98MODULE_PARM_DESC(buf_sz, "DMA buffer size");
99 99
@@ -136,8 +136,8 @@ static void stmmac_verify_args(void)
136 dma_rxsize = DMA_RX_SIZE; 136 dma_rxsize = DMA_RX_SIZE;
137 if (unlikely(dma_txsize < 0)) 137 if (unlikely(dma_txsize < 0))
138 dma_txsize = DMA_TX_SIZE; 138 dma_txsize = DMA_TX_SIZE;
139 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) 139 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
140 buf_sz = DMA_BUFFER_SIZE; 140 buf_sz = DEFAULT_BUFSIZE;
141 if (unlikely(flow_ctrl > 1)) 141 if (unlikely(flow_ctrl > 1))
142 flow_ctrl = FLOW_AUTO; 142 flow_ctrl = FLOW_AUTO;
143 else if (likely(flow_ctrl < 0)) 143 else if (likely(flow_ctrl < 0))
@@ -286,10 +286,25 @@ bool stmmac_eee_init(struct stmmac_priv *priv)
286 286
287 /* MAC core supports the EEE feature. */ 287 /* MAC core supports the EEE feature. */
288 if (priv->dma_cap.eee) { 288 if (priv->dma_cap.eee) {
289 int tx_lpi_timer = priv->tx_lpi_timer;
290
289 /* Check if the PHY supports EEE */ 291 /* Check if the PHY supports EEE */
290 if (phy_init_eee(priv->phydev, 1)) 292 if (phy_init_eee(priv->phydev, 1)) {
293 /* To manage at run-time if the EEE cannot be supported
294 * anymore (for example because the lp caps have been
295 * changed).
296 * In that case the driver disable own timers.
297 */
298 if (priv->eee_active) {
299 pr_debug("stmmac: disable EEE\n");
300 del_timer_sync(&priv->eee_ctrl_timer);
301 priv->hw->mac->set_eee_timer(priv->ioaddr, 0,
302 tx_lpi_timer);
303 }
304 priv->eee_active = 0;
291 goto out; 305 goto out;
292 306 }
307 /* Activate the EEE and start timers */
293 if (!priv->eee_active) { 308 if (!priv->eee_active) {
294 priv->eee_active = 1; 309 priv->eee_active = 1;
295 init_timer(&priv->eee_ctrl_timer); 310 init_timer(&priv->eee_ctrl_timer);
@@ -300,13 +315,13 @@ bool stmmac_eee_init(struct stmmac_priv *priv)
300 315
301 priv->hw->mac->set_eee_timer(priv->ioaddr, 316 priv->hw->mac->set_eee_timer(priv->ioaddr,
302 STMMAC_DEFAULT_LIT_LS, 317 STMMAC_DEFAULT_LIT_LS,
303 priv->tx_lpi_timer); 318 tx_lpi_timer);
304 } else 319 } else
305 /* Set HW EEE according to the speed */ 320 /* Set HW EEE according to the speed */
306 priv->hw->mac->set_eee_pls(priv->ioaddr, 321 priv->hw->mac->set_eee_pls(priv->ioaddr,
307 priv->phydev->link); 322 priv->phydev->link);
308 323
309 pr_info("stmmac: Energy-Efficient Ethernet initialized\n"); 324 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
310 325
311 ret = true; 326 ret = true;
312 } 327 }
@@ -886,10 +901,10 @@ static int stmmac_set_bfsize(int mtu, int bufsize)
886 ret = BUF_SIZE_8KiB; 901 ret = BUF_SIZE_8KiB;
887 else if (mtu >= BUF_SIZE_2KiB) 902 else if (mtu >= BUF_SIZE_2KiB)
888 ret = BUF_SIZE_4KiB; 903 ret = BUF_SIZE_4KiB;
889 else if (mtu >= DMA_BUFFER_SIZE) 904 else if (mtu > DEFAULT_BUFSIZE)
890 ret = BUF_SIZE_2KiB; 905 ret = BUF_SIZE_2KiB;
891 else 906 else
892 ret = DMA_BUFFER_SIZE; 907 ret = DEFAULT_BUFSIZE;
893 908
894 return ret; 909 return ret;
895} 910}
@@ -951,9 +966,9 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
951 966
952 p->des2 = priv->rx_skbuff_dma[i]; 967 p->des2 = priv->rx_skbuff_dma[i];
953 968
954 if ((priv->mode == STMMAC_RING_MODE) && 969 if ((priv->hw->mode->init_desc3) &&
955 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 970 (priv->dma_buf_sz == BUF_SIZE_16KiB))
956 priv->hw->ring->init_desc3(p); 971 priv->hw->mode->init_desc3(p);
957 972
958 return 0; 973 return 0;
959} 974}
@@ -984,11 +999,8 @@ static int init_dma_desc_rings(struct net_device *dev)
984 unsigned int bfsize = 0; 999 unsigned int bfsize = 0;
985 int ret = -ENOMEM; 1000 int ret = -ENOMEM;
986 1001
987 /* Set the max buffer size according to the DESC mode 1002 if (priv->hw->mode->set_16kib_bfsize)
988 * and the MTU. Note that RING mode allows 16KiB bsize. 1003 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
989 */
990 if (priv->mode == STMMAC_RING_MODE)
991 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
992 1004
993 if (bfsize < BUF_SIZE_16KiB) 1005 if (bfsize < BUF_SIZE_16KiB)
994 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1006 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
@@ -1029,15 +1041,15 @@ static int init_dma_desc_rings(struct net_device *dev)
1029 /* Setup the chained descriptor addresses */ 1041 /* Setup the chained descriptor addresses */
1030 if (priv->mode == STMMAC_CHAIN_MODE) { 1042 if (priv->mode == STMMAC_CHAIN_MODE) {
1031 if (priv->extend_desc) { 1043 if (priv->extend_desc) {
1032 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy, 1044 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1033 rxsize, 1); 1045 rxsize, 1);
1034 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy, 1046 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1035 txsize, 1); 1047 txsize, 1);
1036 } else { 1048 } else {
1037 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy, 1049 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1038 rxsize, 0); 1050 rxsize, 0);
1039 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy, 1051 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1040 txsize, 0); 1052 txsize, 0);
1041 } 1053 }
1042 } 1054 }
1043 1055
@@ -1288,7 +1300,7 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
1288 DMA_TO_DEVICE); 1300 DMA_TO_DEVICE);
1289 priv->tx_skbuff_dma[entry] = 0; 1301 priv->tx_skbuff_dma[entry] = 0;
1290 } 1302 }
1291 priv->hw->ring->clean_desc3(priv, p); 1303 priv->hw->mode->clean_desc3(priv, p);
1292 1304
1293 if (likely(skb != NULL)) { 1305 if (likely(skb != NULL)) {
1294 dev_kfree_skb(skb); 1306 dev_kfree_skb(skb);
@@ -1705,7 +1717,7 @@ static int stmmac_open(struct net_device *dev)
1705 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1717 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1706 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1718 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1707 1719
1708 alloc_dma_desc_resources(priv); 1720 ret = alloc_dma_desc_resources(priv);
1709 if (ret < 0) { 1721 if (ret < 0) {
1710 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1722 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1711 goto dma_desc_error; 1723 goto dma_desc_error;
@@ -1844,6 +1856,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1844 int nfrags = skb_shinfo(skb)->nr_frags; 1856 int nfrags = skb_shinfo(skb)->nr_frags;
1845 struct dma_desc *desc, *first; 1857 struct dma_desc *desc, *first;
1846 unsigned int nopaged_len = skb_headlen(skb); 1858 unsigned int nopaged_len = skb_headlen(skb);
1859 unsigned int enh_desc = priv->plat->enh_desc;
1847 1860
1848 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1861 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1849 if (!netif_queue_stopped(dev)) { 1862 if (!netif_queue_stopped(dev)) {
@@ -1871,27 +1884,19 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1871 first = desc; 1884 first = desc;
1872 1885
1873 /* To program the descriptors according to the size of the frame */ 1886 /* To program the descriptors according to the size of the frame */
1874 if (priv->mode == STMMAC_RING_MODE) { 1887 if (enh_desc)
1875 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len, 1888 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1876 priv->plat->enh_desc); 1889
1877 if (unlikely(is_jumbo))
1878 entry = priv->hw->ring->jumbo_frm(priv, skb,
1879 csum_insertion);
1880 } else {
1881 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1882 priv->plat->enh_desc);
1883 if (unlikely(is_jumbo))
1884 entry = priv->hw->chain->jumbo_frm(priv, skb,
1885 csum_insertion);
1886 }
1887 if (likely(!is_jumbo)) { 1890 if (likely(!is_jumbo)) {
1888 desc->des2 = dma_map_single(priv->device, skb->data, 1891 desc->des2 = dma_map_single(priv->device, skb->data,
1889 nopaged_len, DMA_TO_DEVICE); 1892 nopaged_len, DMA_TO_DEVICE);
1890 priv->tx_skbuff_dma[entry] = desc->des2; 1893 priv->tx_skbuff_dma[entry] = desc->des2;
1891 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1894 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1892 csum_insertion, priv->mode); 1895 csum_insertion, priv->mode);
1893 } else 1896 } else {
1894 desc = first; 1897 desc = first;
1898 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1899 }
1895 1900
1896 for (i = 0; i < nfrags; i++) { 1901 for (i = 0; i < nfrags; i++) {
1897 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1902 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
@@ -2029,7 +2034,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2029 2034
2030 p->des2 = priv->rx_skbuff_dma[entry]; 2035 p->des2 = priv->rx_skbuff_dma[entry];
2031 2036
2032 priv->hw->ring->refill_desc3(priv, p); 2037 priv->hw->mode->refill_desc3(priv, p);
2033 2038
2034 if (netif_msg_rx_status(priv)) 2039 if (netif_msg_rx_status(priv))
2035 pr_debug("\trefill entry #%d\n", entry); 2040 pr_debug("\trefill entry #%d\n", entry);
@@ -2633,11 +2638,11 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
2633 2638
2634 /* To use the chained or ring mode */ 2639 /* To use the chained or ring mode */
2635 if (chain_mode) { 2640 if (chain_mode) {
2636 priv->hw->chain = &chain_mode_ops; 2641 priv->hw->mode = &chain_mode_ops;
2637 pr_info(" Chain mode enabled\n"); 2642 pr_info(" Chain mode enabled\n");
2638 priv->mode = STMMAC_CHAIN_MODE; 2643 priv->mode = STMMAC_CHAIN_MODE;
2639 } else { 2644 } else {
2640 priv->hw->ring = &ring_mode_ops; 2645 priv->hw->mode = &ring_mode_ops;
2641 pr_info(" Ring mode enabled\n"); 2646 pr_info(" Ring mode enabled\n");
2642 priv->mode = STMMAC_RING_MODE; 2647 priv->mode = STMMAC_RING_MODE;
2643 } 2648 }
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 5884a7d2063b..8fb32a80f1c1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -33,6 +33,11 @@ static const struct of_device_id stmmac_dt_ids[] = {
33#ifdef CONFIG_DWMAC_SUNXI 33#ifdef CONFIG_DWMAC_SUNXI
34 { .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data}, 34 { .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data},
35#endif 35#endif
36#ifdef CONFIG_DWMAC_STI
37 { .compatible = "st,stih415-dwmac", .data = &sti_gmac_data},
38 { .compatible = "st,stih416-dwmac", .data = &sti_gmac_data},
39 { .compatible = "st,stid127-dwmac", .data = &sti_gmac_data},
40#endif
36 /* SoC specific glue layers should come before generic bindings */ 41 /* SoC specific glue layers should come before generic bindings */
37 { .compatible = "st,spear600-gmac"}, 42 { .compatible = "st,spear600-gmac"},
38 { .compatible = "snps,dwmac-3.610"}, 43 { .compatible = "snps,dwmac-3.610"},
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-04 07:27:26 -0400