aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/ethernet/qlogic/qlcnic/qlcnic.h')
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic.h416
1 files changed, 149 insertions, 267 deletions
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
index eaa1db9fec32..082eecbf4148 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
@@ -89,16 +89,6 @@
89#define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 89#define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
90#define QLCNIC_LRO_BUFFER_EXTRA 2048 90#define QLCNIC_LRO_BUFFER_EXTRA 2048
91 91
92/* Opcodes to be used with the commands */
93#define TX_ETHER_PKT 0x01
94#define TX_TCP_PKT 0x02
95#define TX_UDP_PKT 0x03
96#define TX_IP_PKT 0x04
97#define TX_TCP_LSO 0x05
98#define TX_TCP_LSO6 0x06
99#define TX_TCPV6_PKT 0x0b
100#define TX_UDPV6_PKT 0x0c
101
102/* Tx defines */ 92/* Tx defines */
103#define QLCNIC_MAX_FRAGS_PER_TX 14 93#define QLCNIC_MAX_FRAGS_PER_TX 14
104#define MAX_TSO_HEADER_DESC 2 94#define MAX_TSO_HEADER_DESC 2
@@ -147,28 +137,6 @@
147 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 137 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
148 * we are doing LSO (above the 1500 size packet) only. 138 * we are doing LSO (above the 1500 size packet) only.
149 */ 139 */
150
151#define FLAGS_VLAN_TAGGED 0x10
152#define FLAGS_VLAN_OOB 0x40
153
154#define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
155 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
156#define qlcnic_set_cmd_desc_port(cmd_desc, var) \
157 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
158#define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
159 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
160
161#define qlcnic_set_tx_port(_desc, _port) \
162 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
163
164#define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
165 ((_desc)->flags_opcode |= \
166 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
167
168#define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
169 ((_desc)->nfrags__length = \
170 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
171
172struct cmd_desc_type0 { 140struct cmd_desc_type0 {
173 u8 tcp_hdr_offset; /* For LSO only */ 141 u8 tcp_hdr_offset; /* For LSO only */
174 u8 ip_hdr_offset; /* For LSO only */ 142 u8 ip_hdr_offset; /* For LSO only */
@@ -203,65 +171,6 @@ struct rcv_desc {
203 __le64 addr_buffer; 171 __le64 addr_buffer;
204} __packed; 172} __packed;
205 173
206/* opcode field in status_desc */
207#define QLCNIC_SYN_OFFLOAD 0x03
208#define QLCNIC_RXPKT_DESC 0x04
209#define QLCNIC_OLD_RXPKT_DESC 0x3f
210#define QLCNIC_RESPONSE_DESC 0x05
211#define QLCNIC_LRO_DESC 0x12
212
213/* for status field in status_desc */
214#define STATUS_CKSUM_LOOP 0
215#define STATUS_CKSUM_OK 2
216
217/* owner bits of status_desc */
218#define STATUS_OWNER_HOST (0x1ULL << 56)
219#define STATUS_OWNER_PHANTOM (0x2ULL << 56)
220
221/* Status descriptor:
222 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
223 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
224 53-55 desc_cnt, 56-57 owner, 58-63 opcode
225 */
226#define qlcnic_get_sts_port(sts_data) \
227 ((sts_data) & 0x0F)
228#define qlcnic_get_sts_status(sts_data) \
229 (((sts_data) >> 4) & 0x0F)
230#define qlcnic_get_sts_type(sts_data) \
231 (((sts_data) >> 8) & 0x0F)
232#define qlcnic_get_sts_totallength(sts_data) \
233 (((sts_data) >> 12) & 0xFFFF)
234#define qlcnic_get_sts_refhandle(sts_data) \
235 (((sts_data) >> 28) & 0xFFFF)
236#define qlcnic_get_sts_prot(sts_data) \
237 (((sts_data) >> 44) & 0x0F)
238#define qlcnic_get_sts_pkt_offset(sts_data) \
239 (((sts_data) >> 48) & 0x1F)
240#define qlcnic_get_sts_desc_cnt(sts_data) \
241 (((sts_data) >> 53) & 0x7)
242#define qlcnic_get_sts_opcode(sts_data) \
243 (((sts_data) >> 58) & 0x03F)
244
245#define qlcnic_get_lro_sts_refhandle(sts_data) \
246 ((sts_data) & 0x0FFFF)
247#define qlcnic_get_lro_sts_length(sts_data) \
248 (((sts_data) >> 16) & 0x0FFFF)
249#define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
250 (((sts_data) >> 32) & 0x0FF)
251#define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
252 (((sts_data) >> 40) & 0x0FF)
253#define qlcnic_get_lro_sts_timestamp(sts_data) \
254 (((sts_data) >> 48) & 0x1)
255#define qlcnic_get_lro_sts_type(sts_data) \
256 (((sts_data) >> 49) & 0x7)
257#define qlcnic_get_lro_sts_push_flag(sts_data) \
258 (((sts_data) >> 52) & 0x1)
259#define qlcnic_get_lro_sts_seq_number(sts_data) \
260 ((sts_data) & 0x0FFFFFFFF)
261#define qlcnic_get_lro_sts_mss(sts_data1) \
262 ((sts_data1 >> 32) & 0x0FFFF)
263
264
265struct status_desc { 174struct status_desc {
266 __le64 status_desc_data[2]; 175 __le64 status_desc_data[2];
267} __attribute__ ((aligned(16))); 176} __attribute__ ((aligned(16)));
@@ -280,16 +189,16 @@ struct status_desc {
280#define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 189#define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
281 190
282struct uni_table_desc{ 191struct uni_table_desc{
283 u32 findex; 192 __le32 findex;
284 u32 num_entries; 193 __le32 num_entries;
285 u32 entry_size; 194 __le32 entry_size;
286 u32 reserved[5]; 195 __le32 reserved[5];
287}; 196};
288 197
289struct uni_data_desc{ 198struct uni_data_desc{
290 u32 findex; 199 __le32 findex;
291 u32 size; 200 __le32 size;
292 u32 reserved[5]; 201 __le32 reserved[5];
293}; 202};
294 203
295/* Flash Defines and Structures */ 204/* Flash Defines and Structures */
@@ -416,19 +325,19 @@ struct qlcnic_nic_intr_coalesce {
416}; 325};
417 326
418struct qlcnic_dump_template_hdr { 327struct qlcnic_dump_template_hdr {
419 __le32 type; 328 u32 type;
420 __le32 offset; 329 u32 offset;
421 __le32 size; 330 u32 size;
422 __le32 cap_mask; 331 u32 cap_mask;
423 __le32 num_entries; 332 u32 num_entries;
424 __le32 version; 333 u32 version;
425 __le32 timestamp; 334 u32 timestamp;
426 __le32 checksum; 335 u32 checksum;
427 __le32 drv_cap_mask; 336 u32 drv_cap_mask;
428 __le32 sys_info[3]; 337 u32 sys_info[3];
429 __le32 saved_state[16]; 338 u32 saved_state[16];
430 __le32 cap_sizes[8]; 339 u32 cap_sizes[8];
431 __le32 rsvd[0]; 340 u32 rsvd[0];
432}; 341};
433 342
434struct qlcnic_fw_dump { 343struct qlcnic_fw_dump {
@@ -1065,16 +974,16 @@ struct qlcnic_adapter {
1065 974
1066 spinlock_t tx_clean_lock; 975 spinlock_t tx_clean_lock;
1067 spinlock_t mac_learn_lock; 976 spinlock_t mac_learn_lock;
1068 __le32 file_prd_off; /*File fw product offset*/ 977 u32 file_prd_off; /*File fw product offset*/
1069 u32 fw_version; 978 u32 fw_version;
1070 const struct firmware *fw; 979 const struct firmware *fw;
1071}; 980};
1072 981
1073struct qlcnic_info { 982struct qlcnic_info_le {
1074 __le16 pci_func; 983 __le16 pci_func;
1075 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 984 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1076 __le16 phys_port; 985 __le16 phys_port;
1077 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 986 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1078 987
1079 __le32 capabilities; 988 __le32 capabilities;
1080 u8 max_mac_filters; 989 u8 max_mac_filters;
@@ -1088,13 +997,28 @@ struct qlcnic_info {
1088 u8 reserved2[104]; 997 u8 reserved2[104];
1089} __packed; 998} __packed;
1090 999
1091struct qlcnic_pci_info { 1000struct qlcnic_info {
1092 __le16 id; /* pci function id */ 1001 u16 pci_func;
1093 __le16 active; /* 1 = Enabled */ 1002 u16 op_mode;
1094 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1003 u16 phys_port;
1095 __le16 default_port; /* default port number */ 1004 u16 switch_mode;
1005 u32 capabilities;
1006 u8 max_mac_filters;
1007 u8 reserved1;
1008 u16 max_mtu;
1009 u16 max_tx_ques;
1010 u16 max_rx_ques;
1011 u16 min_tx_bw;
1012 u16 max_tx_bw;
1013};
1096 1014
1097 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1015struct qlcnic_pci_info_le {
1016 __le16 id; /* pci function id */
1017 __le16 active; /* 1 = Enabled */
1018 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1019 __le16 default_port; /* default port number */
1020
1021 __le16 tx_min_bw; /* Multiple of 100mbpc */
1098 __le16 tx_max_bw; 1022 __le16 tx_max_bw;
1099 __le16 reserved1[2]; 1023 __le16 reserved1[2];
1100 1024
@@ -1102,6 +1026,16 @@ struct qlcnic_pci_info {
1102 u8 reserved2[106]; 1026 u8 reserved2[106];
1103} __packed; 1027} __packed;
1104 1028
1029struct qlcnic_pci_info {
1030 u16 id;
1031 u16 active;
1032 u16 type;
1033 u16 default_port;
1034 u16 tx_min_bw;
1035 u16 tx_max_bw;
1036 u8 mac[ETH_ALEN];
1037};
1038
1105struct qlcnic_npar_info { 1039struct qlcnic_npar_info {
1106 u16 pvid; 1040 u16 pvid;
1107 u16 min_bw; 1041 u16 min_bw;
@@ -1208,7 +1142,7 @@ do { \
1208 (VAL1) += (VAL2); \ 1142 (VAL1) += (VAL2); \
1209} while (0) 1143} while (0)
1210 1144
1211struct qlcnic_mac_statistics{ 1145struct qlcnic_mac_statistics_le {
1212 __le64 mac_tx_frames; 1146 __le64 mac_tx_frames;
1213 __le64 mac_tx_bytes; 1147 __le64 mac_tx_bytes;
1214 __le64 mac_tx_mcast_pkts; 1148 __le64 mac_tx_mcast_pkts;
@@ -1248,7 +1182,45 @@ struct qlcnic_mac_statistics{
1248 __le64 mac_align_error; 1182 __le64 mac_align_error;
1249} __packed; 1183} __packed;
1250 1184
1251struct __qlcnic_esw_statistics { 1185struct qlcnic_mac_statistics {
1186 u64 mac_tx_frames;
1187 u64 mac_tx_bytes;
1188 u64 mac_tx_mcast_pkts;
1189 u64 mac_tx_bcast_pkts;
1190 u64 mac_tx_pause_cnt;
1191 u64 mac_tx_ctrl_pkt;
1192 u64 mac_tx_lt_64b_pkts;
1193 u64 mac_tx_lt_127b_pkts;
1194 u64 mac_tx_lt_255b_pkts;
1195 u64 mac_tx_lt_511b_pkts;
1196 u64 mac_tx_lt_1023b_pkts;
1197 u64 mac_tx_lt_1518b_pkts;
1198 u64 mac_tx_gt_1518b_pkts;
1199 u64 rsvd1[3];
1200 u64 mac_rx_frames;
1201 u64 mac_rx_bytes;
1202 u64 mac_rx_mcast_pkts;
1203 u64 mac_rx_bcast_pkts;
1204 u64 mac_rx_pause_cnt;
1205 u64 mac_rx_ctrl_pkt;
1206 u64 mac_rx_lt_64b_pkts;
1207 u64 mac_rx_lt_127b_pkts;
1208 u64 mac_rx_lt_255b_pkts;
1209 u64 mac_rx_lt_511b_pkts;
1210 u64 mac_rx_lt_1023b_pkts;
1211 u64 mac_rx_lt_1518b_pkts;
1212 u64 mac_rx_gt_1518b_pkts;
1213 u64 rsvd2[3];
1214 u64 mac_rx_length_error;
1215 u64 mac_rx_length_small;
1216 u64 mac_rx_length_large;
1217 u64 mac_rx_jabber;
1218 u64 mac_rx_dropped;
1219 u64 mac_rx_crc_error;
1220 u64 mac_align_error;
1221};
1222
1223struct qlcnic_esw_stats_le {
1252 __le16 context_id; 1224 __le16 context_id;
1253 __le16 version; 1225 __le16 version;
1254 __le16 size; 1226 __le16 size;
@@ -1263,147 +1235,27 @@ struct __qlcnic_esw_statistics {
1263 __le64 rsvd[3]; 1235 __le64 rsvd[3];
1264} __packed; 1236} __packed;
1265 1237
1238struct __qlcnic_esw_statistics {
1239 u16 context_id;
1240 u16 version;
1241 u16 size;
1242 u16 unused;
1243 u64 unicast_frames;
1244 u64 multicast_frames;
1245 u64 broadcast_frames;
1246 u64 dropped_frames;
1247 u64 errors;
1248 u64 local_frames;
1249 u64 numbytes;
1250 u64 rsvd[3];
1251};
1252
1266struct qlcnic_esw_statistics { 1253struct qlcnic_esw_statistics {
1267 struct __qlcnic_esw_statistics rx; 1254 struct __qlcnic_esw_statistics rx;
1268 struct __qlcnic_esw_statistics tx; 1255 struct __qlcnic_esw_statistics tx;
1269}; 1256};
1270 1257
1271struct qlcnic_common_entry_hdr {
1272 __le32 type;
1273 __le32 offset;
1274 __le32 cap_size;
1275 u8 mask;
1276 u8 rsvd[2];
1277 u8 flags;
1278} __packed;
1279
1280struct __crb {
1281 __le32 addr;
1282 u8 stride;
1283 u8 rsvd1[3];
1284 __le32 data_size;
1285 __le32 no_ops;
1286 __le32 rsvd2[4];
1287} __packed;
1288
1289struct __ctrl {
1290 __le32 addr;
1291 u8 stride;
1292 u8 index_a;
1293 __le16 timeout;
1294 __le32 data_size;
1295 __le32 no_ops;
1296 u8 opcode;
1297 u8 index_v;
1298 u8 shl_val;
1299 u8 shr_val;
1300 __le32 val1;
1301 __le32 val2;
1302 __le32 val3;
1303} __packed;
1304
1305struct __cache {
1306 __le32 addr;
1307 __le16 stride;
1308 __le16 init_tag_val;
1309 __le32 size;
1310 __le32 no_ops;
1311 __le32 ctrl_addr;
1312 __le32 ctrl_val;
1313 __le32 read_addr;
1314 u8 read_addr_stride;
1315 u8 read_addr_num;
1316 u8 rsvd1[2];
1317} __packed;
1318
1319struct __ocm {
1320 u8 rsvd[8];
1321 __le32 size;
1322 __le32 no_ops;
1323 u8 rsvd1[8];
1324 __le32 read_addr;
1325 __le32 read_addr_stride;
1326} __packed;
1327
1328struct __mem {
1329 u8 rsvd[24];
1330 __le32 addr;
1331 __le32 size;
1332} __packed;
1333
1334struct __mux {
1335 __le32 addr;
1336 u8 rsvd[4];
1337 __le32 size;
1338 __le32 no_ops;
1339 __le32 val;
1340 __le32 val_stride;
1341 __le32 read_addr;
1342 u8 rsvd2[4];
1343} __packed;
1344
1345struct __queue {
1346 __le32 sel_addr;
1347 __le16 stride;
1348 u8 rsvd[2];
1349 __le32 size;
1350 __le32 no_ops;
1351 u8 rsvd2[8];
1352 __le32 read_addr;
1353 u8 read_addr_stride;
1354 u8 read_addr_cnt;
1355 u8 rsvd3[2];
1356} __packed;
1357
1358struct qlcnic_dump_entry {
1359 struct qlcnic_common_entry_hdr hdr;
1360 union {
1361 struct __crb crb;
1362 struct __cache cache;
1363 struct __ocm ocm;
1364 struct __mem mem;
1365 struct __mux mux;
1366 struct __queue que;
1367 struct __ctrl ctrl;
1368 } region;
1369} __packed;
1370
1371enum op_codes {
1372 QLCNIC_DUMP_NOP = 0,
1373 QLCNIC_DUMP_READ_CRB = 1,
1374 QLCNIC_DUMP_READ_MUX = 2,
1375 QLCNIC_DUMP_QUEUE = 3,
1376 QLCNIC_DUMP_BRD_CONFIG = 4,
1377 QLCNIC_DUMP_READ_OCM = 6,
1378 QLCNIC_DUMP_PEG_REG = 7,
1379 QLCNIC_DUMP_L1_DTAG = 8,
1380 QLCNIC_DUMP_L1_ITAG = 9,
1381 QLCNIC_DUMP_L1_DATA = 11,
1382 QLCNIC_DUMP_L1_INST = 12,
1383 QLCNIC_DUMP_L2_DTAG = 21,
1384 QLCNIC_DUMP_L2_ITAG = 22,
1385 QLCNIC_DUMP_L2_DATA = 23,
1386 QLCNIC_DUMP_L2_INST = 24,
1387 QLCNIC_DUMP_READ_ROM = 71,
1388 QLCNIC_DUMP_READ_MEM = 72,
1389 QLCNIC_DUMP_READ_CTRL = 98,
1390 QLCNIC_DUMP_TLHDR = 99,
1391 QLCNIC_DUMP_RDEND = 255
1392};
1393
1394#define QLCNIC_DUMP_WCRB BIT_0
1395#define QLCNIC_DUMP_RWCRB BIT_1
1396#define QLCNIC_DUMP_ANDCRB BIT_2
1397#define QLCNIC_DUMP_ORCRB BIT_3
1398#define QLCNIC_DUMP_POLLCRB BIT_4
1399#define QLCNIC_DUMP_RD_SAVE BIT_5
1400#define QLCNIC_DUMP_WRT_SAVED BIT_6
1401#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
1402#define QLCNIC_DUMP_SKIP BIT_7
1403
1404#define QLCNIC_DUMP_MASK_MIN 3
1405#define QLCNIC_DUMP_MASK_DEF 0x1f 1258#define QLCNIC_DUMP_MASK_DEF 0x1f
1406#define QLCNIC_DUMP_MASK_MAX 0xff
1407#define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1259#define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1408#define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1260#define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1409#define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1261#define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
@@ -1411,12 +1263,6 @@ enum op_codes {
1411#define QLCNIC_SET_QUIESCENT 0xadd00010 1263#define QLCNIC_SET_QUIESCENT 0xadd00010
1412#define QLCNIC_RESET_QUIESCENT 0xadd00020 1264#define QLCNIC_RESET_QUIESCENT 0xadd00020
1413 1265
1414struct qlcnic_dump_operations {
1415 enum op_codes opcode;
1416 u32 (*handler)(struct qlcnic_adapter *,
1417 struct qlcnic_dump_entry *, u32 *);
1418};
1419
1420struct _cdrp_cmd { 1266struct _cdrp_cmd {
1421 u32 cmd; 1267 u32 cmd;
1422 u32 arg1; 1268 u32 arg1;
@@ -1474,6 +1320,8 @@ void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1474#define __QLCNIC_MAX_LED_RATE 0xf 1320#define __QLCNIC_MAX_LED_RATE 0xf
1475#define __QLCNIC_MAX_LED_STATE 0x2 1321#define __QLCNIC_MAX_LED_STATE 0x2
1476 1322
1323#define MAX_CTL_CHECK 1000
1324
1477int qlcnic_get_board_info(struct qlcnic_adapter *adapter); 1325int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1478int qlcnic_wol_supported(struct qlcnic_adapter *adapter); 1326int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1479int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); 1327int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
@@ -1530,9 +1378,8 @@ int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1530int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable); 1378int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1531int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1379int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1532int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); 1380int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1533void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter, 1381void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1534 struct qlcnic_host_tx_ring *tx_ring); 1382void qlcnic_fetch_mac(u32, u32, u8, u8 *);
1535void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1536void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); 1383void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1537void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter); 1384void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter);
1538int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode); 1385int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode);
@@ -1571,6 +1418,26 @@ int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1571int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); 1418int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1572extern int qlcnic_config_tso; 1419extern int qlcnic_config_tso;
1573 1420
1421int qlcnic_napi_add(struct qlcnic_adapter *, struct net_device *);
1422void qlcnic_napi_del(struct qlcnic_adapter *adapter);
1423void qlcnic_napi_enable(struct qlcnic_adapter *adapter);
1424void qlcnic_napi_disable(struct qlcnic_adapter *adapter);
1425int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1426void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1427void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1428int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1429
1430void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1431void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1432void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter);
1433void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter);
1434int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1435int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1436void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1437 struct qlcnic_esw_func_cfg *);
1438void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1439 struct qlcnic_esw_func_cfg *);
1440
1574/* 1441/*
1575 * QLOGIC Board information 1442 * QLOGIC Board information
1576 */ 1443 */
@@ -1617,6 +1484,21 @@ static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1617 tx_ring->producer; 1484 tx_ring->producer;
1618} 1485}
1619 1486
1487static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring)
1488{
1489 writel(0, sds_ring->crb_intr_mask);
1490}
1491
1492static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring)
1493{
1494 struct qlcnic_adapter *adapter = sds_ring->adapter;
1495
1496 writel(0x1, sds_ring->crb_intr_mask);
1497
1498 if (!QLCNIC_IS_MSI_FAMILY(adapter))
1499 writel(0xfbff, adapter->tgt_mask_reg);
1500}
1501
1620extern const struct ethtool_ops qlcnic_ethtool_ops; 1502extern const struct ethtool_ops qlcnic_ethtool_ops;
1621extern const struct ethtool_ops qlcnic_ethtool_failed_ops; 1503extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
1622 1504
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 10:28:10 -0500