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path: root/drivers/net/ethernet/mellanox/mlx4/mlx4.h
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Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx4/mlx4.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/mlx4.h34
1 files changed, 26 insertions, 8 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4.h b/drivers/net/ethernet/mellanox/mlx4/mlx4.h
index ed4a6959e828..cf883345af88 100644
--- a/drivers/net/ethernet/mellanox/mlx4/mlx4.h
+++ b/drivers/net/ethernet/mellanox/mlx4/mlx4.h
@@ -60,6 +60,8 @@
60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61#define MLX4_FS_NUM_MCG (1 << 17) 61#define MLX4_FS_NUM_MCG (1 << 17)
62 62
63#define INIT_HCA_TPT_MW_ENABLE (1 << 7)
64
63#define MLX4_NUM_UP 8 65#define MLX4_NUM_UP 8
64#define MLX4_NUM_TC 8 66#define MLX4_NUM_TC 8
65#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */ 67#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
@@ -113,10 +115,10 @@ enum {
113 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 115 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
114}; 116};
115 117
116enum mlx4_mr_state { 118enum mlx4_mpt_state {
117 MLX4_MR_DISABLED = 0, 119 MLX4_MPT_DISABLED = 0,
118 MLX4_MR_EN_HW, 120 MLX4_MPT_EN_HW,
119 MLX4_MR_EN_SW 121 MLX4_MPT_EN_SW
120}; 122};
121 123
122#define MLX4_COMM_TIME 10000 124#define MLX4_COMM_TIME 10000
@@ -263,6 +265,22 @@ struct mlx4_icm_table {
263 struct mlx4_icm **icm; 265 struct mlx4_icm **icm;
264}; 266};
265 267
268#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
269#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
270#define MLX4_MPT_FLAG_MIO (1 << 17)
271#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
272#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
273#define MLX4_MPT_FLAG_REGION (1 << 8)
274
275#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
276#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
277#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
278
279#define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
280
281#define MLX4_MPT_STATUS_SW 0xF0
282#define MLX4_MPT_STATUS_HW 0x00
283
266/* 284/*
267 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 285 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
268 */ 286 */
@@ -863,10 +881,10 @@ int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
863void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 881void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
864int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 882int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
865void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 883void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
866int __mlx4_mr_reserve(struct mlx4_dev *dev); 884int __mlx4_mpt_reserve(struct mlx4_dev *dev);
867void __mlx4_mr_release(struct mlx4_dev *dev, u32 index); 885void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
868int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index); 886int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
869void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index); 887void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
870u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 888u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
871void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 889void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
872 890