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path: root/drivers/net/ethernet/mellanox/mlx4/fw.c
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Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx4/fw.c')
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/fw.c91
1 files changed, 90 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c
index 688e1eabab29..494753e44ae3 100644
--- a/drivers/net/ethernet/mellanox/mlx4/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.c
@@ -136,7 +136,8 @@ static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
136 [7] = "FSM (MAC anti-spoofing) support", 136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support", 137 [8] = "Dynamic QP updates support",
138 [9] = "Device managed flow steering IPoIB support", 138 [9] = "Device managed flow steering IPoIB support",
139 [10] = "TCP/IP offloads/flow-steering for VXLAN support" 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
140 [11] = "MAD DEMUX (Secure-Host) support"
140 }; 141 };
141 int i; 142 int i;
142 143
@@ -571,6 +572,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
571#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 572#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
572#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 573#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
573#define QUERY_DEV_CAP_VXLAN 0x9e 574#define QUERY_DEV_CAP_VXLAN 0x9e
575#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
574 576
575 dev_cap->flags2 = 0; 577 dev_cap->flags2 = 0;
576 mailbox = mlx4_alloc_cmd_mailbox(dev); 578 mailbox = mlx4_alloc_cmd_mailbox(dev);
@@ -748,6 +750,11 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
748 MLX4_GET(dev_cap->max_counters, outbox, 750 MLX4_GET(dev_cap->max_counters, outbox,
749 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 751 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
750 752
753 MLX4_GET(field32, outbox,
754 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
755 if (field32 & (1 << 0))
756 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
757
751 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 758 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
752 if (field32 & (1 << 16)) 759 if (field32 & (1 << 16))
753 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 760 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
@@ -2016,3 +2023,85 @@ void mlx4_opreq_action(struct work_struct *work)
2016out: 2023out:
2017 mlx4_free_cmd_mailbox(dev, mailbox); 2024 mlx4_free_cmd_mailbox(dev, mailbox);
2018} 2025}
2026
2027static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2028 struct mlx4_cmd_mailbox *mailbox)
2029{
2030#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2031#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2032#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2033#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2034
2035 u32 set_attr_mask, getresp_attr_mask;
2036 u32 trap_attr_mask, traprepress_attr_mask;
2037
2038 MLX4_GET(set_attr_mask, mailbox->buf,
2039 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2040 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2041 set_attr_mask);
2042
2043 MLX4_GET(getresp_attr_mask, mailbox->buf,
2044 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2045 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2046 getresp_attr_mask);
2047
2048 MLX4_GET(trap_attr_mask, mailbox->buf,
2049 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2050 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2051 trap_attr_mask);
2052
2053 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2054 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2055 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2056 traprepress_attr_mask);
2057
2058 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2059 traprepress_attr_mask)
2060 return 1;
2061
2062 return 0;
2063}
2064
2065int mlx4_config_mad_demux(struct mlx4_dev *dev)
2066{
2067 struct mlx4_cmd_mailbox *mailbox;
2068 int secure_host_active;
2069 int err;
2070
2071 /* Check if mad_demux is supported */
2072 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2073 return 0;
2074
2075 mailbox = mlx4_alloc_cmd_mailbox(dev);
2076 if (IS_ERR(mailbox)) {
2077 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2078 return -ENOMEM;
2079 }
2080
2081 /* Query mad_demux to find out which MADs are handled by internal sma */
2082 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2083 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2084 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2085 if (err) {
2086 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2087 err);
2088 goto out;
2089 }
2090
2091 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2092
2093 /* Config mad_demux to handle all MADs returned by the query above */
2094 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2095 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2096 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2097 if (err) {
2098 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2099 goto out;
2100 }
2101
2102 if (secure_host_active)
2103 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2104out:
2105 mlx4_free_cmd_mailbox(dev, mailbox);
2106 return err;
2107}