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path: root/drivers/net/ethernet/mellanox/mlx4/eq.c
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Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx4/eq.c')
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/eq.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/eq.c b/drivers/net/ethernet/mellanox/mlx4/eq.c
index 8fa41f3082cf..9129ace02560 100644
--- a/drivers/net/ethernet/mellanox/mlx4/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx4/eq.c
@@ -1036,7 +1036,7 @@ int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector)
1036 struct mlx4_priv *priv = mlx4_priv(dev); 1036 struct mlx4_priv *priv = mlx4_priv(dev);
1037 int vec = 0, err = 0, i; 1037 int vec = 0, err = 0, i;
1038 1038
1039 spin_lock(&priv->msix_ctl.pool_lock); 1039 mutex_lock(&priv->msix_ctl.pool_lock);
1040 for (i = 0; !vec && i < dev->caps.comp_pool; i++) { 1040 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1041 if (~priv->msix_ctl.pool_bm & 1ULL << i) { 1041 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1042 priv->msix_ctl.pool_bm |= 1ULL << i; 1042 priv->msix_ctl.pool_bm |= 1ULL << i;
@@ -1058,7 +1058,7 @@ int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector)
1058 eq_set_ci(&priv->eq_table.eq[vec], 1); 1058 eq_set_ci(&priv->eq_table.eq[vec], 1);
1059 } 1059 }
1060 } 1060 }
1061 spin_unlock(&priv->msix_ctl.pool_lock); 1061 mutex_unlock(&priv->msix_ctl.pool_lock);
1062 1062
1063 if (vec) { 1063 if (vec) {
1064 *vector = vec; 1064 *vector = vec;
@@ -1079,13 +1079,13 @@ void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1079 if (likely(i >= 0)) { 1079 if (likely(i >= 0)) {
1080 /*sanity check , making sure were not trying to free irq's 1080 /*sanity check , making sure were not trying to free irq's
1081 Belonging to a legacy EQ*/ 1081 Belonging to a legacy EQ*/
1082 spin_lock(&priv->msix_ctl.pool_lock); 1082 mutex_lock(&priv->msix_ctl.pool_lock);
1083 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1083 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1084 free_irq(priv->eq_table.eq[vec].irq, 1084 free_irq(priv->eq_table.eq[vec].irq,
1085 &priv->eq_table.eq[vec]); 1085 &priv->eq_table.eq[vec]);
1086 priv->msix_ctl.pool_bm &= ~(1ULL << i); 1086 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1087 } 1087 }
1088 spin_unlock(&priv->msix_ctl.pool_lock); 1088 mutex_unlock(&priv->msix_ctl.pool_lock);
1089 } 1089 }
1090 1090
1091} 1091}