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-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.h72
1 files changed, 44 insertions, 28 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
index 217090df33e7..bead50f9187b 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.h
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
@@ -1,30 +1,23 @@
1/******************************************************************************* 1/* Intel PRO/1000 Linux driver
2 2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 Intel PRO/1000 Linux driver 3 *
4 Copyright(c) 1999 - 2013 Intel Corporation. 4 * This program is free software; you can redistribute it and/or modify it
5 5 * under the terms and conditions of the GNU General Public License,
6 This program is free software; you can redistribute it and/or modify it 6 * version 2, as published by the Free Software Foundation.
7 under the terms and conditions of the GNU General Public License, 7 *
8 version 2, as published by the Free Software Foundation. 8 * This program is distributed in the hope it will be useful, but WITHOUT
9 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 This program is distributed in the hope it will be useful, but WITHOUT 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * more details.
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 *
13 more details. 13 * The full GNU General Public License is included in this distribution in
14 14 * the file called "COPYING".
15 You should have received a copy of the GNU General Public License along with 15 *
16 this program; if not, write to the Free Software Foundation, Inc., 16 * Contact Information:
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * Linux NICS <linux.nics@intel.com>
18 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 The full GNU General Public License is included in this distribution in 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 the file called "COPYING". 20 */
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28 21
29#ifndef _E1000E_ICH8LAN_H_ 22#ifndef _E1000E_ICH8LAN_H_
30#define _E1000E_ICH8LAN_H_ 23#define _E1000E_ICH8LAN_H_
@@ -65,11 +58,16 @@
65 58
66#define E1000_FWSM_WLOCK_MAC_MASK 0x0380 59#define E1000_FWSM_WLOCK_MAC_MASK 0x0380
67#define E1000_FWSM_WLOCK_MAC_SHIFT 7 60#define E1000_FWSM_WLOCK_MAC_SHIFT 7
61#define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
68 62
69/* Shared Receive Address Registers */ 63/* Shared Receive Address Registers */
70#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 64#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
71#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 65#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
72 66
67#define E1000_H2ME 0x05B50 /* Host to ME */
68#define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
69#define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
70
73#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 71#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
74 (ID_LED_OFF1_OFF2 << 8) | \ 72 (ID_LED_OFF1_OFF2 << 8) | \
75 (ID_LED_OFF1_ON2 << 4) | \ 73 (ID_LED_OFF1_ON2 << 4) | \
@@ -82,6 +80,9 @@
82 80
83#define E1000_ICH8_LAN_INIT_TIMEOUT 1500 81#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
84 82
83/* FEXT register bit definition */
84#define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
85
85#define E1000_FEXTNVM_SW_CONFIG 1 86#define E1000_FEXTNVM_SW_CONFIG 1
86#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ 87#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
87 88
@@ -95,10 +96,12 @@
95#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 96#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
96#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 97#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
97 98
99#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
100
98#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 101#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
99 102
100#define E1000_ICH_RAR_ENTRIES 7 103#define E1000_ICH_RAR_ENTRIES 7
101#define E1000_PCH2_RAR_ENTRIES 11 /* RAR[0-6], SHRA[0-3] */ 104#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
102#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 105#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
103 106
104#define PHY_PAGE_SHIFT 5 107#define PHY_PAGE_SHIFT 5
@@ -161,6 +164,16 @@
161#define CV_SMB_CTRL PHY_REG(769, 23) 164#define CV_SMB_CTRL PHY_REG(769, 23)
162#define CV_SMB_CTRL_FORCE_SMBUS 0x0001 165#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
163 166
167/* I218 Ultra Low Power Configuration 1 Register */
168#define I218_ULP_CONFIG1 PHY_REG(779, 16)
169#define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
170#define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
171#define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
172#define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
173#define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
174#define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
175#define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
176
164/* SMBus Address Phy Register */ 177/* SMBus Address Phy Register */
165#define HV_SMB_ADDR PHY_REG(768, 26) 178#define HV_SMB_ADDR PHY_REG(768, 26)
166#define HV_SMB_ADDR_MASK 0x007F 179#define HV_SMB_ADDR_MASK 0x007F
@@ -195,6 +208,7 @@
195/* PHY Power Management Control */ 208/* PHY Power Management Control */
196#define HV_PM_CTRL PHY_REG(770, 17) 209#define HV_PM_CTRL PHY_REG(770, 17)
197#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 210#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
211#define HV_PM_CTRL_K1_ENABLE 0x4000
198 212
199#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 213#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
200 214
@@ -268,4 +282,6 @@ void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
268s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 282s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
269s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 283s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
270s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 284s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
285s32 e1000_set_eee_pchlan(struct e1000_hw *hw);
286s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
271#endif /* _E1000E_ICH8LAN_H_ */ 287#endif /* _E1000E_ICH8LAN_H_ */