1 files changed, 23 insertions, 43 deletions

diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
index 4dd18a1f45d2..e73c2c355993 100644
--- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
@@ -26,8 +26,7 @@
 
 *******************************************************************************/
 
-/*
- * 80003ES2LAN Gigabit Ethernet Controller (Copper)
+/* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  */
 
@@ -80,7 +79,8 @@
                                                            1 = 50-80M
                                                            2 = 80-110M
                                                            3 = 110-140M
-                                                           4 = >140M */
+                                                           4 = >140M
+                                                        */
 
 /* Kumeran Mode Control Register (Page 193, Register 16) */
 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
@@ -95,8 +95,7 @@
 /* In-Band Control Register (Page 194, Register 18) */
 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
 
-/*
- * A table for the GG82563 cable length where the range is defined
+/* A table for the GG82563 cable length where the range is defined
  * with a lower bound at "index" and the upper bound at
  * "index + 5".
  */
@@ -183,8 +182,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
                           E1000_EECD_SIZE_EX_SHIFT);
 
-        /*
-         * Added to a constant, "size" becomes the left-shift value
+        /* Added to a constant, "size" becomes the left-shift value
          * for setting word_size.
          */
         size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -375,8 +373,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
                 if (!(swfw_sync & (fwmask | swmask)))
                         break;
 
-                /*
-                 * Firmware currently using resource (fwmask)
+                /* Firmware currently using resource (fwmask)
                  * or other software thread using resource (swmask)
                  */
                 e1000e_put_hw_semaphore(hw);
@@ -442,8 +439,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
                 page_select = GG82563_PHY_PAGE_SELECT;
         } else {
-                /*
-                 * Use Alternative Page Select register to access
+                /* Use Alternative Page Select register to access
                  * registers 30 and 31
                  */
                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -457,8 +453,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
         }
 
         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
-                /*
-                 * The "ready" bit in the MDIC register may be incorrectly set
+                /* The "ready" bit in the MDIC register may be incorrectly set
                  * before the device has completed the "Page Select" MDI
                  * transaction.  So we wait 200us after each MDI command...
                  */
@@ -513,8 +508,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
                 page_select = GG82563_PHY_PAGE_SELECT;
         } else {
-                /*
-                 * Use Alternative Page Select register to access
+                /* Use Alternative Page Select register to access
                  * registers 30 and 31
                  */
                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -528,8 +522,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
         }
 
         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
-                /*
-                 * The "ready" bit in the MDIC register may be incorrectly set
+                /* The "ready" bit in the MDIC register may be incorrectly set
                  * before the device has completed the "Page Select" MDI
                  * transaction.  So we wait 200us after each MDI command...
                  */
@@ -618,8 +611,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
         u16 phy_data;
         bool link;
 
-        /*
-         * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
+        /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
          * forced whenever speed and duplex are forced.
          */
         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -657,8 +649,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
                         return ret_val;
 
                 if (!link) {
-                        /*
-                         * We didn't get link.
+                        /* We didn't get link.
                          * Reset the DSP and cross our fingers.
                          */
                         ret_val = e1000e_phy_reset_dsp(hw);
@@ -677,8 +668,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /*
-         * Resetting the phy means we need to verify the TX_CLK corresponds
+        /* Resetting the phy means we need to verify the TX_CLK corresponds
          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
          */
         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
@@ -687,8 +677,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
         else
                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 
-        /*
-         * In addition, we must re-enable CRS on Tx for both half and full
+        /* In addition, we must re-enable CRS on Tx for both half and full
          * duplex.
          */
         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -766,8 +755,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
         s32 ret_val;
         u16 kum_reg_data;
 
-        /*
-         * Prevent the PCI-E bus from sticking if there is no TLP connection
+        /* Prevent the PCI-E bus from sticking if there is no TLP connection
          * on the last TLP read/write transaction when MAC is reset.
          */
         ret_val = e1000e_disable_pcie_master(hw);
@@ -899,8 +887,7 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
         }
 
-        /*
-         * Clear all of the statistics registers (clear on read).  It is
+        /* Clear all of the statistics registers (clear on read).  It is
          * important that we do this after we have tried to establish link
          * because the symbol error count will increment wildly if there
          * is no link.
@@ -945,8 +932,7 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
                 reg |= (1 << 28);
         ew32(TARC(1), reg);
 
-        /*
-         * Disable IPv6 extension header parsing because some malformed
+        /* Disable IPv6 extension header parsing because some malformed
          * IPv6 headers can hang the Rx.
          */
         reg = er32(RFCTL);
@@ -979,8 +965,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /*
-         * Options:
+        /* Options:
          *   MDI/MDI-X = 0 (default)
          *   0 - Auto for all speeds
          *   1 - MDI mode
@@ -1006,8 +991,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
                 break;
         }
 
-        /*
-         * Options:
+        /* Options:
          *   disable_polarity_correction = 0 (default)
          *       Automatic Correction for Reversed Cable Polarity
          *   0 - Disabled
@@ -1065,8 +1049,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
         if (ret_val)
                 return ret_val;
 
-        /*
-         * Do not init these registers when the HW is in IAMT mode, since the
+        /* Do not init these registers when the HW is in IAMT mode, since the
          * firmware will have already initialized them.  We only initialize
          * them if the HW is not in IAMT mode.
          */
@@ -1087,8 +1070,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
                         return ret_val;
         }
 
-        /*
-         * Workaround: Disable padding in Kumeran interface in the MAC
+        /* Workaround: Disable padding in Kumeran interface in the MAC
          * and in the PHY to avoid CRC errors.
          */
         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
@@ -1121,8 +1103,7 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
         ew32(CTRL, ctrl);
 
-        /*
-         * Set the mac to wait the maximum time between each
+        /* Set the mac to wait the maximum time between each
          * iteration and increase the max iterations when
          * polling the phy; this fixes erroneous timeouts at 10Mbps.
          */
@@ -1352,8 +1333,7 @@ static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
 {
         s32 ret_val = 0;
 
-        /*
-         * If there's an alternate MAC address place it in RAR0
+        /* If there's an alternate MAC address place it in RAR0
          * so that it will override the Si installed default perm
          * address.
          */