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Diffstat (limited to 'drivers/net/ethernet/freescale/fec.c')
-rw-r--r--drivers/net/ethernet/freescale/fec.c1663
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diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
new file mode 100644
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1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010 Freescale Semiconductor, Inc.
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/pci.h>
33#include <linux/init.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/spinlock.h>
39#include <linux/workqueue.h>
40#include <linux/bitops.h>
41#include <linux/io.h>
42#include <linux/irq.h>
43#include <linux/clk.h>
44#include <linux/platform_device.h>
45#include <linux/phy.h>
46#include <linux/fec.h>
47#include <linux/of.h>
48#include <linux/of_device.h>
49#include <linux/of_gpio.h>
50#include <linux/of_net.h>
51
52#include <asm/cacheflush.h>
53
54#ifndef CONFIG_ARM
55#include <asm/coldfire.h>
56#include <asm/mcfsim.h>
57#endif
58
59#include "fec.h"
60
61#if defined(CONFIG_ARM)
62#define FEC_ALIGNMENT 0xf
63#else
64#define FEC_ALIGNMENT 0x3
65#endif
66
67#define DRIVER_NAME "fec"
68
69/* Controller is ENET-MAC */
70#define FEC_QUIRK_ENET_MAC (1 << 0)
71/* Controller needs driver to swap frame */
72#define FEC_QUIRK_SWAP_FRAME (1 << 1)
73/* Controller uses gasket */
74#define FEC_QUIRK_USE_GASKET (1 << 2)
75
76static struct platform_device_id fec_devtype[] = {
77 {
78 /* keep it for coldfire */
79 .name = DRIVER_NAME,
80 .driver_data = 0,
81 }, {
82 .name = "imx25-fec",
83 .driver_data = FEC_QUIRK_USE_GASKET,
84 }, {
85 .name = "imx27-fec",
86 .driver_data = 0,
87 }, {
88 .name = "imx28-fec",
89 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
90 }, {
91 /* sentinel */
92 }
93};
94MODULE_DEVICE_TABLE(platform, fec_devtype);
95
96enum imx_fec_type {
97 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
98 IMX27_FEC, /* runs on i.mx27/35/51 */
99 IMX28_FEC,
100};
101
102static const struct of_device_id fec_dt_ids[] = {
103 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
104 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
105 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
106 { /* sentinel */ }
107};
108MODULE_DEVICE_TABLE(of, fec_dt_ids);
109
110static unsigned char macaddr[ETH_ALEN];
111module_param_array(macaddr, byte, NULL, 0);
112MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
113
114#if defined(CONFIG_M5272)
115/*
116 * Some hardware gets it MAC address out of local flash memory.
117 * if this is non-zero then assume it is the address to get MAC from.
118 */
119#if defined(CONFIG_NETtel)
120#define FEC_FLASHMAC 0xf0006006
121#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
122#define FEC_FLASHMAC 0xf0006000
123#elif defined(CONFIG_CANCam)
124#define FEC_FLASHMAC 0xf0020000
125#elif defined (CONFIG_M5272C3)
126#define FEC_FLASHMAC (0xffe04000 + 4)
127#elif defined(CONFIG_MOD5272)
128#define FEC_FLASHMAC 0xffc0406b
129#else
130#define FEC_FLASHMAC 0
131#endif
132#endif /* CONFIG_M5272 */
133
134/* The number of Tx and Rx buffers. These are allocated from the page
135 * pool. The code may assume these are power of two, so it it best
136 * to keep them that size.
137 * We don't need to allocate pages for the transmitter. We just use
138 * the skbuffer directly.
139 */
140#define FEC_ENET_RX_PAGES 8
141#define FEC_ENET_RX_FRSIZE 2048
142#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
143#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
144#define FEC_ENET_TX_FRSIZE 2048
145#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
146#define TX_RING_SIZE 16 /* Must be power of two */
147#define TX_RING_MOD_MASK 15 /* for this to work */
148
149#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
150#error "FEC: descriptor ring size constants too large"
151#endif
152
153/* Interrupt events/masks. */
154#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
155#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
156#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
157#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
158#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
159#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
160#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
161#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
162#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
163#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
164
165#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
166
167/* The FEC stores dest/src/type, data, and checksum for receive packets.
168 */
169#define PKT_MAXBUF_SIZE 1518
170#define PKT_MINBUF_SIZE 64
171#define PKT_MAXBLR_SIZE 1520
172
173
174/*
175 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
176 * size bits. Other FEC hardware does not, so we need to take that into
177 * account when setting it.
178 */
179#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
180 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
181#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
182#else
183#define OPT_FRAME_SIZE 0
184#endif
185
186/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
187 * tx_bd_base always point to the base of the buffer descriptors. The
188 * cur_rx and cur_tx point to the currently available buffer.
189 * The dirty_tx tracks the current buffer that is being sent by the
190 * controller. The cur_tx and dirty_tx are equal under both completely
191 * empty and completely full conditions. The empty/ready indicator in
192 * the buffer descriptor determines the actual condition.
193 */
194struct fec_enet_private {
195 /* Hardware registers of the FEC device */
196 void __iomem *hwp;
197
198 struct net_device *netdev;
199
200 struct clk *clk;
201
202 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
203 unsigned char *tx_bounce[TX_RING_SIZE];
204 struct sk_buff* tx_skbuff[TX_RING_SIZE];
205 struct sk_buff* rx_skbuff[RX_RING_SIZE];
206 ushort skb_cur;
207 ushort skb_dirty;
208
209 /* CPM dual port RAM relative addresses */
210 dma_addr_t bd_dma;
211 /* Address of Rx and Tx buffers */
212 struct bufdesc *rx_bd_base;
213 struct bufdesc *tx_bd_base;
214 /* The next free ring entry */
215 struct bufdesc *cur_rx, *cur_tx;
216 /* The ring entries to be free()ed */
217 struct bufdesc *dirty_tx;
218
219 uint tx_full;
220 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
221 spinlock_t hw_lock;
222
223 struct platform_device *pdev;
224
225 int opened;
226
227 /* Phylib and MDIO interface */
228 struct mii_bus *mii_bus;
229 struct phy_device *phy_dev;
230 int mii_timeout;
231 uint phy_speed;
232 phy_interface_t phy_interface;
233 int link;
234 int full_duplex;
235 struct completion mdio_done;
236};
237
238/* FEC MII MMFR bits definition */
239#define FEC_MMFR_ST (1 << 30)
240#define FEC_MMFR_OP_READ (2 << 28)
241#define FEC_MMFR_OP_WRITE (1 << 28)
242#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
243#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
244#define FEC_MMFR_TA (2 << 16)
245#define FEC_MMFR_DATA(v) (v & 0xffff)
246
247#define FEC_MII_TIMEOUT 1000 /* us */
248
249/* Transmitter timeout */
250#define TX_TIMEOUT (2 * HZ)
251
252static void *swap_buffer(void *bufaddr, int len)
253{
254 int i;
255 unsigned int *buf = bufaddr;
256
257 for (i = 0; i < (len + 3) / 4; i++, buf++)
258 *buf = cpu_to_be32(*buf);
259
260 return bufaddr;
261}
262
263static netdev_tx_t
264fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
265{
266 struct fec_enet_private *fep = netdev_priv(ndev);
267 const struct platform_device_id *id_entry =
268 platform_get_device_id(fep->pdev);
269 struct bufdesc *bdp;
270 void *bufaddr;
271 unsigned short status;
272 unsigned long flags;
273
274 if (!fep->link) {
275 /* Link is down or autonegotiation is in progress. */
276 return NETDEV_TX_BUSY;
277 }
278
279 spin_lock_irqsave(&fep->hw_lock, flags);
280 /* Fill in a Tx ring entry */
281 bdp = fep->cur_tx;
282
283 status = bdp->cbd_sc;
284
285 if (status & BD_ENET_TX_READY) {
286 /* Ooops. All transmit buffers are full. Bail out.
287 * This should not happen, since ndev->tbusy should be set.
288 */
289 printk("%s: tx queue full!.\n", ndev->name);
290 spin_unlock_irqrestore(&fep->hw_lock, flags);
291 return NETDEV_TX_BUSY;
292 }
293
294 /* Clear all of the status flags */
295 status &= ~BD_ENET_TX_STATS;
296
297 /* Set buffer length and buffer pointer */
298 bufaddr = skb->data;
299 bdp->cbd_datlen = skb->len;
300
301 /*
302 * On some FEC implementations data must be aligned on
303 * 4-byte boundaries. Use bounce buffers to copy data
304 * and get it aligned. Ugh.
305 */
306 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
307 unsigned int index;
308 index = bdp - fep->tx_bd_base;
309 memcpy(fep->tx_bounce[index], skb->data, skb->len);
310 bufaddr = fep->tx_bounce[index];
311 }
312
313 /*
314 * Some design made an incorrect assumption on endian mode of
315 * the system that it's running on. As the result, driver has to
316 * swap every frame going to and coming from the controller.
317 */
318 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
319 swap_buffer(bufaddr, skb->len);
320
321 /* Save skb pointer */
322 fep->tx_skbuff[fep->skb_cur] = skb;
323
324 ndev->stats.tx_bytes += skb->len;
325 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
326
327 /* Push the data cache so the CPM does not get stale memory
328 * data.
329 */
330 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
331 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
332
333 /* Send it on its way. Tell FEC it's ready, interrupt when done,
334 * it's the last BD of the frame, and to put the CRC on the end.
335 */
336 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
337 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
338 bdp->cbd_sc = status;
339
340 /* Trigger transmission start */
341 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
342
343 /* If this was the last BD in the ring, start at the beginning again. */
344 if (status & BD_ENET_TX_WRAP)
345 bdp = fep->tx_bd_base;
346 else
347 bdp++;
348
349 if (bdp == fep->dirty_tx) {
350 fep->tx_full = 1;
351 netif_stop_queue(ndev);
352 }
353
354 fep->cur_tx = bdp;
355
356 skb_tx_timestamp(skb);
357
358 spin_unlock_irqrestore(&fep->hw_lock, flags);
359
360 return NETDEV_TX_OK;
361}
362
363/* This function is called to start or restart the FEC during a link
364 * change. This only happens when switching between half and full
365 * duplex.
366 */
367static void
368fec_restart(struct net_device *ndev, int duplex)
369{
370 struct fec_enet_private *fep = netdev_priv(ndev);
371 const struct platform_device_id *id_entry =
372 platform_get_device_id(fep->pdev);
373 int i;
374 u32 temp_mac[2];
375 u32 rcntl = OPT_FRAME_SIZE | 0x04;
376
377 /* Whack a reset. We should wait for this. */
378 writel(1, fep->hwp + FEC_ECNTRL);
379 udelay(10);
380
381 /*
382 * enet-mac reset will reset mac address registers too,
383 * so need to reconfigure it.
384 */
385 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
386 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
387 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
388 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
389 }
390
391 /* Clear any outstanding interrupt. */
392 writel(0xffc00000, fep->hwp + FEC_IEVENT);
393
394 /* Reset all multicast. */
395 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
396 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
397#ifndef CONFIG_M5272
398 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
399 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
400#endif
401
402 /* Set maximum receive buffer size. */
403 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
404
405 /* Set receive and transmit descriptor base. */
406 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
407 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
408 fep->hwp + FEC_X_DES_START);
409
410 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
411 fep->cur_rx = fep->rx_bd_base;
412
413 /* Reset SKB transmit buffers. */
414 fep->skb_cur = fep->skb_dirty = 0;
415 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
416 if (fep->tx_skbuff[i]) {
417 dev_kfree_skb_any(fep->tx_skbuff[i]);
418 fep->tx_skbuff[i] = NULL;
419 }
420 }
421
422 /* Enable MII mode */
423 if (duplex) {
424 /* FD enable */
425 writel(0x04, fep->hwp + FEC_X_CNTRL);
426 } else {
427 /* No Rcv on Xmit */
428 rcntl |= 0x02;
429 writel(0x0, fep->hwp + FEC_X_CNTRL);
430 }
431
432 fep->full_duplex = duplex;
433
434 /* Set MII speed */
435 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
436
437 /*
438 * The phy interface and speed need to get configured
439 * differently on enet-mac.
440 */
441 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
442 /* Enable flow control and length check */
443 rcntl |= 0x40000000 | 0x00000020;
444
445 /* MII or RMII */
446 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
447 rcntl |= (1 << 8);
448 else
449 rcntl &= ~(1 << 8);
450
451 /* 10M or 100M */
452 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
453 rcntl &= ~(1 << 9);
454 else
455 rcntl |= (1 << 9);
456
457 } else {
458#ifdef FEC_MIIGSK_ENR
459 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
460 /* disable the gasket and wait */
461 writel(0, fep->hwp + FEC_MIIGSK_ENR);
462 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
463 udelay(1);
464
465 /*
466 * configure the gasket:
467 * RMII, 50 MHz, no loopback, no echo
468 * MII, 25 MHz, no loopback, no echo
469 */
470 writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ?
471 1 : 0, fep->hwp + FEC_MIIGSK_CFGR);
472
473
474 /* re-enable the gasket */
475 writel(2, fep->hwp + FEC_MIIGSK_ENR);
476 }
477#endif
478 }
479 writel(rcntl, fep->hwp + FEC_R_CNTRL);
480
481 /* And last, enable the transmit and receive processing */
482 writel(2, fep->hwp + FEC_ECNTRL);
483 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
484
485 /* Enable interrupts we wish to service */
486 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
487}
488
489static void
490fec_stop(struct net_device *ndev)
491{
492 struct fec_enet_private *fep = netdev_priv(ndev);
493
494 /* We cannot expect a graceful transmit stop without link !!! */
495 if (fep->link) {
496 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
497 udelay(10);
498 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
499 printk("fec_stop : Graceful transmit stop did not complete !\n");
500 }
501
502 /* Whack a reset. We should wait for this. */
503 writel(1, fep->hwp + FEC_ECNTRL);
504 udelay(10);
505 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
506 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
507}
508
509
510static void
511fec_timeout(struct net_device *ndev)
512{
513 struct fec_enet_private *fep = netdev_priv(ndev);
514
515 ndev->stats.tx_errors++;
516
517 fec_restart(ndev, fep->full_duplex);
518 netif_wake_queue(ndev);
519}
520
521static void
522fec_enet_tx(struct net_device *ndev)
523{
524 struct fec_enet_private *fep;
525 struct bufdesc *bdp;
526 unsigned short status;
527 struct sk_buff *skb;
528
529 fep = netdev_priv(ndev);
530 spin_lock(&fep->hw_lock);
531 bdp = fep->dirty_tx;
532
533 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
534 if (bdp == fep->cur_tx && fep->tx_full == 0)
535 break;
536
537 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
538 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
539 bdp->cbd_bufaddr = 0;
540
541 skb = fep->tx_skbuff[fep->skb_dirty];
542 /* Check for errors. */
543 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
544 BD_ENET_TX_RL | BD_ENET_TX_UN |
545 BD_ENET_TX_CSL)) {
546 ndev->stats.tx_errors++;
547 if (status & BD_ENET_TX_HB) /* No heartbeat */
548 ndev->stats.tx_heartbeat_errors++;
549 if (status & BD_ENET_TX_LC) /* Late collision */
550 ndev->stats.tx_window_errors++;
551 if (status & BD_ENET_TX_RL) /* Retrans limit */
552 ndev->stats.tx_aborted_errors++;
553 if (status & BD_ENET_TX_UN) /* Underrun */
554 ndev->stats.tx_fifo_errors++;
555 if (status & BD_ENET_TX_CSL) /* Carrier lost */
556 ndev->stats.tx_carrier_errors++;
557 } else {
558 ndev->stats.tx_packets++;
559 }
560
561 if (status & BD_ENET_TX_READY)
562 printk("HEY! Enet xmit interrupt and TX_READY.\n");
563
564 /* Deferred means some collisions occurred during transmit,
565 * but we eventually sent the packet OK.
566 */
567 if (status & BD_ENET_TX_DEF)
568 ndev->stats.collisions++;
569
570 /* Free the sk buffer associated with this last transmit */
571 dev_kfree_skb_any(skb);
572 fep->tx_skbuff[fep->skb_dirty] = NULL;
573 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
574
575 /* Update pointer to next buffer descriptor to be transmitted */
576 if (status & BD_ENET_TX_WRAP)
577 bdp = fep->tx_bd_base;
578 else
579 bdp++;
580
581 /* Since we have freed up a buffer, the ring is no longer full
582 */
583 if (fep->tx_full) {
584 fep->tx_full = 0;
585 if (netif_queue_stopped(ndev))
586 netif_wake_queue(ndev);
587 }
588 }
589 fep->dirty_tx = bdp;
590 spin_unlock(&fep->hw_lock);
591}
592
593
594/* During a receive, the cur_rx points to the current incoming buffer.
595 * When we update through the ring, if the next incoming buffer has
596 * not been given to the system, we just set the empty indicator,
597 * effectively tossing the packet.
598 */
599static void
600fec_enet_rx(struct net_device *ndev)
601{
602 struct fec_enet_private *fep = netdev_priv(ndev);
603 const struct platform_device_id *id_entry =
604 platform_get_device_id(fep->pdev);
605 struct bufdesc *bdp;
606 unsigned short status;
607 struct sk_buff *skb;
608 ushort pkt_len;
609 __u8 *data;
610
611#ifdef CONFIG_M532x
612 flush_cache_all();
613#endif
614
615 spin_lock(&fep->hw_lock);
616
617 /* First, grab all of the stats for the incoming packet.
618 * These get messed up if we get called due to a busy condition.
619 */
620 bdp = fep->cur_rx;
621
622 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
623
624 /* Since we have allocated space to hold a complete frame,
625 * the last indicator should be set.
626 */
627 if ((status & BD_ENET_RX_LAST) == 0)
628 printk("FEC ENET: rcv is not +last\n");
629
630 if (!fep->opened)
631 goto rx_processing_done;
632
633 /* Check for errors. */
634 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
635 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
636 ndev->stats.rx_errors++;
637 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
638 /* Frame too long or too short. */
639 ndev->stats.rx_length_errors++;
640 }
641 if (status & BD_ENET_RX_NO) /* Frame alignment */
642 ndev->stats.rx_frame_errors++;
643 if (status & BD_ENET_RX_CR) /* CRC Error */
644 ndev->stats.rx_crc_errors++;
645 if (status & BD_ENET_RX_OV) /* FIFO overrun */
646 ndev->stats.rx_fifo_errors++;
647 }
648
649 /* Report late collisions as a frame error.
650 * On this error, the BD is closed, but we don't know what we
651 * have in the buffer. So, just drop this frame on the floor.
652 */
653 if (status & BD_ENET_RX_CL) {
654 ndev->stats.rx_errors++;
655 ndev->stats.rx_frame_errors++;
656 goto rx_processing_done;
657 }
658
659 /* Process the incoming frame. */
660 ndev->stats.rx_packets++;
661 pkt_len = bdp->cbd_datlen;
662 ndev->stats.rx_bytes += pkt_len;
663 data = (__u8*)__va(bdp->cbd_bufaddr);
664
665 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
666 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
667
668 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
669 swap_buffer(data, pkt_len);
670
671 /* This does 16 byte alignment, exactly what we need.
672 * The packet length includes FCS, but we don't want to
673 * include that when passing upstream as it messes up
674 * bridging applications.
675 */
676 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
677
678 if (unlikely(!skb)) {
679 printk("%s: Memory squeeze, dropping packet.\n",
680 ndev->name);
681 ndev->stats.rx_dropped++;
682 } else {
683 skb_reserve(skb, NET_IP_ALIGN);
684 skb_put(skb, pkt_len - 4); /* Make room */
685 skb_copy_to_linear_data(skb, data, pkt_len - 4);
686 skb->protocol = eth_type_trans(skb, ndev);
687 if (!skb_defer_rx_timestamp(skb))
688 netif_rx(skb);
689 }
690
691 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
692 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
693rx_processing_done:
694 /* Clear the status flags for this buffer */
695 status &= ~BD_ENET_RX_STATS;
696
697 /* Mark the buffer empty */
698 status |= BD_ENET_RX_EMPTY;
699 bdp->cbd_sc = status;
700
701 /* Update BD pointer to next entry */
702 if (status & BD_ENET_RX_WRAP)
703 bdp = fep->rx_bd_base;
704 else
705 bdp++;
706 /* Doing this here will keep the FEC running while we process
707 * incoming frames. On a heavily loaded network, we should be
708 * able to keep up at the expense of system resources.
709 */
710 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
711 }
712 fep->cur_rx = bdp;
713
714 spin_unlock(&fep->hw_lock);
715}
716
717static irqreturn_t
718fec_enet_interrupt(int irq, void *dev_id)
719{
720 struct net_device *ndev = dev_id;
721 struct fec_enet_private *fep = netdev_priv(ndev);
722 uint int_events;
723 irqreturn_t ret = IRQ_NONE;
724
725 do {
726 int_events = readl(fep->hwp + FEC_IEVENT);
727 writel(int_events, fep->hwp + FEC_IEVENT);
728
729 if (int_events & FEC_ENET_RXF) {
730 ret = IRQ_HANDLED;
731 fec_enet_rx(ndev);
732 }
733
734 /* Transmit OK, or non-fatal error. Update the buffer
735 * descriptors. FEC handles all errors, we just discover
736 * them as part of the transmit process.
737 */
738 if (int_events & FEC_ENET_TXF) {
739 ret = IRQ_HANDLED;
740 fec_enet_tx(ndev);
741 }
742
743 if (int_events & FEC_ENET_MII) {
744 ret = IRQ_HANDLED;
745 complete(&fep->mdio_done);
746 }
747 } while (int_events);
748
749 return ret;
750}
751
752
753
754/* ------------------------------------------------------------------------- */
755static void __inline__ fec_get_mac(struct net_device *ndev)
756{
757 struct fec_enet_private *fep = netdev_priv(ndev);
758 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
759 unsigned char *iap, tmpaddr[ETH_ALEN];
760
761 /*
762 * try to get mac address in following order:
763 *
764 * 1) module parameter via kernel command line in form
765 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
766 */
767 iap = macaddr;
768
769#ifdef CONFIG_OF
770 /*
771 * 2) from device tree data
772 */
773 if (!is_valid_ether_addr(iap)) {
774 struct device_node *np = fep->pdev->dev.of_node;
775 if (np) {
776 const char *mac = of_get_mac_address(np);
777 if (mac)
778 iap = (unsigned char *) mac;
779 }
780 }
781#endif
782
783 /*
784 * 3) from flash or fuse (via platform data)
785 */
786 if (!is_valid_ether_addr(iap)) {
787#ifdef CONFIG_M5272
788 if (FEC_FLASHMAC)
789 iap = (unsigned char *)FEC_FLASHMAC;
790#else
791 if (pdata)
792 memcpy(iap, pdata->mac, ETH_ALEN);
793#endif
794 }
795
796 /*
797 * 4) FEC mac registers set by bootloader
798 */
799 if (!is_valid_ether_addr(iap)) {
800 *((unsigned long *) &tmpaddr[0]) =
801 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
802 *((unsigned short *) &tmpaddr[4]) =
803 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
804 iap = &tmpaddr[0];
805 }
806
807 memcpy(ndev->dev_addr, iap, ETH_ALEN);
808
809 /* Adjust MAC if using macaddr */
810 if (iap == macaddr)
811 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
812}
813
814/* ------------------------------------------------------------------------- */
815
816/*
817 * Phy section
818 */
819static void fec_enet_adjust_link(struct net_device *ndev)
820{
821 struct fec_enet_private *fep = netdev_priv(ndev);
822 struct phy_device *phy_dev = fep->phy_dev;
823 unsigned long flags;
824
825 int status_change = 0;
826
827 spin_lock_irqsave(&fep->hw_lock, flags);
828
829 /* Prevent a state halted on mii error */
830 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
831 phy_dev->state = PHY_RESUMING;
832 goto spin_unlock;
833 }
834
835 /* Duplex link change */
836 if (phy_dev->link) {
837 if (fep->full_duplex != phy_dev->duplex) {
838 fec_restart(ndev, phy_dev->duplex);
839 status_change = 1;
840 }
841 }
842
843 /* Link on or off change */
844 if (phy_dev->link != fep->link) {
845 fep->link = phy_dev->link;
846 if (phy_dev->link)
847 fec_restart(ndev, phy_dev->duplex);
848 else
849 fec_stop(ndev);
850 status_change = 1;
851 }
852
853spin_unlock:
854 spin_unlock_irqrestore(&fep->hw_lock, flags);
855
856 if (status_change)
857 phy_print_status(phy_dev);
858}
859
860static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
861{
862 struct fec_enet_private *fep = bus->priv;
863 unsigned long time_left;
864
865 fep->mii_timeout = 0;
866 init_completion(&fep->mdio_done);
867
868 /* start a read op */
869 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
870 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
871 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
872
873 /* wait for end of transfer */
874 time_left = wait_for_completion_timeout(&fep->mdio_done,
875 usecs_to_jiffies(FEC_MII_TIMEOUT));
876 if (time_left == 0) {
877 fep->mii_timeout = 1;
878 printk(KERN_ERR "FEC: MDIO read timeout\n");
879 return -ETIMEDOUT;
880 }
881
882 /* return value */
883 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
884}
885
886static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
887 u16 value)
888{
889 struct fec_enet_private *fep = bus->priv;
890 unsigned long time_left;
891
892 fep->mii_timeout = 0;
893 init_completion(&fep->mdio_done);
894
895 /* start a write op */
896 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
897 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
898 FEC_MMFR_TA | FEC_MMFR_DATA(value),
899 fep->hwp + FEC_MII_DATA);
900
901 /* wait for end of transfer */
902 time_left = wait_for_completion_timeout(&fep->mdio_done,
903 usecs_to_jiffies(FEC_MII_TIMEOUT));
904 if (time_left == 0) {
905 fep->mii_timeout = 1;
906 printk(KERN_ERR "FEC: MDIO write timeout\n");
907 return -ETIMEDOUT;
908 }
909
910 return 0;
911}
912
913static int fec_enet_mdio_reset(struct mii_bus *bus)
914{
915 return 0;
916}
917
918static int fec_enet_mii_probe(struct net_device *ndev)
919{
920 struct fec_enet_private *fep = netdev_priv(ndev);
921 struct phy_device *phy_dev = NULL;
922 char mdio_bus_id[MII_BUS_ID_SIZE];
923 char phy_name[MII_BUS_ID_SIZE + 3];
924 int phy_id;
925 int dev_id = fep->pdev->id;
926
927 fep->phy_dev = NULL;
928
929 /* check for attached phy */
930 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
931 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
932 continue;
933 if (fep->mii_bus->phy_map[phy_id] == NULL)
934 continue;
935 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
936 continue;
937 if (dev_id--)
938 continue;
939 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
940 break;
941 }
942
943 if (phy_id >= PHY_MAX_ADDR) {
944 printk(KERN_INFO "%s: no PHY, assuming direct connection "
945 "to switch\n", ndev->name);
946 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
947 phy_id = 0;
948 }
949
950 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
951 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
952 PHY_INTERFACE_MODE_MII);
953 if (IS_ERR(phy_dev)) {
954 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
955 return PTR_ERR(phy_dev);
956 }
957
958 /* mask with MAC supported features */
959 phy_dev->supported &= PHY_BASIC_FEATURES;
960 phy_dev->advertising = phy_dev->supported;
961
962 fep->phy_dev = phy_dev;
963 fep->link = 0;
964 fep->full_duplex = 0;
965
966 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
967 "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name,
968 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
969 fep->phy_dev->irq);
970
971 return 0;
972}
973
974static int fec_enet_mii_init(struct platform_device *pdev)
975{
976 static struct mii_bus *fec0_mii_bus;
977 struct net_device *ndev = platform_get_drvdata(pdev);
978 struct fec_enet_private *fep = netdev_priv(ndev);
979 const struct platform_device_id *id_entry =
980 platform_get_device_id(fep->pdev);
981 int err = -ENXIO, i;
982
983 /*
984 * The dual fec interfaces are not equivalent with enet-mac.
985 * Here are the differences:
986 *
987 * - fec0 supports MII & RMII modes while fec1 only supports RMII
988 * - fec0 acts as the 1588 time master while fec1 is slave
989 * - external phys can only be configured by fec0
990 *
991 * That is to say fec1 can not work independently. It only works
992 * when fec0 is working. The reason behind this design is that the
993 * second interface is added primarily for Switch mode.
994 *
995 * Because of the last point above, both phys are attached on fec0
996 * mdio interface in board design, and need to be configured by
997 * fec0 mii_bus.
998 */
999 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
1000 /* fec1 uses fec0 mii_bus */
1001 fep->mii_bus = fec0_mii_bus;
1002 return 0;
1003 }
1004
1005 fep->mii_timeout = 0;
1006
1007 /*
1008 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1009 */
1010 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
1011 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1012
1013 fep->mii_bus = mdiobus_alloc();
1014 if (fep->mii_bus == NULL) {
1015 err = -ENOMEM;
1016 goto err_out;
1017 }
1018
1019 fep->mii_bus->name = "fec_enet_mii_bus";
1020 fep->mii_bus->read = fec_enet_mdio_read;
1021 fep->mii_bus->write = fec_enet_mdio_write;
1022 fep->mii_bus->reset = fec_enet_mdio_reset;
1023 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
1024 fep->mii_bus->priv = fep;
1025 fep->mii_bus->parent = &pdev->dev;
1026
1027 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1028 if (!fep->mii_bus->irq) {
1029 err = -ENOMEM;
1030 goto err_out_free_mdiobus;
1031 }
1032
1033 for (i = 0; i < PHY_MAX_ADDR; i++)
1034 fep->mii_bus->irq[i] = PHY_POLL;
1035
1036 if (mdiobus_register(fep->mii_bus))
1037 goto err_out_free_mdio_irq;
1038
1039 /* save fec0 mii_bus */
1040 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1041 fec0_mii_bus = fep->mii_bus;
1042
1043 return 0;
1044
1045err_out_free_mdio_irq:
1046 kfree(fep->mii_bus->irq);
1047err_out_free_mdiobus:
1048 mdiobus_free(fep->mii_bus);
1049err_out:
1050 return err;
1051}
1052
1053static void fec_enet_mii_remove(struct fec_enet_private *fep)
1054{
1055 if (fep->phy_dev)
1056 phy_disconnect(fep->phy_dev);
1057 mdiobus_unregister(fep->mii_bus);
1058 kfree(fep->mii_bus->irq);
1059 mdiobus_free(fep->mii_bus);
1060}
1061
1062static int fec_enet_get_settings(struct net_device *ndev,
1063 struct ethtool_cmd *cmd)
1064{
1065 struct fec_enet_private *fep = netdev_priv(ndev);
1066 struct phy_device *phydev = fep->phy_dev;
1067
1068 if (!phydev)
1069 return -ENODEV;
1070
1071 return phy_ethtool_gset(phydev, cmd);
1072}
1073
1074static int fec_enet_set_settings(struct net_device *ndev,
1075 struct ethtool_cmd *cmd)
1076{
1077 struct fec_enet_private *fep = netdev_priv(ndev);
1078 struct phy_device *phydev = fep->phy_dev;
1079
1080 if (!phydev)
1081 return -ENODEV;
1082
1083 return phy_ethtool_sset(phydev, cmd);
1084}
1085
1086static void fec_enet_get_drvinfo(struct net_device *ndev,
1087 struct ethtool_drvinfo *info)
1088{
1089 struct fec_enet_private *fep = netdev_priv(ndev);
1090
1091 strcpy(info->driver, fep->pdev->dev.driver->name);
1092 strcpy(info->version, "Revision: 1.0");
1093 strcpy(info->bus_info, dev_name(&ndev->dev));
1094}
1095
1096static struct ethtool_ops fec_enet_ethtool_ops = {
1097 .get_settings = fec_enet_get_settings,
1098 .set_settings = fec_enet_set_settings,
1099 .get_drvinfo = fec_enet_get_drvinfo,
1100 .get_link = ethtool_op_get_link,
1101};
1102
1103static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1104{
1105 struct fec_enet_private *fep = netdev_priv(ndev);
1106 struct phy_device *phydev = fep->phy_dev;
1107
1108 if (!netif_running(ndev))
1109 return -EINVAL;
1110
1111 if (!phydev)
1112 return -ENODEV;
1113
1114 return phy_mii_ioctl(phydev, rq, cmd);
1115}
1116
1117static void fec_enet_free_buffers(struct net_device *ndev)
1118{
1119 struct fec_enet_private *fep = netdev_priv(ndev);
1120 int i;
1121 struct sk_buff *skb;
1122 struct bufdesc *bdp;
1123
1124 bdp = fep->rx_bd_base;
1125 for (i = 0; i < RX_RING_SIZE; i++) {
1126 skb = fep->rx_skbuff[i];
1127
1128 if (bdp->cbd_bufaddr)
1129 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1130 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1131 if (skb)
1132 dev_kfree_skb(skb);
1133 bdp++;
1134 }
1135
1136 bdp = fep->tx_bd_base;
1137 for (i = 0; i < TX_RING_SIZE; i++)
1138 kfree(fep->tx_bounce[i]);
1139}
1140
1141static int fec_enet_alloc_buffers(struct net_device *ndev)
1142{
1143 struct fec_enet_private *fep = netdev_priv(ndev);
1144 int i;
1145 struct sk_buff *skb;
1146 struct bufdesc *bdp;
1147
1148 bdp = fep->rx_bd_base;
1149 for (i = 0; i < RX_RING_SIZE; i++) {
1150 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
1151 if (!skb) {
1152 fec_enet_free_buffers(ndev);
1153 return -ENOMEM;
1154 }
1155 fep->rx_skbuff[i] = skb;
1156
1157 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1158 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1159 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1160 bdp++;
1161 }
1162
1163 /* Set the last buffer to wrap. */
1164 bdp--;
1165 bdp->cbd_sc |= BD_SC_WRAP;
1166
1167 bdp = fep->tx_bd_base;
1168 for (i = 0; i < TX_RING_SIZE; i++) {
1169 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1170
1171 bdp->cbd_sc = 0;
1172 bdp->cbd_bufaddr = 0;
1173 bdp++;
1174 }
1175
1176 /* Set the last buffer to wrap. */
1177 bdp--;
1178 bdp->cbd_sc |= BD_SC_WRAP;
1179
1180 return 0;
1181}
1182
1183static int
1184fec_enet_open(struct net_device *ndev)
1185{
1186 struct fec_enet_private *fep = netdev_priv(ndev);
1187 int ret;
1188
1189 /* I should reset the ring buffers here, but I don't yet know
1190 * a simple way to do that.
1191 */
1192
1193 ret = fec_enet_alloc_buffers(ndev);
1194 if (ret)
1195 return ret;
1196
1197 /* Probe and connect to PHY when open the interface */
1198 ret = fec_enet_mii_probe(ndev);
1199 if (ret) {
1200 fec_enet_free_buffers(ndev);
1201 return ret;
1202 }
1203 phy_start(fep->phy_dev);
1204 netif_start_queue(ndev);
1205 fep->opened = 1;
1206 return 0;
1207}
1208
1209static int
1210fec_enet_close(struct net_device *ndev)
1211{
1212 struct fec_enet_private *fep = netdev_priv(ndev);
1213
1214 /* Don't know what to do yet. */
1215 fep->opened = 0;
1216 netif_stop_queue(ndev);
1217 fec_stop(ndev);
1218
1219 if (fep->phy_dev) {
1220 phy_stop(fep->phy_dev);
1221 phy_disconnect(fep->phy_dev);
1222 }
1223
1224 fec_enet_free_buffers(ndev);
1225
1226 return 0;
1227}
1228
1229/* Set or clear the multicast filter for this adaptor.
1230 * Skeleton taken from sunlance driver.
1231 * The CPM Ethernet implementation allows Multicast as well as individual
1232 * MAC address filtering. Some of the drivers check to make sure it is
1233 * a group multicast address, and discard those that are not. I guess I
1234 * will do the same for now, but just remove the test if you want
1235 * individual filtering as well (do the upper net layers want or support
1236 * this kind of feature?).
1237 */
1238
1239#define HASH_BITS 6 /* #bits in hash */
1240#define CRC32_POLY 0xEDB88320
1241
1242static void set_multicast_list(struct net_device *ndev)
1243{
1244 struct fec_enet_private *fep = netdev_priv(ndev);
1245 struct netdev_hw_addr *ha;
1246 unsigned int i, bit, data, crc, tmp;
1247 unsigned char hash;
1248
1249 if (ndev->flags & IFF_PROMISC) {
1250 tmp = readl(fep->hwp + FEC_R_CNTRL);
1251 tmp |= 0x8;
1252 writel(tmp, fep->hwp + FEC_R_CNTRL);
1253 return;
1254 }
1255
1256 tmp = readl(fep->hwp + FEC_R_CNTRL);
1257 tmp &= ~0x8;
1258 writel(tmp, fep->hwp + FEC_R_CNTRL);
1259
1260 if (ndev->flags & IFF_ALLMULTI) {
1261 /* Catch all multicast addresses, so set the
1262 * filter to all 1's
1263 */
1264 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1265 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1266
1267 return;
1268 }
1269
1270 /* Clear filter and add the addresses in hash register
1271 */
1272 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1273 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1274
1275 netdev_for_each_mc_addr(ha, ndev) {
1276 /* calculate crc32 value of mac address */
1277 crc = 0xffffffff;
1278
1279 for (i = 0; i < ndev->addr_len; i++) {
1280 data = ha->addr[i];
1281 for (bit = 0; bit < 8; bit++, data >>= 1) {
1282 crc = (crc >> 1) ^
1283 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1284 }
1285 }
1286
1287 /* only upper 6 bits (HASH_BITS) are used
1288 * which point to specific bit in he hash registers
1289 */
1290 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1291
1292 if (hash > 31) {
1293 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1294 tmp |= 1 << (hash - 32);
1295 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1296 } else {
1297 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1298 tmp |= 1 << hash;
1299 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1300 }
1301 }
1302}
1303
1304/* Set a MAC change in hardware. */
1305static int
1306fec_set_mac_address(struct net_device *ndev, void *p)
1307{
1308 struct fec_enet_private *fep = netdev_priv(ndev);
1309 struct sockaddr *addr = p;
1310
1311 if (!is_valid_ether_addr(addr->sa_data))
1312 return -EADDRNOTAVAIL;
1313
1314 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1315
1316 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1317 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1318 fep->hwp + FEC_ADDR_LOW);
1319 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1320 fep->hwp + FEC_ADDR_HIGH);
1321 return 0;
1322}
1323
1324static const struct net_device_ops fec_netdev_ops = {
1325 .ndo_open = fec_enet_open,
1326 .ndo_stop = fec_enet_close,
1327 .ndo_start_xmit = fec_enet_start_xmit,
1328 .ndo_set_multicast_list = set_multicast_list,
1329 .ndo_change_mtu = eth_change_mtu,
1330 .ndo_validate_addr = eth_validate_addr,
1331 .ndo_tx_timeout = fec_timeout,
1332 .ndo_set_mac_address = fec_set_mac_address,
1333 .ndo_do_ioctl = fec_enet_ioctl,
1334};
1335
1336 /*
1337 * XXX: We need to clean up on failure exits here.
1338 *
1339 */
1340static int fec_enet_init(struct net_device *ndev)
1341{
1342 struct fec_enet_private *fep = netdev_priv(ndev);
1343 struct bufdesc *cbd_base;
1344 struct bufdesc *bdp;
1345 int i;
1346
1347 /* Allocate memory for buffer descriptors. */
1348 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1349 GFP_KERNEL);
1350 if (!cbd_base) {
1351 printk("FEC: allocate descriptor memory failed?\n");
1352 return -ENOMEM;
1353 }
1354
1355 spin_lock_init(&fep->hw_lock);
1356
1357 fep->netdev = ndev;
1358
1359 /* Get the Ethernet address */
1360 fec_get_mac(ndev);
1361
1362 /* Set receive and transmit descriptor base. */
1363 fep->rx_bd_base = cbd_base;
1364 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1365
1366 /* The FEC Ethernet specific entries in the device structure */
1367 ndev->watchdog_timeo = TX_TIMEOUT;
1368 ndev->netdev_ops = &fec_netdev_ops;
1369 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1370
1371 /* Initialize the receive buffer descriptors. */
1372 bdp = fep->rx_bd_base;
1373 for (i = 0; i < RX_RING_SIZE; i++) {
1374
1375 /* Initialize the BD for every fragment in the page. */
1376 bdp->cbd_sc = 0;
1377 bdp++;
1378 }
1379
1380 /* Set the last buffer to wrap */
1381 bdp--;
1382 bdp->cbd_sc |= BD_SC_WRAP;
1383
1384 /* ...and the same for transmit */
1385 bdp = fep->tx_bd_base;
1386 for (i = 0; i < TX_RING_SIZE; i++) {
1387
1388 /* Initialize the BD for every fragment in the page. */
1389 bdp->cbd_sc = 0;
1390 bdp->cbd_bufaddr = 0;
1391 bdp++;
1392 }
1393
1394 /* Set the last buffer to wrap */
1395 bdp--;
1396 bdp->cbd_sc |= BD_SC_WRAP;
1397
1398 fec_restart(ndev, 0);
1399
1400 return 0;
1401}
1402
1403#ifdef CONFIG_OF
1404static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev)
1405{
1406 struct device_node *np = pdev->dev.of_node;
1407
1408 if (np)
1409 return of_get_phy_mode(np);
1410
1411 return -ENODEV;
1412}
1413
1414static int __devinit fec_reset_phy(struct platform_device *pdev)
1415{
1416 int err, phy_reset;
1417 struct device_node *np = pdev->dev.of_node;
1418
1419 if (!np)
1420 return -ENODEV;
1421
1422 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1423 err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset");
1424 if (err) {
1425 pr_warn("FEC: failed to get gpio phy-reset: %d\n", err);
1426 return err;
1427 }
1428 msleep(1);
1429 gpio_set_value(phy_reset, 1);
1430
1431 return 0;
1432}
1433#else /* CONFIG_OF */
1434static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
1435{
1436 return -ENODEV;
1437}
1438
1439static inline int fec_reset_phy(struct platform_device *pdev)
1440{
1441 /*
1442 * In case of platform probe, the reset has been done
1443 * by machine code.
1444 */
1445 return 0;
1446}
1447#endif /* CONFIG_OF */
1448
1449static int __devinit
1450fec_probe(struct platform_device *pdev)
1451{
1452 struct fec_enet_private *fep;
1453 struct fec_platform_data *pdata;
1454 struct net_device *ndev;
1455 int i, irq, ret = 0;
1456 struct resource *r;
1457 const struct of_device_id *of_id;
1458
1459 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1460 if (of_id)
1461 pdev->id_entry = of_id->data;
1462
1463 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1464 if (!r)
1465 return -ENXIO;
1466
1467 r = request_mem_region(r->start, resource_size(r), pdev->name);
1468 if (!r)
1469 return -EBUSY;
1470
1471 /* Init network device */
1472 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1473 if (!ndev) {
1474 ret = -ENOMEM;
1475 goto failed_alloc_etherdev;
1476 }
1477
1478 SET_NETDEV_DEV(ndev, &pdev->dev);
1479
1480 /* setup board info structure */
1481 fep = netdev_priv(ndev);
1482
1483 fep->hwp = ioremap(r->start, resource_size(r));
1484 fep->pdev = pdev;
1485
1486 if (!fep->hwp) {
1487 ret = -ENOMEM;
1488 goto failed_ioremap;
1489 }
1490
1491 platform_set_drvdata(pdev, ndev);
1492
1493 ret = fec_get_phy_mode_dt(pdev);
1494 if (ret < 0) {
1495 pdata = pdev->dev.platform_data;
1496 if (pdata)
1497 fep->phy_interface = pdata->phy;
1498 else
1499 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1500 } else {
1501 fep->phy_interface = ret;
1502 }
1503
1504 fec_reset_phy(pdev);
1505
1506 /* This device has up to three irqs on some platforms */
1507 for (i = 0; i < 3; i++) {
1508 irq = platform_get_irq(pdev, i);
1509 if (i && irq < 0)
1510 break;
1511 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1512 if (ret) {
1513 while (--i >= 0) {
1514 irq = platform_get_irq(pdev, i);
1515 free_irq(irq, ndev);
1516 }
1517 goto failed_irq;
1518 }
1519 }
1520
1521 fep->clk = clk_get(&pdev->dev, "fec_clk");
1522 if (IS_ERR(fep->clk)) {
1523 ret = PTR_ERR(fep->clk);
1524 goto failed_clk;
1525 }
1526 clk_enable(fep->clk);
1527
1528 ret = fec_enet_init(ndev);
1529 if (ret)
1530 goto failed_init;
1531
1532 ret = fec_enet_mii_init(pdev);
1533 if (ret)
1534 goto failed_mii_init;
1535
1536 /* Carrier starts down, phylib will bring it up */
1537 netif_carrier_off(ndev);
1538
1539 ret = register_netdev(ndev);
1540 if (ret)
1541 goto failed_register;
1542
1543 return 0;
1544
1545failed_register:
1546 fec_enet_mii_remove(fep);
1547failed_mii_init:
1548failed_init:
1549 clk_disable(fep->clk);
1550 clk_put(fep->clk);
1551failed_clk:
1552 for (i = 0; i < 3; i++) {
1553 irq = platform_get_irq(pdev, i);
1554 if (irq > 0)
1555 free_irq(irq, ndev);
1556 }
1557failed_irq:
1558 iounmap(fep->hwp);
1559failed_ioremap:
1560 free_netdev(ndev);
1561failed_alloc_etherdev:
1562 release_mem_region(r->start, resource_size(r));
1563
1564 return ret;
1565}
1566
1567static int __devexit
1568fec_drv_remove(struct platform_device *pdev)
1569{
1570 struct net_device *ndev = platform_get_drvdata(pdev);
1571 struct fec_enet_private *fep = netdev_priv(ndev);
1572 struct resource *r;
1573
1574 fec_stop(ndev);
1575 fec_enet_mii_remove(fep);
1576 clk_disable(fep->clk);
1577 clk_put(fep->clk);
1578 iounmap(fep->hwp);
1579 unregister_netdev(ndev);
1580 free_netdev(ndev);
1581
1582 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1583 BUG_ON(!r);
1584 release_mem_region(r->start, resource_size(r));
1585
1586 platform_set_drvdata(pdev, NULL);
1587
1588 return 0;
1589}
1590
1591#ifdef CONFIG_PM
1592static int
1593fec_suspend(struct device *dev)
1594{
1595 struct net_device *ndev = dev_get_drvdata(dev);
1596 struct fec_enet_private *fep = netdev_priv(ndev);
1597
1598 if (netif_running(ndev)) {
1599 fec_stop(ndev);
1600 netif_device_detach(ndev);
1601 }
1602 clk_disable(fep->clk);
1603
1604 return 0;
1605}
1606
1607static int
1608fec_resume(struct device *dev)
1609{
1610 struct net_device *ndev = dev_get_drvdata(dev);
1611 struct fec_enet_private *fep = netdev_priv(ndev);
1612
1613 clk_enable(fep->clk);
1614 if (netif_running(ndev)) {
1615 fec_restart(ndev, fep->full_duplex);
1616 netif_device_attach(ndev);
1617 }
1618
1619 return 0;
1620}
1621
1622static const struct dev_pm_ops fec_pm_ops = {
1623 .suspend = fec_suspend,
1624 .resume = fec_resume,
1625 .freeze = fec_suspend,
1626 .thaw = fec_resume,
1627 .poweroff = fec_suspend,
1628 .restore = fec_resume,
1629};
1630#endif
1631
1632static struct platform_driver fec_driver = {
1633 .driver = {
1634 .name = DRIVER_NAME,
1635 .owner = THIS_MODULE,
1636#ifdef CONFIG_PM
1637 .pm = &fec_pm_ops,
1638#endif
1639 .of_match_table = fec_dt_ids,
1640 },
1641 .id_table = fec_devtype,
1642 .probe = fec_probe,
1643 .remove = __devexit_p(fec_drv_remove),
1644};
1645
1646static int __init
1647fec_enet_module_init(void)
1648{
1649 printk(KERN_INFO "FEC Ethernet Driver\n");
1650
1651 return platform_driver_register(&fec_driver);
1652}
1653
1654static void __exit
1655fec_enet_cleanup(void)
1656{
1657 platform_driver_unregister(&fec_driver);
1658}
1659
1660module_exit(fec_enet_cleanup);
1661module_init(fec_enet_module_init);
1662
1663MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-13 07:59:14 -0400