1 files changed, 74 insertions, 18 deletions

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 728d42ab2a76..c777b9013164 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -94,10 +94,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
 
 #define DRV_MODULE_NAME         "tg3"
 #define TG3_MAJ_NUM                     3
-#define TG3_MIN_NUM                     131
+#define TG3_MIN_NUM                     132
 #define DRV_MODULE_VERSION      \
         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
-#define DRV_MODULE_RELDATE      "April 09, 2013"
+#define DRV_MODULE_RELDATE      "May 21, 2013"
 
 #define RESET_KIND_SHUTDOWN     0
 #define RESET_KIND_INIT         1
@@ -1800,6 +1800,9 @@ static int tg3_poll_fw(struct tg3 *tp)
         int i;
         u32 val;
 
+        if (tg3_flag(tp, NO_FWARE_REPORTED))
+                return 0;
+
         if (tg3_flag(tp, IS_SSB_CORE)) {
                 /* We don't use firmware. */
                 return 0;
@@ -2957,6 +2960,31 @@ static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
         return 0;
 }
 
+static bool tg3_phy_power_bug(struct tg3 *tp)
+{
+        switch (tg3_asic_rev(tp)) {
+        case ASIC_REV_5700:
+        case ASIC_REV_5704:
+                return true;
+        case ASIC_REV_5780:
+                if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
+                        return true;
+                return false;
+        case ASIC_REV_5717:
+                if (!tp->pci_fn)
+                        return true;
+                return false;
+        case ASIC_REV_5719:
+        case ASIC_REV_5720:
+                if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
+                    !tp->pci_fn)
+                        return true;
+                return false;
+        }
+
+        return false;
+}
+
 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
 {
         u32 val;
@@ -3016,12 +3044,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
         /* The PHY should not be powered down on some chips because
          * of bugs.
          */
-        if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
-            tg3_asic_rev(tp) == ASIC_REV_5704 ||
-            (tg3_asic_rev(tp) == ASIC_REV_5780 &&
-             (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
-            (tg3_asic_rev(tp) == ASIC_REV_5717 &&
-             !tp->pci_fn))
+        if (tg3_phy_power_bug(tp))
                 return;
 
         if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
@@ -7428,6 +7451,20 @@ static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
         return (base > 0xffffdcc0) && (base + len + 8 < base);
 }
 
+/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
+ * of any 4GB boundaries: 4G, 8G, etc
+ */
+static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
+                                           u32 len, u32 mss)
+{
+        if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
+                u32 base = (u32) mapping & 0xffffffff;
+
+                return ((base + len + (mss & 0x3fff)) < base);
+        }
+        return 0;
+}
+
 /* Test for DMA addresses > 40-bit */
 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
                                           int len)
@@ -7464,6 +7501,9 @@ static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
         if (tg3_4g_overflow_test(map, len))
                 hwbug = true;
 
+        if (tg3_4g_tso_overflow_test(tp, map, len, mss))
+                hwbug = true;
+
         if (tg3_40bit_overflow_test(tp, map, len))
                 hwbug = true;
 
@@ -8874,6 +8914,10 @@ static int tg3_chip_reset(struct tg3 *tp)
                 tg3_halt_cpu(tp, RX_CPU_BASE);
         }
 
+        err = tg3_poll_fw(tp);
+        if (err)
+                return err;
+
         tw32(GRC_MODE, tp->grc_mode);
 
         if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
@@ -8904,10 +8948,6 @@ static int tg3_chip_reset(struct tg3 *tp)
 
         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
 
-        err = tg3_poll_fw(tp);
-        if (err)
-                return err;
-
         tg3_mdio_start(tp);
 
         if (tg3_flag(tp, PCI_EXPRESS) &&
@@ -9431,6 +9471,14 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp)
         }
 }
 
+static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
+{
+        if (tg3_asic_rev(tp) == ASIC_REV_5719)
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
+        else
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
+}
+
 /* tp->lock is held. */
 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
 {
@@ -10116,16 +10164,17 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
         tw32_f(RDMAC_MODE, rdmac_mode);
         udelay(40);
 
-        if (tg3_asic_rev(tp) == ASIC_REV_5719) {
+        if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
+            tg3_asic_rev(tp) == ASIC_REV_5720) {
                 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
                         if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
                                 break;
                 }
                 if (i < TG3_NUM_RDMA_CHANNELS) {
                         val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                        val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                        val |= tg3_lso_rd_dma_workaround_bit(tp);
                         tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                        tg3_flag_set(tp, 5719_RDMA_BUG);
+                        tg3_flag_set(tp, 5719_5720_RDMA_BUG);
                 }
         }
 
@@ -10358,6 +10407,13 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
  */
 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
 {
+        /* Chip may have been just powered on. If so, the boot code may still
+         * be running initialization. Wait for it to finish to avoid races in
+         * accessing the hardware.
+         */
+        tg3_enable_register_access(tp);
+        tg3_poll_fw(tp);
+
         tg3_switch_clocks(tp);
 
         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
@@ -10489,15 +10545,15 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
-        if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
+        if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
                      (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
                       sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
                 u32 val;
 
                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                val &= ~tg3_lso_rd_dma_workaround_bit(tp);
                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                tg3_flag_clear(tp, 5719_RDMA_BUG);
+                tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
         }
 
         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);