7 files changed, 477 insertions, 159 deletions

diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h
index c0f185beb8bc..1190167a8b3d 100644
--- a/drivers/net/e1000e/defines.h
+++ b/drivers/net/e1000e/defines.h
@@ -76,6 +76,7 @@
 /* Extended Device Control */
 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
 #define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
 #define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
@@ -347,6 +348,7 @@
 /* Extended Configuration Control and Size */
 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
+#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
 #define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index 405a144ebcad..3e187b0e4203 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -141,6 +141,22 @@ struct e1000_info;
 #define HV_TNCRS_UPPER          PHY_REG(778, 29) /* Transmit with no CRS */
 #define HV_TNCRS_LOWER          PHY_REG(778, 30)
 
+#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
+
+/* BM PHY Copper Specific Status */
+#define BM_CS_STATUS                      17
+#define BM_CS_STATUS_LINK_UP              0x0400
+#define BM_CS_STATUS_RESOLVED             0x0800
+#define BM_CS_STATUS_SPEED_MASK           0xC000
+#define BM_CS_STATUS_SPEED_1000           0x8000
+
+/* 82577 Mobile Phy Status Register */
+#define HV_M_STATUS                       26
+#define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
+#define HV_M_STATUS_SPEED_MASK            0x0300
+#define HV_M_STATUS_SPEED_1000            0x0200
+#define HV_M_STATUS_LINK_UP               0x0040
+
 enum e1000_boards {
         board_82571,
         board_82572,
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c
index 1bf4d2a5d34f..e82638ecae88 100644
--- a/drivers/net/e1000e/ethtool.c
+++ b/drivers/net/e1000e/ethtool.c
@@ -327,10 +327,18 @@ static int e1000_set_pauseparam(struct net_device *netdev,
 
                 hw->fc.current_mode = hw->fc.requested_mode;
 
-                retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
-                          hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw));
+                if (hw->phy.media_type == e1000_media_type_fiber) {
+                        retval = hw->mac.ops.setup_link(hw);
+                        /* implicit goto out */
+                } else {
+                        retval = e1000e_force_mac_fc(hw);
+                        if (retval)
+                                goto out;
+                        e1000e_set_fc_watermarks(hw);
+                }
         }
 
+out:
         clear_bit(__E1000_RESETTING, &adapter->state);
         return retval;
 }
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index 7b05cf47f7f5..aaea41ef794d 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -903,6 +903,7 @@ struct e1000_shadow_ram {
 struct e1000_dev_spec_ich8lan {
         bool kmrn_lock_loss_workaround_enabled;
         struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
+        bool nvm_k1_enabled;
 };
 
 struct e1000_hw {
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index b6388b9535fd..eff3f4783655 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -124,11 +124,25 @@
 
 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 
+/* SMBus Address Phy Register */
+#define HV_SMB_ADDR            PHY_REG(768, 26)
+#define HV_SMB_ADDR_PEC_EN     0x0200
+#define HV_SMB_ADDR_VALID      0x0080
+
+/* Strapping Option Register - RO */
+#define E1000_STRAP                     0x0000C
+#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
+#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
+
 /* OEM Bits Phy Register */
 #define HV_OEM_BITS            PHY_REG(768, 25)
 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
+#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 
+#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
+#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
+
 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 /* Offset 04h HSFSTS */
 union ich8_hws_flash_status {
@@ -208,6 +222,9 @@ static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
+static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
+static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
+static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
 
 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 {
@@ -483,14 +500,6 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                 goto out;
         }
 
-        if (hw->mac.type == e1000_pchlan) {
-                ret_val = e1000e_write_kmrn_reg(hw,
-                                                   E1000_KMRNCTRLSTA_K1_CONFIG,
-                                                   E1000_KMRNCTRLSTA_K1_ENABLE);
-                if (ret_val)
-                        goto out;
-        }
-
         /*
          * First we want to see if the MII Status Register reports
          * link.  If so, then we want to get the current speed/duplex
@@ -500,6 +509,12 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
         if (ret_val)
                 goto out;
 
+        if (hw->mac.type == e1000_pchlan) {
+                ret_val = e1000_k1_gig_workaround_hv(hw, link);
+                if (ret_val)
+                        goto out;
+        }
+
         if (!link)
                 goto out; /* No link detected */
 
@@ -794,6 +809,327 @@ static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
+ *  @hw:   pointer to the HW structure
+ *
+ *  SW should configure the LCD from the NVM extended configuration region
+ *  as a workaround for certain parts.
+ **/
+static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
+{
+        struct e1000_phy_info *phy = &hw->phy;
+        u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
+        s32 ret_val;
+        u16 word_addr, reg_data, reg_addr, phy_page = 0;
+
+        ret_val = hw->phy.ops.acquire_phy(hw);
+        if (ret_val)
+                return ret_val;
+
+        /*
+         * Initialize the PHY from the NVM on ICH platforms.  This
+         * is needed due to an issue where the NVM configuration is
+         * not properly autoloaded after power transitions.
+         * Therefore, after each PHY reset, we will load the
+         * configuration data out of the NVM manually.
+         */
+        if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
+                (hw->mac.type == e1000_pchlan)) {
+                struct e1000_adapter *adapter = hw->adapter;
+
+                /* Check if SW needs to configure the PHY */
+                if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
+                    (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
+                    (hw->mac.type == e1000_pchlan))
+                        sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
+                else
+                        sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
+
+                data = er32(FEXTNVM);
+                if (!(data & sw_cfg_mask))
+                        goto out;
+
+                /* Wait for basic configuration completes before proceeding */
+                e1000_lan_init_done_ich8lan(hw);
+
+                /*
+                 * Make sure HW does not configure LCD from PHY
+                 * extended configuration before SW configuration
+                 */
+                data = er32(EXTCNF_CTRL);
+                if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
+                        goto out;
+
+                cnf_size = er32(EXTCNF_SIZE);
+                cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
+                cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
+                if (!cnf_size)
+                        goto out;
+
+                cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
+                cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
+
+                if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
+                    (hw->mac.type == e1000_pchlan)) {
+                        /*
+                         * HW configures the SMBus address and LEDs when the
+                         * OEM and LCD Write Enable bits are set in the NVM.
+                         * When both NVM bits are cleared, SW will configure
+                         * them instead.
+                         */
+                        data = er32(STRAP);
+                        data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
+                        reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
+                        reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
+                        ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
+                                                                reg_data);
+                        if (ret_val)
+                                goto out;
+
+                        data = er32(LEDCTL);
+                        ret_val = e1000_write_phy_reg_hv_locked(hw,
+                                                                HV_LED_CONFIG,
+                                                                (u16)data);
+                        if (ret_val)
+                                goto out;
+                }
+                /* Configure LCD from extended configuration region. */
+
+                /* cnf_base_addr is in DWORD */
+                word_addr = (u16)(cnf_base_addr << 1);
+
+                for (i = 0; i < cnf_size; i++) {
+                        ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
+                                                   &reg_data);
+                        if (ret_val)
+                                goto out;
+
+                        ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
+                                                   1, &reg_addr);
+                        if (ret_val)
+                                goto out;
+
+                        /* Save off the PHY page for future writes. */
+                        if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
+                                phy_page = reg_data;
+                                continue;
+                        }
+
+                        reg_addr &= PHY_REG_MASK;
+                        reg_addr |= phy_page;
+
+                        ret_val = phy->ops.write_phy_reg_locked(hw,
+                                                            (u32)reg_addr,
+                                                            reg_data);
+                        if (ret_val)
+                                goto out;
+                }
+        }
+
+out:
+        hw->phy.ops.release_phy(hw);
+        return ret_val;
+}
+
+/**
+ *  e1000_k1_gig_workaround_hv - K1 Si workaround
+ *  @hw:   pointer to the HW structure
+ *  @link: link up bool flag
+ *
+ *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
+ *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
+ *  If link is down, the function will restore the default K1 setting located
+ *  in the NVM.
+ **/
+static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
+{
+        s32 ret_val = 0;
+        u16 status_reg = 0;
+        bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
+
+        if (hw->mac.type != e1000_pchlan)
+                goto out;
+
+        /* Wrap the whole flow with the sw flag */
+        ret_val = hw->phy.ops.acquire_phy(hw);
+        if (ret_val)
+                goto out;
+
+        /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
+        if (link) {
+                if (hw->phy.type == e1000_phy_82578) {
+                        ret_val = hw->phy.ops.read_phy_reg_locked(hw,
+                                                                  BM_CS_STATUS,
+                                                                  &status_reg);
+                        if (ret_val)
+                                goto release;
+
+                        status_reg &= BM_CS_STATUS_LINK_UP |
+                                      BM_CS_STATUS_RESOLVED |
+                                      BM_CS_STATUS_SPEED_MASK;
+
+                        if (status_reg == (BM_CS_STATUS_LINK_UP |
+                                           BM_CS_STATUS_RESOLVED |
+                                           BM_CS_STATUS_SPEED_1000))
+                                k1_enable = false;
+                }
+
+                if (hw->phy.type == e1000_phy_82577) {
+                        ret_val = hw->phy.ops.read_phy_reg_locked(hw,
+                                                                  HV_M_STATUS,
+                                                                  &status_reg);
+                        if (ret_val)
+                                goto release;
+
+                        status_reg &= HV_M_STATUS_LINK_UP |
+                                      HV_M_STATUS_AUTONEG_COMPLETE |
+                                      HV_M_STATUS_SPEED_MASK;
+
+                        if (status_reg == (HV_M_STATUS_LINK_UP |
+                                           HV_M_STATUS_AUTONEG_COMPLETE |
+                                           HV_M_STATUS_SPEED_1000))
+                                k1_enable = false;
+                }
+
+                /* Link stall fix for link up */
+                ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
+                                                           0x0100);
+                if (ret_val)
+                        goto release;
+
+        } else {
+                /* Link stall fix for link down */
+                ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
+                                                           0x4100);
+                if (ret_val)
+                        goto release;
+        }
+
+        ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
+
+release:
+        hw->phy.ops.release_phy(hw);
+out:
+        return ret_val;
+}
+
+/**
+ *  e1000_configure_k1_ich8lan - Configure K1 power state
+ *  @hw: pointer to the HW structure
+ *  @enable: K1 state to configure
+ *
+ *  Configure the K1 power state based on the provided parameter.
+ *  Assumes semaphore already acquired.
+ *
+ *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
+ **/
+static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
+{
+        s32 ret_val = 0;
+        u32 ctrl_reg = 0;
+        u32 ctrl_ext = 0;
+        u32 reg = 0;
+        u16 kmrn_reg = 0;
+
+        ret_val = e1000e_read_kmrn_reg_locked(hw,
+                                             E1000_KMRNCTRLSTA_K1_CONFIG,
+                                             &kmrn_reg);
+        if (ret_val)
+                goto out;
+
+        if (k1_enable)
+                kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
+        else
+                kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
+
+        ret_val = e1000e_write_kmrn_reg_locked(hw,
+                                              E1000_KMRNCTRLSTA_K1_CONFIG,
+                                              kmrn_reg);
+        if (ret_val)
+                goto out;
+
+        udelay(20);
+        ctrl_ext = er32(CTRL_EXT);
+        ctrl_reg = er32(CTRL);
+
+        reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+        reg |= E1000_CTRL_FRCSPD;
+        ew32(CTRL, reg);
+
+        ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
+        udelay(20);
+        ew32(CTRL, ctrl_reg);
+        ew32(CTRL_EXT, ctrl_ext);
+        udelay(20);
+
+out:
+        return ret_val;
+}
+
+/**
+ *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
+ *  @hw:       pointer to the HW structure
+ *  @d0_state: boolean if entering d0 or d3 device state
+ *
+ *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
+ *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
+ *  in NVM determines whether HW should configure LPLU and Gbe Disable.
+ **/
+static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
+{
+        s32 ret_val = 0;
+        u32 mac_reg;
+        u16 oem_reg;
+
+        if (hw->mac.type != e1000_pchlan)
+                return ret_val;
+
+        ret_val = hw->phy.ops.acquire_phy(hw);
+        if (ret_val)
+                return ret_val;
+
+        mac_reg = er32(EXTCNF_CTRL);
+        if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
+                goto out;
+
+        mac_reg = er32(FEXTNVM);
+        if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
+                goto out;
+
+        mac_reg = er32(PHY_CTRL);
+
+        ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
+        if (ret_val)
+                goto out;
+
+        oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
+
+        if (d0_state) {
+                if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
+                        oem_reg |= HV_OEM_BITS_GBE_DIS;
+
+                if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
+                        oem_reg |= HV_OEM_BITS_LPLU;
+        } else {
+                if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
+                        oem_reg |= HV_OEM_BITS_GBE_DIS;
+
+                if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
+                        oem_reg |= HV_OEM_BITS_LPLU;
+        }
+        /* Restart auto-neg to activate the bits */
+        if (!e1000_check_reset_block(hw))
+                oem_reg |= HV_OEM_BITS_RESTART_AN;
+        ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
+
+out:
+        hw->phy.ops.release_phy(hw);
+
+        return ret_val;
+}
+
+
+/**
  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
  *  done after every PHY reset.
  **/
@@ -833,10 +1169,20 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
         ret_val = hw->phy.ops.acquire_phy(hw);
         if (ret_val)
                 return ret_val;
+
         hw->phy.addr = 1;
-        e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
+        ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
+        if (ret_val)
+                goto out;
         hw->phy.ops.release_phy(hw);
 
+        /*
+         * Configure the K1 Si workaround during phy reset assuming there is
+         * link so that it disables K1 if link is in 1Gbps.
+         */
+        ret_val = e1000_k1_gig_workaround_hv(hw, true);
+
+out:
         return ret_val;
 }
 
@@ -882,11 +1228,8 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
  **/
 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 {
-        struct e1000_phy_info *phy = &hw->phy;
-        u32 i;
-        u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
-        s32 ret_val;
-        u16 reg, word_addr, reg_data, reg_addr, phy_page = 0;
+        s32 ret_val = 0;
+        u16 reg;
 
         ret_val = e1000e_phy_hw_reset_generic(hw);
         if (ret_val)
@@ -905,81 +1248,16 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
         if (hw->mac.type == e1000_pchlan)
                 e1e_rphy(hw, BM_WUC, &reg);
 
-        /*
-         * Initialize the PHY from the NVM on ICH platforms.  This
-         * is needed due to an issue where the NVM configuration is
-         * not properly autoloaded after power transitions.
-         * Therefore, after each PHY reset, we will load the
-         * configuration data out of the NVM manually.
-         */
-        if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
-                struct e1000_adapter *adapter = hw->adapter;
-
-                /* Check if SW needs configure the PHY */
-                if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
-                    (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
-                        sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
-                else
-                        sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
-
-                data = er32(FEXTNVM);
-                if (!(data & sw_cfg_mask))
-                        return 0;
-
-                /* Wait for basic configuration completes before proceeding */
-                e1000_lan_init_done_ich8lan(hw);
-
-                /*
-                 * Make sure HW does not configure LCD from PHY
-                 * extended configuration before SW configuration
-                 */
-                data = er32(EXTCNF_CTRL);
-                if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
-                        return 0;
-
-                cnf_size = er32(EXTCNF_SIZE);
-                cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
-                cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
-                if (!cnf_size)
-                        return 0;
-
-                cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
-                cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
-
-                /* Configure LCD from extended configuration region. */
-
-                /* cnf_base_addr is in DWORD */
-                word_addr = (u16)(cnf_base_addr << 1);
-
-                for (i = 0; i < cnf_size; i++) {
-                        ret_val = e1000_read_nvm(hw,
-                                                (word_addr + i * 2),
-                                                1,
-                                                &reg_data);
-                        if (ret_val)
-                                return ret_val;
-
-                        ret_val = e1000_read_nvm(hw,
-                                                (word_addr + i * 2 + 1),
-                                                1,
-                                                &reg_addr);
-                        if (ret_val)
-                                return ret_val;
-
-                        /* Save off the PHY page for future writes. */
-                        if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
-                                phy_page = reg_data;
-                                continue;
-                        }
-
-                        reg_addr |= phy_page;
+        /* Configure the LCD with the extended configuration region in NVM */
+        ret_val = e1000_sw_lcd_config_ich8lan(hw);
+        if (ret_val)
+                goto out;
 
-                        ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
-                        if (ret_val)
-                                return ret_val;
-                }
-        }
+        /* Configure the LCD with the OEM bits in NVM */
+        if (hw->mac.type == e1000_pchlan)
+                ret_val = e1000_oem_bits_config_ich8lan(hw, true);
 
+out:
         return 0;
 }
 
@@ -2306,6 +2584,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
  **/
 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
 {
+        struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
         u16 reg;
         u32 ctrl, icr, kab;
         s32 ret_val;
@@ -2341,6 +2620,18 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                 ew32(PBS, E1000_PBS_16K);
         }
 
+        if (hw->mac.type == e1000_pchlan) {
+                /* Save the NVM K1 bit setting*/
+                ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
+                if (ret_val)
+                        return ret_val;
+
+                if (reg & E1000_NVM_K1_ENABLE)
+                        dev_spec->nvm_k1_enabled = true;
+                else
+                        dev_spec->nvm_k1_enabled = false;
+        }
+
         ctrl = er32(CTRL);
 
         if (!e1000_check_reset_block(hw)) {
@@ -2386,6 +2677,15 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
         if (hw->mac.type == e1000_pchlan)
                 e1e_rphy(hw, BM_WUC, &reg);
 
+        ret_val = e1000_sw_lcd_config_ich8lan(hw);
+        if (ret_val)
+                goto out;
+
+        if (hw->mac.type == e1000_pchlan) {
+                ret_val = e1000_oem_bits_config_ich8lan(hw, true);
+                if (ret_val)
+                        goto out;
+        }
         /*
          * For PCH, this write will make sure that any noise
          * will be detected as a CRC error and be dropped rather than show up
@@ -2404,6 +2704,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
         if (hw->mac.type == e1000_pchlan)
                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
 
+out:
         return ret_val;
 }
 
@@ -2708,14 +3009,6 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
         if (ret_val)
                 return ret_val;
 
-        if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
-                ret_val = e1000e_write_kmrn_reg(hw,
-                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
-                                                  E1000_KMRNCTRLSTA_K1_DISABLE);
-                if (ret_val)
-                        return ret_val;
-        }
-
         if ((hw->mac.type == e1000_ich8lan) &&
             (hw->phy.type == e1000_phy_igp_3) &&
             (*speed == SPEED_1000)) {
@@ -3266,6 +3559,7 @@ struct e1000_info e1000_pch_info = {
                                   | FLAG_HAS_AMT
                                   | FLAG_HAS_FLASH
                                   | FLAG_HAS_JUMBO_FRAMES
+                                  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
                                   | FLAG_APME_IN_WUC,
         .pba                    = 26,
         .max_hw_frame_size      = 4096,
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 0687c6aa4e46..fad8f9ea0043 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -2769,25 +2769,38 @@ void e1000e_reset(struct e1000_adapter *adapter)
         /*
          * flow control settings
          *
-         * The high water mark must be low enough to fit two full frame
+         * The high water mark must be low enough to fit one full frame
          * (or the size used for early receive) above it in the Rx FIFO.
          * Set it to the lower of:
          * - 90% of the Rx FIFO size, and
          * - the full Rx FIFO size minus the early receive size (for parts
          *   with ERT support assuming ERT set to E1000_ERT_2048), or
-         * - the full Rx FIFO size minus two full frames
+         * - the full Rx FIFO size minus one full frame
          */
-        if ((adapter->flags & FLAG_HAS_ERT) &&
-            (adapter->netdev->mtu > ETH_DATA_LEN))
-                hwm = min(((pba << 10) * 9 / 10),
-                          ((pba << 10) - (E1000_ERT_2048 << 3)));
-        else
-                hwm = min(((pba << 10) * 9 / 10),
-                          ((pba << 10) - (2 * adapter->max_frame_size)));
+        if (hw->mac.type == e1000_pchlan) {
+                /*
+                 * Workaround PCH LOM adapter hangs with certain network
+                 * loads.  If hangs persist, try disabling Tx flow control.
+                 */
+                if (adapter->netdev->mtu > ETH_DATA_LEN) {
+                        fc->high_water = 0x3500;
+                        fc->low_water  = 0x1500;
+                } else {
+                        fc->high_water = 0x5000;
+                        fc->low_water  = 0x3000;
+                }
+        } else {
+                if ((adapter->flags & FLAG_HAS_ERT) &&
+                    (adapter->netdev->mtu > ETH_DATA_LEN))
+                        hwm = min(((pba << 10) * 9 / 10),
+                                  ((pba << 10) - (E1000_ERT_2048 << 3)));
+                else
+                        hwm = min(((pba << 10) * 9 / 10),
+                                  ((pba << 10) - adapter->max_frame_size));
 
-        fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
-        fc->low_water = (fc->high_water - (2 * adapter->max_frame_size));
-        fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */
+                fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
+                fc->low_water = fc->high_water - 8;
+        }
 
         if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
                 fc->pause_time = 0xFFFF;
@@ -2813,6 +2826,10 @@ void e1000e_reset(struct e1000_adapter *adapter)
         if (mac->ops.init_hw(hw))
                 e_err("Hardware Error\n");
 
+        /* additional part of the flow-control workaround above */
+        if (hw->mac.type == e1000_pchlan)
+                ew32(FCRTV_PCH, 0x1000);
+
         e1000_update_mng_vlan(adapter);
 
         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
@@ -3610,7 +3627,7 @@ static void e1000_watchdog_task(struct work_struct *work)
                         case SPEED_100:
                                 txb2b = 0;
                                 netdev->tx_queue_len = 100;
-                                /* maybe add some timeout factor ? */
+                                adapter->tx_timeout_factor = 10;
                                 break;
                         }
 
@@ -4288,8 +4305,10 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
 
         while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
                 msleep(1);
-        /* e1000e_down has a dependency on max_frame_size */
+        /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
         adapter->max_frame_size = max_frame;
+        e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
+        netdev->mtu = new_mtu;
         if (netif_running(netdev))
                 e1000e_down(adapter);
 
@@ -4319,9 +4338,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
                 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
                                          + ETH_FCS_LEN;
 
-        e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
-        netdev->mtu = new_mtu;
-
         if (netif_running(netdev))
                 e1000e_up(adapter);
         else
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index f9d33ab05e97..85f955f70417 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -71,7 +71,6 @@ static const u16 e1000_igp_2_cable_length_table[] =
 #define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
 #define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
 #define I82577_CTRL_REG                   23
-#define I82577_CTRL_DOWNSHIFT_MASK        (7 << 10)
 
 /* 82577 specific PHY registers */
 #define I82577_PHY_CTRL_2            18
@@ -95,13 +94,6 @@ static const u16 e1000_igp_2_cable_length_table[] =
 /* BM PHY Copper Specific Control 1 */
 #define BM_CS_CTRL1                       16
 
-/* BM PHY Copper Specific Status */
-#define BM_CS_STATUS                      17
-#define BM_CS_STATUS_LINK_UP              0x0400
-#define BM_CS_STATUS_RESOLVED             0x0800
-#define BM_CS_STATUS_SPEED_MASK           0xC000
-#define BM_CS_STATUS_SPEED_1000           0x8000
-
 #define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
 #define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
 #define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
@@ -563,7 +555,7 @@ s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 }
 
 /**
- *  e1000_read_kmrn_reg_locked -  Read kumeran register
+ *  e1000e_read_kmrn_reg_locked -  Read kumeran register
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read
  *  @data: pointer to the read data
@@ -572,7 +564,7 @@ s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
  *  information retrieved is stored in data.
  *  Assumes semaphore already acquired.
  **/
-s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
+s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
 {
         return __e1000_read_kmrn_reg(hw, offset, data, true);
 }
@@ -631,7 +623,7 @@ s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
 }
 
 /**
- *  e1000_write_kmrn_reg_locked -  Write kumeran register
+ *  e1000e_write_kmrn_reg_locked -  Write kumeran register
  *  @hw: pointer to the HW structure
  *  @offset: register offset to write to
  *  @data: data to write at register offset
@@ -639,7 +631,7 @@ s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
  *  Write the data to PHY register at the offset using the kumeran interface.
  *  Assumes semaphore already acquired.
  **/
-s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
+s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
 {
         return __e1000_write_kmrn_reg(hw, offset, data, true);
 }
@@ -667,15 +659,6 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
         phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
 
         ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data);
-        if (ret_val)
-                goto out;
-
-        /* Set number of link attempts before downshift */
-        ret_val = phy->ops.read_phy_reg(hw, I82577_CTRL_REG, &phy_data);
-        if (ret_val)
-                goto out;
-        phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
-        ret_val = phy->ops.write_phy_reg(hw, I82577_CTRL_REG, phy_data);
 
 out:
         return ret_val;
@@ -2665,19 +2648,18 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
                 page = 0;
 
         if (reg > MAX_PHY_MULTI_PAGE_REG) {
-                if ((hw->phy.type != e1000_phy_82578) ||
-                    ((reg != I82578_ADDR_REG) &&
-                     (reg != I82578_ADDR_REG + 1))) {
-                        u32 phy_addr = hw->phy.addr;
+                u32 phy_addr = hw->phy.addr;
 
-                        hw->phy.addr = 1;
+                hw->phy.addr = 1;
 
-                        /* Page is shifted left, PHY expects (page x 32) */
-                        ret_val = e1000e_write_phy_reg_mdic(hw,
-                                                     IGP01E1000_PHY_PAGE_SELECT,
-                                                     (page << IGP_PAGE_SHIFT));
-                        hw->phy.addr = phy_addr;
-                }
+                /* Page is shifted left, PHY expects (page x 32) */
+                ret_val = e1000e_write_phy_reg_mdic(hw,
+                                             IGP01E1000_PHY_PAGE_SELECT,
+                                             (page << IGP_PAGE_SHIFT));
+                hw->phy.addr = phy_addr;
+
+                if (ret_val)
+                        goto out;
         }
 
         ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2685,7 +2667,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
 out:
         /* Revert to MDIO fast mode, if applicable */
         if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
-                ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
+                ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
 
         if (!locked)
                 hw->phy.ops.release_phy(hw);
@@ -2791,19 +2773,18 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
         }
 
         if (reg > MAX_PHY_MULTI_PAGE_REG) {
-                if ((hw->phy.type != e1000_phy_82578) ||
-                    ((reg != I82578_ADDR_REG) &&
-                     (reg != I82578_ADDR_REG + 1))) {
-                        u32 phy_addr = hw->phy.addr;
+                u32 phy_addr = hw->phy.addr;
 
-                        hw->phy.addr = 1;
+                hw->phy.addr = 1;
 
-                        /* Page is shifted left, PHY expects (page x 32) */
-                        ret_val = e1000e_write_phy_reg_mdic(hw,
-                                                     IGP01E1000_PHY_PAGE_SELECT,
-                                                     (page << IGP_PAGE_SHIFT));
-                        hw->phy.addr = phy_addr;
-                }
+                /* Page is shifted left, PHY expects (page x 32) */
+                ret_val = e1000e_write_phy_reg_mdic(hw,
+                                             IGP01E1000_PHY_PAGE_SELECT,
+                                             (page << IGP_PAGE_SHIFT));
+                hw->phy.addr = phy_addr;
+
+                if (ret_val)
+                        goto out;
         }
 
         ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2812,7 +2793,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
 out:
         /* Revert to MDIO fast mode, if applicable */
         if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
-                ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
+                ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
 
         if (!locked)
                 hw->phy.ops.release_phy(hw);