diff options
Diffstat (limited to 'drivers/net/e1000e')
-rw-r--r-- | drivers/net/e1000e/e1000.h | 12 | ||||
-rw-r--r-- | drivers/net/e1000e/hw.h | 2 | ||||
-rw-r--r-- | drivers/net/e1000e/ich8lan.c | 150 | ||||
-rw-r--r-- | drivers/net/e1000e/phy.c | 469 |
4 files changed, 457 insertions, 176 deletions
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index 1211df9ae883..08a4f9dd20e9 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h | |||
@@ -518,9 +518,13 @@ extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); | |||
518 | extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); | 518 | extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); |
519 | extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); | 519 | extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); |
520 | extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); | 520 | extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); |
521 | extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, | ||
522 | u16 *data); | ||
521 | extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); | 523 | extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); |
522 | extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); | 524 | extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
523 | extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); | 525 | extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); |
526 | extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, | ||
527 | u16 data); | ||
524 | extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw); | 528 | extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw); |
525 | extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); | 529 | extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); |
526 | extern s32 e1000e_get_cfg_done(struct e1000_hw *hw); | 530 | extern s32 e1000e_get_cfg_done(struct e1000_hw *hw); |
@@ -537,7 +541,11 @@ extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); | |||
537 | extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); | 541 | extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); |
538 | extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); | 542 | extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); |
539 | extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); | 543 | extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); |
544 | extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, | ||
545 | u16 data); | ||
540 | extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); | 546 | extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); |
547 | extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, | ||
548 | u16 *data); | ||
541 | extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | 549 | extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
542 | u32 usec_interval, bool *success); | 550 | u32 usec_interval, bool *success); |
543 | extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); | 551 | extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); |
@@ -545,7 +553,11 @@ extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); | |||
545 | extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); | 553 | extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); |
546 | extern s32 e1000e_check_downshift(struct e1000_hw *hw); | 554 | extern s32 e1000e_check_downshift(struct e1000_hw *hw); |
547 | extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); | 555 | extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
556 | extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, | ||
557 | u16 *data); | ||
548 | extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); | 558 | extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); |
559 | extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, | ||
560 | u16 data); | ||
549 | extern s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow); | 561 | extern s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow); |
550 | extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); | 562 | extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); |
551 | extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); | 563 | extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); |
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index fd44d9f90769..7b05cf47f7f5 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h | |||
@@ -764,11 +764,13 @@ struct e1000_phy_operations { | |||
764 | s32 (*get_cable_length)(struct e1000_hw *); | 764 | s32 (*get_cable_length)(struct e1000_hw *); |
765 | s32 (*get_phy_info)(struct e1000_hw *); | 765 | s32 (*get_phy_info)(struct e1000_hw *); |
766 | s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); | 766 | s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); |
767 | s32 (*read_phy_reg_locked)(struct e1000_hw *, u32, u16 *); | ||
767 | void (*release_phy)(struct e1000_hw *); | 768 | void (*release_phy)(struct e1000_hw *); |
768 | s32 (*reset_phy)(struct e1000_hw *); | 769 | s32 (*reset_phy)(struct e1000_hw *); |
769 | s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); | 770 | s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); |
770 | s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); | 771 | s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); |
771 | s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); | 772 | s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); |
773 | s32 (*write_phy_reg_locked)(struct e1000_hw *, u32, u16); | ||
772 | s32 (*cfg_on_link_up)(struct e1000_hw *); | 774 | s32 (*cfg_on_link_up)(struct e1000_hw *); |
773 | }; | 775 | }; |
774 | 776 | ||
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 99df2abf82a9..b6388b9535fd 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -122,6 +122,13 @@ | |||
122 | 122 | ||
123 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ | 123 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
124 | 124 | ||
125 | #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ | ||
126 | |||
127 | /* OEM Bits Phy Register */ | ||
128 | #define HV_OEM_BITS PHY_REG(768, 25) | ||
129 | #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ | ||
130 | #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ | ||
131 | |||
125 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ | 132 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ |
126 | /* Offset 04h HSFSTS */ | 133 | /* Offset 04h HSFSTS */ |
127 | union ich8_hws_flash_status { | 134 | union ich8_hws_flash_status { |
@@ -200,6 +207,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); | |||
200 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); | 207 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); |
201 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); | 208 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); |
202 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); | 209 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); |
210 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); | ||
203 | 211 | ||
204 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | 212 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) |
205 | { | 213 | { |
@@ -242,7 +250,11 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |||
242 | 250 | ||
243 | phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; | 251 | phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; |
244 | phy->ops.read_phy_reg = e1000_read_phy_reg_hv; | 252 | phy->ops.read_phy_reg = e1000_read_phy_reg_hv; |
253 | phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked; | ||
254 | phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; | ||
255 | phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; | ||
245 | phy->ops.write_phy_reg = e1000_write_phy_reg_hv; | 256 | phy->ops.write_phy_reg = e1000_write_phy_reg_hv; |
257 | phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked; | ||
246 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | 258 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
247 | 259 | ||
248 | phy->id = e1000_phy_unknown; | 260 | phy->id = e1000_phy_unknown; |
@@ -303,6 +315,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) | |||
303 | case IGP03E1000_E_PHY_ID: | 315 | case IGP03E1000_E_PHY_ID: |
304 | phy->type = e1000_phy_igp_3; | 316 | phy->type = e1000_phy_igp_3; |
305 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | 317 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
318 | phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked; | ||
319 | phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked; | ||
306 | break; | 320 | break; |
307 | case IFE_E_PHY_ID: | 321 | case IFE_E_PHY_ID: |
308 | case IFE_PLUS_E_PHY_ID: | 322 | case IFE_PLUS_E_PHY_ID: |
@@ -568,12 +582,39 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) | |||
568 | static DEFINE_MUTEX(nvm_mutex); | 582 | static DEFINE_MUTEX(nvm_mutex); |
569 | 583 | ||
570 | /** | 584 | /** |
585 | * e1000_acquire_nvm_ich8lan - Acquire NVM mutex | ||
586 | * @hw: pointer to the HW structure | ||
587 | * | ||
588 | * Acquires the mutex for performing NVM operations. | ||
589 | **/ | ||
590 | static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) | ||
591 | { | ||
592 | mutex_lock(&nvm_mutex); | ||
593 | |||
594 | return 0; | ||
595 | } | ||
596 | |||
597 | /** | ||
598 | * e1000_release_nvm_ich8lan - Release NVM mutex | ||
599 | * @hw: pointer to the HW structure | ||
600 | * | ||
601 | * Releases the mutex used while performing NVM operations. | ||
602 | **/ | ||
603 | static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) | ||
604 | { | ||
605 | mutex_unlock(&nvm_mutex); | ||
606 | |||
607 | return; | ||
608 | } | ||
609 | |||
610 | static DEFINE_MUTEX(swflag_mutex); | ||
611 | |||
612 | /** | ||
571 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | 613 | * e1000_acquire_swflag_ich8lan - Acquire software control flag |
572 | * @hw: pointer to the HW structure | 614 | * @hw: pointer to the HW structure |
573 | * | 615 | * |
574 | * Acquires the software control flag for performing NVM and PHY | 616 | * Acquires the software control flag for performing PHY and select |
575 | * operations. This is a function pointer entry point only called by | 617 | * MAC CSR accesses. |
576 | * read/write routines for the PHY and NVM parts. | ||
577 | **/ | 618 | **/ |
578 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | 619 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) |
579 | { | 620 | { |
@@ -582,7 +623,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |||
582 | 623 | ||
583 | might_sleep(); | 624 | might_sleep(); |
584 | 625 | ||
585 | mutex_lock(&nvm_mutex); | 626 | mutex_lock(&swflag_mutex); |
586 | 627 | ||
587 | while (timeout) { | 628 | while (timeout) { |
588 | extcnf_ctrl = er32(EXTCNF_CTRL); | 629 | extcnf_ctrl = er32(EXTCNF_CTRL); |
@@ -599,7 +640,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |||
599 | goto out; | 640 | goto out; |
600 | } | 641 | } |
601 | 642 | ||
602 | timeout = PHY_CFG_TIMEOUT * 2; | 643 | timeout = SW_FLAG_TIMEOUT; |
603 | 644 | ||
604 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | 645 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
605 | ew32(EXTCNF_CTRL, extcnf_ctrl); | 646 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
@@ -623,7 +664,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |||
623 | 664 | ||
624 | out: | 665 | out: |
625 | if (ret_val) | 666 | if (ret_val) |
626 | mutex_unlock(&nvm_mutex); | 667 | mutex_unlock(&swflag_mutex); |
627 | 668 | ||
628 | return ret_val; | 669 | return ret_val; |
629 | } | 670 | } |
@@ -632,9 +673,8 @@ out: | |||
632 | * e1000_release_swflag_ich8lan - Release software control flag | 673 | * e1000_release_swflag_ich8lan - Release software control flag |
633 | * @hw: pointer to the HW structure | 674 | * @hw: pointer to the HW structure |
634 | * | 675 | * |
635 | * Releases the software control flag for performing NVM and PHY operations. | 676 | * Releases the software control flag for performing PHY and select |
636 | * This is a function pointer entry point only called by read/write | 677 | * MAC CSR accesses. |
637 | * routines for the PHY and NVM parts. | ||
638 | **/ | 678 | **/ |
639 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | 679 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) |
640 | { | 680 | { |
@@ -644,7 +684,9 @@ static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |||
644 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | 684 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
645 | ew32(EXTCNF_CTRL, extcnf_ctrl); | 685 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
646 | 686 | ||
647 | mutex_unlock(&nvm_mutex); | 687 | mutex_unlock(&swflag_mutex); |
688 | |||
689 | return; | ||
648 | } | 690 | } |
649 | 691 | ||
650 | /** | 692 | /** |
@@ -844,7 +886,7 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |||
844 | u32 i; | 886 | u32 i; |
845 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; | 887 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; |
846 | s32 ret_val; | 888 | s32 ret_val; |
847 | u16 word_addr, reg_data, reg_addr, phy_page = 0; | 889 | u16 reg, word_addr, reg_data, reg_addr, phy_page = 0; |
848 | 890 | ||
849 | ret_val = e1000e_phy_hw_reset_generic(hw); | 891 | ret_val = e1000e_phy_hw_reset_generic(hw); |
850 | if (ret_val) | 892 | if (ret_val) |
@@ -859,6 +901,10 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |||
859 | return ret_val; | 901 | return ret_val; |
860 | } | 902 | } |
861 | 903 | ||
904 | /* Dummy read to clear the phy wakeup bit after lcd reset */ | ||
905 | if (hw->mac.type == e1000_pchlan) | ||
906 | e1e_rphy(hw, BM_WUC, ®); | ||
907 | |||
862 | /* | 908 | /* |
863 | * Initialize the PHY from the NVM on ICH platforms. This | 909 | * Initialize the PHY from the NVM on ICH platforms. This |
864 | * is needed due to an issue where the NVM configuration is | 910 | * is needed due to an issue where the NVM configuration is |
@@ -1054,6 +1100,38 @@ static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) | |||
1054 | } | 1100 | } |
1055 | 1101 | ||
1056 | /** | 1102 | /** |
1103 | * e1000_set_lplu_state_pchlan - Set Low Power Link Up state | ||
1104 | * @hw: pointer to the HW structure | ||
1105 | * @active: true to enable LPLU, false to disable | ||
1106 | * | ||
1107 | * Sets the LPLU state according to the active flag. For PCH, if OEM write | ||
1108 | * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set | ||
1109 | * the phy speed. This function will manually set the LPLU bit and restart | ||
1110 | * auto-neg as hw would do. D3 and D0 LPLU will call the same function | ||
1111 | * since it configures the same bit. | ||
1112 | **/ | ||
1113 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) | ||
1114 | { | ||
1115 | s32 ret_val = 0; | ||
1116 | u16 oem_reg; | ||
1117 | |||
1118 | ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); | ||
1119 | if (ret_val) | ||
1120 | goto out; | ||
1121 | |||
1122 | if (active) | ||
1123 | oem_reg |= HV_OEM_BITS_LPLU; | ||
1124 | else | ||
1125 | oem_reg &= ~HV_OEM_BITS_LPLU; | ||
1126 | |||
1127 | oem_reg |= HV_OEM_BITS_RESTART_AN; | ||
1128 | ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg); | ||
1129 | |||
1130 | out: | ||
1131 | return ret_val; | ||
1132 | } | ||
1133 | |||
1134 | /** | ||
1057 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state | 1135 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state |
1058 | * @hw: pointer to the HW structure | 1136 | * @hw: pointer to the HW structure |
1059 | * @active: TRUE to enable LPLU, FALSE to disable | 1137 | * @active: TRUE to enable LPLU, FALSE to disable |
@@ -1314,12 +1392,11 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1314 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | 1392 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
1315 | (words == 0)) { | 1393 | (words == 0)) { |
1316 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | 1394 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); |
1317 | return -E1000_ERR_NVM; | 1395 | ret_val = -E1000_ERR_NVM; |
1396 | goto out; | ||
1318 | } | 1397 | } |
1319 | 1398 | ||
1320 | ret_val = e1000_acquire_swflag_ich8lan(hw); | 1399 | nvm->ops.acquire_nvm(hw); |
1321 | if (ret_val) | ||
1322 | goto out; | ||
1323 | 1400 | ||
1324 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); | 1401 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
1325 | if (ret_val) { | 1402 | if (ret_val) { |
@@ -1345,7 +1422,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1345 | } | 1422 | } |
1346 | } | 1423 | } |
1347 | 1424 | ||
1348 | e1000_release_swflag_ich8lan(hw); | 1425 | nvm->ops.release_nvm(hw); |
1349 | 1426 | ||
1350 | out: | 1427 | out: |
1351 | if (ret_val) | 1428 | if (ret_val) |
@@ -1603,11 +1680,15 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1603 | return -E1000_ERR_NVM; | 1680 | return -E1000_ERR_NVM; |
1604 | } | 1681 | } |
1605 | 1682 | ||
1683 | nvm->ops.acquire_nvm(hw); | ||
1684 | |||
1606 | for (i = 0; i < words; i++) { | 1685 | for (i = 0; i < words; i++) { |
1607 | dev_spec->shadow_ram[offset+i].modified = 1; | 1686 | dev_spec->shadow_ram[offset+i].modified = 1; |
1608 | dev_spec->shadow_ram[offset+i].value = data[i]; | 1687 | dev_spec->shadow_ram[offset+i].value = data[i]; |
1609 | } | 1688 | } |
1610 | 1689 | ||
1690 | nvm->ops.release_nvm(hw); | ||
1691 | |||
1611 | return 0; | 1692 | return 0; |
1612 | } | 1693 | } |
1613 | 1694 | ||
@@ -1637,9 +1718,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1637 | if (nvm->type != e1000_nvm_flash_sw) | 1718 | if (nvm->type != e1000_nvm_flash_sw) |
1638 | goto out; | 1719 | goto out; |
1639 | 1720 | ||
1640 | ret_val = e1000_acquire_swflag_ich8lan(hw); | 1721 | nvm->ops.acquire_nvm(hw); |
1641 | if (ret_val) | ||
1642 | goto out; | ||
1643 | 1722 | ||
1644 | /* | 1723 | /* |
1645 | * We're writing to the opposite bank so if we're on bank 1, | 1724 | * We're writing to the opposite bank so if we're on bank 1, |
@@ -1657,7 +1736,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1657 | old_bank_offset = 0; | 1736 | old_bank_offset = 0; |
1658 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); | 1737 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
1659 | if (ret_val) { | 1738 | if (ret_val) { |
1660 | e1000_release_swflag_ich8lan(hw); | 1739 | nvm->ops.release_nvm(hw); |
1661 | goto out; | 1740 | goto out; |
1662 | } | 1741 | } |
1663 | } else { | 1742 | } else { |
@@ -1665,7 +1744,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1665 | new_bank_offset = 0; | 1744 | new_bank_offset = 0; |
1666 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); | 1745 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
1667 | if (ret_val) { | 1746 | if (ret_val) { |
1668 | e1000_release_swflag_ich8lan(hw); | 1747 | nvm->ops.release_nvm(hw); |
1669 | goto out; | 1748 | goto out; |
1670 | } | 1749 | } |
1671 | } | 1750 | } |
@@ -1723,7 +1802,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1723 | if (ret_val) { | 1802 | if (ret_val) { |
1724 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ | 1803 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
1725 | hw_dbg(hw, "Flash commit failed.\n"); | 1804 | hw_dbg(hw, "Flash commit failed.\n"); |
1726 | e1000_release_swflag_ich8lan(hw); | 1805 | nvm->ops.release_nvm(hw); |
1727 | goto out; | 1806 | goto out; |
1728 | } | 1807 | } |
1729 | 1808 | ||
@@ -1736,7 +1815,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1736 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; | 1815 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
1737 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); | 1816 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); |
1738 | if (ret_val) { | 1817 | if (ret_val) { |
1739 | e1000_release_swflag_ich8lan(hw); | 1818 | nvm->ops.release_nvm(hw); |
1740 | goto out; | 1819 | goto out; |
1741 | } | 1820 | } |
1742 | data &= 0xBFFF; | 1821 | data &= 0xBFFF; |
@@ -1744,7 +1823,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1744 | act_offset * 2 + 1, | 1823 | act_offset * 2 + 1, |
1745 | (u8)(data >> 8)); | 1824 | (u8)(data >> 8)); |
1746 | if (ret_val) { | 1825 | if (ret_val) { |
1747 | e1000_release_swflag_ich8lan(hw); | 1826 | nvm->ops.release_nvm(hw); |
1748 | goto out; | 1827 | goto out; |
1749 | } | 1828 | } |
1750 | 1829 | ||
@@ -1757,7 +1836,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1757 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; | 1836 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
1758 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); | 1837 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); |
1759 | if (ret_val) { | 1838 | if (ret_val) { |
1760 | e1000_release_swflag_ich8lan(hw); | 1839 | nvm->ops.release_nvm(hw); |
1761 | goto out; | 1840 | goto out; |
1762 | } | 1841 | } |
1763 | 1842 | ||
@@ -1767,7 +1846,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1767 | dev_spec->shadow_ram[i].value = 0xFFFF; | 1846 | dev_spec->shadow_ram[i].value = 0xFFFF; |
1768 | } | 1847 | } |
1769 | 1848 | ||
1770 | e1000_release_swflag_ich8lan(hw); | 1849 | nvm->ops.release_nvm(hw); |
1771 | 1850 | ||
1772 | /* | 1851 | /* |
1773 | * Reload the EEPROM, or else modifications will not appear | 1852 | * Reload the EEPROM, or else modifications will not appear |
@@ -1831,14 +1910,12 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) | |||
1831 | **/ | 1910 | **/ |
1832 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) | 1911 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) |
1833 | { | 1912 | { |
1913 | struct e1000_nvm_info *nvm = &hw->nvm; | ||
1834 | union ich8_flash_protected_range pr0; | 1914 | union ich8_flash_protected_range pr0; |
1835 | union ich8_hws_flash_status hsfsts; | 1915 | union ich8_hws_flash_status hsfsts; |
1836 | u32 gfpreg; | 1916 | u32 gfpreg; |
1837 | s32 ret_val; | ||
1838 | 1917 | ||
1839 | ret_val = e1000_acquire_swflag_ich8lan(hw); | 1918 | nvm->ops.acquire_nvm(hw); |
1840 | if (ret_val) | ||
1841 | return; | ||
1842 | 1919 | ||
1843 | gfpreg = er32flash(ICH_FLASH_GFPREG); | 1920 | gfpreg = er32flash(ICH_FLASH_GFPREG); |
1844 | 1921 | ||
@@ -1859,7 +1936,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) | |||
1859 | hsfsts.hsf_status.flockdn = true; | 1936 | hsfsts.hsf_status.flockdn = true; |
1860 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); | 1937 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
1861 | 1938 | ||
1862 | e1000_release_swflag_ich8lan(hw); | 1939 | nvm->ops.release_nvm(hw); |
1863 | } | 1940 | } |
1864 | 1941 | ||
1865 | /** | 1942 | /** |
@@ -2229,6 +2306,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |||
2229 | **/ | 2306 | **/ |
2230 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | 2307 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) |
2231 | { | 2308 | { |
2309 | u16 reg; | ||
2232 | u32 ctrl, icr, kab; | 2310 | u32 ctrl, icr, kab; |
2233 | s32 ret_val; | 2311 | s32 ret_val; |
2234 | 2312 | ||
@@ -2304,6 +2382,9 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
2304 | hw_dbg(hw, "Auto Read Done did not complete\n"); | 2382 | hw_dbg(hw, "Auto Read Done did not complete\n"); |
2305 | } | 2383 | } |
2306 | } | 2384 | } |
2385 | /* Dummy read to clear the phy wakeup bit after lcd reset */ | ||
2386 | if (hw->mac.type == e1000_pchlan) | ||
2387 | e1e_rphy(hw, BM_WUC, ®); | ||
2307 | 2388 | ||
2308 | /* | 2389 | /* |
2309 | * For PCH, this write will make sure that any noise | 2390 | * For PCH, this write will make sure that any noise |
@@ -2843,9 +2924,8 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) | |||
2843 | E1000_PHY_CTRL_GBE_DISABLE; | 2924 | E1000_PHY_CTRL_GBE_DISABLE; |
2844 | ew32(PHY_CTRL, phy_ctrl); | 2925 | ew32(PHY_CTRL, phy_ctrl); |
2845 | 2926 | ||
2846 | /* Workaround SWFLAG unexpectedly set during S0->Sx */ | ||
2847 | if (hw->mac.type == e1000_pchlan) | 2927 | if (hw->mac.type == e1000_pchlan) |
2848 | udelay(500); | 2928 | e1000_phy_hw_reset_ich8lan(hw); |
2849 | default: | 2929 | default: |
2850 | break; | 2930 | break; |
2851 | } | 2931 | } |
@@ -3113,9 +3193,9 @@ static struct e1000_phy_operations ich8_phy_ops = { | |||
3113 | }; | 3193 | }; |
3114 | 3194 | ||
3115 | static struct e1000_nvm_operations ich8_nvm_ops = { | 3195 | static struct e1000_nvm_operations ich8_nvm_ops = { |
3116 | .acquire_nvm = e1000_acquire_swflag_ich8lan, | 3196 | .acquire_nvm = e1000_acquire_nvm_ich8lan, |
3117 | .read_nvm = e1000_read_nvm_ich8lan, | 3197 | .read_nvm = e1000_read_nvm_ich8lan, |
3118 | .release_nvm = e1000_release_swflag_ich8lan, | 3198 | .release_nvm = e1000_release_nvm_ich8lan, |
3119 | .update_nvm = e1000_update_nvm_checksum_ich8lan, | 3199 | .update_nvm = e1000_update_nvm_checksum_ich8lan, |
3120 | .valid_led_default = e1000_valid_led_default_ich8lan, | 3200 | .valid_led_default = e1000_valid_led_default_ich8lan, |
3121 | .validate_nvm = e1000_validate_nvm_checksum_ich8lan, | 3201 | .validate_nvm = e1000_validate_nvm_checksum_ich8lan, |
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index 994401fd0664..f9d33ab05e97 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c | |||
@@ -164,16 +164,25 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw) | |||
164 | * MDIC mode. No harm in trying again in this case since | 164 | * MDIC mode. No harm in trying again in this case since |
165 | * the PHY ID is unknown at this point anyway | 165 | * the PHY ID is unknown at this point anyway |
166 | */ | 166 | */ |
167 | ret_val = phy->ops.acquire_phy(hw); | ||
168 | if (ret_val) | ||
169 | goto out; | ||
167 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); | 170 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); |
168 | if (ret_val) | 171 | if (ret_val) |
169 | goto out; | 172 | goto out; |
173 | phy->ops.release_phy(hw); | ||
170 | 174 | ||
171 | retry_count++; | 175 | retry_count++; |
172 | } | 176 | } |
173 | out: | 177 | out: |
174 | /* Revert to MDIO fast mode, if applicable */ | 178 | /* Revert to MDIO fast mode, if applicable */ |
175 | if (retry_count) | 179 | if (retry_count) { |
180 | ret_val = phy->ops.acquire_phy(hw); | ||
181 | if (ret_val) | ||
182 | return ret_val; | ||
176 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | 183 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); |
184 | phy->ops.release_phy(hw); | ||
185 | } | ||
177 | 186 | ||
178 | return ret_val; | 187 | return ret_val; |
179 | } | 188 | } |
@@ -354,94 +363,173 @@ s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) | |||
354 | } | 363 | } |
355 | 364 | ||
356 | /** | 365 | /** |
357 | * e1000e_read_phy_reg_igp - Read igp PHY register | 366 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
358 | * @hw: pointer to the HW structure | 367 | * @hw: pointer to the HW structure |
359 | * @offset: register offset to be read | 368 | * @offset: register offset to be read |
360 | * @data: pointer to the read data | 369 | * @data: pointer to the read data |
370 | * @locked: semaphore has already been acquired or not | ||
361 | * | 371 | * |
362 | * Acquires semaphore, if necessary, then reads the PHY register at offset | 372 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
363 | * and storing the retrieved information in data. Release any acquired | 373 | * and stores the retrieved information in data. Release any acquired |
364 | * semaphores before exiting. | 374 | * semaphores before exiting. |
365 | **/ | 375 | **/ |
366 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | 376 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
377 | bool locked) | ||
367 | { | 378 | { |
368 | s32 ret_val; | 379 | s32 ret_val = 0; |
369 | 380 | ||
370 | ret_val = hw->phy.ops.acquire_phy(hw); | 381 | if (!locked) { |
371 | if (ret_val) | 382 | if (!(hw->phy.ops.acquire_phy)) |
372 | return ret_val; | 383 | goto out; |
384 | |||
385 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
386 | if (ret_val) | ||
387 | goto out; | ||
388 | } | ||
373 | 389 | ||
374 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 390 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
375 | ret_val = e1000e_write_phy_reg_mdic(hw, | 391 | ret_val = e1000e_write_phy_reg_mdic(hw, |
376 | IGP01E1000_PHY_PAGE_SELECT, | 392 | IGP01E1000_PHY_PAGE_SELECT, |
377 | (u16)offset); | 393 | (u16)offset); |
378 | if (ret_val) { | 394 | if (ret_val) |
379 | hw->phy.ops.release_phy(hw); | 395 | goto release; |
380 | return ret_val; | ||
381 | } | ||
382 | } | 396 | } |
383 | 397 | ||
384 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | 398 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
385 | data); | 399 | data); |
386 | |||
387 | hw->phy.ops.release_phy(hw); | ||
388 | 400 | ||
401 | release: | ||
402 | if (!locked) | ||
403 | hw->phy.ops.release_phy(hw); | ||
404 | out: | ||
389 | return ret_val; | 405 | return ret_val; |
390 | } | 406 | } |
391 | 407 | ||
392 | /** | 408 | /** |
409 | * e1000e_read_phy_reg_igp - Read igp PHY register | ||
410 | * @hw: pointer to the HW structure | ||
411 | * @offset: register offset to be read | ||
412 | * @data: pointer to the read data | ||
413 | * | ||
414 | * Acquires semaphore then reads the PHY register at offset and stores the | ||
415 | * retrieved information in data. | ||
416 | * Release the acquired semaphore before exiting. | ||
417 | **/ | ||
418 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | ||
419 | { | ||
420 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); | ||
421 | } | ||
422 | |||
423 | /** | ||
424 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register | ||
425 | * @hw: pointer to the HW structure | ||
426 | * @offset: register offset to be read | ||
427 | * @data: pointer to the read data | ||
428 | * | ||
429 | * Reads the PHY register at offset and stores the retrieved information | ||
430 | * in data. Assumes semaphore already acquired. | ||
431 | **/ | ||
432 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) | ||
433 | { | ||
434 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); | ||
435 | } | ||
436 | |||
437 | /** | ||
393 | * e1000e_write_phy_reg_igp - Write igp PHY register | 438 | * e1000e_write_phy_reg_igp - Write igp PHY register |
394 | * @hw: pointer to the HW structure | 439 | * @hw: pointer to the HW structure |
395 | * @offset: register offset to write to | 440 | * @offset: register offset to write to |
396 | * @data: data to write at register offset | 441 | * @data: data to write at register offset |
442 | * @locked: semaphore has already been acquired or not | ||
397 | * | 443 | * |
398 | * Acquires semaphore, if necessary, then writes the data to PHY register | 444 | * Acquires semaphore, if necessary, then writes the data to PHY register |
399 | * at the offset. Release any acquired semaphores before exiting. | 445 | * at the offset. Release any acquired semaphores before exiting. |
400 | **/ | 446 | **/ |
401 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | 447 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
448 | bool locked) | ||
402 | { | 449 | { |
403 | s32 ret_val; | 450 | s32 ret_val = 0; |
404 | 451 | ||
405 | ret_val = hw->phy.ops.acquire_phy(hw); | 452 | if (!locked) { |
406 | if (ret_val) | 453 | if (!(hw->phy.ops.acquire_phy)) |
407 | return ret_val; | 454 | goto out; |
455 | |||
456 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
457 | if (ret_val) | ||
458 | goto out; | ||
459 | } | ||
408 | 460 | ||
409 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 461 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
410 | ret_val = e1000e_write_phy_reg_mdic(hw, | 462 | ret_val = e1000e_write_phy_reg_mdic(hw, |
411 | IGP01E1000_PHY_PAGE_SELECT, | 463 | IGP01E1000_PHY_PAGE_SELECT, |
412 | (u16)offset); | 464 | (u16)offset); |
413 | if (ret_val) { | 465 | if (ret_val) |
414 | hw->phy.ops.release_phy(hw); | 466 | goto release; |
415 | return ret_val; | ||
416 | } | ||
417 | } | 467 | } |
418 | 468 | ||
419 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | 469 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
420 | data); | 470 | data); |
421 | 471 | ||
422 | hw->phy.ops.release_phy(hw); | 472 | release: |
473 | if (!locked) | ||
474 | hw->phy.ops.release_phy(hw); | ||
423 | 475 | ||
476 | out: | ||
424 | return ret_val; | 477 | return ret_val; |
425 | } | 478 | } |
426 | 479 | ||
427 | /** | 480 | /** |
428 | * e1000e_read_kmrn_reg - Read kumeran register | 481 | * e1000e_write_phy_reg_igp - Write igp PHY register |
482 | * @hw: pointer to the HW structure | ||
483 | * @offset: register offset to write to | ||
484 | * @data: data to write at register offset | ||
485 | * | ||
486 | * Acquires semaphore then writes the data to PHY register | ||
487 | * at the offset. Release any acquired semaphores before exiting. | ||
488 | **/ | ||
489 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | ||
490 | { | ||
491 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); | ||
492 | } | ||
493 | |||
494 | /** | ||
495 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register | ||
496 | * @hw: pointer to the HW structure | ||
497 | * @offset: register offset to write to | ||
498 | * @data: data to write at register offset | ||
499 | * | ||
500 | * Writes the data to PHY register at the offset. | ||
501 | * Assumes semaphore already acquired. | ||
502 | **/ | ||
503 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) | ||
504 | { | ||
505 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); | ||
506 | } | ||
507 | |||
508 | /** | ||
509 | * __e1000_read_kmrn_reg - Read kumeran register | ||
429 | * @hw: pointer to the HW structure | 510 | * @hw: pointer to the HW structure |
430 | * @offset: register offset to be read | 511 | * @offset: register offset to be read |
431 | * @data: pointer to the read data | 512 | * @data: pointer to the read data |
513 | * @locked: semaphore has already been acquired or not | ||
432 | * | 514 | * |
433 | * Acquires semaphore, if necessary. Then reads the PHY register at offset | 515 | * Acquires semaphore, if necessary. Then reads the PHY register at offset |
434 | * using the kumeran interface. The information retrieved is stored in data. | 516 | * using the kumeran interface. The information retrieved is stored in data. |
435 | * Release any acquired semaphores before exiting. | 517 | * Release any acquired semaphores before exiting. |
436 | **/ | 518 | **/ |
437 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | 519 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
520 | bool locked) | ||
438 | { | 521 | { |
439 | u32 kmrnctrlsta; | 522 | u32 kmrnctrlsta; |
440 | s32 ret_val; | 523 | s32 ret_val = 0; |
441 | 524 | ||
442 | ret_val = hw->phy.ops.acquire_phy(hw); | 525 | if (!locked) { |
443 | if (ret_val) | 526 | if (!(hw->phy.ops.acquire_phy)) |
444 | return ret_val; | 527 | goto out; |
528 | |||
529 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
530 | if (ret_val) | ||
531 | goto out; | ||
532 | } | ||
445 | 533 | ||
446 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | 534 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
447 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | 535 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
@@ -452,41 +540,111 @@ s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |||
452 | kmrnctrlsta = er32(KMRNCTRLSTA); | 540 | kmrnctrlsta = er32(KMRNCTRLSTA); |
453 | *data = (u16)kmrnctrlsta; | 541 | *data = (u16)kmrnctrlsta; |
454 | 542 | ||
455 | hw->phy.ops.release_phy(hw); | 543 | if (!locked) |
544 | hw->phy.ops.release_phy(hw); | ||
456 | 545 | ||
546 | out: | ||
457 | return ret_val; | 547 | return ret_val; |
458 | } | 548 | } |
459 | 549 | ||
460 | /** | 550 | /** |
461 | * e1000e_write_kmrn_reg - Write kumeran register | 551 | * e1000e_read_kmrn_reg - Read kumeran register |
552 | * @hw: pointer to the HW structure | ||
553 | * @offset: register offset to be read | ||
554 | * @data: pointer to the read data | ||
555 | * | ||
556 | * Acquires semaphore then reads the PHY register at offset using the | ||
557 | * kumeran interface. The information retrieved is stored in data. | ||
558 | * Release the acquired semaphore before exiting. | ||
559 | **/ | ||
560 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | ||
561 | { | ||
562 | return __e1000_read_kmrn_reg(hw, offset, data, false); | ||
563 | } | ||
564 | |||
565 | /** | ||
566 | * e1000_read_kmrn_reg_locked - Read kumeran register | ||
567 | * @hw: pointer to the HW structure | ||
568 | * @offset: register offset to be read | ||
569 | * @data: pointer to the read data | ||
570 | * | ||
571 | * Reads the PHY register at offset using the kumeran interface. The | ||
572 | * information retrieved is stored in data. | ||
573 | * Assumes semaphore already acquired. | ||
574 | **/ | ||
575 | s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) | ||
576 | { | ||
577 | return __e1000_read_kmrn_reg(hw, offset, data, true); | ||
578 | } | ||
579 | |||
580 | /** | ||
581 | * __e1000_write_kmrn_reg - Write kumeran register | ||
462 | * @hw: pointer to the HW structure | 582 | * @hw: pointer to the HW structure |
463 | * @offset: register offset to write to | 583 | * @offset: register offset to write to |
464 | * @data: data to write at register offset | 584 | * @data: data to write at register offset |
585 | * @locked: semaphore has already been acquired or not | ||
465 | * | 586 | * |
466 | * Acquires semaphore, if necessary. Then write the data to PHY register | 587 | * Acquires semaphore, if necessary. Then write the data to PHY register |
467 | * at the offset using the kumeran interface. Release any acquired semaphores | 588 | * at the offset using the kumeran interface. Release any acquired semaphores |
468 | * before exiting. | 589 | * before exiting. |
469 | **/ | 590 | **/ |
470 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) | 591 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
592 | bool locked) | ||
471 | { | 593 | { |
472 | u32 kmrnctrlsta; | 594 | u32 kmrnctrlsta; |
473 | s32 ret_val; | 595 | s32 ret_val = 0; |
474 | 596 | ||
475 | ret_val = hw->phy.ops.acquire_phy(hw); | 597 | if (!locked) { |
476 | if (ret_val) | 598 | if (!(hw->phy.ops.acquire_phy)) |
477 | return ret_val; | 599 | goto out; |
600 | |||
601 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
602 | if (ret_val) | ||
603 | goto out; | ||
604 | } | ||
478 | 605 | ||
479 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | 606 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
480 | E1000_KMRNCTRLSTA_OFFSET) | data; | 607 | E1000_KMRNCTRLSTA_OFFSET) | data; |
481 | ew32(KMRNCTRLSTA, kmrnctrlsta); | 608 | ew32(KMRNCTRLSTA, kmrnctrlsta); |
482 | 609 | ||
483 | udelay(2); | 610 | udelay(2); |
484 | hw->phy.ops.release_phy(hw); | ||
485 | 611 | ||
612 | if (!locked) | ||
613 | hw->phy.ops.release_phy(hw); | ||
614 | |||
615 | out: | ||
486 | return ret_val; | 616 | return ret_val; |
487 | } | 617 | } |
488 | 618 | ||
489 | /** | 619 | /** |
620 | * e1000e_write_kmrn_reg - Write kumeran register | ||
621 | * @hw: pointer to the HW structure | ||
622 | * @offset: register offset to write to | ||
623 | * @data: data to write at register offset | ||
624 | * | ||
625 | * Acquires semaphore then writes the data to the PHY register at the offset | ||
626 | * using the kumeran interface. Release the acquired semaphore before exiting. | ||
627 | **/ | ||
628 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) | ||
629 | { | ||
630 | return __e1000_write_kmrn_reg(hw, offset, data, false); | ||
631 | } | ||
632 | |||
633 | /** | ||
634 | * e1000_write_kmrn_reg_locked - Write kumeran register | ||
635 | * @hw: pointer to the HW structure | ||
636 | * @offset: register offset to write to | ||
637 | * @data: data to write at register offset | ||
638 | * | ||
639 | * Write the data to PHY register at the offset using the kumeran interface. | ||
640 | * Assumes semaphore already acquired. | ||
641 | **/ | ||
642 | s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) | ||
643 | { | ||
644 | return __e1000_write_kmrn_reg(hw, offset, data, true); | ||
645 | } | ||
646 | |||
647 | /** | ||
490 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link | 648 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link |
491 | * @hw: pointer to the HW structure | 649 | * @hw: pointer to the HW structure |
492 | * | 650 | * |
@@ -2105,6 +2263,10 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |||
2105 | u32 page = offset >> IGP_PAGE_SHIFT; | 2263 | u32 page = offset >> IGP_PAGE_SHIFT; |
2106 | u32 page_shift = 0; | 2264 | u32 page_shift = 0; |
2107 | 2265 | ||
2266 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2267 | if (ret_val) | ||
2268 | return ret_val; | ||
2269 | |||
2108 | /* Page 800 works differently than the rest so it has its own func */ | 2270 | /* Page 800 works differently than the rest so it has its own func */ |
2109 | if (page == BM_WUC_PAGE) { | 2271 | if (page == BM_WUC_PAGE) { |
2110 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | 2272 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
@@ -2112,10 +2274,6 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |||
2112 | goto out; | 2274 | goto out; |
2113 | } | 2275 | } |
2114 | 2276 | ||
2115 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2116 | if (ret_val) | ||
2117 | goto out; | ||
2118 | |||
2119 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); | 2277 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2120 | 2278 | ||
2121 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 2279 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
@@ -2135,18 +2293,15 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |||
2135 | /* Page is shifted left, PHY expects (page x 32) */ | 2293 | /* Page is shifted left, PHY expects (page x 32) */ |
2136 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | 2294 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
2137 | (page << page_shift)); | 2295 | (page << page_shift)); |
2138 | if (ret_val) { | 2296 | if (ret_val) |
2139 | hw->phy.ops.release_phy(hw); | ||
2140 | goto out; | 2297 | goto out; |
2141 | } | ||
2142 | } | 2298 | } |
2143 | 2299 | ||
2144 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | 2300 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
2145 | data); | 2301 | data); |
2146 | 2302 | ||
2147 | hw->phy.ops.release_phy(hw); | ||
2148 | |||
2149 | out: | 2303 | out: |
2304 | hw->phy.ops.release_phy(hw); | ||
2150 | return ret_val; | 2305 | return ret_val; |
2151 | } | 2306 | } |
2152 | 2307 | ||
@@ -2167,6 +2322,10 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |||
2167 | u32 page = offset >> IGP_PAGE_SHIFT; | 2322 | u32 page = offset >> IGP_PAGE_SHIFT; |
2168 | u32 page_shift = 0; | 2323 | u32 page_shift = 0; |
2169 | 2324 | ||
2325 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2326 | if (ret_val) | ||
2327 | return ret_val; | ||
2328 | |||
2170 | /* Page 800 works differently than the rest so it has its own func */ | 2329 | /* Page 800 works differently than the rest so it has its own func */ |
2171 | if (page == BM_WUC_PAGE) { | 2330 | if (page == BM_WUC_PAGE) { |
2172 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | 2331 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
@@ -2174,10 +2333,6 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |||
2174 | goto out; | 2333 | goto out; |
2175 | } | 2334 | } |
2176 | 2335 | ||
2177 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2178 | if (ret_val) | ||
2179 | goto out; | ||
2180 | |||
2181 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); | 2336 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2182 | 2337 | ||
2183 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 2338 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
@@ -2197,17 +2352,14 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |||
2197 | /* Page is shifted left, PHY expects (page x 32) */ | 2352 | /* Page is shifted left, PHY expects (page x 32) */ |
2198 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | 2353 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
2199 | (page << page_shift)); | 2354 | (page << page_shift)); |
2200 | if (ret_val) { | 2355 | if (ret_val) |
2201 | hw->phy.ops.release_phy(hw); | ||
2202 | goto out; | 2356 | goto out; |
2203 | } | ||
2204 | } | 2357 | } |
2205 | 2358 | ||
2206 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | 2359 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
2207 | data); | 2360 | data); |
2208 | hw->phy.ops.release_phy(hw); | ||
2209 | |||
2210 | out: | 2361 | out: |
2362 | hw->phy.ops.release_phy(hw); | ||
2211 | return ret_val; | 2363 | return ret_val; |
2212 | } | 2364 | } |
2213 | 2365 | ||
@@ -2226,17 +2378,17 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) | |||
2226 | s32 ret_val; | 2378 | s32 ret_val; |
2227 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | 2379 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
2228 | 2380 | ||
2381 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2382 | if (ret_val) | ||
2383 | return ret_val; | ||
2384 | |||
2229 | /* Page 800 works differently than the rest so it has its own func */ | 2385 | /* Page 800 works differently than the rest so it has its own func */ |
2230 | if (page == BM_WUC_PAGE) { | 2386 | if (page == BM_WUC_PAGE) { |
2231 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | 2387 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
2232 | true); | 2388 | true); |
2233 | return ret_val; | 2389 | goto out; |
2234 | } | 2390 | } |
2235 | 2391 | ||
2236 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2237 | if (ret_val) | ||
2238 | return ret_val; | ||
2239 | |||
2240 | hw->phy.addr = 1; | 2392 | hw->phy.addr = 1; |
2241 | 2393 | ||
2242 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 2394 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
@@ -2245,16 +2397,14 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) | |||
2245 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | 2397 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
2246 | page); | 2398 | page); |
2247 | 2399 | ||
2248 | if (ret_val) { | 2400 | if (ret_val) |
2249 | hw->phy.ops.release_phy(hw); | 2401 | goto out; |
2250 | return ret_val; | ||
2251 | } | ||
2252 | } | 2402 | } |
2253 | 2403 | ||
2254 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | 2404 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
2255 | data); | 2405 | data); |
2406 | out: | ||
2256 | hw->phy.ops.release_phy(hw); | 2407 | hw->phy.ops.release_phy(hw); |
2257 | |||
2258 | return ret_val; | 2408 | return ret_val; |
2259 | } | 2409 | } |
2260 | 2410 | ||
@@ -2272,17 +2422,17 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |||
2272 | s32 ret_val; | 2422 | s32 ret_val; |
2273 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | 2423 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
2274 | 2424 | ||
2425 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2426 | if (ret_val) | ||
2427 | return ret_val; | ||
2428 | |||
2275 | /* Page 800 works differently than the rest so it has its own func */ | 2429 | /* Page 800 works differently than the rest so it has its own func */ |
2276 | if (page == BM_WUC_PAGE) { | 2430 | if (page == BM_WUC_PAGE) { |
2277 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | 2431 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
2278 | false); | 2432 | false); |
2279 | return ret_val; | 2433 | goto out; |
2280 | } | 2434 | } |
2281 | 2435 | ||
2282 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2283 | if (ret_val) | ||
2284 | return ret_val; | ||
2285 | |||
2286 | hw->phy.addr = 1; | 2436 | hw->phy.addr = 1; |
2287 | 2437 | ||
2288 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 2438 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
@@ -2290,17 +2440,15 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |||
2290 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | 2440 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
2291 | page); | 2441 | page); |
2292 | 2442 | ||
2293 | if (ret_val) { | 2443 | if (ret_val) |
2294 | hw->phy.ops.release_phy(hw); | 2444 | goto out; |
2295 | return ret_val; | ||
2296 | } | ||
2297 | } | 2445 | } |
2298 | 2446 | ||
2299 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | 2447 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
2300 | data); | 2448 | data); |
2301 | 2449 | ||
2450 | out: | ||
2302 | hw->phy.ops.release_phy(hw); | 2451 | hw->phy.ops.release_phy(hw); |
2303 | |||
2304 | return ret_val; | 2452 | return ret_val; |
2305 | } | 2453 | } |
2306 | 2454 | ||
@@ -2320,6 +2468,8 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |||
2320 | * 3) Write the address using the address opcode (0x11) | 2468 | * 3) Write the address using the address opcode (0x11) |
2321 | * 4) Read or write the data using the data opcode (0x12) | 2469 | * 4) Read or write the data using the data opcode (0x12) |
2322 | * 5) Restore 769_17.2 to its original value | 2470 | * 5) Restore 769_17.2 to its original value |
2471 | * | ||
2472 | * Assumes semaphore already acquired. | ||
2323 | **/ | 2473 | **/ |
2324 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | 2474 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
2325 | u16 *data, bool read) | 2475 | u16 *data, bool read) |
@@ -2327,20 +2477,12 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |||
2327 | s32 ret_val; | 2477 | s32 ret_val; |
2328 | u16 reg = BM_PHY_REG_NUM(offset); | 2478 | u16 reg = BM_PHY_REG_NUM(offset); |
2329 | u16 phy_reg = 0; | 2479 | u16 phy_reg = 0; |
2330 | u8 phy_acquired = 1; | ||
2331 | |||
2332 | 2480 | ||
2333 | /* Gig must be disabled for MDIO accesses to page 800 */ | 2481 | /* Gig must be disabled for MDIO accesses to page 800 */ |
2334 | if ((hw->mac.type == e1000_pchlan) && | 2482 | if ((hw->mac.type == e1000_pchlan) && |
2335 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) | 2483 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) |
2336 | hw_dbg(hw, "Attempting to access page 800 while gig enabled\n"); | 2484 | hw_dbg(hw, "Attempting to access page 800 while gig enabled\n"); |
2337 | 2485 | ||
2338 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2339 | if (ret_val) { | ||
2340 | phy_acquired = 0; | ||
2341 | goto out; | ||
2342 | } | ||
2343 | |||
2344 | /* All operations in this function are phy address 1 */ | 2486 | /* All operations in this function are phy address 1 */ |
2345 | hw->phy.addr = 1; | 2487 | hw->phy.addr = 1; |
2346 | 2488 | ||
@@ -2397,8 +2539,6 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |||
2397 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | 2539 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
2398 | 2540 | ||
2399 | out: | 2541 | out: |
2400 | if (phy_acquired == 1) | ||
2401 | hw->phy.ops.release_phy(hw); | ||
2402 | return ret_val; | 2542 | return ret_val; |
2403 | } | 2543 | } |
2404 | 2544 | ||
@@ -2439,52 +2579,63 @@ static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) | |||
2439 | return 0; | 2579 | return 0; |
2440 | } | 2580 | } |
2441 | 2581 | ||
2582 | /** | ||
2583 | * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode | ||
2584 | * @hw: pointer to the HW structure | ||
2585 | * @slow: true for slow mode, false for normal mode | ||
2586 | * | ||
2587 | * Assumes semaphore already acquired. | ||
2588 | **/ | ||
2442 | s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow) | 2589 | s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow) |
2443 | { | 2590 | { |
2444 | s32 ret_val = 0; | 2591 | s32 ret_val = 0; |
2445 | u16 data = 0; | 2592 | u16 data = 0; |
2446 | 2593 | ||
2447 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2448 | if (ret_val) | ||
2449 | return ret_val; | ||
2450 | |||
2451 | /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ | 2594 | /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ |
2452 | hw->phy.addr = 1; | 2595 | hw->phy.addr = 1; |
2453 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | 2596 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, |
2454 | (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | 2597 | (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
2455 | if (ret_val) { | 2598 | if (ret_val) |
2456 | hw->phy.ops.release_phy(hw); | 2599 | goto out; |
2457 | return ret_val; | 2600 | |
2458 | } | ||
2459 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1, | 2601 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1, |
2460 | (0x2180 | (slow << 10))); | 2602 | (0x2180 | (slow << 10))); |
2603 | if (ret_val) | ||
2604 | goto out; | ||
2461 | 2605 | ||
2462 | /* dummy read when reverting to fast mode - throw away result */ | 2606 | /* dummy read when reverting to fast mode - throw away result */ |
2463 | if (!slow) | 2607 | if (!slow) |
2464 | e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); | 2608 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); |
2465 | |||
2466 | hw->phy.ops.release_phy(hw); | ||
2467 | 2609 | ||
2610 | out: | ||
2468 | return ret_val; | 2611 | return ret_val; |
2469 | } | 2612 | } |
2470 | 2613 | ||
2471 | /** | 2614 | /** |
2472 | * e1000_read_phy_reg_hv - Read HV PHY register | 2615 | * __e1000_read_phy_reg_hv - Read HV PHY register |
2473 | * @hw: pointer to the HW structure | 2616 | * @hw: pointer to the HW structure |
2474 | * @offset: register offset to be read | 2617 | * @offset: register offset to be read |
2475 | * @data: pointer to the read data | 2618 | * @data: pointer to the read data |
2619 | * @locked: semaphore has already been acquired or not | ||
2476 | * | 2620 | * |
2477 | * Acquires semaphore, if necessary, then reads the PHY register at offset | 2621 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
2478 | * and storing the retrieved information in data. Release any acquired | 2622 | * and stores the retrieved information in data. Release any acquired |
2479 | * semaphore before exiting. | 2623 | * semaphore before exiting. |
2480 | **/ | 2624 | **/ |
2481 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | 2625 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
2626 | bool locked) | ||
2482 | { | 2627 | { |
2483 | s32 ret_val; | 2628 | s32 ret_val; |
2484 | u16 page = BM_PHY_REG_PAGE(offset); | 2629 | u16 page = BM_PHY_REG_PAGE(offset); |
2485 | u16 reg = BM_PHY_REG_NUM(offset); | 2630 | u16 reg = BM_PHY_REG_NUM(offset); |
2486 | bool in_slow_mode = false; | 2631 | bool in_slow_mode = false; |
2487 | 2632 | ||
2633 | if (!locked) { | ||
2634 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2635 | if (ret_val) | ||
2636 | return ret_val; | ||
2637 | } | ||
2638 | |||
2488 | /* Workaround failure in MDIO access while cable is disconnected */ | 2639 | /* Workaround failure in MDIO access while cable is disconnected */ |
2489 | if ((hw->phy.type == e1000_phy_82577) && | 2640 | if ((hw->phy.type == e1000_phy_82577) && |
2490 | !(er32(STATUS) & E1000_STATUS_LU)) { | 2641 | !(er32(STATUS) & E1000_STATUS_LU)) { |
@@ -2508,10 +2659,6 @@ s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |||
2508 | goto out; | 2659 | goto out; |
2509 | } | 2660 | } |
2510 | 2661 | ||
2511 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2512 | if (ret_val) | ||
2513 | goto out; | ||
2514 | |||
2515 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); | 2662 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2516 | 2663 | ||
2517 | if (page == HV_INTC_FC_PAGE_START) | 2664 | if (page == HV_INTC_FC_PAGE_START) |
@@ -2529,42 +2676,76 @@ s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |||
2529 | ret_val = e1000e_write_phy_reg_mdic(hw, | 2676 | ret_val = e1000e_write_phy_reg_mdic(hw, |
2530 | IGP01E1000_PHY_PAGE_SELECT, | 2677 | IGP01E1000_PHY_PAGE_SELECT, |
2531 | (page << IGP_PAGE_SHIFT)); | 2678 | (page << IGP_PAGE_SHIFT)); |
2532 | if (ret_val) { | ||
2533 | hw->phy.ops.release_phy(hw); | ||
2534 | goto out; | ||
2535 | } | ||
2536 | hw->phy.addr = phy_addr; | 2679 | hw->phy.addr = phy_addr; |
2537 | } | 2680 | } |
2538 | } | 2681 | } |
2539 | 2682 | ||
2540 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | 2683 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
2541 | data); | 2684 | data); |
2542 | hw->phy.ops.release_phy(hw); | ||
2543 | |||
2544 | out: | 2685 | out: |
2545 | /* Revert to MDIO fast mode, if applicable */ | 2686 | /* Revert to MDIO fast mode, if applicable */ |
2546 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | 2687 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) |
2547 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | 2688 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); |
2548 | 2689 | ||
2690 | if (!locked) | ||
2691 | hw->phy.ops.release_phy(hw); | ||
2692 | |||
2549 | return ret_val; | 2693 | return ret_val; |
2550 | } | 2694 | } |
2551 | 2695 | ||
2552 | /** | 2696 | /** |
2553 | * e1000_write_phy_reg_hv - Write HV PHY register | 2697 | * e1000_read_phy_reg_hv - Read HV PHY register |
2698 | * @hw: pointer to the HW structure | ||
2699 | * @offset: register offset to be read | ||
2700 | * @data: pointer to the read data | ||
2701 | * | ||
2702 | * Acquires semaphore then reads the PHY register at offset and stores | ||
2703 | * the retrieved information in data. Release the acquired semaphore | ||
2704 | * before exiting. | ||
2705 | **/ | ||
2706 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | ||
2707 | { | ||
2708 | return __e1000_read_phy_reg_hv(hw, offset, data, false); | ||
2709 | } | ||
2710 | |||
2711 | /** | ||
2712 | * e1000_read_phy_reg_hv_locked - Read HV PHY register | ||
2713 | * @hw: pointer to the HW structure | ||
2714 | * @offset: register offset to be read | ||
2715 | * @data: pointer to the read data | ||
2716 | * | ||
2717 | * Reads the PHY register at offset and stores the retrieved information | ||
2718 | * in data. Assumes semaphore already acquired. | ||
2719 | **/ | ||
2720 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) | ||
2721 | { | ||
2722 | return __e1000_read_phy_reg_hv(hw, offset, data, true); | ||
2723 | } | ||
2724 | |||
2725 | /** | ||
2726 | * __e1000_write_phy_reg_hv - Write HV PHY register | ||
2554 | * @hw: pointer to the HW structure | 2727 | * @hw: pointer to the HW structure |
2555 | * @offset: register offset to write to | 2728 | * @offset: register offset to write to |
2556 | * @data: data to write at register offset | 2729 | * @data: data to write at register offset |
2730 | * @locked: semaphore has already been acquired or not | ||
2557 | * | 2731 | * |
2558 | * Acquires semaphore, if necessary, then writes the data to PHY register | 2732 | * Acquires semaphore, if necessary, then writes the data to PHY register |
2559 | * at the offset. Release any acquired semaphores before exiting. | 2733 | * at the offset. Release any acquired semaphores before exiting. |
2560 | **/ | 2734 | **/ |
2561 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | 2735 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
2736 | bool locked) | ||
2562 | { | 2737 | { |
2563 | s32 ret_val; | 2738 | s32 ret_val; |
2564 | u16 page = BM_PHY_REG_PAGE(offset); | 2739 | u16 page = BM_PHY_REG_PAGE(offset); |
2565 | u16 reg = BM_PHY_REG_NUM(offset); | 2740 | u16 reg = BM_PHY_REG_NUM(offset); |
2566 | bool in_slow_mode = false; | 2741 | bool in_slow_mode = false; |
2567 | 2742 | ||
2743 | if (!locked) { | ||
2744 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2745 | if (ret_val) | ||
2746 | return ret_val; | ||
2747 | } | ||
2748 | |||
2568 | /* Workaround failure in MDIO access while cable is disconnected */ | 2749 | /* Workaround failure in MDIO access while cable is disconnected */ |
2569 | if ((hw->phy.type == e1000_phy_82577) && | 2750 | if ((hw->phy.type == e1000_phy_82577) && |
2570 | !(er32(STATUS) & E1000_STATUS_LU)) { | 2751 | !(er32(STATUS) & E1000_STATUS_LU)) { |
@@ -2588,10 +2769,6 @@ s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |||
2588 | goto out; | 2769 | goto out; |
2589 | } | 2770 | } |
2590 | 2771 | ||
2591 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2592 | if (ret_val) | ||
2593 | goto out; | ||
2594 | |||
2595 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); | 2772 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2596 | 2773 | ||
2597 | if (page == HV_INTC_FC_PAGE_START) | 2774 | if (page == HV_INTC_FC_PAGE_START) |
@@ -2607,15 +2784,10 @@ s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |||
2607 | ((MAX_PHY_REG_ADDRESS & reg) == 0) && | 2784 | ((MAX_PHY_REG_ADDRESS & reg) == 0) && |
2608 | (data & (1 << 11))) { | 2785 | (data & (1 << 11))) { |
2609 | u16 data2 = 0x7EFF; | 2786 | u16 data2 = 0x7EFF; |
2610 | hw->phy.ops.release_phy(hw); | ||
2611 | ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, | 2787 | ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, |
2612 | &data2, false); | 2788 | &data2, false); |
2613 | if (ret_val) | 2789 | if (ret_val) |
2614 | goto out; | 2790 | goto out; |
2615 | |||
2616 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2617 | if (ret_val) | ||
2618 | goto out; | ||
2619 | } | 2791 | } |
2620 | 2792 | ||
2621 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | 2793 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
@@ -2630,27 +2802,53 @@ s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |||
2630 | ret_val = e1000e_write_phy_reg_mdic(hw, | 2802 | ret_val = e1000e_write_phy_reg_mdic(hw, |
2631 | IGP01E1000_PHY_PAGE_SELECT, | 2803 | IGP01E1000_PHY_PAGE_SELECT, |
2632 | (page << IGP_PAGE_SHIFT)); | 2804 | (page << IGP_PAGE_SHIFT)); |
2633 | if (ret_val) { | ||
2634 | hw->phy.ops.release_phy(hw); | ||
2635 | goto out; | ||
2636 | } | ||
2637 | hw->phy.addr = phy_addr; | 2805 | hw->phy.addr = phy_addr; |
2638 | } | 2806 | } |
2639 | } | 2807 | } |
2640 | 2808 | ||
2641 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | 2809 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
2642 | data); | 2810 | data); |
2643 | hw->phy.ops.release_phy(hw); | ||
2644 | 2811 | ||
2645 | out: | 2812 | out: |
2646 | /* Revert to MDIO fast mode, if applicable */ | 2813 | /* Revert to MDIO fast mode, if applicable */ |
2647 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | 2814 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) |
2648 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | 2815 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); |
2649 | 2816 | ||
2817 | if (!locked) | ||
2818 | hw->phy.ops.release_phy(hw); | ||
2819 | |||
2650 | return ret_val; | 2820 | return ret_val; |
2651 | } | 2821 | } |
2652 | 2822 | ||
2653 | /** | 2823 | /** |
2824 | * e1000_write_phy_reg_hv - Write HV PHY register | ||
2825 | * @hw: pointer to the HW structure | ||
2826 | * @offset: register offset to write to | ||
2827 | * @data: data to write at register offset | ||
2828 | * | ||
2829 | * Acquires semaphore then writes the data to PHY register at the offset. | ||
2830 | * Release the acquired semaphores before exiting. | ||
2831 | **/ | ||
2832 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | ||
2833 | { | ||
2834 | return __e1000_write_phy_reg_hv(hw, offset, data, false); | ||
2835 | } | ||
2836 | |||
2837 | /** | ||
2838 | * e1000_write_phy_reg_hv_locked - Write HV PHY register | ||
2839 | * @hw: pointer to the HW structure | ||
2840 | * @offset: register offset to write to | ||
2841 | * @data: data to write at register offset | ||
2842 | * | ||
2843 | * Writes the data to PHY register at the offset. Assumes semaphore | ||
2844 | * already acquired. | ||
2845 | **/ | ||
2846 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) | ||
2847 | { | ||
2848 | return __e1000_write_phy_reg_hv(hw, offset, data, true); | ||
2849 | } | ||
2850 | |||
2851 | /** | ||
2654 | * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page | 2852 | * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page |
2655 | * @page: page to be accessed | 2853 | * @page: page to be accessed |
2656 | **/ | 2854 | **/ |
@@ -2671,10 +2869,9 @@ static u32 e1000_get_phy_addr_for_hv_page(u32 page) | |||
2671 | * @data: pointer to the data to be read or written | 2869 | * @data: pointer to the data to be read or written |
2672 | * @read: determines if operation is read or written | 2870 | * @read: determines if operation is read or written |
2673 | * | 2871 | * |
2674 | * Acquires semaphore, if necessary, then reads the PHY register at offset | 2872 | * Reads the PHY register at offset and stores the retreived information |
2675 | * and storing the retreived information in data. Release any acquired | 2873 | * in data. Assumes semaphore already acquired. Note that the procedure |
2676 | * semaphores before exiting. Note that the procedure to read these regs | 2874 | * to read these regs uses the address port and data port to read/write. |
2677 | * uses the address port and data port to read/write. | ||
2678 | **/ | 2875 | **/ |
2679 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | 2876 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
2680 | u16 *data, bool read) | 2877 | u16 *data, bool read) |
@@ -2682,20 +2879,12 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |||
2682 | s32 ret_val; | 2879 | s32 ret_val; |
2683 | u32 addr_reg = 0; | 2880 | u32 addr_reg = 0; |
2684 | u32 data_reg = 0; | 2881 | u32 data_reg = 0; |
2685 | u8 phy_acquired = 1; | ||
2686 | 2882 | ||
2687 | /* This takes care of the difference with desktop vs mobile phy */ | 2883 | /* This takes care of the difference with desktop vs mobile phy */ |
2688 | addr_reg = (hw->phy.type == e1000_phy_82578) ? | 2884 | addr_reg = (hw->phy.type == e1000_phy_82578) ? |
2689 | I82578_ADDR_REG : I82577_ADDR_REG; | 2885 | I82578_ADDR_REG : I82577_ADDR_REG; |
2690 | data_reg = addr_reg + 1; | 2886 | data_reg = addr_reg + 1; |
2691 | 2887 | ||
2692 | ret_val = hw->phy.ops.acquire_phy(hw); | ||
2693 | if (ret_val) { | ||
2694 | hw_dbg(hw, "Could not acquire PHY\n"); | ||
2695 | phy_acquired = 0; | ||
2696 | goto out; | ||
2697 | } | ||
2698 | |||
2699 | /* All operations in this function are phy address 2 */ | 2888 | /* All operations in this function are phy address 2 */ |
2700 | hw->phy.addr = 2; | 2889 | hw->phy.addr = 2; |
2701 | 2890 | ||
@@ -2718,8 +2907,6 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |||
2718 | } | 2907 | } |
2719 | 2908 | ||
2720 | out: | 2909 | out: |
2721 | if (phy_acquired == 1) | ||
2722 | hw->phy.ops.release_phy(hw); | ||
2723 | return ret_val; | 2910 | return ret_val; |
2724 | } | 2911 | } |
2725 | 2912 | ||