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-rw-r--r--drivers/net/e1000e/82571.c54
-rw-r--r--drivers/net/e1000e/e1000.h16
-rw-r--r--drivers/net/e1000e/es2lan.c26
-rw-r--r--drivers/net/e1000e/hw.h32
-rw-r--r--drivers/net/e1000e/ich8lan.c156
-rw-r--r--drivers/net/e1000e/lib.c6
-rw-r--r--drivers/net/e1000e/netdev.c4
-rw-r--r--drivers/net/e1000e/phy.c110
8 files changed, 201 insertions, 203 deletions
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index 680b7c703062..6fe1b3c73c16 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -1671,64 +1671,64 @@ static struct e1000_mac_operations e82571_mac_ops = {
1671}; 1671};
1672 1672
1673static struct e1000_phy_operations e82_phy_ops_igp = { 1673static struct e1000_phy_operations e82_phy_ops_igp = {
1674 .acquire_phy = e1000_get_hw_semaphore_82571, 1674 .acquire = e1000_get_hw_semaphore_82571,
1675 .check_reset_block = e1000e_check_reset_block_generic, 1675 .check_reset_block = e1000e_check_reset_block_generic,
1676 .commit_phy = NULL, 1676 .commit = NULL,
1677 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, 1677 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1678 .get_cfg_done = e1000_get_cfg_done_82571, 1678 .get_cfg_done = e1000_get_cfg_done_82571,
1679 .get_cable_length = e1000e_get_cable_length_igp_2, 1679 .get_cable_length = e1000e_get_cable_length_igp_2,
1680 .get_phy_info = e1000e_get_phy_info_igp, 1680 .get_info = e1000e_get_phy_info_igp,
1681 .read_phy_reg = e1000e_read_phy_reg_igp, 1681 .read_reg = e1000e_read_phy_reg_igp,
1682 .release_phy = e1000_put_hw_semaphore_82571, 1682 .release = e1000_put_hw_semaphore_82571,
1683 .reset_phy = e1000e_phy_hw_reset_generic, 1683 .reset = e1000e_phy_hw_reset_generic,
1684 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1684 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1685 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1685 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1686 .write_phy_reg = e1000e_write_phy_reg_igp, 1686 .write_reg = e1000e_write_phy_reg_igp,
1687 .cfg_on_link_up = NULL, 1687 .cfg_on_link_up = NULL,
1688}; 1688};
1689 1689
1690static struct e1000_phy_operations e82_phy_ops_m88 = { 1690static struct e1000_phy_operations e82_phy_ops_m88 = {
1691 .acquire_phy = e1000_get_hw_semaphore_82571, 1691 .acquire = e1000_get_hw_semaphore_82571,
1692 .check_reset_block = e1000e_check_reset_block_generic, 1692 .check_reset_block = e1000e_check_reset_block_generic,
1693 .commit_phy = e1000e_phy_sw_reset, 1693 .commit = e1000e_phy_sw_reset,
1694 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1694 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1695 .get_cfg_done = e1000e_get_cfg_done, 1695 .get_cfg_done = e1000e_get_cfg_done,
1696 .get_cable_length = e1000e_get_cable_length_m88, 1696 .get_cable_length = e1000e_get_cable_length_m88,
1697 .get_phy_info = e1000e_get_phy_info_m88, 1697 .get_info = e1000e_get_phy_info_m88,
1698 .read_phy_reg = e1000e_read_phy_reg_m88, 1698 .read_reg = e1000e_read_phy_reg_m88,
1699 .release_phy = e1000_put_hw_semaphore_82571, 1699 .release = e1000_put_hw_semaphore_82571,
1700 .reset_phy = e1000e_phy_hw_reset_generic, 1700 .reset = e1000e_phy_hw_reset_generic,
1701 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1701 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1702 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1702 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1703 .write_phy_reg = e1000e_write_phy_reg_m88, 1703 .write_reg = e1000e_write_phy_reg_m88,
1704 .cfg_on_link_up = NULL, 1704 .cfg_on_link_up = NULL,
1705}; 1705};
1706 1706
1707static struct e1000_phy_operations e82_phy_ops_bm = { 1707static struct e1000_phy_operations e82_phy_ops_bm = {
1708 .acquire_phy = e1000_get_hw_semaphore_82571, 1708 .acquire = e1000_get_hw_semaphore_82571,
1709 .check_reset_block = e1000e_check_reset_block_generic, 1709 .check_reset_block = e1000e_check_reset_block_generic,
1710 .commit_phy = e1000e_phy_sw_reset, 1710 .commit = e1000e_phy_sw_reset,
1711 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1711 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1712 .get_cfg_done = e1000e_get_cfg_done, 1712 .get_cfg_done = e1000e_get_cfg_done,
1713 .get_cable_length = e1000e_get_cable_length_m88, 1713 .get_cable_length = e1000e_get_cable_length_m88,
1714 .get_phy_info = e1000e_get_phy_info_m88, 1714 .get_info = e1000e_get_phy_info_m88,
1715 .read_phy_reg = e1000e_read_phy_reg_bm2, 1715 .read_reg = e1000e_read_phy_reg_bm2,
1716 .release_phy = e1000_put_hw_semaphore_82571, 1716 .release = e1000_put_hw_semaphore_82571,
1717 .reset_phy = e1000e_phy_hw_reset_generic, 1717 .reset = e1000e_phy_hw_reset_generic,
1718 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1718 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1719 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1719 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1720 .write_phy_reg = e1000e_write_phy_reg_bm2, 1720 .write_reg = e1000e_write_phy_reg_bm2,
1721 .cfg_on_link_up = NULL, 1721 .cfg_on_link_up = NULL,
1722}; 1722};
1723 1723
1724static struct e1000_nvm_operations e82571_nvm_ops = { 1724static struct e1000_nvm_operations e82571_nvm_ops = {
1725 .acquire_nvm = e1000_acquire_nvm_82571, 1725 .acquire = e1000_acquire_nvm_82571,
1726 .read_nvm = e1000e_read_nvm_eerd, 1726 .read = e1000e_read_nvm_eerd,
1727 .release_nvm = e1000_release_nvm_82571, 1727 .release = e1000_release_nvm_82571,
1728 .update_nvm = e1000_update_nvm_checksum_82571, 1728 .update = e1000_update_nvm_checksum_82571,
1729 .valid_led_default = e1000_valid_led_default_82571, 1729 .valid_led_default = e1000_valid_led_default_82571,
1730 .validate_nvm = e1000_validate_nvm_checksum_82571, 1730 .validate = e1000_validate_nvm_checksum_82571,
1731 .write_nvm = e1000_write_nvm_82571, 1731 .write = e1000_write_nvm_82571,
1732}; 1732};
1733 1733
1734struct e1000_info e1000_82571_info = { 1734struct e1000_info e1000_82571_info = {
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index dac00a023835..602598c8c186 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -584,7 +584,7 @@ extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
584 584
585static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 585static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
586{ 586{
587 return hw->phy.ops.reset_phy(hw); 587 return hw->phy.ops.reset(hw);
588} 588}
589 589
590static inline s32 e1000_check_reset_block(struct e1000_hw *hw) 590static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
@@ -594,12 +594,12 @@ static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
594 594
595static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 595static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
596{ 596{
597 return hw->phy.ops.read_phy_reg(hw, offset, data); 597 return hw->phy.ops.read_reg(hw, offset, data);
598} 598}
599 599
600static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 600static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
601{ 601{
602 return hw->phy.ops.write_phy_reg(hw, offset, data); 602 return hw->phy.ops.write_reg(hw, offset, data);
603} 603}
604 604
605static inline s32 e1000_get_cable_length(struct e1000_hw *hw) 605static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
@@ -619,27 +619,27 @@ extern s32 e1000e_read_mac_addr(struct e1000_hw *hw);
619 619
620static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 620static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
621{ 621{
622 return hw->nvm.ops.validate_nvm(hw); 622 return hw->nvm.ops.validate(hw);
623} 623}
624 624
625static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 625static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
626{ 626{
627 return hw->nvm.ops.update_nvm(hw); 627 return hw->nvm.ops.update(hw);
628} 628}
629 629
630static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 630static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
631{ 631{
632 return hw->nvm.ops.read_nvm(hw, offset, words, data); 632 return hw->nvm.ops.read(hw, offset, words, data);
633} 633}
634 634
635static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 635static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
636{ 636{
637 return hw->nvm.ops.write_nvm(hw, offset, words, data); 637 return hw->nvm.ops.write(hw, offset, words, data);
638} 638}
639 639
640static inline s32 e1000_get_phy_info(struct e1000_hw *hw) 640static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
641{ 641{
642 return hw->phy.ops.get_phy_info(hw); 642 return hw->phy.ops.get_info(hw);
643} 643}
644 644
645static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw) 645static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c
index f5601c5ff7af..d024e20bc6a3 100644
--- a/drivers/net/e1000e/es2lan.c
+++ b/drivers/net/e1000e/es2lan.c
@@ -1378,30 +1378,30 @@ static struct e1000_mac_operations es2_mac_ops = {
1378}; 1378};
1379 1379
1380static struct e1000_phy_operations es2_phy_ops = { 1380static struct e1000_phy_operations es2_phy_ops = {
1381 .acquire_phy = e1000_acquire_phy_80003es2lan, 1381 .acquire = e1000_acquire_phy_80003es2lan,
1382 .check_reset_block = e1000e_check_reset_block_generic, 1382 .check_reset_block = e1000e_check_reset_block_generic,
1383 .commit_phy = e1000e_phy_sw_reset, 1383 .commit = e1000e_phy_sw_reset,
1384 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, 1384 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1385 .get_cfg_done = e1000_get_cfg_done_80003es2lan, 1385 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1386 .get_cable_length = e1000_get_cable_length_80003es2lan, 1386 .get_cable_length = e1000_get_cable_length_80003es2lan,
1387 .get_phy_info = e1000e_get_phy_info_m88, 1387 .get_info = e1000e_get_phy_info_m88,
1388 .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan, 1388 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1389 .release_phy = e1000_release_phy_80003es2lan, 1389 .release = e1000_release_phy_80003es2lan,
1390 .reset_phy = e1000e_phy_hw_reset_generic, 1390 .reset = e1000e_phy_hw_reset_generic,
1391 .set_d0_lplu_state = NULL, 1391 .set_d0_lplu_state = NULL,
1392 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1392 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1393 .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan, 1393 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1394 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, 1394 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1395}; 1395};
1396 1396
1397static struct e1000_nvm_operations es2_nvm_ops = { 1397static struct e1000_nvm_operations es2_nvm_ops = {
1398 .acquire_nvm = e1000_acquire_nvm_80003es2lan, 1398 .acquire = e1000_acquire_nvm_80003es2lan,
1399 .read_nvm = e1000e_read_nvm_eerd, 1399 .read = e1000e_read_nvm_eerd,
1400 .release_nvm = e1000_release_nvm_80003es2lan, 1400 .release = e1000_release_nvm_80003es2lan,
1401 .update_nvm = e1000e_update_nvm_checksum_generic, 1401 .update = e1000e_update_nvm_checksum_generic,
1402 .valid_led_default = e1000e_valid_led_default, 1402 .valid_led_default = e1000e_valid_led_default,
1403 .validate_nvm = e1000e_validate_nvm_checksum_generic, 1403 .validate = e1000e_validate_nvm_checksum_generic,
1404 .write_nvm = e1000_write_nvm_80003es2lan, 1404 .write = e1000_write_nvm_80003es2lan,
1405}; 1405};
1406 1406
1407struct e1000_info e1000_es2_info = { 1407struct e1000_info e1000_es2_info = {
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index 44808b053fcc..842d8e7e9c27 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -755,34 +755,34 @@ struct e1000_mac_operations {
755 755
756/* Function pointers for the PHY. */ 756/* Function pointers for the PHY. */
757struct e1000_phy_operations { 757struct e1000_phy_operations {
758 s32 (*acquire_phy)(struct e1000_hw *); 758 s32 (*acquire)(struct e1000_hw *);
759 s32 (*cfg_on_link_up)(struct e1000_hw *);
759 s32 (*check_polarity)(struct e1000_hw *); 760 s32 (*check_polarity)(struct e1000_hw *);
760 s32 (*check_reset_block)(struct e1000_hw *); 761 s32 (*check_reset_block)(struct e1000_hw *);
761 s32 (*commit_phy)(struct e1000_hw *); 762 s32 (*commit)(struct e1000_hw *);
762 s32 (*force_speed_duplex)(struct e1000_hw *); 763 s32 (*force_speed_duplex)(struct e1000_hw *);
763 s32 (*get_cfg_done)(struct e1000_hw *hw); 764 s32 (*get_cfg_done)(struct e1000_hw *hw);
764 s32 (*get_cable_length)(struct e1000_hw *); 765 s32 (*get_cable_length)(struct e1000_hw *);
765 s32 (*get_phy_info)(struct e1000_hw *); 766 s32 (*get_info)(struct e1000_hw *);
766 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); 767 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
767 s32 (*read_phy_reg_locked)(struct e1000_hw *, u32, u16 *); 768 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
768 void (*release_phy)(struct e1000_hw *); 769 void (*release)(struct e1000_hw *);
769 s32 (*reset_phy)(struct e1000_hw *); 770 s32 (*reset)(struct e1000_hw *);
770 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 771 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
771 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 772 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
772 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); 773 s32 (*write_reg)(struct e1000_hw *, u32, u16);
773 s32 (*write_phy_reg_locked)(struct e1000_hw *, u32, u16); 774 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
774 s32 (*cfg_on_link_up)(struct e1000_hw *);
775}; 775};
776 776
777/* Function pointers for the NVM. */ 777/* Function pointers for the NVM. */
778struct e1000_nvm_operations { 778struct e1000_nvm_operations {
779 s32 (*acquire_nvm)(struct e1000_hw *); 779 s32 (*acquire)(struct e1000_hw *);
780 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *); 780 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
781 void (*release_nvm)(struct e1000_hw *); 781 void (*release)(struct e1000_hw *);
782 s32 (*update_nvm)(struct e1000_hw *); 782 s32 (*update)(struct e1000_hw *);
783 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 783 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
784 s32 (*validate_nvm)(struct e1000_hw *); 784 s32 (*validate)(struct e1000_hw *);
785 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *); 785 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
786}; 786};
787 787
788struct e1000_mac_info { 788struct e1000_mac_info {
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 101a2714467e..dd94fc2e4b82 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -260,12 +260,12 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
260 phy->reset_delay_us = 100; 260 phy->reset_delay_us = 100;
261 261
262 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; 262 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
263 phy->ops.read_phy_reg = e1000_read_phy_reg_hv; 263 phy->ops.read_reg = e1000_read_phy_reg_hv;
264 phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked; 264 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
265 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 265 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
266 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 266 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
267 phy->ops.write_phy_reg = e1000_write_phy_reg_hv; 267 phy->ops.write_reg = e1000_write_phy_reg_hv;
268 phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked; 268 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
269 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 269 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
270 270
271 phy->id = e1000_phy_unknown; 271 phy->id = e1000_phy_unknown;
@@ -277,8 +277,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
277 phy->ops.force_speed_duplex = 277 phy->ops.force_speed_duplex =
278 e1000_phy_force_speed_duplex_82577; 278 e1000_phy_force_speed_duplex_82577;
279 phy->ops.get_cable_length = e1000_get_cable_length_82577; 279 phy->ops.get_cable_length = e1000_get_cable_length_82577;
280 phy->ops.get_phy_info = e1000_get_phy_info_82577; 280 phy->ops.get_info = e1000_get_phy_info_82577;
281 phy->ops.commit_phy = e1000e_phy_sw_reset; 281 phy->ops.commit = e1000e_phy_sw_reset;
282 } 282 }
283 283
284 return ret_val; 284 return ret_val;
@@ -305,8 +305,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
305 */ 305 */
306 ret_val = e1000e_determine_phy_address(hw); 306 ret_val = e1000e_determine_phy_address(hw);
307 if (ret_val) { 307 if (ret_val) {
308 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; 308 phy->ops.write_reg = e1000e_write_phy_reg_bm;
309 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; 309 phy->ops.read_reg = e1000e_read_phy_reg_bm;
310 ret_val = e1000e_determine_phy_address(hw); 310 ret_val = e1000e_determine_phy_address(hw);
311 if (ret_val) 311 if (ret_val)
312 return ret_val; 312 return ret_val;
@@ -326,8 +326,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
326 case IGP03E1000_E_PHY_ID: 326 case IGP03E1000_E_PHY_ID:
327 phy->type = e1000_phy_igp_3; 327 phy->type = e1000_phy_igp_3;
328 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 328 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
329 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked; 329 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
330 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked; 330 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
331 break; 331 break;
332 case IFE_E_PHY_ID: 332 case IFE_E_PHY_ID:
333 case IFE_PLUS_E_PHY_ID: 333 case IFE_PLUS_E_PHY_ID:
@@ -338,9 +338,9 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
338 case BME1000_E_PHY_ID: 338 case BME1000_E_PHY_ID:
339 phy->type = e1000_phy_bm; 339 phy->type = e1000_phy_bm;
340 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 340 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
341 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; 341 phy->ops.read_reg = e1000e_read_phy_reg_bm;
342 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; 342 phy->ops.write_reg = e1000e_write_phy_reg_bm;
343 hw->phy.ops.commit_phy = e1000e_phy_sw_reset; 343 phy->ops.commit = e1000e_phy_sw_reset;
344 break; 344 break;
345 default: 345 default:
346 return -E1000_ERR_PHY; 346 return -E1000_ERR_PHY;
@@ -816,7 +816,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
816 s32 ret_val; 816 s32 ret_val;
817 u16 word_addr, reg_data, reg_addr, phy_page = 0; 817 u16 word_addr, reg_data, reg_addr, phy_page = 0;
818 818
819 ret_val = hw->phy.ops.acquire_phy(hw); 819 ret_val = hw->phy.ops.acquire(hw);
820 if (ret_val) 820 if (ret_val)
821 return ret_val; 821 return ret_val;
822 822
@@ -912,7 +912,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
912 reg_addr &= PHY_REG_MASK; 912 reg_addr &= PHY_REG_MASK;
913 reg_addr |= phy_page; 913 reg_addr |= phy_page;
914 914
915 ret_val = phy->ops.write_phy_reg_locked(hw, 915 ret_val = phy->ops.write_reg_locked(hw,
916 (u32)reg_addr, 916 (u32)reg_addr,
917 reg_data); 917 reg_data);
918 if (ret_val) 918 if (ret_val)
@@ -921,7 +921,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
921 } 921 }
922 922
923out: 923out:
924 hw->phy.ops.release_phy(hw); 924 hw->phy.ops.release(hw);
925 return ret_val; 925 return ret_val;
926} 926}
927 927
@@ -945,15 +945,14 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
945 goto out; 945 goto out;
946 946
947 /* Wrap the whole flow with the sw flag */ 947 /* Wrap the whole flow with the sw flag */
948 ret_val = hw->phy.ops.acquire_phy(hw); 948 ret_val = hw->phy.ops.acquire(hw);
949 if (ret_val) 949 if (ret_val)
950 goto out; 950 goto out;
951 951
952 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 952 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
953 if (link) { 953 if (link) {
954 if (hw->phy.type == e1000_phy_82578) { 954 if (hw->phy.type == e1000_phy_82578) {
955 ret_val = hw->phy.ops.read_phy_reg_locked(hw, 955 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
956 BM_CS_STATUS,
957 &status_reg); 956 &status_reg);
958 if (ret_val) 957 if (ret_val)
959 goto release; 958 goto release;
@@ -969,8 +968,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
969 } 968 }
970 969
971 if (hw->phy.type == e1000_phy_82577) { 970 if (hw->phy.type == e1000_phy_82577) {
972 ret_val = hw->phy.ops.read_phy_reg_locked(hw, 971 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
973 HV_M_STATUS,
974 &status_reg); 972 &status_reg);
975 if (ret_val) 973 if (ret_val)
976 goto release; 974 goto release;
@@ -986,14 +984,14 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
986 } 984 }
987 985
988 /* Link stall fix for link up */ 986 /* Link stall fix for link up */
989 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19), 987 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
990 0x0100); 988 0x0100);
991 if (ret_val) 989 if (ret_val)
992 goto release; 990 goto release;
993 991
994 } else { 992 } else {
995 /* Link stall fix for link down */ 993 /* Link stall fix for link down */
996 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19), 994 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
997 0x4100); 995 0x4100);
998 if (ret_val) 996 if (ret_val)
999 goto release; 997 goto release;
@@ -1002,7 +1000,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1002 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1000 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1003 1001
1004release: 1002release:
1005 hw->phy.ops.release_phy(hw); 1003 hw->phy.ops.release(hw);
1006out: 1004out:
1007 return ret_val; 1005 return ret_val;
1008} 1006}
@@ -1078,7 +1076,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1078 if (hw->mac.type != e1000_pchlan) 1076 if (hw->mac.type != e1000_pchlan)
1079 return ret_val; 1077 return ret_val;
1080 1078
1081 ret_val = hw->phy.ops.acquire_phy(hw); 1079 ret_val = hw->phy.ops.acquire(hw);
1082 if (ret_val) 1080 if (ret_val)
1083 return ret_val; 1081 return ret_val;
1084 1082
@@ -1092,7 +1090,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1092 1090
1093 mac_reg = er32(PHY_CTRL); 1091 mac_reg = er32(PHY_CTRL);
1094 1092
1095 ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg); 1093 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1096 if (ret_val) 1094 if (ret_val)
1097 goto out; 1095 goto out;
1098 1096
@@ -1113,10 +1111,10 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1113 } 1111 }
1114 /* Restart auto-neg to activate the bits */ 1112 /* Restart auto-neg to activate the bits */
1115 oem_reg |= HV_OEM_BITS_RESTART_AN; 1113 oem_reg |= HV_OEM_BITS_RESTART_AN;
1116 ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg); 1114 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1117 1115
1118out: 1116out:
1119 hw->phy.ops.release_phy(hw); 1117 hw->phy.ops.release(hw);
1120 1118
1121 return ret_val; 1119 return ret_val;
1122} 1120}
@@ -1159,7 +1157,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1159 } 1157 }
1160 1158
1161 /* Select page 0 */ 1159 /* Select page 0 */
1162 ret_val = hw->phy.ops.acquire_phy(hw); 1160 ret_val = hw->phy.ops.acquire(hw);
1163 if (ret_val) 1161 if (ret_val)
1164 return ret_val; 1162 return ret_val;
1165 1163
@@ -1167,7 +1165,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1167 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1165 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1168 if (ret_val) 1166 if (ret_val)
1169 goto out; 1167 goto out;
1170 hw->phy.ops.release_phy(hw); 1168 hw->phy.ops.release(hw);
1171 1169
1172 /* 1170 /*
1173 * Configure the K1 Si workaround during phy reset assuming there is 1171 * Configure the K1 Si workaround during phy reset assuming there is
@@ -1667,7 +1665,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1667 goto out; 1665 goto out;
1668 } 1666 }
1669 1667
1670 nvm->ops.acquire_nvm(hw); 1668 nvm->ops.acquire(hw);
1671 1669
1672 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1670 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1673 if (ret_val) { 1671 if (ret_val) {
@@ -1693,7 +1691,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1693 } 1691 }
1694 } 1692 }
1695 1693
1696 nvm->ops.release_nvm(hw); 1694 nvm->ops.release(hw);
1697 1695
1698out: 1696out:
1699 if (ret_val) 1697 if (ret_val)
@@ -1951,14 +1949,14 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1951 return -E1000_ERR_NVM; 1949 return -E1000_ERR_NVM;
1952 } 1950 }
1953 1951
1954 nvm->ops.acquire_nvm(hw); 1952 nvm->ops.acquire(hw);
1955 1953
1956 for (i = 0; i < words; i++) { 1954 for (i = 0; i < words; i++) {
1957 dev_spec->shadow_ram[offset+i].modified = 1; 1955 dev_spec->shadow_ram[offset+i].modified = 1;
1958 dev_spec->shadow_ram[offset+i].value = data[i]; 1956 dev_spec->shadow_ram[offset+i].value = data[i];
1959 } 1957 }
1960 1958
1961 nvm->ops.release_nvm(hw); 1959 nvm->ops.release(hw);
1962 1960
1963 return 0; 1961 return 0;
1964} 1962}
@@ -1989,7 +1987,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1989 if (nvm->type != e1000_nvm_flash_sw) 1987 if (nvm->type != e1000_nvm_flash_sw)
1990 goto out; 1988 goto out;
1991 1989
1992 nvm->ops.acquire_nvm(hw); 1990 nvm->ops.acquire(hw);
1993 1991
1994 /* 1992 /*
1995 * We're writing to the opposite bank so if we're on bank 1, 1993 * We're writing to the opposite bank so if we're on bank 1,
@@ -2007,7 +2005,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2007 old_bank_offset = 0; 2005 old_bank_offset = 0;
2008 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 2006 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2009 if (ret_val) { 2007 if (ret_val) {
2010 nvm->ops.release_nvm(hw); 2008 nvm->ops.release(hw);
2011 goto out; 2009 goto out;
2012 } 2010 }
2013 } else { 2011 } else {
@@ -2015,7 +2013,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2015 new_bank_offset = 0; 2013 new_bank_offset = 0;
2016 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 2014 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2017 if (ret_val) { 2015 if (ret_val) {
2018 nvm->ops.release_nvm(hw); 2016 nvm->ops.release(hw);
2019 goto out; 2017 goto out;
2020 } 2018 }
2021 } 2019 }
@@ -2073,7 +2071,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2073 if (ret_val) { 2071 if (ret_val) {
2074 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 2072 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2075 e_dbg("Flash commit failed.\n"); 2073 e_dbg("Flash commit failed.\n");
2076 nvm->ops.release_nvm(hw); 2074 nvm->ops.release(hw);
2077 goto out; 2075 goto out;
2078 } 2076 }
2079 2077
@@ -2086,7 +2084,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2086 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 2084 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2087 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 2085 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2088 if (ret_val) { 2086 if (ret_val) {
2089 nvm->ops.release_nvm(hw); 2087 nvm->ops.release(hw);
2090 goto out; 2088 goto out;
2091 } 2089 }
2092 data &= 0xBFFF; 2090 data &= 0xBFFF;
@@ -2094,7 +2092,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2094 act_offset * 2 + 1, 2092 act_offset * 2 + 1,
2095 (u8)(data >> 8)); 2093 (u8)(data >> 8));
2096 if (ret_val) { 2094 if (ret_val) {
2097 nvm->ops.release_nvm(hw); 2095 nvm->ops.release(hw);
2098 goto out; 2096 goto out;
2099 } 2097 }
2100 2098
@@ -2107,7 +2105,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2107 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 2105 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2108 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 2106 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2109 if (ret_val) { 2107 if (ret_val) {
2110 nvm->ops.release_nvm(hw); 2108 nvm->ops.release(hw);
2111 goto out; 2109 goto out;
2112 } 2110 }
2113 2111
@@ -2117,7 +2115,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2117 dev_spec->shadow_ram[i].value = 0xFFFF; 2115 dev_spec->shadow_ram[i].value = 0xFFFF;
2118 } 2116 }
2119 2117
2120 nvm->ops.release_nvm(hw); 2118 nvm->ops.release(hw);
2121 2119
2122 /* 2120 /*
2123 * Reload the EEPROM, or else modifications will not appear 2121 * Reload the EEPROM, or else modifications will not appear
@@ -2186,7 +2184,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2186 union ich8_hws_flash_status hsfsts; 2184 union ich8_hws_flash_status hsfsts;
2187 u32 gfpreg; 2185 u32 gfpreg;
2188 2186
2189 nvm->ops.acquire_nvm(hw); 2187 nvm->ops.acquire(hw);
2190 2188
2191 gfpreg = er32flash(ICH_FLASH_GFPREG); 2189 gfpreg = er32flash(ICH_FLASH_GFPREG);
2192 2190
@@ -2207,7 +2205,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2207 hsfsts.hsf_status.flockdn = true; 2205 hsfsts.hsf_status.flockdn = true;
2208 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2206 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2209 2207
2210 nvm->ops.release_nvm(hw); 2208 nvm->ops.release(hw);
2211} 2209}
2212 2210
2213/** 2211/**
@@ -2743,7 +2741,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2743 * Reset the phy after disabling host wakeup to reset the Rx buffer. 2741 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2744 */ 2742 */
2745 if (hw->phy.type == e1000_phy_82578) { 2743 if (hw->phy.type == e1000_phy_82578) {
2746 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i); 2744 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2747 ret_val = e1000_phy_hw_reset_ich8lan(hw); 2745 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2748 if (ret_val) 2746 if (ret_val)
2749 return ret_val; 2747 return ret_val;
@@ -2890,7 +2888,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2890 ew32(FCTTV, hw->fc.pause_time); 2888 ew32(FCTTV, hw->fc.pause_time);
2891 if ((hw->phy.type == e1000_phy_82578) || 2889 if ((hw->phy.type == e1000_phy_82578) ||
2892 (hw->phy.type == e1000_phy_82577)) { 2890 (hw->phy.type == e1000_phy_82577)) {
2893 ret_val = hw->phy.ops.write_phy_reg(hw, 2891 ret_val = hw->phy.ops.write_reg(hw,
2894 PHY_REG(BM_PORT_CTRL_PAGE, 27), 2892 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2895 hw->fc.pause_time); 2893 hw->fc.pause_time);
2896 if (ret_val) 2894 if (ret_val)
@@ -2953,7 +2951,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2953 return ret_val; 2951 return ret_val;
2954 break; 2952 break;
2955 case e1000_phy_ife: 2953 case e1000_phy_ife:
2956 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, 2954 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2957 &reg_data); 2955 &reg_data);
2958 if (ret_val) 2956 if (ret_val)
2959 return ret_val; 2957 return ret_val;
@@ -2972,7 +2970,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2972 reg_data |= IFE_PMC_AUTO_MDIX; 2970 reg_data |= IFE_PMC_AUTO_MDIX;
2973 break; 2971 break;
2974 } 2972 }
2975 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, 2973 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2976 reg_data); 2974 reg_data);
2977 if (ret_val) 2975 if (ret_val)
2978 return ret_val; 2976 return ret_val;
@@ -3274,7 +3272,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3274 **/ 3272 **/
3275static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3273static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3276{ 3274{
3277 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, 3275 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3278 (u16)hw->mac.ledctl_mode1); 3276 (u16)hw->mac.ledctl_mode1);
3279} 3277}
3280 3278
@@ -3286,7 +3284,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3286 **/ 3284 **/
3287static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 3285static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3288{ 3286{
3289 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, 3287 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3290 (u16)hw->mac.ledctl_default); 3288 (u16)hw->mac.ledctl_default);
3291} 3289}
3292 3290
@@ -3318,7 +3316,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3318 } 3316 }
3319 } 3317 }
3320 3318
3321 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); 3319 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3322} 3320}
3323 3321
3324/** 3322/**
@@ -3349,7 +3347,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3349 } 3347 }
3350 } 3348 }
3351 3349
3352 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); 3350 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3353} 3351}
3354 3352
3355/** 3353/**
@@ -3426,20 +3424,20 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3426 /* Clear PHY statistics registers */ 3424 /* Clear PHY statistics registers */
3427 if ((hw->phy.type == e1000_phy_82578) || 3425 if ((hw->phy.type == e1000_phy_82578) ||
3428 (hw->phy.type == e1000_phy_82577)) { 3426 (hw->phy.type == e1000_phy_82577)) {
3429 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 3427 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3430 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 3428 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3431 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 3429 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3432 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 3430 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3433 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 3431 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3434 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 3432 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3435 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 3433 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3436 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 3434 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3437 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 3435 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3438 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 3436 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3439 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data); 3437 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3440 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data); 3438 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3441 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 3439 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3442 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 3440 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3443 } 3441 }
3444} 3442}
3445 3443
@@ -3462,29 +3460,29 @@ static struct e1000_mac_operations ich8_mac_ops = {
3462}; 3460};
3463 3461
3464static struct e1000_phy_operations ich8_phy_ops = { 3462static struct e1000_phy_operations ich8_phy_ops = {
3465 .acquire_phy = e1000_acquire_swflag_ich8lan, 3463 .acquire = e1000_acquire_swflag_ich8lan,
3466 .check_reset_block = e1000_check_reset_block_ich8lan, 3464 .check_reset_block = e1000_check_reset_block_ich8lan,
3467 .commit_phy = NULL, 3465 .commit = NULL,
3468 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, 3466 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
3469 .get_cfg_done = e1000_get_cfg_done_ich8lan, 3467 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3470 .get_cable_length = e1000e_get_cable_length_igp_2, 3468 .get_cable_length = e1000e_get_cable_length_igp_2,
3471 .get_phy_info = e1000_get_phy_info_ich8lan, 3469 .get_info = e1000_get_phy_info_ich8lan,
3472 .read_phy_reg = e1000e_read_phy_reg_igp, 3470 .read_reg = e1000e_read_phy_reg_igp,
3473 .release_phy = e1000_release_swflag_ich8lan, 3471 .release = e1000_release_swflag_ich8lan,
3474 .reset_phy = e1000_phy_hw_reset_ich8lan, 3472 .reset = e1000_phy_hw_reset_ich8lan,
3475 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 3473 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3476 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 3474 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3477 .write_phy_reg = e1000e_write_phy_reg_igp, 3475 .write_reg = e1000e_write_phy_reg_igp,
3478}; 3476};
3479 3477
3480static struct e1000_nvm_operations ich8_nvm_ops = { 3478static struct e1000_nvm_operations ich8_nvm_ops = {
3481 .acquire_nvm = e1000_acquire_nvm_ich8lan, 3479 .acquire = e1000_acquire_nvm_ich8lan,
3482 .read_nvm = e1000_read_nvm_ich8lan, 3480 .read = e1000_read_nvm_ich8lan,
3483 .release_nvm = e1000_release_nvm_ich8lan, 3481 .release = e1000_release_nvm_ich8lan,
3484 .update_nvm = e1000_update_nvm_checksum_ich8lan, 3482 .update = e1000_update_nvm_checksum_ich8lan,
3485 .valid_led_default = e1000_valid_led_default_ich8lan, 3483 .valid_led_default = e1000_valid_led_default_ich8lan,
3486 .validate_nvm = e1000_validate_nvm_checksum_ich8lan, 3484 .validate = e1000_validate_nvm_checksum_ich8lan,
3487 .write_nvm = e1000_write_nvm_ich8lan, 3485 .write = e1000_write_nvm_ich8lan,
3488}; 3486};
3489 3487
3490struct e1000_info e1000_ich8_info = { 3488struct e1000_info e1000_ich8_info = {
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c
index fa31c51e5642..f664fc03aa2b 100644
--- a/drivers/net/e1000e/lib.c
+++ b/drivers/net/e1000e/lib.c
@@ -1985,7 +1985,7 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1985 return -E1000_ERR_NVM; 1985 return -E1000_ERR_NVM;
1986 } 1986 }
1987 1987
1988 ret_val = nvm->ops.acquire_nvm(hw); 1988 ret_val = nvm->ops.acquire(hw);
1989 if (ret_val) 1989 if (ret_val)
1990 return ret_val; 1990 return ret_val;
1991 1991
@@ -1996,7 +1996,7 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1996 1996
1997 ret_val = e1000_ready_nvm_eeprom(hw); 1997 ret_val = e1000_ready_nvm_eeprom(hw);
1998 if (ret_val) { 1998 if (ret_val) {
1999 nvm->ops.release_nvm(hw); 1999 nvm->ops.release(hw);
2000 return ret_val; 2000 return ret_val;
2001 } 2001 }
2002 2002
@@ -2035,7 +2035,7 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2035 } 2035 }
2036 2036
2037 msleep(10); 2037 msleep(10);
2038 nvm->ops.release_nvm(hw); 2038 nvm->ops.release(hw);
2039 return 0; 2039 return 0;
2040} 2040}
2041 2041
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 0b5352307f16..6eb96935f8aa 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -4419,7 +4419,7 @@ static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
4419 e1e_wphy(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 4419 e1e_wphy(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
4420 4420
4421 /* activate PHY wakeup */ 4421 /* activate PHY wakeup */
4422 retval = hw->phy.ops.acquire_phy(hw); 4422 retval = hw->phy.ops.acquire(hw);
4423 if (retval) { 4423 if (retval) {
4424 e_err("Could not acquire PHY\n"); 4424 e_err("Could not acquire PHY\n");
4425 return retval; 4425 return retval;
@@ -4436,7 +4436,7 @@ static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
4436 if (retval) 4436 if (retval)
4437 e_err("Could not set PHY Host Wakeup bit\n"); 4437 e_err("Could not set PHY Host Wakeup bit\n");
4438out: 4438out:
4439 hw->phy.ops.release_phy(hw); 4439 hw->phy.ops.release(hw);
4440 4440
4441 return retval; 4441 return retval;
4442} 4442}
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index cff1df204031..765dc389561b 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -131,7 +131,7 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
131 u16 phy_id; 131 u16 phy_id;
132 u16 retry_count = 0; 132 u16 retry_count = 0;
133 133
134 if (!(phy->ops.read_phy_reg)) 134 if (!(phy->ops.read_reg))
135 goto out; 135 goto out;
136 136
137 while (retry_count < 2) { 137 while (retry_count < 2) {
@@ -157,24 +157,24 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
157 * MDIC mode. No harm in trying again in this case since 157 * MDIC mode. No harm in trying again in this case since
158 * the PHY ID is unknown at this point anyway 158 * the PHY ID is unknown at this point anyway
159 */ 159 */
160 ret_val = phy->ops.acquire_phy(hw); 160 ret_val = phy->ops.acquire(hw);
161 if (ret_val) 161 if (ret_val)
162 goto out; 162 goto out;
163 ret_val = e1000_set_mdio_slow_mode_hv(hw, true); 163 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
164 if (ret_val) 164 if (ret_val)
165 goto out; 165 goto out;
166 phy->ops.release_phy(hw); 166 phy->ops.release(hw);
167 167
168 retry_count++; 168 retry_count++;
169 } 169 }
170out: 170out:
171 /* Revert to MDIO fast mode, if applicable */ 171 /* Revert to MDIO fast mode, if applicable */
172 if (retry_count) { 172 if (retry_count) {
173 ret_val = phy->ops.acquire_phy(hw); 173 ret_val = phy->ops.acquire(hw);
174 if (ret_val) 174 if (ret_val)
175 return ret_val; 175 return ret_val;
176 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 176 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
177 phy->ops.release_phy(hw); 177 phy->ops.release(hw);
178 } 178 }
179 179
180 return ret_val; 180 return ret_val;
@@ -318,14 +318,14 @@ s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
318{ 318{
319 s32 ret_val; 319 s32 ret_val;
320 320
321 ret_val = hw->phy.ops.acquire_phy(hw); 321 ret_val = hw->phy.ops.acquire(hw);
322 if (ret_val) 322 if (ret_val)
323 return ret_val; 323 return ret_val;
324 324
325 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 325 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
326 data); 326 data);
327 327
328 hw->phy.ops.release_phy(hw); 328 hw->phy.ops.release(hw);
329 329
330 return ret_val; 330 return ret_val;
331} 331}
@@ -343,14 +343,14 @@ s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
343{ 343{
344 s32 ret_val; 344 s32 ret_val;
345 345
346 ret_val = hw->phy.ops.acquire_phy(hw); 346 ret_val = hw->phy.ops.acquire(hw);
347 if (ret_val) 347 if (ret_val)
348 return ret_val; 348 return ret_val;
349 349
350 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 350 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
351 data); 351 data);
352 352
353 hw->phy.ops.release_phy(hw); 353 hw->phy.ops.release(hw);
354 354
355 return ret_val; 355 return ret_val;
356} 356}
@@ -372,10 +372,10 @@ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
372 s32 ret_val = 0; 372 s32 ret_val = 0;
373 373
374 if (!locked) { 374 if (!locked) {
375 if (!(hw->phy.ops.acquire_phy)) 375 if (!(hw->phy.ops.acquire))
376 goto out; 376 goto out;
377 377
378 ret_val = hw->phy.ops.acquire_phy(hw); 378 ret_val = hw->phy.ops.acquire(hw);
379 if (ret_val) 379 if (ret_val)
380 goto out; 380 goto out;
381 } 381 }
@@ -393,7 +393,7 @@ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
393 393
394release: 394release:
395 if (!locked) 395 if (!locked)
396 hw->phy.ops.release_phy(hw); 396 hw->phy.ops.release(hw);
397out: 397out:
398 return ret_val; 398 return ret_val;
399} 399}
@@ -443,10 +443,10 @@ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
443 s32 ret_val = 0; 443 s32 ret_val = 0;
444 444
445 if (!locked) { 445 if (!locked) {
446 if (!(hw->phy.ops.acquire_phy)) 446 if (!(hw->phy.ops.acquire))
447 goto out; 447 goto out;
448 448
449 ret_val = hw->phy.ops.acquire_phy(hw); 449 ret_val = hw->phy.ops.acquire(hw);
450 if (ret_val) 450 if (ret_val)
451 goto out; 451 goto out;
452 } 452 }
@@ -464,7 +464,7 @@ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
464 464
465release: 465release:
466 if (!locked) 466 if (!locked)
467 hw->phy.ops.release_phy(hw); 467 hw->phy.ops.release(hw);
468 468
469out: 469out:
470 return ret_val; 470 return ret_val;
@@ -516,10 +516,10 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
516 s32 ret_val = 0; 516 s32 ret_val = 0;
517 517
518 if (!locked) { 518 if (!locked) {
519 if (!(hw->phy.ops.acquire_phy)) 519 if (!(hw->phy.ops.acquire))
520 goto out; 520 goto out;
521 521
522 ret_val = hw->phy.ops.acquire_phy(hw); 522 ret_val = hw->phy.ops.acquire(hw);
523 if (ret_val) 523 if (ret_val)
524 goto out; 524 goto out;
525 } 525 }
@@ -534,7 +534,7 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
534 *data = (u16)kmrnctrlsta; 534 *data = (u16)kmrnctrlsta;
535 535
536 if (!locked) 536 if (!locked)
537 hw->phy.ops.release_phy(hw); 537 hw->phy.ops.release(hw);
538 538
539out: 539out:
540 return ret_val; 540 return ret_val;
@@ -588,10 +588,10 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
588 s32 ret_val = 0; 588 s32 ret_val = 0;
589 589
590 if (!locked) { 590 if (!locked) {
591 if (!(hw->phy.ops.acquire_phy)) 591 if (!(hw->phy.ops.acquire))
592 goto out; 592 goto out;
593 593
594 ret_val = hw->phy.ops.acquire_phy(hw); 594 ret_val = hw->phy.ops.acquire(hw);
595 if (ret_val) 595 if (ret_val)
596 goto out; 596 goto out;
597 } 597 }
@@ -603,7 +603,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
603 udelay(2); 603 udelay(2);
604 604
605 if (!locked) 605 if (!locked)
606 hw->phy.ops.release_phy(hw); 606 hw->phy.ops.release(hw);
607 607
608out: 608out:
609 return ret_val; 609 return ret_val;
@@ -650,7 +650,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
650 u16 phy_data; 650 u16 phy_data;
651 651
652 /* Enable CRS on TX. This must be set for half-duplex operation. */ 652 /* Enable CRS on TX. This must be set for half-duplex operation. */
653 ret_val = phy->ops.read_phy_reg(hw, I82577_CFG_REG, &phy_data); 653 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
654 if (ret_val) 654 if (ret_val)
655 goto out; 655 goto out;
656 656
@@ -659,16 +659,16 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
659 /* Enable downshift */ 659 /* Enable downshift */
660 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 660 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
661 661
662 ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data); 662 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
663 if (ret_val) 663 if (ret_val)
664 goto out; 664 goto out;
665 665
666 /* Set number of link attempts before downshift */ 666 /* Set number of link attempts before downshift */
667 ret_val = phy->ops.read_phy_reg(hw, I82577_CTRL_REG, &phy_data); 667 ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data);
668 if (ret_val) 668 if (ret_val)
669 goto out; 669 goto out;
670 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; 670 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
671 ret_val = phy->ops.write_phy_reg(hw, I82577_CTRL_REG, phy_data); 671 ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data);
672 672
673out: 673out:
674 return ret_val; 674 return ret_val;
@@ -791,7 +791,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
791 } 791 }
792 792
793 if (phy->type == e1000_phy_82578) { 793 if (phy->type == e1000_phy_82578) {
794 ret_val = phy->ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 794 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
795 &phy_data); 795 &phy_data);
796 if (ret_val) 796 if (ret_val)
797 return ret_val; 797 return ret_val;
@@ -799,7 +799,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
799 /* 82578 PHY - set the downshift count to 1x. */ 799 /* 82578 PHY - set the downshift count to 1x. */
800 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 800 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
801 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 801 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
802 ret_val = phy->ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 802 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
803 phy_data); 803 phy_data);
804 if (ret_val) 804 if (ret_val)
805 return ret_val; 805 return ret_val;
@@ -1990,7 +1990,7 @@ s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1990 if (ret_val) 1990 if (ret_val)
1991 return 0; 1991 return 0;
1992 1992
1993 ret_val = phy->ops.acquire_phy(hw); 1993 ret_val = phy->ops.acquire(hw);
1994 if (ret_val) 1994 if (ret_val)
1995 return ret_val; 1995 return ret_val;
1996 1996
@@ -2005,7 +2005,7 @@ s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2005 2005
2006 udelay(150); 2006 udelay(150);
2007 2007
2008 phy->ops.release_phy(hw); 2008 phy->ops.release(hw);
2009 2009
2010 return e1000_get_phy_cfg_done(hw); 2010 return e1000_get_phy_cfg_done(hw);
2011} 2011}
@@ -2256,7 +2256,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2256 u32 page = offset >> IGP_PAGE_SHIFT; 2256 u32 page = offset >> IGP_PAGE_SHIFT;
2257 u32 page_shift = 0; 2257 u32 page_shift = 0;
2258 2258
2259 ret_val = hw->phy.ops.acquire_phy(hw); 2259 ret_val = hw->phy.ops.acquire(hw);
2260 if (ret_val) 2260 if (ret_val)
2261 return ret_val; 2261 return ret_val;
2262 2262
@@ -2294,7 +2294,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2294 data); 2294 data);
2295 2295
2296out: 2296out:
2297 hw->phy.ops.release_phy(hw); 2297 hw->phy.ops.release(hw);
2298 return ret_val; 2298 return ret_val;
2299} 2299}
2300 2300
@@ -2315,7 +2315,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2315 u32 page = offset >> IGP_PAGE_SHIFT; 2315 u32 page = offset >> IGP_PAGE_SHIFT;
2316 u32 page_shift = 0; 2316 u32 page_shift = 0;
2317 2317
2318 ret_val = hw->phy.ops.acquire_phy(hw); 2318 ret_val = hw->phy.ops.acquire(hw);
2319 if (ret_val) 2319 if (ret_val)
2320 return ret_val; 2320 return ret_val;
2321 2321
@@ -2352,7 +2352,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2352 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2352 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2353 data); 2353 data);
2354out: 2354out:
2355 hw->phy.ops.release_phy(hw); 2355 hw->phy.ops.release(hw);
2356 return ret_val; 2356 return ret_val;
2357} 2357}
2358 2358
@@ -2371,7 +2371,7 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2371 s32 ret_val; 2371 s32 ret_val;
2372 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2372 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2373 2373
2374 ret_val = hw->phy.ops.acquire_phy(hw); 2374 ret_val = hw->phy.ops.acquire(hw);
2375 if (ret_val) 2375 if (ret_val)
2376 return ret_val; 2376 return ret_val;
2377 2377
@@ -2397,7 +2397,7 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2397 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2397 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2398 data); 2398 data);
2399out: 2399out:
2400 hw->phy.ops.release_phy(hw); 2400 hw->phy.ops.release(hw);
2401 return ret_val; 2401 return ret_val;
2402} 2402}
2403 2403
@@ -2415,7 +2415,7 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2415 s32 ret_val; 2415 s32 ret_val;
2416 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2416 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2417 2417
2418 ret_val = hw->phy.ops.acquire_phy(hw); 2418 ret_val = hw->phy.ops.acquire(hw);
2419 if (ret_val) 2419 if (ret_val)
2420 return ret_val; 2420 return ret_val;
2421 2421
@@ -2441,7 +2441,7 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2441 data); 2441 data);
2442 2442
2443out: 2443out:
2444 hw->phy.ops.release_phy(hw); 2444 hw->phy.ops.release(hw);
2445 return ret_val; 2445 return ret_val;
2446} 2446}
2447 2447
@@ -2544,8 +2544,8 @@ out:
2544 **/ 2544 **/
2545s32 e1000e_commit_phy(struct e1000_hw *hw) 2545s32 e1000e_commit_phy(struct e1000_hw *hw)
2546{ 2546{
2547 if (hw->phy.ops.commit_phy) 2547 if (hw->phy.ops.commit)
2548 return hw->phy.ops.commit_phy(hw); 2548 return hw->phy.ops.commit(hw);
2549 2549
2550 return 0; 2550 return 0;
2551} 2551}
@@ -2624,7 +2624,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2624 bool in_slow_mode = false; 2624 bool in_slow_mode = false;
2625 2625
2626 if (!locked) { 2626 if (!locked) {
2627 ret_val = hw->phy.ops.acquire_phy(hw); 2627 ret_val = hw->phy.ops.acquire(hw);
2628 if (ret_val) 2628 if (ret_val)
2629 return ret_val; 2629 return ret_val;
2630 } 2630 }
@@ -2681,7 +2681,7 @@ out:
2681 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 2681 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
2682 2682
2683 if (!locked) 2683 if (!locked)
2684 hw->phy.ops.release_phy(hw); 2684 hw->phy.ops.release(hw);
2685 2685
2686 return ret_val; 2686 return ret_val;
2687} 2687}
@@ -2734,7 +2734,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2734 bool in_slow_mode = false; 2734 bool in_slow_mode = false;
2735 2735
2736 if (!locked) { 2736 if (!locked) {
2737 ret_val = hw->phy.ops.acquire_phy(hw); 2737 ret_val = hw->phy.ops.acquire(hw);
2738 if (ret_val) 2738 if (ret_val)
2739 return ret_val; 2739 return ret_val;
2740 } 2740 }
@@ -2808,7 +2808,7 @@ out:
2808 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 2808 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
2809 2809
2810 if (!locked) 2810 if (!locked)
2811 hw->phy.ops.release_phy(hw); 2811 hw->phy.ops.release(hw);
2812 2812
2813 return ret_val; 2813 return ret_val;
2814} 2814}
@@ -2923,12 +2923,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2923 goto out; 2923 goto out;
2924 2924
2925 /* Do not apply workaround if in PHY loopback bit 14 set */ 2925 /* Do not apply workaround if in PHY loopback bit 14 set */
2926 hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &data); 2926 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
2927 if (data & PHY_CONTROL_LB) 2927 if (data & PHY_CONTROL_LB)
2928 goto out; 2928 goto out;
2929 2929
2930 /* check if link is up and at 1Gbps */ 2930 /* check if link is up and at 1Gbps */
2931 ret_val = hw->phy.ops.read_phy_reg(hw, BM_CS_STATUS, &data); 2931 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
2932 if (ret_val) 2932 if (ret_val)
2933 goto out; 2933 goto out;
2934 2934
@@ -2944,13 +2944,13 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2944 mdelay(200); 2944 mdelay(200);
2945 2945
2946 /* flush the packets in the fifo buffer */ 2946 /* flush the packets in the fifo buffer */
2947 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL, 2947 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
2948 HV_MUX_DATA_CTRL_GEN_TO_MAC | 2948 HV_MUX_DATA_CTRL_GEN_TO_MAC |
2949 HV_MUX_DATA_CTRL_FORCE_SPEED); 2949 HV_MUX_DATA_CTRL_FORCE_SPEED);
2950 if (ret_val) 2950 if (ret_val)
2951 goto out; 2951 goto out;
2952 2952
2953 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL, 2953 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
2954 HV_MUX_DATA_CTRL_GEN_TO_MAC); 2954 HV_MUX_DATA_CTRL_GEN_TO_MAC);
2955 2955
2956out: 2956out:
@@ -2971,7 +2971,7 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2971 s32 ret_val; 2971 s32 ret_val;
2972 u16 data; 2972 u16 data;
2973 2973
2974 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data); 2974 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2975 2975
2976 if (!ret_val) 2976 if (!ret_val)
2977 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 2977 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
@@ -2996,13 +2996,13 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2996 u16 phy_data; 2996 u16 phy_data;
2997 bool link; 2997 bool link;
2998 2998
2999 ret_val = phy->ops.read_phy_reg(hw, PHY_CONTROL, &phy_data); 2999 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3000 if (ret_val) 3000 if (ret_val)
3001 goto out; 3001 goto out;
3002 3002
3003 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3003 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3004 3004
3005 ret_val = phy->ops.write_phy_reg(hw, PHY_CONTROL, phy_data); 3005 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3006 if (ret_val) 3006 if (ret_val)
3007 goto out; 3007 goto out;
3008 3008
@@ -3010,14 +3010,14 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3010 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI 3010 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
3011 * forced whenever speed and duplex are forced. 3011 * forced whenever speed and duplex are forced.
3012 */ 3012 */
3013 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_CTRL_2, &phy_data); 3013 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
3014 if (ret_val) 3014 if (ret_val)
3015 goto out; 3015 goto out;
3016 3016
3017 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; 3017 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
3018 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; 3018 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
3019 3019
3020 ret_val = phy->ops.write_phy_reg(hw, I82577_PHY_CTRL_2, phy_data); 3020 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
3021 if (ret_val) 3021 if (ret_val)
3022 goto out; 3022 goto out;
3023 3023
@@ -3083,7 +3083,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3083 if (ret_val) 3083 if (ret_val)
3084 goto out; 3084 goto out;
3085 3085
3086 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data); 3086 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3087 if (ret_val) 3087 if (ret_val)
3088 goto out; 3088 goto out;
3089 3089
@@ -3095,7 +3095,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3095 if (ret_val) 3095 if (ret_val)
3096 goto out; 3096 goto out;
3097 3097
3098 ret_val = phy->ops.read_phy_reg(hw, PHY_1000T_STATUS, &data); 3098 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3099 if (ret_val) 3099 if (ret_val)
3100 goto out; 3100 goto out;
3101 3101
@@ -3129,7 +3129,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3129 s32 ret_val; 3129 s32 ret_val;
3130 u16 phy_data, length; 3130 u16 phy_data, length;
3131 3131
3132 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3132 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3133 if (ret_val) 3133 if (ret_val)
3134 goto out; 3134 goto out;
3135 3135
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 02:24:36 -0500