4 files changed, 60 insertions, 52 deletions

diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index c9fcef7f8462..3102d738cfd1 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -142,6 +142,8 @@ struct e1000_info;
 #define HV_TNCRS_UPPER          PHY_REG(778, 29) /* Transmit with no CRS */
 #define HV_TNCRS_LOWER          PHY_REG(778, 30)
 
+#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
+
 /* BM PHY Copper Specific Status */
 #define BM_CS_STATUS                      17
 #define BM_CS_STATUS_LINK_UP              0x0400
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 568bb259c6fd..7530fc5d81c3 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -1110,7 +1110,8 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
                         oem_reg |= HV_OEM_BITS_LPLU;
         }
         /* Restart auto-neg to activate the bits */
-        oem_reg |= HV_OEM_BITS_RESTART_AN;
+        if (!e1000_check_reset_block(hw))
+                oem_reg |= HV_OEM_BITS_RESTART_AN;
         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
 
 out:
@@ -3545,6 +3546,7 @@ struct e1000_info e1000_pch_info = {
                                   | FLAG_HAS_AMT
                                   | FLAG_HAS_FLASH
                                   | FLAG_HAS_JUMBO_FRAMES
+                                  | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
                                   | FLAG_APME_IN_WUC,
         .pba                    = 26,
         .max_hw_frame_size      = 4096,
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 11a527484e18..e546b4ebf155 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -2760,25 +2760,38 @@ void e1000e_reset(struct e1000_adapter *adapter)
         /*
          * flow control settings
          *
-         * The high water mark must be low enough to fit two full frame
+         * The high water mark must be low enough to fit one full frame
          * (or the size used for early receive) above it in the Rx FIFO.
          * Set it to the lower of:
          * - 90% of the Rx FIFO size, and
          * - the full Rx FIFO size minus the early receive size (for parts
          *   with ERT support assuming ERT set to E1000_ERT_2048), or
-         * - the full Rx FIFO size minus two full frames
+         * - the full Rx FIFO size minus one full frame
          */
-        if ((adapter->flags & FLAG_HAS_ERT) &&
-            (adapter->netdev->mtu > ETH_DATA_LEN))
-                hwm = min(((pba << 10) * 9 / 10),
-                          ((pba << 10) - (E1000_ERT_2048 << 3)));
-        else
-                hwm = min(((pba << 10) * 9 / 10),
-                          ((pba << 10) - (2 * adapter->max_frame_size)));
+        if (hw->mac.type == e1000_pchlan) {
+                /*
+                 * Workaround PCH LOM adapter hangs with certain network
+                 * loads.  If hangs persist, try disabling Tx flow control.
+                 */
+                if (adapter->netdev->mtu > ETH_DATA_LEN) {
+                        fc->high_water = 0x3500;
+                        fc->low_water  = 0x1500;
+                } else {
+                        fc->high_water = 0x5000;
+                        fc->low_water  = 0x3000;
+                }
+        } else {
+                if ((adapter->flags & FLAG_HAS_ERT) &&
+                    (adapter->netdev->mtu > ETH_DATA_LEN))
+                        hwm = min(((pba << 10) * 9 / 10),
+                                  ((pba << 10) - (E1000_ERT_2048 << 3)));
+                else
+                        hwm = min(((pba << 10) * 9 / 10),
+                                  ((pba << 10) - adapter->max_frame_size));
 
-        fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
-        fc->low_water = (fc->high_water - (2 * adapter->max_frame_size));
-        fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */
+                fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
+                fc->low_water = fc->high_water - 8;
+        }
 
         if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
                 fc->pause_time = 0xFFFF;
@@ -2804,6 +2817,10 @@ void e1000e_reset(struct e1000_adapter *adapter)
         if (mac->ops.init_hw(hw))
                 e_err("Hardware Error\n");
 
+        /* additional part of the flow-control workaround above */
+        if (hw->mac.type == e1000_pchlan)
+                ew32(FCRTV_PCH, 0x1000);
+
         e1000_update_mng_vlan(adapter);
 
         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
@@ -3612,7 +3629,7 @@ static void e1000_watchdog_task(struct work_struct *work)
                         case SPEED_100:
                                 txb2b = 0;
                                 netdev->tx_queue_len = 100;
-                                /* maybe add some timeout factor ? */
+                                adapter->tx_timeout_factor = 10;
                                 break;
                         }
 
@@ -4284,8 +4301,10 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
 
         while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
                 msleep(1);
-        /* e1000e_down has a dependency on max_frame_size */
+        /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
         adapter->max_frame_size = max_frame;
+        e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
+        netdev->mtu = new_mtu;
         if (netif_running(netdev))
                 e1000e_down(adapter);
 
@@ -4315,9 +4334,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
                 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
                                          + ETH_FCS_LEN;
 
-        e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
-        netdev->mtu = new_mtu;
-
         if (netif_running(netdev))
                 e1000e_up(adapter);
         else
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 99d53fae4307..5cd01c691c53 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -71,7 +71,6 @@ static const u16 e1000_igp_2_cable_length_table[] =
 #define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
 #define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
 #define I82577_CTRL_REG                   23
-#define I82577_CTRL_DOWNSHIFT_MASK        (7 << 10)
 
 /* 82577 specific PHY registers */
 #define I82577_PHY_CTRL_2            18
@@ -660,15 +659,6 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
         phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
 
         ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
-        if (ret_val)
-                goto out;
-
-        /* Set number of link attempts before downshift */
-        ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data);
-        if (ret_val)
-                goto out;
-        phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
-        ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data);
 
 out:
         return ret_val;
@@ -2658,19 +2648,18 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
                 page = 0;
 
         if (reg > MAX_PHY_MULTI_PAGE_REG) {
-                if ((hw->phy.type != e1000_phy_82578) ||
-                    ((reg != I82578_ADDR_REG) &&
-                     (reg != I82578_ADDR_REG + 1))) {
-                        u32 phy_addr = hw->phy.addr;
+                u32 phy_addr = hw->phy.addr;
 
-                        hw->phy.addr = 1;
+                hw->phy.addr = 1;
 
-                        /* Page is shifted left, PHY expects (page x 32) */
-                        ret_val = e1000e_write_phy_reg_mdic(hw,
-                                                     IGP01E1000_PHY_PAGE_SELECT,
-                                                     (page << IGP_PAGE_SHIFT));
-                        hw->phy.addr = phy_addr;
-                }
+                /* Page is shifted left, PHY expects (page x 32) */
+                ret_val = e1000e_write_phy_reg_mdic(hw,
+                                             IGP01E1000_PHY_PAGE_SELECT,
+                                             (page << IGP_PAGE_SHIFT));
+                hw->phy.addr = phy_addr;
+
+                if (ret_val)
+                        goto out;
         }
 
         ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2678,7 +2667,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
 out:
         /* Revert to MDIO fast mode, if applicable */
         if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
-                ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
+                ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
 
         if (!locked)
                 hw->phy.ops.release(hw);
@@ -2784,19 +2773,18 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
         }
 
         if (reg > MAX_PHY_MULTI_PAGE_REG) {
-                if ((hw->phy.type != e1000_phy_82578) ||
-                    ((reg != I82578_ADDR_REG) &&
-                     (reg != I82578_ADDR_REG + 1))) {
-                        u32 phy_addr = hw->phy.addr;
+                u32 phy_addr = hw->phy.addr;
 
-                        hw->phy.addr = 1;
+                hw->phy.addr = 1;
 
-                        /* Page is shifted left, PHY expects (page x 32) */
-                        ret_val = e1000e_write_phy_reg_mdic(hw,
-                                                     IGP01E1000_PHY_PAGE_SELECT,
-                                                     (page << IGP_PAGE_SHIFT));
-                        hw->phy.addr = phy_addr;
-                }
+                /* Page is shifted left, PHY expects (page x 32) */
+                ret_val = e1000e_write_phy_reg_mdic(hw,
+                                             IGP01E1000_PHY_PAGE_SELECT,
+                                             (page << IGP_PAGE_SHIFT));
+                hw->phy.addr = phy_addr;
+
+                if (ret_val)
+                        goto out;
         }
 
         ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2805,7 +2793,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
 out:
         /* Revert to MDIO fast mode, if applicable */
         if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
-                ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
+                ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
 
         if (!locked)
                 hw->phy.ops.release(hw);