diff options
Diffstat (limited to 'drivers/net/e1000e')
-rw-r--r-- | drivers/net/e1000e/e1000.h | 2 | ||||
-rw-r--r-- | drivers/net/e1000e/ich8lan.c | 4 | ||||
-rw-r--r-- | drivers/net/e1000e/netdev.c | 50 | ||||
-rw-r--r-- | drivers/net/e1000e/phy.c | 56 |
4 files changed, 60 insertions, 52 deletions
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index c9fcef7f8462..3102d738cfd1 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h | |||
@@ -142,6 +142,8 @@ struct e1000_info; | |||
142 | #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ | 142 | #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ |
143 | #define HV_TNCRS_LOWER PHY_REG(778, 30) | 143 | #define HV_TNCRS_LOWER PHY_REG(778, 30) |
144 | 144 | ||
145 | #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ | ||
146 | |||
145 | /* BM PHY Copper Specific Status */ | 147 | /* BM PHY Copper Specific Status */ |
146 | #define BM_CS_STATUS 17 | 148 | #define BM_CS_STATUS 17 |
147 | #define BM_CS_STATUS_LINK_UP 0x0400 | 149 | #define BM_CS_STATUS_LINK_UP 0x0400 |
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 568bb259c6fd..7530fc5d81c3 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -1110,7 +1110,8 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) | |||
1110 | oem_reg |= HV_OEM_BITS_LPLU; | 1110 | oem_reg |= HV_OEM_BITS_LPLU; |
1111 | } | 1111 | } |
1112 | /* Restart auto-neg to activate the bits */ | 1112 | /* Restart auto-neg to activate the bits */ |
1113 | oem_reg |= HV_OEM_BITS_RESTART_AN; | 1113 | if (!e1000_check_reset_block(hw)) |
1114 | oem_reg |= HV_OEM_BITS_RESTART_AN; | ||
1114 | ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); | 1115 | ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); |
1115 | 1116 | ||
1116 | out: | 1117 | out: |
@@ -3545,6 +3546,7 @@ struct e1000_info e1000_pch_info = { | |||
3545 | | FLAG_HAS_AMT | 3546 | | FLAG_HAS_AMT |
3546 | | FLAG_HAS_FLASH | 3547 | | FLAG_HAS_FLASH |
3547 | | FLAG_HAS_JUMBO_FRAMES | 3548 | | FLAG_HAS_JUMBO_FRAMES |
3549 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | ||
3548 | | FLAG_APME_IN_WUC, | 3550 | | FLAG_APME_IN_WUC, |
3549 | .pba = 26, | 3551 | .pba = 26, |
3550 | .max_hw_frame_size = 4096, | 3552 | .max_hw_frame_size = 4096, |
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index 11a527484e18..e546b4ebf155 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
@@ -2760,25 +2760,38 @@ void e1000e_reset(struct e1000_adapter *adapter) | |||
2760 | /* | 2760 | /* |
2761 | * flow control settings | 2761 | * flow control settings |
2762 | * | 2762 | * |
2763 | * The high water mark must be low enough to fit two full frame | 2763 | * The high water mark must be low enough to fit one full frame |
2764 | * (or the size used for early receive) above it in the Rx FIFO. | 2764 | * (or the size used for early receive) above it in the Rx FIFO. |
2765 | * Set it to the lower of: | 2765 | * Set it to the lower of: |
2766 | * - 90% of the Rx FIFO size, and | 2766 | * - 90% of the Rx FIFO size, and |
2767 | * - the full Rx FIFO size minus the early receive size (for parts | 2767 | * - the full Rx FIFO size minus the early receive size (for parts |
2768 | * with ERT support assuming ERT set to E1000_ERT_2048), or | 2768 | * with ERT support assuming ERT set to E1000_ERT_2048), or |
2769 | * - the full Rx FIFO size minus two full frames | 2769 | * - the full Rx FIFO size minus one full frame |
2770 | */ | 2770 | */ |
2771 | if ((adapter->flags & FLAG_HAS_ERT) && | 2771 | if (hw->mac.type == e1000_pchlan) { |
2772 | (adapter->netdev->mtu > ETH_DATA_LEN)) | 2772 | /* |
2773 | hwm = min(((pba << 10) * 9 / 10), | 2773 | * Workaround PCH LOM adapter hangs with certain network |
2774 | ((pba << 10) - (E1000_ERT_2048 << 3))); | 2774 | * loads. If hangs persist, try disabling Tx flow control. |
2775 | else | 2775 | */ |
2776 | hwm = min(((pba << 10) * 9 / 10), | 2776 | if (adapter->netdev->mtu > ETH_DATA_LEN) { |
2777 | ((pba << 10) - (2 * adapter->max_frame_size))); | 2777 | fc->high_water = 0x3500; |
2778 | fc->low_water = 0x1500; | ||
2779 | } else { | ||
2780 | fc->high_water = 0x5000; | ||
2781 | fc->low_water = 0x3000; | ||
2782 | } | ||
2783 | } else { | ||
2784 | if ((adapter->flags & FLAG_HAS_ERT) && | ||
2785 | (adapter->netdev->mtu > ETH_DATA_LEN)) | ||
2786 | hwm = min(((pba << 10) * 9 / 10), | ||
2787 | ((pba << 10) - (E1000_ERT_2048 << 3))); | ||
2788 | else | ||
2789 | hwm = min(((pba << 10) * 9 / 10), | ||
2790 | ((pba << 10) - adapter->max_frame_size)); | ||
2778 | 2791 | ||
2779 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ | 2792 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ |
2780 | fc->low_water = (fc->high_water - (2 * adapter->max_frame_size)); | 2793 | fc->low_water = fc->high_water - 8; |
2781 | fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */ | 2794 | } |
2782 | 2795 | ||
2783 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) | 2796 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) |
2784 | fc->pause_time = 0xFFFF; | 2797 | fc->pause_time = 0xFFFF; |
@@ -2804,6 +2817,10 @@ void e1000e_reset(struct e1000_adapter *adapter) | |||
2804 | if (mac->ops.init_hw(hw)) | 2817 | if (mac->ops.init_hw(hw)) |
2805 | e_err("Hardware Error\n"); | 2818 | e_err("Hardware Error\n"); |
2806 | 2819 | ||
2820 | /* additional part of the flow-control workaround above */ | ||
2821 | if (hw->mac.type == e1000_pchlan) | ||
2822 | ew32(FCRTV_PCH, 0x1000); | ||
2823 | |||
2807 | e1000_update_mng_vlan(adapter); | 2824 | e1000_update_mng_vlan(adapter); |
2808 | 2825 | ||
2809 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | 2826 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ |
@@ -3612,7 +3629,7 @@ static void e1000_watchdog_task(struct work_struct *work) | |||
3612 | case SPEED_100: | 3629 | case SPEED_100: |
3613 | txb2b = 0; | 3630 | txb2b = 0; |
3614 | netdev->tx_queue_len = 100; | 3631 | netdev->tx_queue_len = 100; |
3615 | /* maybe add some timeout factor ? */ | 3632 | adapter->tx_timeout_factor = 10; |
3616 | break; | 3633 | break; |
3617 | } | 3634 | } |
3618 | 3635 | ||
@@ -4284,8 +4301,10 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
4284 | 4301 | ||
4285 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) | 4302 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) |
4286 | msleep(1); | 4303 | msleep(1); |
4287 | /* e1000e_down has a dependency on max_frame_size */ | 4304 | /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ |
4288 | adapter->max_frame_size = max_frame; | 4305 | adapter->max_frame_size = max_frame; |
4306 | e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); | ||
4307 | netdev->mtu = new_mtu; | ||
4289 | if (netif_running(netdev)) | 4308 | if (netif_running(netdev)) |
4290 | e1000e_down(adapter); | 4309 | e1000e_down(adapter); |
4291 | 4310 | ||
@@ -4315,9 +4334,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
4315 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN | 4334 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN |
4316 | + ETH_FCS_LEN; | 4335 | + ETH_FCS_LEN; |
4317 | 4336 | ||
4318 | e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); | ||
4319 | netdev->mtu = new_mtu; | ||
4320 | |||
4321 | if (netif_running(netdev)) | 4337 | if (netif_running(netdev)) |
4322 | e1000e_up(adapter); | 4338 | e1000e_up(adapter); |
4323 | else | 4339 | else |
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index 99d53fae4307..5cd01c691c53 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c | |||
@@ -71,7 +71,6 @@ static const u16 e1000_igp_2_cable_length_table[] = | |||
71 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) | 71 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
72 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ | 72 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ |
73 | #define I82577_CTRL_REG 23 | 73 | #define I82577_CTRL_REG 23 |
74 | #define I82577_CTRL_DOWNSHIFT_MASK (7 << 10) | ||
75 | 74 | ||
76 | /* 82577 specific PHY registers */ | 75 | /* 82577 specific PHY registers */ |
77 | #define I82577_PHY_CTRL_2 18 | 76 | #define I82577_PHY_CTRL_2 18 |
@@ -660,15 +659,6 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |||
660 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | 659 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
661 | 660 | ||
662 | ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); | 661 | ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); |
663 | if (ret_val) | ||
664 | goto out; | ||
665 | |||
666 | /* Set number of link attempts before downshift */ | ||
667 | ret_val = phy->ops.read_reg(hw, I82577_CTRL_REG, &phy_data); | ||
668 | if (ret_val) | ||
669 | goto out; | ||
670 | phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; | ||
671 | ret_val = phy->ops.write_reg(hw, I82577_CTRL_REG, phy_data); | ||
672 | 662 | ||
673 | out: | 663 | out: |
674 | return ret_val; | 664 | return ret_val; |
@@ -2658,19 +2648,18 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, | |||
2658 | page = 0; | 2648 | page = 0; |
2659 | 2649 | ||
2660 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | 2650 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
2661 | if ((hw->phy.type != e1000_phy_82578) || | 2651 | u32 phy_addr = hw->phy.addr; |
2662 | ((reg != I82578_ADDR_REG) && | ||
2663 | (reg != I82578_ADDR_REG + 1))) { | ||
2664 | u32 phy_addr = hw->phy.addr; | ||
2665 | 2652 | ||
2666 | hw->phy.addr = 1; | 2653 | hw->phy.addr = 1; |
2667 | 2654 | ||
2668 | /* Page is shifted left, PHY expects (page x 32) */ | 2655 | /* Page is shifted left, PHY expects (page x 32) */ |
2669 | ret_val = e1000e_write_phy_reg_mdic(hw, | 2656 | ret_val = e1000e_write_phy_reg_mdic(hw, |
2670 | IGP01E1000_PHY_PAGE_SELECT, | 2657 | IGP01E1000_PHY_PAGE_SELECT, |
2671 | (page << IGP_PAGE_SHIFT)); | 2658 | (page << IGP_PAGE_SHIFT)); |
2672 | hw->phy.addr = phy_addr; | 2659 | hw->phy.addr = phy_addr; |
2673 | } | 2660 | |
2661 | if (ret_val) | ||
2662 | goto out; | ||
2674 | } | 2663 | } |
2675 | 2664 | ||
2676 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | 2665 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
@@ -2678,7 +2667,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, | |||
2678 | out: | 2667 | out: |
2679 | /* Revert to MDIO fast mode, if applicable */ | 2668 | /* Revert to MDIO fast mode, if applicable */ |
2680 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | 2669 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) |
2681 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | 2670 | ret_val |= e1000_set_mdio_slow_mode_hv(hw, false); |
2682 | 2671 | ||
2683 | if (!locked) | 2672 | if (!locked) |
2684 | hw->phy.ops.release(hw); | 2673 | hw->phy.ops.release(hw); |
@@ -2784,19 +2773,18 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, | |||
2784 | } | 2773 | } |
2785 | 2774 | ||
2786 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | 2775 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
2787 | if ((hw->phy.type != e1000_phy_82578) || | 2776 | u32 phy_addr = hw->phy.addr; |
2788 | ((reg != I82578_ADDR_REG) && | ||
2789 | (reg != I82578_ADDR_REG + 1))) { | ||
2790 | u32 phy_addr = hw->phy.addr; | ||
2791 | 2777 | ||
2792 | hw->phy.addr = 1; | 2778 | hw->phy.addr = 1; |
2793 | 2779 | ||
2794 | /* Page is shifted left, PHY expects (page x 32) */ | 2780 | /* Page is shifted left, PHY expects (page x 32) */ |
2795 | ret_val = e1000e_write_phy_reg_mdic(hw, | 2781 | ret_val = e1000e_write_phy_reg_mdic(hw, |
2796 | IGP01E1000_PHY_PAGE_SELECT, | 2782 | IGP01E1000_PHY_PAGE_SELECT, |
2797 | (page << IGP_PAGE_SHIFT)); | 2783 | (page << IGP_PAGE_SHIFT)); |
2798 | hw->phy.addr = phy_addr; | 2784 | hw->phy.addr = phy_addr; |
2799 | } | 2785 | |
2786 | if (ret_val) | ||
2787 | goto out; | ||
2800 | } | 2788 | } |
2801 | 2789 | ||
2802 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | 2790 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
@@ -2805,7 +2793,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, | |||
2805 | out: | 2793 | out: |
2806 | /* Revert to MDIO fast mode, if applicable */ | 2794 | /* Revert to MDIO fast mode, if applicable */ |
2807 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | 2795 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) |
2808 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | 2796 | ret_val |= e1000_set_mdio_slow_mode_hv(hw, false); |
2809 | 2797 | ||
2810 | if (!locked) | 2798 | if (!locked) |
2811 | hw->phy.ops.release(hw); | 2799 | hw->phy.ops.release(hw); |