diff options
Diffstat (limited to 'drivers/net/e1000e')
| -rw-r--r-- | drivers/net/e1000e/e1000.h | 2 | ||||
| -rw-r--r-- | drivers/net/e1000e/ethtool.c | 12 | ||||
| -rw-r--r-- | drivers/net/e1000e/ich8lan.c | 4 | ||||
| -rw-r--r-- | drivers/net/e1000e/netdev.c | 50 | ||||
| -rw-r--r-- | drivers/net/e1000e/phy.c | 56 |
5 files changed, 70 insertions, 54 deletions
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index 189dfa2d6c76..3e187b0e4203 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h | |||
| @@ -141,6 +141,8 @@ struct e1000_info; | |||
| 141 | #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ | 141 | #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ |
| 142 | #define HV_TNCRS_LOWER PHY_REG(778, 30) | 142 | #define HV_TNCRS_LOWER PHY_REG(778, 30) |
| 143 | 143 | ||
| 144 | #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ | ||
| 145 | |||
| 144 | /* BM PHY Copper Specific Status */ | 146 | /* BM PHY Copper Specific Status */ |
| 145 | #define BM_CS_STATUS 17 | 147 | #define BM_CS_STATUS 17 |
| 146 | #define BM_CS_STATUS_LINK_UP 0x0400 | 148 | #define BM_CS_STATUS_LINK_UP 0x0400 |
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c index 1bf4d2a5d34f..e82638ecae88 100644 --- a/drivers/net/e1000e/ethtool.c +++ b/drivers/net/e1000e/ethtool.c | |||
| @@ -327,10 +327,18 @@ static int e1000_set_pauseparam(struct net_device *netdev, | |||
| 327 | 327 | ||
| 328 | hw->fc.current_mode = hw->fc.requested_mode; | 328 | hw->fc.current_mode = hw->fc.requested_mode; |
| 329 | 329 | ||
| 330 | retval = ((hw->phy.media_type == e1000_media_type_fiber) ? | 330 | if (hw->phy.media_type == e1000_media_type_fiber) { |
| 331 | hw->mac.ops.setup_link(hw) : e1000e_force_mac_fc(hw)); | 331 | retval = hw->mac.ops.setup_link(hw); |
| 332 | /* implicit goto out */ | ||
| 333 | } else { | ||
| 334 | retval = e1000e_force_mac_fc(hw); | ||
| 335 | if (retval) | ||
| 336 | goto out; | ||
| 337 | e1000e_set_fc_watermarks(hw); | ||
| 338 | } | ||
| 332 | } | 339 | } |
| 333 | 340 | ||
| 341 | out: | ||
| 334 | clear_bit(__E1000_RESETTING, &adapter->state); | 342 | clear_bit(__E1000_RESETTING, &adapter->state); |
| 335 | return retval; | 343 | return retval; |
| 336 | } | 344 | } |
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 51ddb04ab195..eff3f4783655 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
| @@ -1118,7 +1118,8 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) | |||
| 1118 | oem_reg |= HV_OEM_BITS_LPLU; | 1118 | oem_reg |= HV_OEM_BITS_LPLU; |
| 1119 | } | 1119 | } |
| 1120 | /* Restart auto-neg to activate the bits */ | 1120 | /* Restart auto-neg to activate the bits */ |
| 1121 | oem_reg |= HV_OEM_BITS_RESTART_AN; | 1121 | if (!e1000_check_reset_block(hw)) |
| 1122 | oem_reg |= HV_OEM_BITS_RESTART_AN; | ||
| 1122 | ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg); | 1123 | ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg); |
| 1123 | 1124 | ||
| 1124 | out: | 1125 | out: |
| @@ -3558,6 +3559,7 @@ struct e1000_info e1000_pch_info = { | |||
| 3558 | | FLAG_HAS_AMT | 3559 | | FLAG_HAS_AMT |
| 3559 | | FLAG_HAS_FLASH | 3560 | | FLAG_HAS_FLASH |
| 3560 | | FLAG_HAS_JUMBO_FRAMES | 3561 | | FLAG_HAS_JUMBO_FRAMES |
| 3562 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | ||
| 3561 | | FLAG_APME_IN_WUC, | 3563 | | FLAG_APME_IN_WUC, |
| 3562 | .pba = 26, | 3564 | .pba = 26, |
| 3563 | .max_hw_frame_size = 4096, | 3565 | .max_hw_frame_size = 4096, |
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index 0687c6aa4e46..fad8f9ea0043 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
| @@ -2769,25 +2769,38 @@ void e1000e_reset(struct e1000_adapter *adapter) | |||
| 2769 | /* | 2769 | /* |
| 2770 | * flow control settings | 2770 | * flow control settings |
| 2771 | * | 2771 | * |
| 2772 | * The high water mark must be low enough to fit two full frame | 2772 | * The high water mark must be low enough to fit one full frame |
| 2773 | * (or the size used for early receive) above it in the Rx FIFO. | 2773 | * (or the size used for early receive) above it in the Rx FIFO. |
| 2774 | * Set it to the lower of: | 2774 | * Set it to the lower of: |
| 2775 | * - 90% of the Rx FIFO size, and | 2775 | * - 90% of the Rx FIFO size, and |
| 2776 | * - the full Rx FIFO size minus the early receive size (for parts | 2776 | * - the full Rx FIFO size minus the early receive size (for parts |
| 2777 | * with ERT support assuming ERT set to E1000_ERT_2048), or | 2777 | * with ERT support assuming ERT set to E1000_ERT_2048), or |
| 2778 | * - the full Rx FIFO size minus two full frames | 2778 | * - the full Rx FIFO size minus one full frame |
| 2779 | */ | 2779 | */ |
| 2780 | if ((adapter->flags & FLAG_HAS_ERT) && | 2780 | if (hw->mac.type == e1000_pchlan) { |
| 2781 | (adapter->netdev->mtu > ETH_DATA_LEN)) | 2781 | /* |
| 2782 | hwm = min(((pba << 10) * 9 / 10), | 2782 | * Workaround PCH LOM adapter hangs with certain network |
| 2783 | ((pba << 10) - (E1000_ERT_2048 << 3))); | 2783 | * loads. If hangs persist, try disabling Tx flow control. |
| 2784 | else | 2784 | */ |
| 2785 | hwm = min(((pba << 10) * 9 / 10), | 2785 | if (adapter->netdev->mtu > ETH_DATA_LEN) { |
| 2786 | ((pba << 10) - (2 * adapter->max_frame_size))); | 2786 | fc->high_water = 0x3500; |
| 2787 | fc->low_water = 0x1500; | ||
| 2788 | } else { | ||
| 2789 | fc->high_water = 0x5000; | ||
| 2790 | fc->low_water = 0x3000; | ||
| 2791 | } | ||
| 2792 | } else { | ||
| 2793 | if ((adapter->flags & FLAG_HAS_ERT) && | ||
| 2794 | (adapter->netdev->mtu > ETH_DATA_LEN)) | ||
| 2795 | hwm = min(((pba << 10) * 9 / 10), | ||
| 2796 | ((pba << 10) - (E1000_ERT_2048 << 3))); | ||
| 2797 | else | ||
| 2798 | hwm = min(((pba << 10) * 9 / 10), | ||
| 2799 | ((pba << 10) - adapter->max_frame_size)); | ||
| 2787 | 2800 | ||
| 2788 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ | 2801 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ |
| 2789 | fc->low_water = (fc->high_water - (2 * adapter->max_frame_size)); | 2802 | fc->low_water = fc->high_water - 8; |
| 2790 | fc->low_water &= E1000_FCRTL_RTL; /* 8-byte granularity */ | 2803 | } |
| 2791 | 2804 | ||
| 2792 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) | 2805 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) |
| 2793 | fc->pause_time = 0xFFFF; | 2806 | fc->pause_time = 0xFFFF; |
| @@ -2813,6 +2826,10 @@ void e1000e_reset(struct e1000_adapter *adapter) | |||
| 2813 | if (mac->ops.init_hw(hw)) | 2826 | if (mac->ops.init_hw(hw)) |
| 2814 | e_err("Hardware Error\n"); | 2827 | e_err("Hardware Error\n"); |
| 2815 | 2828 | ||
| 2829 | /* additional part of the flow-control workaround above */ | ||
| 2830 | if (hw->mac.type == e1000_pchlan) | ||
| 2831 | ew32(FCRTV_PCH, 0x1000); | ||
| 2832 | |||
| 2816 | e1000_update_mng_vlan(adapter); | 2833 | e1000_update_mng_vlan(adapter); |
| 2817 | 2834 | ||
| 2818 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | 2835 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ |
| @@ -3610,7 +3627,7 @@ static void e1000_watchdog_task(struct work_struct *work) | |||
| 3610 | case SPEED_100: | 3627 | case SPEED_100: |
| 3611 | txb2b = 0; | 3628 | txb2b = 0; |
| 3612 | netdev->tx_queue_len = 100; | 3629 | netdev->tx_queue_len = 100; |
| 3613 | /* maybe add some timeout factor ? */ | 3630 | adapter->tx_timeout_factor = 10; |
| 3614 | break; | 3631 | break; |
| 3615 | } | 3632 | } |
| 3616 | 3633 | ||
| @@ -4288,8 +4305,10 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
| 4288 | 4305 | ||
| 4289 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) | 4306 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) |
| 4290 | msleep(1); | 4307 | msleep(1); |
| 4291 | /* e1000e_down has a dependency on max_frame_size */ | 4308 | /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ |
| 4292 | adapter->max_frame_size = max_frame; | 4309 | adapter->max_frame_size = max_frame; |
| 4310 | e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); | ||
| 4311 | netdev->mtu = new_mtu; | ||
| 4293 | if (netif_running(netdev)) | 4312 | if (netif_running(netdev)) |
| 4294 | e1000e_down(adapter); | 4313 | e1000e_down(adapter); |
| 4295 | 4314 | ||
| @@ -4319,9 +4338,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
| 4319 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN | 4338 | adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN |
| 4320 | + ETH_FCS_LEN; | 4339 | + ETH_FCS_LEN; |
| 4321 | 4340 | ||
| 4322 | e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); | ||
| 4323 | netdev->mtu = new_mtu; | ||
| 4324 | |||
| 4325 | if (netif_running(netdev)) | 4341 | if (netif_running(netdev)) |
| 4326 | e1000e_up(adapter); | 4342 | e1000e_up(adapter); |
| 4327 | else | 4343 | else |
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index 03175b3a2c9e..85f955f70417 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c | |||
| @@ -71,7 +71,6 @@ static const u16 e1000_igp_2_cable_length_table[] = | |||
| 71 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) | 71 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
| 72 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ | 72 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ |
| 73 | #define I82577_CTRL_REG 23 | 73 | #define I82577_CTRL_REG 23 |
| 74 | #define I82577_CTRL_DOWNSHIFT_MASK (7 << 10) | ||
| 75 | 74 | ||
| 76 | /* 82577 specific PHY registers */ | 75 | /* 82577 specific PHY registers */ |
| 77 | #define I82577_PHY_CTRL_2 18 | 76 | #define I82577_PHY_CTRL_2 18 |
| @@ -660,15 +659,6 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |||
| 660 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | 659 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
| 661 | 660 | ||
| 662 | ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data); | 661 | ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data); |
| 663 | if (ret_val) | ||
| 664 | goto out; | ||
| 665 | |||
| 666 | /* Set number of link attempts before downshift */ | ||
| 667 | ret_val = phy->ops.read_phy_reg(hw, I82577_CTRL_REG, &phy_data); | ||
| 668 | if (ret_val) | ||
| 669 | goto out; | ||
| 670 | phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK; | ||
| 671 | ret_val = phy->ops.write_phy_reg(hw, I82577_CTRL_REG, phy_data); | ||
| 672 | 662 | ||
| 673 | out: | 663 | out: |
| 674 | return ret_val; | 664 | return ret_val; |
| @@ -2658,19 +2648,18 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, | |||
| 2658 | page = 0; | 2648 | page = 0; |
| 2659 | 2649 | ||
| 2660 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | 2650 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
| 2661 | if ((hw->phy.type != e1000_phy_82578) || | 2651 | u32 phy_addr = hw->phy.addr; |
| 2662 | ((reg != I82578_ADDR_REG) && | ||
| 2663 | (reg != I82578_ADDR_REG + 1))) { | ||
| 2664 | u32 phy_addr = hw->phy.addr; | ||
| 2665 | 2652 | ||
| 2666 | hw->phy.addr = 1; | 2653 | hw->phy.addr = 1; |
| 2667 | 2654 | ||
| 2668 | /* Page is shifted left, PHY expects (page x 32) */ | 2655 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2669 | ret_val = e1000e_write_phy_reg_mdic(hw, | 2656 | ret_val = e1000e_write_phy_reg_mdic(hw, |
| 2670 | IGP01E1000_PHY_PAGE_SELECT, | 2657 | IGP01E1000_PHY_PAGE_SELECT, |
| 2671 | (page << IGP_PAGE_SHIFT)); | 2658 | (page << IGP_PAGE_SHIFT)); |
| 2672 | hw->phy.addr = phy_addr; | 2659 | hw->phy.addr = phy_addr; |
| 2673 | } | 2660 | |
| 2661 | if (ret_val) | ||
| 2662 | goto out; | ||
| 2674 | } | 2663 | } |
| 2675 | 2664 | ||
| 2676 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | 2665 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
| @@ -2678,7 +2667,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, | |||
| 2678 | out: | 2667 | out: |
| 2679 | /* Revert to MDIO fast mode, if applicable */ | 2668 | /* Revert to MDIO fast mode, if applicable */ |
| 2680 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | 2669 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) |
| 2681 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | 2670 | ret_val |= e1000_set_mdio_slow_mode_hv(hw, false); |
| 2682 | 2671 | ||
| 2683 | if (!locked) | 2672 | if (!locked) |
| 2684 | hw->phy.ops.release_phy(hw); | 2673 | hw->phy.ops.release_phy(hw); |
| @@ -2784,19 +2773,18 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, | |||
| 2784 | } | 2773 | } |
| 2785 | 2774 | ||
| 2786 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | 2775 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
| 2787 | if ((hw->phy.type != e1000_phy_82578) || | 2776 | u32 phy_addr = hw->phy.addr; |
| 2788 | ((reg != I82578_ADDR_REG) && | ||
| 2789 | (reg != I82578_ADDR_REG + 1))) { | ||
| 2790 | u32 phy_addr = hw->phy.addr; | ||
| 2791 | 2777 | ||
| 2792 | hw->phy.addr = 1; | 2778 | hw->phy.addr = 1; |
| 2793 | 2779 | ||
| 2794 | /* Page is shifted left, PHY expects (page x 32) */ | 2780 | /* Page is shifted left, PHY expects (page x 32) */ |
| 2795 | ret_val = e1000e_write_phy_reg_mdic(hw, | 2781 | ret_val = e1000e_write_phy_reg_mdic(hw, |
| 2796 | IGP01E1000_PHY_PAGE_SELECT, | 2782 | IGP01E1000_PHY_PAGE_SELECT, |
| 2797 | (page << IGP_PAGE_SHIFT)); | 2783 | (page << IGP_PAGE_SHIFT)); |
| 2798 | hw->phy.addr = phy_addr; | 2784 | hw->phy.addr = phy_addr; |
| 2799 | } | 2785 | |
| 2786 | if (ret_val) | ||
| 2787 | goto out; | ||
| 2800 | } | 2788 | } |
| 2801 | 2789 | ||
| 2802 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | 2790 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
| @@ -2805,7 +2793,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, | |||
| 2805 | out: | 2793 | out: |
| 2806 | /* Revert to MDIO fast mode, if applicable */ | 2794 | /* Revert to MDIO fast mode, if applicable */ |
| 2807 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | 2795 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) |
| 2808 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); | 2796 | ret_val |= e1000_set_mdio_slow_mode_hv(hw, false); |
| 2809 | 2797 | ||
| 2810 | if (!locked) | 2798 | if (!locked) |
| 2811 | hw->phy.ops.release_phy(hw); | 2799 | hw->phy.ops.release_phy(hw); |
