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Diffstat (limited to 'drivers/net/e1000e/phy.c')
-rw-r--r--drivers/net/e1000e/phy.c580
1 files changed, 398 insertions, 182 deletions
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 03175b3a2c9e..55a2c0acfee7 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/1000 Linux driver 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation. 4 Copyright(c) 1999 - 2009 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -44,6 +44,8 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
44/* Cable length tables */ 44/* Cable length tables */
45static const u16 e1000_m88_cable_length_table[] = 45static const u16 e1000_m88_cable_length_table[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
47 49
48static const u16 e1000_igp_2_cable_length_table[] = 50static const u16 e1000_igp_2_cable_length_table[] =
49 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
@@ -71,7 +73,6 @@ static const u16 e1000_igp_2_cable_length_table[] =
71#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 73#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 74#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73#define I82577_CTRL_REG 23 75#define I82577_CTRL_REG 23
74#define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
75 76
76/* 82577 specific PHY registers */ 77/* 82577 specific PHY registers */
77#define I82577_PHY_CTRL_2 18 78#define I82577_PHY_CTRL_2 18
@@ -131,7 +132,7 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
131 u16 phy_id; 132 u16 phy_id;
132 u16 retry_count = 0; 133 u16 retry_count = 0;
133 134
134 if (!(phy->ops.read_phy_reg)) 135 if (!(phy->ops.read_reg))
135 goto out; 136 goto out;
136 137
137 while (retry_count < 2) { 138 while (retry_count < 2) {
@@ -152,29 +153,29 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw)
152 goto out; 153 goto out;
153 154
154 /* 155 /*
155 * If the PHY ID is still unknown, we may have an 82577i 156 * If the PHY ID is still unknown, we may have an 82577
156 * without link. We will try again after setting Slow 157 * without link. We will try again after setting Slow MDIC
157 * MDIC mode. No harm in trying again in this case since 158 * mode. No harm in trying again in this case since the PHY
158 * the PHY ID is unknown at this point anyway 159 * ID is unknown at this point anyway.
159 */ 160 */
160 ret_val = phy->ops.acquire_phy(hw); 161 ret_val = phy->ops.acquire(hw);
161 if (ret_val) 162 if (ret_val)
162 goto out; 163 goto out;
163 ret_val = e1000_set_mdio_slow_mode_hv(hw, true); 164 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
164 if (ret_val) 165 if (ret_val)
165 goto out; 166 goto out;
166 phy->ops.release_phy(hw); 167 phy->ops.release(hw);
167 168
168 retry_count++; 169 retry_count++;
169 } 170 }
170out: 171out:
171 /* Revert to MDIO fast mode, if applicable */ 172 /* Revert to MDIO fast mode, if applicable */
172 if (retry_count) { 173 if (retry_count) {
173 ret_val = phy->ops.acquire_phy(hw); 174 ret_val = phy->ops.acquire(hw);
174 if (ret_val) 175 if (ret_val)
175 return ret_val; 176 return ret_val;
176 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 177 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
177 phy->ops.release_phy(hw); 178 phy->ops.release(hw);
178 } 179 }
179 180
180 return ret_val; 181 return ret_val;
@@ -212,7 +213,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
212 u32 i, mdic = 0; 213 u32 i, mdic = 0;
213 214
214 if (offset > MAX_PHY_REG_ADDRESS) { 215 if (offset > MAX_PHY_REG_ADDRESS) {
215 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 216 e_dbg("PHY Address %d is out of range\n", offset);
216 return -E1000_ERR_PARAM; 217 return -E1000_ERR_PARAM;
217 } 218 }
218 219
@@ -239,11 +240,11 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
239 break; 240 break;
240 } 241 }
241 if (!(mdic & E1000_MDIC_READY)) { 242 if (!(mdic & E1000_MDIC_READY)) {
242 hw_dbg(hw, "MDI Read did not complete\n"); 243 e_dbg("MDI Read did not complete\n");
243 return -E1000_ERR_PHY; 244 return -E1000_ERR_PHY;
244 } 245 }
245 if (mdic & E1000_MDIC_ERROR) { 246 if (mdic & E1000_MDIC_ERROR) {
246 hw_dbg(hw, "MDI Error\n"); 247 e_dbg("MDI Error\n");
247 return -E1000_ERR_PHY; 248 return -E1000_ERR_PHY;
248 } 249 }
249 *data = (u16) mdic; 250 *data = (u16) mdic;
@@ -265,7 +266,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
265 u32 i, mdic = 0; 266 u32 i, mdic = 0;
266 267
267 if (offset > MAX_PHY_REG_ADDRESS) { 268 if (offset > MAX_PHY_REG_ADDRESS) {
268 hw_dbg(hw, "PHY Address %d is out of range\n", offset); 269 e_dbg("PHY Address %d is out of range\n", offset);
269 return -E1000_ERR_PARAM; 270 return -E1000_ERR_PARAM;
270 } 271 }
271 272
@@ -293,11 +294,11 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
293 break; 294 break;
294 } 295 }
295 if (!(mdic & E1000_MDIC_READY)) { 296 if (!(mdic & E1000_MDIC_READY)) {
296 hw_dbg(hw, "MDI Write did not complete\n"); 297 e_dbg("MDI Write did not complete\n");
297 return -E1000_ERR_PHY; 298 return -E1000_ERR_PHY;
298 } 299 }
299 if (mdic & E1000_MDIC_ERROR) { 300 if (mdic & E1000_MDIC_ERROR) {
300 hw_dbg(hw, "MDI Error\n"); 301 e_dbg("MDI Error\n");
301 return -E1000_ERR_PHY; 302 return -E1000_ERR_PHY;
302 } 303 }
303 304
@@ -318,14 +319,14 @@ s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
318{ 319{
319 s32 ret_val; 320 s32 ret_val;
320 321
321 ret_val = hw->phy.ops.acquire_phy(hw); 322 ret_val = hw->phy.ops.acquire(hw);
322 if (ret_val) 323 if (ret_val)
323 return ret_val; 324 return ret_val;
324 325
325 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 326 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
326 data); 327 data);
327 328
328 hw->phy.ops.release_phy(hw); 329 hw->phy.ops.release(hw);
329 330
330 return ret_val; 331 return ret_val;
331} 332}
@@ -343,14 +344,14 @@ s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
343{ 344{
344 s32 ret_val; 345 s32 ret_val;
345 346
346 ret_val = hw->phy.ops.acquire_phy(hw); 347 ret_val = hw->phy.ops.acquire(hw);
347 if (ret_val) 348 if (ret_val)
348 return ret_val; 349 return ret_val;
349 350
350 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 351 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
351 data); 352 data);
352 353
353 hw->phy.ops.release_phy(hw); 354 hw->phy.ops.release(hw);
354 355
355 return ret_val; 356 return ret_val;
356} 357}
@@ -372,10 +373,10 @@ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
372 s32 ret_val = 0; 373 s32 ret_val = 0;
373 374
374 if (!locked) { 375 if (!locked) {
375 if (!(hw->phy.ops.acquire_phy)) 376 if (!(hw->phy.ops.acquire))
376 goto out; 377 goto out;
377 378
378 ret_val = hw->phy.ops.acquire_phy(hw); 379 ret_val = hw->phy.ops.acquire(hw);
379 if (ret_val) 380 if (ret_val)
380 goto out; 381 goto out;
381 } 382 }
@@ -393,7 +394,7 @@ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
393 394
394release: 395release:
395 if (!locked) 396 if (!locked)
396 hw->phy.ops.release_phy(hw); 397 hw->phy.ops.release(hw);
397out: 398out:
398 return ret_val; 399 return ret_val;
399} 400}
@@ -443,10 +444,10 @@ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
443 s32 ret_val = 0; 444 s32 ret_val = 0;
444 445
445 if (!locked) { 446 if (!locked) {
446 if (!(hw->phy.ops.acquire_phy)) 447 if (!(hw->phy.ops.acquire))
447 goto out; 448 goto out;
448 449
449 ret_val = hw->phy.ops.acquire_phy(hw); 450 ret_val = hw->phy.ops.acquire(hw);
450 if (ret_val) 451 if (ret_val)
451 goto out; 452 goto out;
452 } 453 }
@@ -464,7 +465,7 @@ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
464 465
465release: 466release:
466 if (!locked) 467 if (!locked)
467 hw->phy.ops.release_phy(hw); 468 hw->phy.ops.release(hw);
468 469
469out: 470out:
470 return ret_val; 471 return ret_val;
@@ -516,10 +517,10 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
516 s32 ret_val = 0; 517 s32 ret_val = 0;
517 518
518 if (!locked) { 519 if (!locked) {
519 if (!(hw->phy.ops.acquire_phy)) 520 if (!(hw->phy.ops.acquire))
520 goto out; 521 goto out;
521 522
522 ret_val = hw->phy.ops.acquire_phy(hw); 523 ret_val = hw->phy.ops.acquire(hw);
523 if (ret_val) 524 if (ret_val)
524 goto out; 525 goto out;
525 } 526 }
@@ -534,7 +535,7 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
534 *data = (u16)kmrnctrlsta; 535 *data = (u16)kmrnctrlsta;
535 536
536 if (!locked) 537 if (!locked)
537 hw->phy.ops.release_phy(hw); 538 hw->phy.ops.release(hw);
538 539
539out: 540out:
540 return ret_val; 541 return ret_val;
@@ -588,10 +589,10 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
588 s32 ret_val = 0; 589 s32 ret_val = 0;
589 590
590 if (!locked) { 591 if (!locked) {
591 if (!(hw->phy.ops.acquire_phy)) 592 if (!(hw->phy.ops.acquire))
592 goto out; 593 goto out;
593 594
594 ret_val = hw->phy.ops.acquire_phy(hw); 595 ret_val = hw->phy.ops.acquire(hw);
595 if (ret_val) 596 if (ret_val)
596 goto out; 597 goto out;
597 } 598 }
@@ -603,7 +604,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
603 udelay(2); 604 udelay(2);
604 605
605 if (!locked) 606 if (!locked)
606 hw->phy.ops.release_phy(hw); 607 hw->phy.ops.release(hw);
607 608
608out: 609out:
609 return ret_val; 610 return ret_val;
@@ -650,7 +651,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
650 u16 phy_data; 651 u16 phy_data;
651 652
652 /* Enable CRS on TX. This must be set for half-duplex operation. */ 653 /* Enable CRS on TX. This must be set for half-duplex operation. */
653 ret_val = phy->ops.read_phy_reg(hw, I82577_CFG_REG, &phy_data); 654 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
654 if (ret_val) 655 if (ret_val)
655 goto out; 656 goto out;
656 657
@@ -659,16 +660,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
659 /* Enable downshift */ 660 /* Enable downshift */
660 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 661 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
661 662
662 ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data); 663 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
663 if (ret_val)
664 goto out;
665
666 /* Set number of link attempts before downshift */
667 ret_val = phy->ops.read_phy_reg(hw, I82577_CTRL_REG, &phy_data);
668 if (ret_val)
669 goto out;
670 phy_data &= ~I82577_CTRL_DOWNSHIFT_MASK;
671 ret_val = phy->ops.write_phy_reg(hw, I82577_CTRL_REG, phy_data);
672 664
673out: 665out:
674 return ret_val; 666 return ret_val;
@@ -786,12 +778,12 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
786 /* Commit the changes. */ 778 /* Commit the changes. */
787 ret_val = e1000e_commit_phy(hw); 779 ret_val = e1000e_commit_phy(hw);
788 if (ret_val) { 780 if (ret_val) {
789 hw_dbg(hw, "Error committing the PHY changes\n"); 781 e_dbg("Error committing the PHY changes\n");
790 return ret_val; 782 return ret_val;
791 } 783 }
792 784
793 if (phy->type == e1000_phy_82578) { 785 if (phy->type == e1000_phy_82578) {
794 ret_val = phy->ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 786 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
795 &phy_data); 787 &phy_data);
796 if (ret_val) 788 if (ret_val)
797 return ret_val; 789 return ret_val;
@@ -799,7 +791,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
799 /* 82578 PHY - set the downshift count to 1x. */ 791 /* 82578 PHY - set the downshift count to 1x. */
800 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 792 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
801 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 793 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
802 ret_val = phy->ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 794 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
803 phy_data); 795 phy_data);
804 if (ret_val) 796 if (ret_val)
805 return ret_val; 797 return ret_val;
@@ -823,7 +815,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
823 815
824 ret_val = e1000_phy_hw_reset(hw); 816 ret_val = e1000_phy_hw_reset(hw);
825 if (ret_val) { 817 if (ret_val) {
826 hw_dbg(hw, "Error resetting the PHY.\n"); 818 e_dbg("Error resetting the PHY.\n");
827 return ret_val; 819 return ret_val;
828 } 820 }
829 821
@@ -834,9 +826,9 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
834 msleep(100); 826 msleep(100);
835 827
836 /* disable lplu d0 during driver init */ 828 /* disable lplu d0 during driver init */
837 ret_val = e1000_set_d0_lplu_state(hw, 0); 829 ret_val = e1000_set_d0_lplu_state(hw, false);
838 if (ret_val) { 830 if (ret_val) {
839 hw_dbg(hw, "Error Disabling LPLU D0\n"); 831 e_dbg("Error Disabling LPLU D0\n");
840 return ret_val; 832 return ret_val;
841 } 833 }
842 /* Configure mdi-mdix settings */ 834 /* Configure mdi-mdix settings */
@@ -972,39 +964,39 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
972 NWAY_AR_10T_HD_CAPS); 964 NWAY_AR_10T_HD_CAPS);
973 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 965 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
974 966
975 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised); 967 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
976 968
977 /* Do we want to advertise 10 Mb Half Duplex? */ 969 /* Do we want to advertise 10 Mb Half Duplex? */
978 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 970 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
979 hw_dbg(hw, "Advertise 10mb Half duplex\n"); 971 e_dbg("Advertise 10mb Half duplex\n");
980 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 972 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
981 } 973 }
982 974
983 /* Do we want to advertise 10 Mb Full Duplex? */ 975 /* Do we want to advertise 10 Mb Full Duplex? */
984 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 976 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
985 hw_dbg(hw, "Advertise 10mb Full duplex\n"); 977 e_dbg("Advertise 10mb Full duplex\n");
986 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 978 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
987 } 979 }
988 980
989 /* Do we want to advertise 100 Mb Half Duplex? */ 981 /* Do we want to advertise 100 Mb Half Duplex? */
990 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 982 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
991 hw_dbg(hw, "Advertise 100mb Half duplex\n"); 983 e_dbg("Advertise 100mb Half duplex\n");
992 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 984 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
993 } 985 }
994 986
995 /* Do we want to advertise 100 Mb Full Duplex? */ 987 /* Do we want to advertise 100 Mb Full Duplex? */
996 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 988 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
997 hw_dbg(hw, "Advertise 100mb Full duplex\n"); 989 e_dbg("Advertise 100mb Full duplex\n");
998 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 990 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
999 } 991 }
1000 992
1001 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 993 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1002 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 994 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1003 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n"); 995 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1004 996
1005 /* Do we want to advertise 1000 Mb Full Duplex? */ 997 /* Do we want to advertise 1000 Mb Full Duplex? */
1006 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 998 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1007 hw_dbg(hw, "Advertise 1000mb Full duplex\n"); 999 e_dbg("Advertise 1000mb Full duplex\n");
1008 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1000 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1009 } 1001 }
1010 1002
@@ -1063,7 +1055,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1063 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1055 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1064 break; 1056 break;
1065 default: 1057 default:
1066 hw_dbg(hw, "Flow control param set incorrectly\n"); 1058 e_dbg("Flow control param set incorrectly\n");
1067 ret_val = -E1000_ERR_CONFIG; 1059 ret_val = -E1000_ERR_CONFIG;
1068 return ret_val; 1060 return ret_val;
1069 } 1061 }
@@ -1072,7 +1064,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1072 if (ret_val) 1064 if (ret_val)
1073 return ret_val; 1065 return ret_val;
1074 1066
1075 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1067 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1076 1068
1077 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1069 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1078 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1070 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
@@ -1109,13 +1101,13 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1109 if (phy->autoneg_advertised == 0) 1101 if (phy->autoneg_advertised == 0)
1110 phy->autoneg_advertised = phy->autoneg_mask; 1102 phy->autoneg_advertised = phy->autoneg_mask;
1111 1103
1112 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n"); 1104 e_dbg("Reconfiguring auto-neg advertisement params\n");
1113 ret_val = e1000_phy_setup_autoneg(hw); 1105 ret_val = e1000_phy_setup_autoneg(hw);
1114 if (ret_val) { 1106 if (ret_val) {
1115 hw_dbg(hw, "Error Setting up Auto-Negotiation\n"); 1107 e_dbg("Error Setting up Auto-Negotiation\n");
1116 return ret_val; 1108 return ret_val;
1117 } 1109 }
1118 hw_dbg(hw, "Restarting Auto-Neg\n"); 1110 e_dbg("Restarting Auto-Neg\n");
1119 1111
1120 /* 1112 /*
1121 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1113 * Restart auto-negotiation by setting the Auto Neg Enable bit and
@@ -1137,7 +1129,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1137 if (phy->autoneg_wait_to_complete) { 1129 if (phy->autoneg_wait_to_complete) {
1138 ret_val = e1000_wait_autoneg(hw); 1130 ret_val = e1000_wait_autoneg(hw);
1139 if (ret_val) { 1131 if (ret_val) {
1140 hw_dbg(hw, "Error while waiting for " 1132 e_dbg("Error while waiting for "
1141 "autoneg to complete\n"); 1133 "autoneg to complete\n");
1142 return ret_val; 1134 return ret_val;
1143 } 1135 }
@@ -1175,10 +1167,10 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1175 * PHY will be set to 10H, 10F, 100H or 100F 1167 * PHY will be set to 10H, 10F, 100H or 100F
1176 * depending on user settings. 1168 * depending on user settings.
1177 */ 1169 */
1178 hw_dbg(hw, "Forcing Speed and Duplex\n"); 1170 e_dbg("Forcing Speed and Duplex\n");
1179 ret_val = e1000_phy_force_speed_duplex(hw); 1171 ret_val = e1000_phy_force_speed_duplex(hw);
1180 if (ret_val) { 1172 if (ret_val) {
1181 hw_dbg(hw, "Error Forcing Speed and Duplex\n"); 1173 e_dbg("Error Forcing Speed and Duplex\n");
1182 return ret_val; 1174 return ret_val;
1183 } 1175 }
1184 } 1176 }
@@ -1195,11 +1187,11 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1195 return ret_val; 1187 return ret_val;
1196 1188
1197 if (link) { 1189 if (link) {
1198 hw_dbg(hw, "Valid link established!!!\n"); 1190 e_dbg("Valid link established!!!\n");
1199 e1000e_config_collision_dist(hw); 1191 e1000e_config_collision_dist(hw);
1200 ret_val = e1000e_config_fc_after_link_up(hw); 1192 ret_val = e1000e_config_fc_after_link_up(hw);
1201 } else { 1193 } else {
1202 hw_dbg(hw, "Unable to establish link!!!\n"); 1194 e_dbg("Unable to establish link!!!\n");
1203 } 1195 }
1204 1196
1205 return ret_val; 1197 return ret_val;
@@ -1245,12 +1237,12 @@ s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1245 if (ret_val) 1237 if (ret_val)
1246 return ret_val; 1238 return ret_val;
1247 1239
1248 hw_dbg(hw, "IGP PSCR: %X\n", phy_data); 1240 e_dbg("IGP PSCR: %X\n", phy_data);
1249 1241
1250 udelay(1); 1242 udelay(1);
1251 1243
1252 if (phy->autoneg_wait_to_complete) { 1244 if (phy->autoneg_wait_to_complete) {
1253 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n"); 1245 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1254 1246
1255 ret_val = e1000e_phy_has_link_generic(hw, 1247 ret_val = e1000e_phy_has_link_generic(hw,
1256 PHY_FORCE_LIMIT, 1248 PHY_FORCE_LIMIT,
@@ -1260,7 +1252,7 @@ s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1260 return ret_val; 1252 return ret_val;
1261 1253
1262 if (!link) 1254 if (!link)
1263 hw_dbg(hw, "Link taking longer than expected.\n"); 1255 e_dbg("Link taking longer than expected.\n");
1264 1256
1265 /* Try once more */ 1257 /* Try once more */
1266 ret_val = e1000e_phy_has_link_generic(hw, 1258 ret_val = e1000e_phy_has_link_generic(hw,
@@ -1304,7 +1296,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1304 if (ret_val) 1296 if (ret_val)
1305 return ret_val; 1297 return ret_val;
1306 1298
1307 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data); 1299 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1308 1300
1309 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); 1301 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1310 if (ret_val) 1302 if (ret_val)
@@ -1322,7 +1314,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1322 return ret_val; 1314 return ret_val;
1323 1315
1324 if (phy->autoneg_wait_to_complete) { 1316 if (phy->autoneg_wait_to_complete) {
1325 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n"); 1317 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1326 1318
1327 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1319 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1328 100000, &link); 1320 100000, &link);
@@ -1330,17 +1322,22 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1330 return ret_val; 1322 return ret_val;
1331 1323
1332 if (!link) { 1324 if (!link) {
1333 /* 1325 if (hw->phy.type != e1000_phy_m88) {
1334 * We didn't get link. 1326 e_dbg("Link taking longer than expected.\n");
1335 * Reset the DSP and cross our fingers. 1327 } else {
1336 */ 1328 /*
1337 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1329 * We didn't get link.
1338 0x001d); 1330 * Reset the DSP and cross our fingers.
1339 if (ret_val) 1331 */
1340 return ret_val; 1332 ret_val = e1e_wphy(hw,
1341 ret_val = e1000e_phy_reset_dsp(hw); 1333 M88E1000_PHY_PAGE_SELECT,
1342 if (ret_val) 1334 0x001d);
1343 return ret_val; 1335 if (ret_val)
1336 return ret_val;
1337 ret_val = e1000e_phy_reset_dsp(hw);
1338 if (ret_val)
1339 return ret_val;
1340 }
1344 } 1341 }
1345 1342
1346 /* Try once more */ 1343 /* Try once more */
@@ -1350,6 +1347,9 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1350 return ret_val; 1347 return ret_val;
1351 } 1348 }
1352 1349
1350 if (hw->phy.type != e1000_phy_m88)
1351 return 0;
1352
1353 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1353 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1354 if (ret_val) 1354 if (ret_val)
1355 return ret_val; 1355 return ret_val;
@@ -1379,6 +1379,73 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1379} 1379}
1380 1380
1381/** 1381/**
1382 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1383 * @hw: pointer to the HW structure
1384 *
1385 * Forces the speed and duplex settings of the PHY.
1386 * This is a function pointer entry point only called by
1387 * PHY setup routines.
1388 **/
1389s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1390{
1391 struct e1000_phy_info *phy = &hw->phy;
1392 s32 ret_val;
1393 u16 data;
1394 bool link;
1395
1396 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1397 if (ret_val)
1398 goto out;
1399
1400 e1000e_phy_force_speed_duplex_setup(hw, &data);
1401
1402 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1403 if (ret_val)
1404 goto out;
1405
1406 /* Disable MDI-X support for 10/100 */
1407 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1408 if (ret_val)
1409 goto out;
1410
1411 data &= ~IFE_PMC_AUTO_MDIX;
1412 data &= ~IFE_PMC_FORCE_MDIX;
1413
1414 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1415 if (ret_val)
1416 goto out;
1417
1418 e_dbg("IFE PMC: %X\n", data);
1419
1420 udelay(1);
1421
1422 if (phy->autoneg_wait_to_complete) {
1423 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1424
1425 ret_val = e1000e_phy_has_link_generic(hw,
1426 PHY_FORCE_LIMIT,
1427 100000,
1428 &link);
1429 if (ret_val)
1430 goto out;
1431
1432 if (!link)
1433 e_dbg("Link taking longer than expected.\n");
1434
1435 /* Try once more */
1436 ret_val = e1000e_phy_has_link_generic(hw,
1437 PHY_FORCE_LIMIT,
1438 100000,
1439 &link);
1440 if (ret_val)
1441 goto out;
1442 }
1443
1444out:
1445 return ret_val;
1446}
1447
1448/**
1382 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1449 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1383 * @hw: pointer to the HW structure 1450 * @hw: pointer to the HW structure
1384 * @phy_ctrl: pointer to current value of PHY_CONTROL 1451 * @phy_ctrl: pointer to current value of PHY_CONTROL
@@ -1413,11 +1480,11 @@ void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1413 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1480 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1414 ctrl &= ~E1000_CTRL_FD; 1481 ctrl &= ~E1000_CTRL_FD;
1415 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1482 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1416 hw_dbg(hw, "Half Duplex\n"); 1483 e_dbg("Half Duplex\n");
1417 } else { 1484 } else {
1418 ctrl |= E1000_CTRL_FD; 1485 ctrl |= E1000_CTRL_FD;
1419 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1486 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1420 hw_dbg(hw, "Full Duplex\n"); 1487 e_dbg("Full Duplex\n");
1421 } 1488 }
1422 1489
1423 /* Forcing 10mb or 100mb? */ 1490 /* Forcing 10mb or 100mb? */
@@ -1425,12 +1492,12 @@ void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1425 ctrl |= E1000_CTRL_SPD_100; 1492 ctrl |= E1000_CTRL_SPD_100;
1426 *phy_ctrl |= MII_CR_SPEED_100; 1493 *phy_ctrl |= MII_CR_SPEED_100;
1427 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1494 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1428 hw_dbg(hw, "Forcing 100mb\n"); 1495 e_dbg("Forcing 100mb\n");
1429 } else { 1496 } else {
1430 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1497 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1431 *phy_ctrl |= MII_CR_SPEED_10; 1498 *phy_ctrl |= MII_CR_SPEED_10;
1432 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1499 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1433 hw_dbg(hw, "Forcing 10mb\n"); 1500 e_dbg("Forcing 10mb\n");
1434 } 1501 }
1435 1502
1436 e1000e_config_collision_dist(hw); 1503 e1000e_config_collision_dist(hw);
@@ -1533,8 +1600,8 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
1533 switch (phy->type) { 1600 switch (phy->type) {
1534 case e1000_phy_m88: 1601 case e1000_phy_m88:
1535 case e1000_phy_gg82563: 1602 case e1000_phy_gg82563:
1603 case e1000_phy_bm:
1536 case e1000_phy_82578: 1604 case e1000_phy_82578:
1537 case e1000_phy_82577:
1538 offset = M88E1000_PHY_SPEC_STATUS; 1605 offset = M88E1000_PHY_SPEC_STATUS;
1539 mask = M88E1000_PSSR_DOWNSHIFT; 1606 mask = M88E1000_PSSR_DOWNSHIFT;
1540 break; 1607 break;
@@ -1545,7 +1612,7 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
1545 break; 1612 break;
1546 default: 1613 default:
1547 /* speed downshift not supported */ 1614 /* speed downshift not supported */
1548 phy->speed_downgraded = 0; 1615 phy->speed_downgraded = false;
1549 return 0; 1616 return 0;
1550 } 1617 }
1551 1618
@@ -1565,7 +1632,7 @@ s32 e1000e_check_downshift(struct e1000_hw *hw)
1565 * 1632 *
1566 * Polarity is determined based on the PHY specific status register. 1633 * Polarity is determined based on the PHY specific status register.
1567 **/ 1634 **/
1568static s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1635s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1569{ 1636{
1570 struct e1000_phy_info *phy = &hw->phy; 1637 struct e1000_phy_info *phy = &hw->phy;
1571 s32 ret_val; 1638 s32 ret_val;
@@ -1590,7 +1657,7 @@ static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1590 * Polarity is determined based on the PHY port status register, and the 1657 * Polarity is determined based on the PHY port status register, and the
1591 * current speed (since there is no polarity at 100Mbps). 1658 * current speed (since there is no polarity at 100Mbps).
1592 **/ 1659 **/
1593static s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1660s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1594{ 1661{
1595 struct e1000_phy_info *phy = &hw->phy; 1662 struct e1000_phy_info *phy = &hw->phy;
1596 s32 ret_val; 1663 s32 ret_val;
@@ -1628,6 +1695,39 @@ static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1628} 1695}
1629 1696
1630/** 1697/**
1698 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1699 * @hw: pointer to the HW structure
1700 *
1701 * Polarity is determined on the polarity reversal feature being enabled.
1702 **/
1703s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1704{
1705 struct e1000_phy_info *phy = &hw->phy;
1706 s32 ret_val;
1707 u16 phy_data, offset, mask;
1708
1709 /*
1710 * Polarity is determined based on the reversal feature being enabled.
1711 */
1712 if (phy->polarity_correction) {
1713 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1714 mask = IFE_PESC_POLARITY_REVERSED;
1715 } else {
1716 offset = IFE_PHY_SPECIAL_CONTROL;
1717 mask = IFE_PSC_FORCE_POLARITY;
1718 }
1719
1720 ret_val = e1e_rphy(hw, offset, &phy_data);
1721
1722 if (!ret_val)
1723 phy->cable_polarity = (phy_data & mask)
1724 ? e1000_rev_polarity_reversed
1725 : e1000_rev_polarity_normal;
1726
1727 return ret_val;
1728}
1729
1730/**
1631 * e1000_wait_autoneg - Wait for auto-neg completion 1731 * e1000_wait_autoneg - Wait for auto-neg completion
1632 * @hw: pointer to the HW structure 1732 * @hw: pointer to the HW structure
1633 * 1733 *
@@ -1727,15 +1827,21 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1727 1827
1728 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1828 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1729 if (ret_val) 1829 if (ret_val)
1730 return ret_val; 1830 goto out;
1731 1831
1732 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1832 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1733 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1833 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1834 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1835 ret_val = -E1000_ERR_PHY;
1836 goto out;
1837 }
1838
1734 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1839 phy->min_cable_length = e1000_m88_cable_length_table[index];
1735 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1840 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1736 1841
1737 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1842 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1738 1843
1844out:
1739 return ret_val; 1845 return ret_val;
1740} 1846}
1741 1847
@@ -1746,7 +1852,7 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1746 * The automatic gain control (agc) normalizes the amplitude of the 1852 * The automatic gain control (agc) normalizes the amplitude of the
1747 * received signal, adjusting for the attenuation produced by the 1853 * received signal, adjusting for the attenuation produced by the
1748 * cable. By reading the AGC registers, which represent the 1854 * cable. By reading the AGC registers, which represent the
1749 * combination of course and fine gain value, the value can be put 1855 * combination of coarse and fine gain value, the value can be put
1750 * into a lookup table to obtain the approximate cable length 1856 * into a lookup table to obtain the approximate cable length
1751 * for each channel. 1857 * for each channel.
1752 **/ 1858 **/
@@ -1771,7 +1877,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1771 1877
1772 /* 1878 /*
1773 * Getting bits 15:9, which represent the combination of 1879 * Getting bits 15:9, which represent the combination of
1774 * course and fine gain values. The result is a number 1880 * coarse and fine gain values. The result is a number
1775 * that can be put into the lookup table to obtain the 1881 * that can be put into the lookup table to obtain the
1776 * approximate cable length. 1882 * approximate cable length.
1777 */ 1883 */
@@ -1825,8 +1931,8 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1825 u16 phy_data; 1931 u16 phy_data;
1826 bool link; 1932 bool link;
1827 1933
1828 if (hw->phy.media_type != e1000_media_type_copper) { 1934 if (phy->media_type != e1000_media_type_copper) {
1829 hw_dbg(hw, "Phy info is only valid for copper media\n"); 1935 e_dbg("Phy info is only valid for copper media\n");
1830 return -E1000_ERR_CONFIG; 1936 return -E1000_ERR_CONFIG;
1831 } 1937 }
1832 1938
@@ -1835,7 +1941,7 @@ s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1835 return ret_val; 1941 return ret_val;
1836 1942
1837 if (!link) { 1943 if (!link) {
1838 hw_dbg(hw, "Phy info is only valid if link is up\n"); 1944 e_dbg("Phy info is only valid if link is up\n");
1839 return -E1000_ERR_CONFIG; 1945 return -E1000_ERR_CONFIG;
1840 } 1946 }
1841 1947
@@ -1903,11 +2009,11 @@ s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1903 return ret_val; 2009 return ret_val;
1904 2010
1905 if (!link) { 2011 if (!link) {
1906 hw_dbg(hw, "Phy info is only valid if link is up\n"); 2012 e_dbg("Phy info is only valid if link is up\n");
1907 return -E1000_ERR_CONFIG; 2013 return -E1000_ERR_CONFIG;
1908 } 2014 }
1909 2015
1910 phy->polarity_correction = 1; 2016 phy->polarity_correction = true;
1911 2017
1912 ret_val = e1000_check_polarity_igp(hw); 2018 ret_val = e1000_check_polarity_igp(hw);
1913 if (ret_val) 2019 if (ret_val)
@@ -1946,6 +2052,61 @@ s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1946} 2052}
1947 2053
1948/** 2054/**
2055 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2056 * @hw: pointer to the HW structure
2057 *
2058 * Populates "phy" structure with various feature states.
2059 **/
2060s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2061{
2062 struct e1000_phy_info *phy = &hw->phy;
2063 s32 ret_val;
2064 u16 data;
2065 bool link;
2066
2067 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2068 if (ret_val)
2069 goto out;
2070
2071 if (!link) {
2072 e_dbg("Phy info is only valid if link is up\n");
2073 ret_val = -E1000_ERR_CONFIG;
2074 goto out;
2075 }
2076
2077 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2078 if (ret_val)
2079 goto out;
2080 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2081 ? false : true;
2082
2083 if (phy->polarity_correction) {
2084 ret_val = e1000_check_polarity_ife(hw);
2085 if (ret_val)
2086 goto out;
2087 } else {
2088 /* Polarity is forced */
2089 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2090 ? e1000_rev_polarity_reversed
2091 : e1000_rev_polarity_normal;
2092 }
2093
2094 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2095 if (ret_val)
2096 goto out;
2097
2098 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2099
2100 /* The following parameters are undefined for 10/100 operation. */
2101 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2102 phy->local_rx = e1000_1000t_rx_status_undefined;
2103 phy->remote_rx = e1000_1000t_rx_status_undefined;
2104
2105out:
2106 return ret_val;
2107}
2108
2109/**
1949 * e1000e_phy_sw_reset - PHY software reset 2110 * e1000e_phy_sw_reset - PHY software reset
1950 * @hw: pointer to the HW structure 2111 * @hw: pointer to the HW structure
1951 * 2112 *
@@ -1990,7 +2151,7 @@ s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1990 if (ret_val) 2151 if (ret_val)
1991 return 0; 2152 return 0;
1992 2153
1993 ret_val = phy->ops.acquire_phy(hw); 2154 ret_val = phy->ops.acquire(hw);
1994 if (ret_val) 2155 if (ret_val)
1995 return ret_val; 2156 return ret_val;
1996 2157
@@ -2005,7 +2166,7 @@ s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2005 2166
2006 udelay(150); 2167 udelay(150);
2007 2168
2008 phy->ops.release_phy(hw); 2169 phy->ops.release(hw);
2009 2170
2010 return e1000_get_phy_cfg_done(hw); 2171 return e1000_get_phy_cfg_done(hw);
2011} 2172}
@@ -2031,7 +2192,7 @@ s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2031 **/ 2192 **/
2032s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) 2193s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2033{ 2194{
2034 hw_dbg(hw, "Running IGP 3 PHY init script\n"); 2195 e_dbg("Running IGP 3 PHY init script\n");
2035 2196
2036 /* PHY init IGP 3 */ 2197 /* PHY init IGP 3 */
2037 /* Enable rise/fall, 10-mode work in class-A */ 2198 /* Enable rise/fall, 10-mode work in class-A */
@@ -2199,28 +2360,34 @@ enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2199s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2360s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2200{ 2361{
2201 s32 ret_val = -E1000_ERR_PHY_TYPE; 2362 s32 ret_val = -E1000_ERR_PHY_TYPE;
2202 u32 phy_addr= 0; 2363 u32 phy_addr = 0;
2203 u32 i = 0; 2364 u32 i;
2204 enum e1000_phy_type phy_type = e1000_phy_unknown; 2365 enum e1000_phy_type phy_type = e1000_phy_unknown;
2205 2366
2206 do { 2367 hw->phy.id = phy_type;
2207 for (phy_addr = 0; phy_addr < 4; phy_addr++) { 2368
2208 hw->phy.addr = phy_addr; 2369 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2370 hw->phy.addr = phy_addr;
2371 i = 0;
2372
2373 do {
2209 e1000e_get_phy_id(hw); 2374 e1000e_get_phy_id(hw);
2210 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2375 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2211 2376
2212 /* 2377 /*
2213 * If phy_type is valid, break - we found our 2378 * If phy_type is valid, break - we found our
2214 * PHY address 2379 * PHY address
2215 */ 2380 */
2216 if (phy_type != e1000_phy_unknown) { 2381 if (phy_type != e1000_phy_unknown) {
2217 ret_val = 0; 2382 ret_val = 0;
2218 break; 2383 goto out;
2219 } 2384 }
2220 } 2385 msleep(1);
2221 i++; 2386 i++;
2222 } while ((ret_val != 0) && (i < 100)); 2387 } while (i < 10);
2388 }
2223 2389
2390out:
2224 return ret_val; 2391 return ret_val;
2225} 2392}
2226 2393
@@ -2256,7 +2423,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2256 u32 page = offset >> IGP_PAGE_SHIFT; 2423 u32 page = offset >> IGP_PAGE_SHIFT;
2257 u32 page_shift = 0; 2424 u32 page_shift = 0;
2258 2425
2259 ret_val = hw->phy.ops.acquire_phy(hw); 2426 ret_val = hw->phy.ops.acquire(hw);
2260 if (ret_val) 2427 if (ret_val)
2261 return ret_val; 2428 return ret_val;
2262 2429
@@ -2294,7 +2461,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2294 data); 2461 data);
2295 2462
2296out: 2463out:
2297 hw->phy.ops.release_phy(hw); 2464 hw->phy.ops.release(hw);
2298 return ret_val; 2465 return ret_val;
2299} 2466}
2300 2467
@@ -2315,7 +2482,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2315 u32 page = offset >> IGP_PAGE_SHIFT; 2482 u32 page = offset >> IGP_PAGE_SHIFT;
2316 u32 page_shift = 0; 2483 u32 page_shift = 0;
2317 2484
2318 ret_val = hw->phy.ops.acquire_phy(hw); 2485 ret_val = hw->phy.ops.acquire(hw);
2319 if (ret_val) 2486 if (ret_val)
2320 return ret_val; 2487 return ret_val;
2321 2488
@@ -2352,7 +2519,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2352 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2519 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2353 data); 2520 data);
2354out: 2521out:
2355 hw->phy.ops.release_phy(hw); 2522 hw->phy.ops.release(hw);
2356 return ret_val; 2523 return ret_val;
2357} 2524}
2358 2525
@@ -2371,7 +2538,7 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2371 s32 ret_val; 2538 s32 ret_val;
2372 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2539 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2373 2540
2374 ret_val = hw->phy.ops.acquire_phy(hw); 2541 ret_val = hw->phy.ops.acquire(hw);
2375 if (ret_val) 2542 if (ret_val)
2376 return ret_val; 2543 return ret_val;
2377 2544
@@ -2397,7 +2564,7 @@ s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2397 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2564 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2398 data); 2565 data);
2399out: 2566out:
2400 hw->phy.ops.release_phy(hw); 2567 hw->phy.ops.release(hw);
2401 return ret_val; 2568 return ret_val;
2402} 2569}
2403 2570
@@ -2415,7 +2582,7 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2415 s32 ret_val; 2582 s32 ret_val;
2416 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2583 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2417 2584
2418 ret_val = hw->phy.ops.acquire_phy(hw); 2585 ret_val = hw->phy.ops.acquire(hw);
2419 if (ret_val) 2586 if (ret_val)
2420 return ret_val; 2587 return ret_val;
2421 2588
@@ -2441,7 +2608,7 @@ s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2441 data); 2608 data);
2442 2609
2443out: 2610out:
2444 hw->phy.ops.release_phy(hw); 2611 hw->phy.ops.release(hw);
2445 return ret_val; 2612 return ret_val;
2446} 2613}
2447 2614
@@ -2474,7 +2641,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2474 /* Gig must be disabled for MDIO accesses to page 800 */ 2641 /* Gig must be disabled for MDIO accesses to page 800 */
2475 if ((hw->mac.type == e1000_pchlan) && 2642 if ((hw->mac.type == e1000_pchlan) &&
2476 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2643 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2477 hw_dbg(hw, "Attempting to access page 800 while gig enabled\n"); 2644 e_dbg("Attempting to access page 800 while gig enabled.\n");
2478 2645
2479 /* All operations in this function are phy address 1 */ 2646 /* All operations in this function are phy address 1 */
2480 hw->phy.addr = 1; 2647 hw->phy.addr = 1;
@@ -2484,20 +2651,26 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2484 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2651 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2485 2652
2486 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2653 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2487 if (ret_val) 2654 if (ret_val) {
2655 e_dbg("Could not read PHY page 769\n");
2488 goto out; 2656 goto out;
2657 }
2489 2658
2490 /* First clear bit 4 to avoid a power state change */ 2659 /* First clear bit 4 to avoid a power state change */
2491 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2660 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2492 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2661 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2493 if (ret_val) 2662 if (ret_val) {
2663 e_dbg("Could not clear PHY page 769 bit 4\n");
2494 goto out; 2664 goto out;
2665 }
2495 2666
2496 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2667 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2497 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2668 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2498 phy_reg | BM_WUC_ENABLE_BIT); 2669 phy_reg | BM_WUC_ENABLE_BIT);
2499 if (ret_val) 2670 if (ret_val) {
2671 e_dbg("Could not write PHY page 769 bit 2\n");
2500 goto out; 2672 goto out;
2673 }
2501 2674
2502 /* Select page 800 */ 2675 /* Select page 800 */
2503 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2676 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -2505,21 +2678,25 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2505 2678
2506 /* Write the page 800 offset value using opcode 0x11 */ 2679 /* Write the page 800 offset value using opcode 0x11 */
2507 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2680 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2508 if (ret_val) 2681 if (ret_val) {
2682 e_dbg("Could not write address opcode to page 800\n");
2509 goto out; 2683 goto out;
2684 }
2510 2685
2511 if (read) { 2686 if (read) {
2512 /* Read the page 800 value using opcode 0x12 */ 2687 /* Read the page 800 value using opcode 0x12 */
2513 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2688 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2514 data); 2689 data);
2515 } else { 2690 } else {
2516 /* Read the page 800 value using opcode 0x12 */ 2691 /* Write the page 800 value using opcode 0x12 */
2517 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2692 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2518 *data); 2693 *data);
2519 } 2694 }
2520 2695
2521 if (ret_val) 2696 if (ret_val) {
2697 e_dbg("Could not access data value from page 800\n");
2522 goto out; 2698 goto out;
2699 }
2523 2700
2524 /* 2701 /*
2525 * Restore 769_17.2 to its original value 2702 * Restore 769_17.2 to its original value
@@ -2530,12 +2707,53 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2530 2707
2531 /* Clear 769_17.2 */ 2708 /* Clear 769_17.2 */
2532 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2709 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2710 if (ret_val) {
2711 e_dbg("Could not clear PHY page 769 bit 2\n");
2712 goto out;
2713 }
2533 2714
2534out: 2715out:
2535 return ret_val; 2716 return ret_val;
2536} 2717}
2537 2718
2538/** 2719/**
2720 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2721 * @hw: pointer to the HW structure
2722 *
2723 * In the case of a PHY power down to save power, or to turn off link during a
2724 * driver unload, or wake on lan is not enabled, restore the link to previous
2725 * settings.
2726 **/
2727void e1000_power_up_phy_copper(struct e1000_hw *hw)
2728{
2729 u16 mii_reg = 0;
2730
2731 /* The PHY will retain its settings across a power down/up cycle */
2732 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2733 mii_reg &= ~MII_CR_POWER_DOWN;
2734 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2735}
2736
2737/**
2738 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2739 * @hw: pointer to the HW structure
2740 *
2741 * In the case of a PHY power down to save power, or to turn off link during a
2742 * driver unload, or wake on lan is not enabled, restore the link to previous
2743 * settings.
2744 **/
2745void e1000_power_down_phy_copper(struct e1000_hw *hw)
2746{
2747 u16 mii_reg = 0;
2748
2749 /* The PHY will retain its settings across a power down/up cycle */
2750 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2751 mii_reg |= MII_CR_POWER_DOWN;
2752 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2753 msleep(1);
2754}
2755
2756/**
2539 * e1000e_commit_phy - Soft PHY reset 2757 * e1000e_commit_phy - Soft PHY reset
2540 * @hw: pointer to the HW structure 2758 * @hw: pointer to the HW structure
2541 * 2759 *
@@ -2544,8 +2762,8 @@ out:
2544 **/ 2762 **/
2545s32 e1000e_commit_phy(struct e1000_hw *hw) 2763s32 e1000e_commit_phy(struct e1000_hw *hw)
2546{ 2764{
2547 if (hw->phy.ops.commit_phy) 2765 if (hw->phy.ops.commit)
2548 return hw->phy.ops.commit_phy(hw); 2766 return hw->phy.ops.commit(hw);
2549 2767
2550 return 0; 2768 return 0;
2551} 2769}
@@ -2624,7 +2842,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2624 bool in_slow_mode = false; 2842 bool in_slow_mode = false;
2625 2843
2626 if (!locked) { 2844 if (!locked) {
2627 ret_val = hw->phy.ops.acquire_phy(hw); 2845 ret_val = hw->phy.ops.acquire(hw);
2628 if (ret_val) 2846 if (ret_val)
2629 return ret_val; 2847 return ret_val;
2630 } 2848 }
@@ -2658,19 +2876,18 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2658 page = 0; 2876 page = 0;
2659 2877
2660 if (reg > MAX_PHY_MULTI_PAGE_REG) { 2878 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2661 if ((hw->phy.type != e1000_phy_82578) || 2879 u32 phy_addr = hw->phy.addr;
2662 ((reg != I82578_ADDR_REG) && 2880
2663 (reg != I82578_ADDR_REG + 1))) { 2881 hw->phy.addr = 1;
2664 u32 phy_addr = hw->phy.addr; 2882
2665 2883 /* Page is shifted left, PHY expects (page x 32) */
2666 hw->phy.addr = 1; 2884 ret_val = e1000e_write_phy_reg_mdic(hw,
2667 2885 IGP01E1000_PHY_PAGE_SELECT,
2668 /* Page is shifted left, PHY expects (page x 32) */ 2886 (page << IGP_PAGE_SHIFT));
2669 ret_val = e1000e_write_phy_reg_mdic(hw, 2887 hw->phy.addr = phy_addr;
2670 IGP01E1000_PHY_PAGE_SELECT, 2888
2671 (page << IGP_PAGE_SHIFT)); 2889 if (ret_val)
2672 hw->phy.addr = phy_addr; 2890 goto out;
2673 }
2674 } 2891 }
2675 2892
2676 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 2893 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2678,10 +2895,10 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2678out: 2895out:
2679 /* Revert to MDIO fast mode, if applicable */ 2896 /* Revert to MDIO fast mode, if applicable */
2680 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 2897 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2681 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 2898 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
2682 2899
2683 if (!locked) 2900 if (!locked)
2684 hw->phy.ops.release_phy(hw); 2901 hw->phy.ops.release(hw);
2685 2902
2686 return ret_val; 2903 return ret_val;
2687} 2904}
@@ -2734,7 +2951,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2734 bool in_slow_mode = false; 2951 bool in_slow_mode = false;
2735 2952
2736 if (!locked) { 2953 if (!locked) {
2737 ret_val = hw->phy.ops.acquire_phy(hw); 2954 ret_val = hw->phy.ops.acquire(hw);
2738 if (ret_val) 2955 if (ret_val)
2739 return ret_val; 2956 return ret_val;
2740 } 2957 }
@@ -2784,19 +3001,18 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2784 } 3001 }
2785 3002
2786 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3003 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2787 if ((hw->phy.type != e1000_phy_82578) || 3004 u32 phy_addr = hw->phy.addr;
2788 ((reg != I82578_ADDR_REG) && 3005
2789 (reg != I82578_ADDR_REG + 1))) { 3006 hw->phy.addr = 1;
2790 u32 phy_addr = hw->phy.addr; 3007
2791 3008 /* Page is shifted left, PHY expects (page x 32) */
2792 hw->phy.addr = 1; 3009 ret_val = e1000e_write_phy_reg_mdic(hw,
2793 3010 IGP01E1000_PHY_PAGE_SELECT,
2794 /* Page is shifted left, PHY expects (page x 32) */ 3011 (page << IGP_PAGE_SHIFT));
2795 ret_val = e1000e_write_phy_reg_mdic(hw, 3012 hw->phy.addr = phy_addr;
2796 IGP01E1000_PHY_PAGE_SELECT, 3013
2797 (page << IGP_PAGE_SHIFT)); 3014 if (ret_val)
2798 hw->phy.addr = phy_addr; 3015 goto out;
2799 }
2800 } 3016 }
2801 3017
2802 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3018 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2805,10 +3021,10 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2805out: 3021out:
2806 /* Revert to MDIO fast mode, if applicable */ 3022 /* Revert to MDIO fast mode, if applicable */
2807 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) 3023 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2808 ret_val = e1000_set_mdio_slow_mode_hv(hw, false); 3024 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
2809 3025
2810 if (!locked) 3026 if (!locked)
2811 hw->phy.ops.release_phy(hw); 3027 hw->phy.ops.release(hw);
2812 3028
2813 return ret_val; 3029 return ret_val;
2814} 3030}
@@ -2884,7 +3100,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2884 /* masking with 0x3F to remove the page from offset */ 3100 /* masking with 0x3F to remove the page from offset */
2885 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3101 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
2886 if (ret_val) { 3102 if (ret_val) {
2887 hw_dbg(hw, "Could not write PHY the HV address register\n"); 3103 e_dbg("Could not write PHY the HV address register\n");
2888 goto out; 3104 goto out;
2889 } 3105 }
2890 3106
@@ -2895,7 +3111,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2895 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); 3111 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
2896 3112
2897 if (ret_val) { 3113 if (ret_val) {
2898 hw_dbg(hw, "Could not read data value from HV data register\n"); 3114 e_dbg("Could not read data value from HV data register\n");
2899 goto out; 3115 goto out;
2900 } 3116 }
2901 3117
@@ -2923,12 +3139,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2923 goto out; 3139 goto out;
2924 3140
2925 /* Do not apply workaround if in PHY loopback bit 14 set */ 3141 /* Do not apply workaround if in PHY loopback bit 14 set */
2926 hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &data); 3142 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
2927 if (data & PHY_CONTROL_LB) 3143 if (data & PHY_CONTROL_LB)
2928 goto out; 3144 goto out;
2929 3145
2930 /* check if link is up and at 1Gbps */ 3146 /* check if link is up and at 1Gbps */
2931 ret_val = hw->phy.ops.read_phy_reg(hw, BM_CS_STATUS, &data); 3147 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
2932 if (ret_val) 3148 if (ret_val)
2933 goto out; 3149 goto out;
2934 3150
@@ -2944,13 +3160,13 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
2944 mdelay(200); 3160 mdelay(200);
2945 3161
2946 /* flush the packets in the fifo buffer */ 3162 /* flush the packets in the fifo buffer */
2947 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL, 3163 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
2948 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3164 HV_MUX_DATA_CTRL_GEN_TO_MAC |
2949 HV_MUX_DATA_CTRL_FORCE_SPEED); 3165 HV_MUX_DATA_CTRL_FORCE_SPEED);
2950 if (ret_val) 3166 if (ret_val)
2951 goto out; 3167 goto out;
2952 3168
2953 ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL, 3169 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
2954 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3170 HV_MUX_DATA_CTRL_GEN_TO_MAC);
2955 3171
2956out: 3172out:
@@ -2971,7 +3187,7 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2971 s32 ret_val; 3187 s32 ret_val;
2972 u16 data; 3188 u16 data;
2973 3189
2974 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data); 3190 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2975 3191
2976 if (!ret_val) 3192 if (!ret_val)
2977 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3193 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
@@ -2996,13 +3212,13 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2996 u16 phy_data; 3212 u16 phy_data;
2997 bool link; 3213 bool link;
2998 3214
2999 ret_val = phy->ops.read_phy_reg(hw, PHY_CONTROL, &phy_data); 3215 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3000 if (ret_val) 3216 if (ret_val)
3001 goto out; 3217 goto out;
3002 3218
3003 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); 3219 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3004 3220
3005 ret_val = phy->ops.write_phy_reg(hw, PHY_CONTROL, phy_data); 3221 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3006 if (ret_val) 3222 if (ret_val)
3007 goto out; 3223 goto out;
3008 3224
@@ -3010,23 +3226,23 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3010 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI 3226 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
3011 * forced whenever speed and duplex are forced. 3227 * forced whenever speed and duplex are forced.
3012 */ 3228 */
3013 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_CTRL_2, &phy_data); 3229 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
3014 if (ret_val) 3230 if (ret_val)
3015 goto out; 3231 goto out;
3016 3232
3017 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; 3233 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
3018 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; 3234 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
3019 3235
3020 ret_val = phy->ops.write_phy_reg(hw, I82577_PHY_CTRL_2, phy_data); 3236 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
3021 if (ret_val) 3237 if (ret_val)
3022 goto out; 3238 goto out;
3023 3239
3024 hw_dbg(hw, "I82577_PHY_CTRL_2: %X\n", phy_data); 3240 e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data);
3025 3241
3026 udelay(1); 3242 udelay(1);
3027 3243
3028 if (phy->autoneg_wait_to_complete) { 3244 if (phy->autoneg_wait_to_complete) {
3029 hw_dbg(hw, "Waiting for forced speed/duplex link on 82577 phy\n"); 3245 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3030 3246
3031 ret_val = e1000e_phy_has_link_generic(hw, 3247 ret_val = e1000e_phy_has_link_generic(hw,
3032 PHY_FORCE_LIMIT, 3248 PHY_FORCE_LIMIT,
@@ -3036,7 +3252,7 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3036 goto out; 3252 goto out;
3037 3253
3038 if (!link) 3254 if (!link)
3039 hw_dbg(hw, "Link taking longer than expected.\n"); 3255 e_dbg("Link taking longer than expected.\n");
3040 3256
3041 /* Try once more */ 3257 /* Try once more */
3042 ret_val = e1000e_phy_has_link_generic(hw, 3258 ret_val = e1000e_phy_has_link_generic(hw,
@@ -3072,7 +3288,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3072 goto out; 3288 goto out;
3073 3289
3074 if (!link) { 3290 if (!link) {
3075 hw_dbg(hw, "Phy info is only valid if link is up\n"); 3291 e_dbg("Phy info is only valid if link is up\n");
3076 ret_val = -E1000_ERR_CONFIG; 3292 ret_val = -E1000_ERR_CONFIG;
3077 goto out; 3293 goto out;
3078 } 3294 }
@@ -3083,7 +3299,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3083 if (ret_val) 3299 if (ret_val)
3084 goto out; 3300 goto out;
3085 3301
3086 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data); 3302 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3087 if (ret_val) 3303 if (ret_val)
3088 goto out; 3304 goto out;
3089 3305
@@ -3095,7 +3311,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3095 if (ret_val) 3311 if (ret_val)
3096 goto out; 3312 goto out;
3097 3313
3098 ret_val = phy->ops.read_phy_reg(hw, PHY_1000T_STATUS, &data); 3314 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3099 if (ret_val) 3315 if (ret_val)
3100 goto out; 3316 goto out;
3101 3317
@@ -3129,7 +3345,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3129 s32 ret_val; 3345 s32 ret_val;
3130 u16 phy_data, length; 3346 u16 phy_data, length;
3131 3347
3132 ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3348 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3133 if (ret_val) 3349 if (ret_val)
3134 goto out; 3350 goto out;
3135 3351
@@ -3137,7 +3353,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3137 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3353 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3138 3354
3139 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3355 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3140 ret_val = E1000_ERR_PHY; 3356 ret_val = -E1000_ERR_PHY;
3141 3357
3142 phy->cable_length = length; 3358 phy->cable_length = length;
3143 3359
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-03 13:19:50 -0400