diff options
Diffstat (limited to 'drivers/net/e1000e/lib.c')
-rw-r--r-- | drivers/net/e1000e/lib.c | 54 |
1 files changed, 38 insertions, 16 deletions
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c index a86c17548c1e..2fa9b36a2c5a 100644 --- a/drivers/net/e1000e/lib.c +++ b/drivers/net/e1000e/lib.c | |||
@@ -125,6 +125,7 @@ void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) | |||
125 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) | 125 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) |
126 | { | 126 | { |
127 | u32 i; | 127 | u32 i; |
128 | u8 mac_addr[ETH_ALEN] = {0}; | ||
128 | 129 | ||
129 | /* Setup the receive address */ | 130 | /* Setup the receive address */ |
130 | e_dbg("Programming MAC Address into RAR[0]\n"); | 131 | e_dbg("Programming MAC Address into RAR[0]\n"); |
@@ -133,12 +134,8 @@ void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) | |||
133 | 134 | ||
134 | /* Zero out the other (rar_entry_count - 1) receive addresses */ | 135 | /* Zero out the other (rar_entry_count - 1) receive addresses */ |
135 | e_dbg("Clearing RAR[1-%u]\n", rar_count-1); | 136 | e_dbg("Clearing RAR[1-%u]\n", rar_count-1); |
136 | for (i = 1; i < rar_count; i++) { | 137 | for (i = 1; i < rar_count; i++) |
137 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); | 138 | e1000e_rar_set(hw, mac_addr, i); |
138 | e1e_flush(); | ||
139 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); | ||
140 | e1e_flush(); | ||
141 | } | ||
142 | } | 139 | } |
143 | 140 | ||
144 | /** | 141 | /** |
@@ -164,10 +161,19 @@ void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) | |||
164 | 161 | ||
165 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | 162 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
166 | 163 | ||
167 | rar_high |= E1000_RAH_AV; | 164 | /* If MAC address zero, no need to set the AV bit */ |
165 | if (rar_low || rar_high) | ||
166 | rar_high |= E1000_RAH_AV; | ||
168 | 167 | ||
169 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); | 168 | /* |
170 | E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); | 169 | * Some bridges will combine consecutive 32-bit writes into |
170 | * a single burst write, which will malfunction on some parts. | ||
171 | * The flushes avoid this. | ||
172 | */ | ||
173 | ew32(RAL(index), rar_low); | ||
174 | e1e_flush(); | ||
175 | ew32(RAH(index), rar_high); | ||
176 | e1e_flush(); | ||
171 | } | 177 | } |
172 | 178 | ||
173 | /** | 179 | /** |
@@ -1609,6 +1615,11 @@ void e1000e_reset_adaptive(struct e1000_hw *hw) | |||
1609 | { | 1615 | { |
1610 | struct e1000_mac_info *mac = &hw->mac; | 1616 | struct e1000_mac_info *mac = &hw->mac; |
1611 | 1617 | ||
1618 | if (!mac->adaptive_ifs) { | ||
1619 | e_dbg("Not in Adaptive IFS mode!\n"); | ||
1620 | goto out; | ||
1621 | } | ||
1622 | |||
1612 | mac->current_ifs_val = 0; | 1623 | mac->current_ifs_val = 0; |
1613 | mac->ifs_min_val = IFS_MIN; | 1624 | mac->ifs_min_val = IFS_MIN; |
1614 | mac->ifs_max_val = IFS_MAX; | 1625 | mac->ifs_max_val = IFS_MAX; |
@@ -1617,6 +1628,8 @@ void e1000e_reset_adaptive(struct e1000_hw *hw) | |||
1617 | 1628 | ||
1618 | mac->in_ifs_mode = false; | 1629 | mac->in_ifs_mode = false; |
1619 | ew32(AIT, 0); | 1630 | ew32(AIT, 0); |
1631 | out: | ||
1632 | return; | ||
1620 | } | 1633 | } |
1621 | 1634 | ||
1622 | /** | 1635 | /** |
@@ -1630,6 +1643,11 @@ void e1000e_update_adaptive(struct e1000_hw *hw) | |||
1630 | { | 1643 | { |
1631 | struct e1000_mac_info *mac = &hw->mac; | 1644 | struct e1000_mac_info *mac = &hw->mac; |
1632 | 1645 | ||
1646 | if (!mac->adaptive_ifs) { | ||
1647 | e_dbg("Not in Adaptive IFS mode!\n"); | ||
1648 | goto out; | ||
1649 | } | ||
1650 | |||
1633 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { | 1651 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { |
1634 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { | 1652 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { |
1635 | mac->in_ifs_mode = true; | 1653 | mac->in_ifs_mode = true; |
@@ -1650,6 +1668,8 @@ void e1000e_update_adaptive(struct e1000_hw *hw) | |||
1650 | ew32(AIT, 0); | 1668 | ew32(AIT, 0); |
1651 | } | 1669 | } |
1652 | } | 1670 | } |
1671 | out: | ||
1672 | return; | ||
1653 | } | 1673 | } |
1654 | 1674 | ||
1655 | /** | 1675 | /** |
@@ -2287,10 +2307,12 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) | |||
2287 | s32 ret_val, hdr_csum, csum; | 2307 | s32 ret_val, hdr_csum, csum; |
2288 | u8 i, len; | 2308 | u8 i, len; |
2289 | 2309 | ||
2310 | hw->mac.tx_pkt_filtering = true; | ||
2311 | |||
2290 | /* No manageability, no filtering */ | 2312 | /* No manageability, no filtering */ |
2291 | if (!e1000e_check_mng_mode(hw)) { | 2313 | if (!e1000e_check_mng_mode(hw)) { |
2292 | hw->mac.tx_pkt_filtering = false; | 2314 | hw->mac.tx_pkt_filtering = false; |
2293 | return 0; | 2315 | goto out; |
2294 | } | 2316 | } |
2295 | 2317 | ||
2296 | /* | 2318 | /* |
@@ -2298,9 +2320,9 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) | |||
2298 | * reason, disable filtering. | 2320 | * reason, disable filtering. |
2299 | */ | 2321 | */ |
2300 | ret_val = e1000_mng_enable_host_if(hw); | 2322 | ret_val = e1000_mng_enable_host_if(hw); |
2301 | if (ret_val != 0) { | 2323 | if (ret_val) { |
2302 | hw->mac.tx_pkt_filtering = false; | 2324 | hw->mac.tx_pkt_filtering = false; |
2303 | return ret_val; | 2325 | goto out; |
2304 | } | 2326 | } |
2305 | 2327 | ||
2306 | /* Read in the header. Length and offset are in dwords. */ | 2328 | /* Read in the header. Length and offset are in dwords. */ |
@@ -2319,17 +2341,17 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) | |||
2319 | */ | 2341 | */ |
2320 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { | 2342 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { |
2321 | hw->mac.tx_pkt_filtering = true; | 2343 | hw->mac.tx_pkt_filtering = true; |
2322 | return 1; | 2344 | goto out; |
2323 | } | 2345 | } |
2324 | 2346 | ||
2325 | /* Cookie area is valid, make the final check for filtering. */ | 2347 | /* Cookie area is valid, make the final check for filtering. */ |
2326 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) { | 2348 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) { |
2327 | hw->mac.tx_pkt_filtering = false; | 2349 | hw->mac.tx_pkt_filtering = false; |
2328 | return 0; | 2350 | goto out; |
2329 | } | 2351 | } |
2330 | 2352 | ||
2331 | hw->mac.tx_pkt_filtering = true; | 2353 | out: |
2332 | return 1; | 2354 | return hw->mac.tx_pkt_filtering; |
2333 | } | 2355 | } |
2334 | 2356 | ||
2335 | /** | 2357 | /** |