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path: root/drivers/net/e1000e/ich8lan.c
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Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
-rw-r--r--drivers/net/e1000e/ich8lan.c270
1 files changed, 219 insertions, 51 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 9e23f50fb9cd..d56c7473144a 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -338,6 +338,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
338{ 338{
339 struct e1000_nvm_info *nvm = &hw->nvm; 339 struct e1000_nvm_info *nvm = &hw->nvm;
340 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 340 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
341 union ich8_hws_flash_status hsfsts;
341 u32 gfpreg; 342 u32 gfpreg;
342 u32 sector_base_addr; 343 u32 sector_base_addr;
343 u32 sector_end_addr; 344 u32 sector_end_addr;
@@ -374,6 +375,20 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
374 /* Adjust to word count */ 375 /* Adjust to word count */
375 nvm->flash_bank_size /= sizeof(u16); 376 nvm->flash_bank_size /= sizeof(u16);
376 377
378 /*
379 * Make sure the flash bank size does not overwrite the 4k
380 * sector ranges. We may have 64k allotted to us but we only care
381 * about the first 2 4k sectors. Therefore, if we have anything less
382 * than 64k set in the HSFSTS register, we will reduce the bank size
383 * down to 4k and let the rest remain unused. If berasesz == 3, then
384 * we are working in 64k mode. Otherwise we are not.
385 */
386 if (nvm->flash_bank_size > E1000_ICH8_SHADOW_RAM_WORDS) {
387 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
388 if (hsfsts.hsf_status.berasesz != 3)
389 nvm->flash_bank_size = E1000_ICH8_SHADOW_RAM_WORDS;
390 }
391
377 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 392 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
378 393
379 /* Clear shadow ram */ 394 /* Clear shadow ram */
@@ -446,6 +461,95 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
446 return 0; 461 return 0;
447} 462}
448 463
464/**
465 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
466 * @hw: pointer to the HW structure
467 *
468 * Checks to see of the link status of the hardware has changed. If a
469 * change in link status has been detected, then we read the PHY registers
470 * to get the current speed/duplex if link exists.
471 **/
472static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
473{
474 struct e1000_mac_info *mac = &hw->mac;
475 s32 ret_val;
476 bool link;
477
478 /*
479 * We only want to go out to the PHY registers to see if Auto-Neg
480 * has completed and/or if our link status has changed. The
481 * get_link_status flag is set upon receiving a Link Status
482 * Change or Rx Sequence Error interrupt.
483 */
484 if (!mac->get_link_status) {
485 ret_val = 0;
486 goto out;
487 }
488
489 if (hw->mac.type == e1000_pchlan) {
490 ret_val = e1000e_write_kmrn_reg(hw,
491 E1000_KMRNCTRLSTA_K1_CONFIG,
492 E1000_KMRNCTRLSTA_K1_ENABLE);
493 if (ret_val)
494 goto out;
495 }
496
497 /*
498 * First we want to see if the MII Status Register reports
499 * link. If so, then we want to get the current speed/duplex
500 * of the PHY.
501 */
502 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
503 if (ret_val)
504 goto out;
505
506 if (!link)
507 goto out; /* No link detected */
508
509 mac->get_link_status = false;
510
511 if (hw->phy.type == e1000_phy_82578) {
512 ret_val = e1000_link_stall_workaround_hv(hw);
513 if (ret_val)
514 goto out;
515 }
516
517 /*
518 * Check if there was DownShift, must be checked
519 * immediately after link-up
520 */
521 e1000e_check_downshift(hw);
522
523 /*
524 * If we are forcing speed/duplex, then we simply return since
525 * we have already determined whether we have link or not.
526 */
527 if (!mac->autoneg) {
528 ret_val = -E1000_ERR_CONFIG;
529 goto out;
530 }
531
532 /*
533 * Auto-Neg is enabled. Auto Speed Detection takes care
534 * of MAC speed/duplex configuration. So we only need to
535 * configure Collision Distance in the MAC.
536 */
537 e1000e_config_collision_dist(hw);
538
539 /*
540 * Configure Flow Control now that Auto-Neg has completed.
541 * First, we need to restore the desired flow control
542 * settings because we may have had to re-autoneg with a
543 * different link partner.
544 */
545 ret_val = e1000e_config_fc_after_link_up(hw);
546 if (ret_val)
547 hw_dbg(hw, "Error configuring flow control\n");
548
549out:
550 return ret_val;
551}
552
449static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 553static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
450{ 554{
451 struct e1000_hw *hw = &adapter->hw; 555 struct e1000_hw *hw = &adapter->hw;
@@ -694,6 +798,38 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
694} 798}
695 799
696/** 800/**
801 * e1000_lan_init_done_ich8lan - Check for PHY config completion
802 * @hw: pointer to the HW structure
803 *
804 * Check the appropriate indication the MAC has finished configuring the
805 * PHY after a software reset.
806 **/
807static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
808{
809 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
810
811 /* Wait for basic configuration completes before proceeding */
812 do {
813 data = er32(STATUS);
814 data &= E1000_STATUS_LAN_INIT_DONE;
815 udelay(100);
816 } while ((!data) && --loop);
817
818 /*
819 * If basic configuration is incomplete before the above loop
820 * count reaches 0, loading the configuration from NVM will
821 * leave the PHY in a bad state possibly resulting in no link.
822 */
823 if (loop == 0)
824 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
825
826 /* Clear the Init Done bit for the next init event */
827 data = er32(STATUS);
828 data &= ~E1000_STATUS_LAN_INIT_DONE;
829 ew32(STATUS, data);
830}
831
832/**
697 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 833 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
698 * @hw: pointer to the HW structure 834 * @hw: pointer to the HW structure
699 * 835 *
@@ -707,13 +843,15 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
707 u32 i; 843 u32 i;
708 u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; 844 u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
709 s32 ret_val; 845 s32 ret_val;
710 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
711 u16 word_addr, reg_data, reg_addr, phy_page = 0; 846 u16 word_addr, reg_data, reg_addr, phy_page = 0;
712 847
713 ret_val = e1000e_phy_hw_reset_generic(hw); 848 ret_val = e1000e_phy_hw_reset_generic(hw);
714 if (ret_val) 849 if (ret_val)
715 return ret_val; 850 return ret_val;
716 851
852 /* Allow time for h/w to get to a quiescent state after reset */
853 mdelay(10);
854
717 if (hw->mac.type == e1000_pchlan) { 855 if (hw->mac.type == e1000_pchlan) {
718 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 856 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
719 if (ret_val) 857 if (ret_val)
@@ -741,26 +879,8 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
741 if (!(data & sw_cfg_mask)) 879 if (!(data & sw_cfg_mask))
742 return 0; 880 return 0;
743 881
744 /* Wait for basic configuration completes before proceeding*/ 882 /* Wait for basic configuration completes before proceeding */
745 do { 883 e1000_lan_init_done_ich8lan(hw);
746 data = er32(STATUS);
747 data &= E1000_STATUS_LAN_INIT_DONE;
748 udelay(100);
749 } while ((!data) && --loop);
750
751 /*
752 * If basic configuration is incomplete before the above loop
753 * count reaches 0, loading the configuration from NVM will
754 * leave the PHY in a bad state possibly resulting in no link.
755 */
756 if (loop == 0) {
757 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
758 }
759
760 /* Clear the Init Done bit for the next init event */
761 data = er32(STATUS);
762 data &= ~E1000_STATUS_LAN_INIT_DONE;
763 ew32(STATUS, data);
764 884
765 /* 885 /*
766 * Make sure HW does not configure LCD from PHY 886 * Make sure HW does not configure LCD from PHY
@@ -961,12 +1081,14 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
961 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 1081 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
962 ew32(PHY_CTRL, phy_ctrl); 1082 ew32(PHY_CTRL, phy_ctrl);
963 1083
1084 if (phy->type != e1000_phy_igp_3)
1085 return 0;
1086
964 /* 1087 /*
965 * Call gig speed drop workaround on LPLU before accessing 1088 * Call gig speed drop workaround on LPLU before accessing
966 * any PHY registers 1089 * any PHY registers
967 */ 1090 */
968 if ((hw->mac.type == e1000_ich8lan) && 1091 if (hw->mac.type == e1000_ich8lan)
969 (hw->phy.type == e1000_phy_igp_3))
970 e1000e_gig_downshift_workaround_ich8lan(hw); 1092 e1000e_gig_downshift_workaround_ich8lan(hw);
971 1093
972 /* When LPLU is enabled, we should disable SmartSpeed */ 1094 /* When LPLU is enabled, we should disable SmartSpeed */
@@ -979,6 +1101,9 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
979 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 1101 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
980 ew32(PHY_CTRL, phy_ctrl); 1102 ew32(PHY_CTRL, phy_ctrl);
981 1103
1104 if (phy->type != e1000_phy_igp_3)
1105 return 0;
1106
982 /* 1107 /*
983 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1108 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
984 * during Dx states where the power conservation is most 1109 * during Dx states where the power conservation is most
@@ -1038,6 +1163,10 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1038 if (!active) { 1163 if (!active) {
1039 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 1164 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1040 ew32(PHY_CTRL, phy_ctrl); 1165 ew32(PHY_CTRL, phy_ctrl);
1166
1167 if (phy->type != e1000_phy_igp_3)
1168 return 0;
1169
1041 /* 1170 /*
1042 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1171 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1043 * during Dx states where the power conservation is most 1172 * during Dx states where the power conservation is most
@@ -1073,12 +1202,14 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1073 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 1202 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1074 ew32(PHY_CTRL, phy_ctrl); 1203 ew32(PHY_CTRL, phy_ctrl);
1075 1204
1205 if (phy->type != e1000_phy_igp_3)
1206 return 0;
1207
1076 /* 1208 /*
1077 * Call gig speed drop workaround on LPLU before accessing 1209 * Call gig speed drop workaround on LPLU before accessing
1078 * any PHY registers 1210 * any PHY registers
1079 */ 1211 */
1080 if ((hw->mac.type == e1000_ich8lan) && 1212 if (hw->mac.type == e1000_ich8lan)
1081 (hw->phy.type == e1000_phy_igp_3))
1082 e1000e_gig_downshift_workaround_ich8lan(hw); 1213 e1000e_gig_downshift_workaround_ich8lan(hw);
1083 1214
1084 /* When LPLU is enabled, we should disable SmartSpeed */ 1215 /* When LPLU is enabled, we should disable SmartSpeed */
@@ -1905,7 +2036,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1905 break; 2036 break;
1906 case 1: 2037 case 1:
1907 sector_size = ICH_FLASH_SEG_SIZE_4K; 2038 sector_size = ICH_FLASH_SEG_SIZE_4K;
1908 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; 2039 iteration = 1;
1909 break; 2040 break;
1910 case 2: 2041 case 2:
1911 if (hw->mac.type == e1000_ich9lan) { 2042 if (hw->mac.type == e1000_ich9lan) {
@@ -1917,7 +2048,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1917 break; 2048 break;
1918 case 3: 2049 case 3:
1919 sector_size = ICH_FLASH_SEG_SIZE_64K; 2050 sector_size = ICH_FLASH_SEG_SIZE_64K;
1920 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; 2051 iteration = 1;
1921 break; 2052 break;
1922 default: 2053 default:
1923 return -E1000_ERR_NVM; 2054 return -E1000_ERR_NVM;
@@ -2143,6 +2274,12 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2143 ctrl = er32(CTRL); 2274 ctrl = er32(CTRL);
2144 2275
2145 if (!e1000_check_reset_block(hw)) { 2276 if (!e1000_check_reset_block(hw)) {
2277 /* Clear PHY Reset Asserted bit */
2278 if (hw->mac.type >= e1000_pchlan) {
2279 u32 status = er32(STATUS);
2280 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2281 }
2282
2146 /* 2283 /*
2147 * PHY HW reset requires MAC CORE reset at the same 2284 * PHY HW reset requires MAC CORE reset at the same
2148 * time to make sure the interface between MAC and the 2285 * time to make sure the interface between MAC and the
@@ -2156,23 +2293,34 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2156 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 2293 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2157 msleep(20); 2294 msleep(20);
2158 2295
2159 if (!ret_val) { 2296 if (!ret_val)
2160 /* release the swflag because it is not reset by
2161 * hardware reset
2162 */
2163 e1000_release_swflag_ich8lan(hw); 2297 e1000_release_swflag_ich8lan(hw);
2164 }
2165 2298
2166 ret_val = e1000e_get_auto_rd_done(hw); 2299 if (ctrl & E1000_CTRL_PHY_RST)
2167 if (ret_val) { 2300 ret_val = hw->phy.ops.get_cfg_done(hw);
2168 /* 2301
2169 * When auto config read does not complete, do not 2302 if (hw->mac.type >= e1000_ich10lan) {
2170 * return with an error. This can happen in situations 2303 e1000_lan_init_done_ich8lan(hw);
2171 * where there is no eeprom and prevents getting link. 2304 } else {
2172 */ 2305 ret_val = e1000e_get_auto_rd_done(hw);
2173 hw_dbg(hw, "Auto Read Done did not complete\n"); 2306 if (ret_val) {
2307 /*
2308 * When auto config read does not complete, do not
2309 * return with an error. This can happen in situations
2310 * where there is no eeprom and prevents getting link.
2311 */
2312 hw_dbg(hw, "Auto Read Done did not complete\n");
2313 }
2174 } 2314 }
2175 2315
2316 /*
2317 * For PCH, this write will make sure that any noise
2318 * will be detected as a CRC error and be dropped rather than show up
2319 * as a bad packet to the DMA engine.
2320 */
2321 if (hw->mac.type == e1000_pchlan)
2322 ew32(CRC_OFFSET, 0x65656565);
2323
2176 ew32(IMC, 0xffffffff); 2324 ew32(IMC, 0xffffffff);
2177 icr = er32(ICR); 2325 icr = er32(ICR);
2178 2326
@@ -2222,6 +2370,18 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2222 for (i = 0; i < mac->mta_reg_count; i++) 2370 for (i = 0; i < mac->mta_reg_count; i++)
2223 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 2371 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2224 2372
2373 /*
2374 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2375 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2376 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2377 */
2378 if (hw->phy.type == e1000_phy_82578) {
2379 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2380 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2381 if (ret_val)
2382 return ret_val;
2383 }
2384
2225 /* Setup link and flow control */ 2385 /* Setup link and flow control */
2226 ret_val = e1000_setup_link_ich8lan(hw); 2386 ret_val = e1000_setup_link_ich8lan(hw);
2227 2387
@@ -2254,16 +2414,6 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2254 ew32(CTRL_EXT, ctrl_ext); 2414 ew32(CTRL_EXT, ctrl_ext);
2255 2415
2256 /* 2416 /*
2257 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2258 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2259 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2260 */
2261 if (hw->phy.type == e1000_phy_82578) {
2262 e1e_rphy(hw, BM_WUC, &i);
2263 e1000e_phy_hw_reset_generic(hw);
2264 }
2265
2266 /*
2267 * Clear all of the statistics registers (clear on read). It is 2417 * Clear all of the statistics registers (clear on read). It is
2268 * important that we do this after we have tried to establish link 2418 * important that we do this after we have tried to establish link
2269 * because the symbol error count will increment wildly if there 2419 * because the symbol error count will increment wildly if there
@@ -2485,6 +2635,14 @@ static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2485 if (ret_val) 2635 if (ret_val)
2486 return ret_val; 2636 return ret_val;
2487 2637
2638 if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
2639 ret_val = e1000e_write_kmrn_reg(hw,
2640 E1000_KMRNCTRLSTA_K1_CONFIG,
2641 E1000_KMRNCTRLSTA_K1_DISABLE);
2642 if (ret_val)
2643 return ret_val;
2644 }
2645
2488 if ((hw->mac.type == e1000_ich8lan) && 2646 if ((hw->mac.type == e1000_ich8lan) &&
2489 (hw->phy.type == e1000_phy_igp_3) && 2647 (hw->phy.type == e1000_phy_igp_3) &&
2490 (*speed == SPEED_1000)) { 2648 (*speed == SPEED_1000)) {
@@ -2850,6 +3008,16 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2850{ 3008{
2851 u32 bank = 0; 3009 u32 bank = 0;
2852 3010
3011 if (hw->mac.type >= e1000_pchlan) {
3012 u32 status = er32(STATUS);
3013
3014 if (status & E1000_STATUS_PHYRA)
3015 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3016 else
3017 hw_dbg(hw,
3018 "PHY Reset Asserted not set - needs delay\n");
3019 }
3020
2853 e1000e_get_cfg_done(hw); 3021 e1000e_get_cfg_done(hw);
2854 3022
2855 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 3023 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
@@ -2921,7 +3089,7 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2921static struct e1000_mac_operations ich8_mac_ops = { 3089static struct e1000_mac_operations ich8_mac_ops = {
2922 .id_led_init = e1000e_id_led_init, 3090 .id_led_init = e1000e_id_led_init,
2923 .check_mng_mode = e1000_check_mng_mode_ich8lan, 3091 .check_mng_mode = e1000_check_mng_mode_ich8lan,
2924 .check_for_link = e1000e_check_for_copper_link, 3092 .check_for_link = e1000_check_for_copper_link_ich8lan,
2925 /* cleanup_led dependent on mac type */ 3093 /* cleanup_led dependent on mac type */
2926 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 3094 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
2927 .get_bus_info = e1000_get_bus_info_ich8lan, 3095 .get_bus_info = e1000_get_bus_info_ich8lan,