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path: root/drivers/net/e1000e/ich8lan.c
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Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
-rw-r--r--drivers/net/e1000e/ich8lan.c54
1 files changed, 25 insertions, 29 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 754590d79f6d..902e4935f3ee 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -3118,7 +3118,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3118 * Reset the phy after disabling host wakeup to reset the Rx buffer. 3118 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3119 */ 3119 */
3120 if (hw->phy.type == e1000_phy_82578) { 3120 if (hw->phy.type == e1000_phy_82578) {
3121 hw->phy.ops.read_reg(hw, BM_WUC, &i); 3121 e1e_rphy(hw, BM_WUC, &i);
3122 ret_val = e1000_phy_hw_reset_ich8lan(hw); 3122 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3123 if (ret_val) 3123 if (ret_val)
3124 return ret_val; 3124 return ret_val;
@@ -3276,9 +3276,8 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3276 (hw->phy.type == e1000_phy_82577)) { 3276 (hw->phy.type == e1000_phy_82577)) {
3277 ew32(FCRTV_PCH, hw->fc.refresh_time); 3277 ew32(FCRTV_PCH, hw->fc.refresh_time);
3278 3278
3279 ret_val = hw->phy.ops.write_reg(hw, 3279 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3280 PHY_REG(BM_PORT_CTRL_PAGE, 27), 3280 hw->fc.pause_time);
3281 hw->fc.pause_time);
3282 if (ret_val) 3281 if (ret_val)
3283 return ret_val; 3282 return ret_val;
3284 } 3283 }
@@ -3342,8 +3341,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3342 return ret_val; 3341 return ret_val;
3343 break; 3342 break;
3344 case e1000_phy_ife: 3343 case e1000_phy_ife:
3345 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, 3344 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3346 &reg_data);
3347 if (ret_val) 3345 if (ret_val)
3348 return ret_val; 3346 return ret_val;
3349 3347
@@ -3361,8 +3359,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3361 reg_data |= IFE_PMC_AUTO_MDIX; 3359 reg_data |= IFE_PMC_AUTO_MDIX;
3362 break; 3360 break;
3363 } 3361 }
3364 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, 3362 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3365 reg_data);
3366 if (ret_val) 3363 if (ret_val)
3367 return ret_val; 3364 return ret_val;
3368 break; 3365 break;
@@ -3646,7 +3643,8 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3646{ 3643{
3647 if (hw->phy.type == e1000_phy_ife) 3644 if (hw->phy.type == e1000_phy_ife)
3648 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 3645 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3649 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 3646 (IFE_PSCL_PROBE_MODE |
3647 IFE_PSCL_PROBE_LEDS_OFF));
3650 3648
3651 ew32(LEDCTL, hw->mac.ledctl_mode1); 3649 ew32(LEDCTL, hw->mac.ledctl_mode1);
3652 return 0; 3650 return 0;
@@ -3660,8 +3658,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3660 **/ 3658 **/
3661static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3659static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3662{ 3660{
3663 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3661 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3664 (u16)hw->mac.ledctl_mode1);
3665} 3662}
3666 3663
3667/** 3664/**
@@ -3672,8 +3669,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3672 **/ 3669 **/
3673static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 3670static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3674{ 3671{
3675 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, 3672 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3676 (u16)hw->mac.ledctl_default);
3677} 3673}
3678 3674
3679/** 3675/**
@@ -3704,7 +3700,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3704 } 3700 }
3705 } 3701 }
3706 3702
3707 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3703 return e1e_wphy(hw, HV_LED_CONFIG, data);
3708} 3704}
3709 3705
3710/** 3706/**
@@ -3735,7 +3731,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3735 } 3731 }
3736 } 3732 }
3737 3733
3738 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); 3734 return e1e_wphy(hw, HV_LED_CONFIG, data);
3739} 3735}
3740 3736
3741/** 3737/**
@@ -3844,20 +3840,20 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3844 if ((hw->phy.type == e1000_phy_82578) || 3840 if ((hw->phy.type == e1000_phy_82578) ||
3845 (hw->phy.type == e1000_phy_82579) || 3841 (hw->phy.type == e1000_phy_82579) ||
3846 (hw->phy.type == e1000_phy_82577)) { 3842 (hw->phy.type == e1000_phy_82577)) {
3847 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data); 3843 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3848 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data); 3844 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3849 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data); 3845 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3850 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data); 3846 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3851 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data); 3847 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3852 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data); 3848 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3853 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data); 3849 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3854 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data); 3850 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3855 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data); 3851 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3856 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data); 3852 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3857 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data); 3853 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3858 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data); 3854 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3859 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data); 3855 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3860 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data); 3856 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3861 } 3857 }
3862} 3858}
3863 3859