1 files changed, 115 insertions, 35 deletions

diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 99df2abf82a9..b6388b9535fd 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -122,6 +122,13 @@
 
 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 
+#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
+
+/* OEM Bits Phy Register */
+#define HV_OEM_BITS            PHY_REG(768, 25)
+#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
+#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
+
 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 /* Offset 04h HSFSTS */
 union ich8_hws_flash_status {
@@ -200,6 +207,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
+static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 
 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 {
@@ -242,7 +250,11 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 
         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
         phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;
+        phy->ops.read_phy_reg_locked  = e1000_read_phy_reg_hv_locked;
+        phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
+        phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
         phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;
+        phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 
         phy->id = e1000_phy_unknown;
@@ -303,6 +315,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
         case IGP03E1000_E_PHY_ID:
                 phy->type = e1000_phy_igp_3;
                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+                phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
+                phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
                 break;
         case IFE_E_PHY_ID:
         case IFE_PLUS_E_PHY_ID:
@@ -568,12 +582,39 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 static DEFINE_MUTEX(nvm_mutex);
 
 /**
+ *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquires the mutex for performing NVM operations.
+ **/
+static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
+{
+        mutex_lock(&nvm_mutex);
+
+        return 0;
+}
+
+/**
+ *  e1000_release_nvm_ich8lan - Release NVM mutex
+ *  @hw: pointer to the HW structure
+ *
+ *  Releases the mutex used while performing NVM operations.
+ **/
+static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
+{
+        mutex_unlock(&nvm_mutex);
+
+        return;
+}
+
+static DEFINE_MUTEX(swflag_mutex);
+
+/**
  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
  *  @hw: pointer to the HW structure
  *
- *  Acquires the software control flag for performing NVM and PHY
- *  operations.  This is a function pointer entry point only called by
- *  read/write routines for the PHY and NVM parts.
+ *  Acquires the software control flag for performing PHY and select
+ *  MAC CSR accesses.
  **/
 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 {
@@ -582,7 +623,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 
         might_sleep();
 
-        mutex_lock(&nvm_mutex);
+        mutex_lock(&swflag_mutex);
 
         while (timeout) {
                 extcnf_ctrl = er32(EXTCNF_CTRL);
@@ -599,7 +640,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
                 goto out;
         }
 
-        timeout = PHY_CFG_TIMEOUT * 2;
+        timeout = SW_FLAG_TIMEOUT;
 
         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
         ew32(EXTCNF_CTRL, extcnf_ctrl);
@@ -623,7 +664,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 
 out:
         if (ret_val)
-                mutex_unlock(&nvm_mutex);
+                mutex_unlock(&swflag_mutex);
 
         return ret_val;
 }
@@ -632,9 +673,8 @@ out:
  *  e1000_release_swflag_ich8lan - Release software control flag
  *  @hw: pointer to the HW structure
  *
- *  Releases the software control flag for performing NVM and PHY operations.
- *  This is a function pointer entry point only called by read/write
- *  routines for the PHY and NVM parts.
+ *  Releases the software control flag for performing PHY and select
+ *  MAC CSR accesses.
  **/
 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 {
@@ -644,7 +684,9 @@ static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
         ew32(EXTCNF_CTRL, extcnf_ctrl);
 
-        mutex_unlock(&nvm_mutex);
+        mutex_unlock(&swflag_mutex);
+
+        return;
 }
 
 /**
@@ -844,7 +886,7 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
         u32 i;
         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
         s32 ret_val;
-        u16 word_addr, reg_data, reg_addr, phy_page = 0;
+        u16 reg, word_addr, reg_data, reg_addr, phy_page = 0;
 
         ret_val = e1000e_phy_hw_reset_generic(hw);
         if (ret_val)
@@ -859,6 +901,10 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
                         return ret_val;
         }
 
+        /* Dummy read to clear the phy wakeup bit after lcd reset */
+        if (hw->mac.type == e1000_pchlan)
+                e1e_rphy(hw, BM_WUC, &reg);
+
         /*
          * Initialize the PHY from the NVM on ICH platforms.  This
          * is needed due to an issue where the NVM configuration is
@@ -1054,6 +1100,38 @@ static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
+ *  @hw: pointer to the HW structure
+ *  @active: true to enable LPLU, false to disable
+ *
+ *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
+ *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
+ *  the phy speed. This function will manually set the LPLU bit and restart
+ *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
+ *  since it configures the same bit.
+ **/
+static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
+{
+        s32 ret_val = 0;
+        u16 oem_reg;
+
+        ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
+        if (ret_val)
+                goto out;
+
+        if (active)
+                oem_reg |= HV_OEM_BITS_LPLU;
+        else
+                oem_reg &= ~HV_OEM_BITS_LPLU;
+
+        oem_reg |= HV_OEM_BITS_RESTART_AN;
+        ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
+
+out:
+        return ret_val;
+}
+
+/**
  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
  *  @hw: pointer to the HW structure
  *  @active: TRUE to enable LPLU, FALSE to disable
@@ -1314,12 +1392,11 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
             (words == 0)) {
                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
-                return -E1000_ERR_NVM;
+                ret_val = -E1000_ERR_NVM;
+                goto out;
         }
 
-        ret_val = e1000_acquire_swflag_ich8lan(hw);
-        if (ret_val)
-                goto out;
+        nvm->ops.acquire_nvm(hw);
 
         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
         if (ret_val) {
@@ -1345,7 +1422,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
                 }
         }
 
-        e1000_release_swflag_ich8lan(hw);
+        nvm->ops.release_nvm(hw);
 
 out:
         if (ret_val)
@@ -1603,11 +1680,15 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
                 return -E1000_ERR_NVM;
         }
 
+        nvm->ops.acquire_nvm(hw);
+
         for (i = 0; i < words; i++) {
                 dev_spec->shadow_ram[offset+i].modified = 1;
                 dev_spec->shadow_ram[offset+i].value = data[i];
         }
 
+        nvm->ops.release_nvm(hw);
+
         return 0;
 }
 
@@ -1637,9 +1718,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
         if (nvm->type != e1000_nvm_flash_sw)
                 goto out;
 
-        ret_val = e1000_acquire_swflag_ich8lan(hw);
-        if (ret_val)
-                goto out;
+        nvm->ops.acquire_nvm(hw);
 
         /*
          * We're writing to the opposite bank so if we're on bank 1,
@@ -1657,7 +1736,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
                 old_bank_offset = 0;
                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
                 if (ret_val) {
-                        e1000_release_swflag_ich8lan(hw);
+                        nvm->ops.release_nvm(hw);
                         goto out;
                 }
         } else {
@@ -1665,7 +1744,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
                 new_bank_offset = 0;
                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
                 if (ret_val) {
-                        e1000_release_swflag_ich8lan(hw);
+                        nvm->ops.release_nvm(hw);
                         goto out;
                 }
         }
@@ -1723,7 +1802,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
         if (ret_val) {
                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
                 hw_dbg(hw, "Flash commit failed.\n");
-                e1000_release_swflag_ich8lan(hw);
+                nvm->ops.release_nvm(hw);
                 goto out;
         }
 
@@ -1736,7 +1815,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
         if (ret_val) {
-                e1000_release_swflag_ich8lan(hw);
+                nvm->ops.release_nvm(hw);
                 goto out;
         }
         data &= 0xBFFF;
@@ -1744,7 +1823,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
                                                        act_offset * 2 + 1,
                                                        (u8)(data >> 8));
         if (ret_val) {
-                e1000_release_swflag_ich8lan(hw);
+                nvm->ops.release_nvm(hw);
                 goto out;
         }
 
@@ -1757,7 +1836,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
         if (ret_val) {
-                e1000_release_swflag_ich8lan(hw);
+                nvm->ops.release_nvm(hw);
                 goto out;
         }
 
@@ -1767,7 +1846,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
                 dev_spec->shadow_ram[i].value = 0xFFFF;
         }
 
-        e1000_release_swflag_ich8lan(hw);
+        nvm->ops.release_nvm(hw);
 
         /*
          * Reload the EEPROM, or else modifications will not appear
@@ -1831,14 +1910,12 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
  **/
 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
 {
+        struct e1000_nvm_info *nvm = &hw->nvm;
         union ich8_flash_protected_range pr0;
         union ich8_hws_flash_status hsfsts;
         u32 gfpreg;
-        s32 ret_val;
 
-        ret_val = e1000_acquire_swflag_ich8lan(hw);
-        if (ret_val)
-                return;
+        nvm->ops.acquire_nvm(hw);
 
         gfpreg = er32flash(ICH_FLASH_GFPREG);
 
@@ -1859,7 +1936,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
         hsfsts.hsf_status.flockdn = true;
         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
 
-        e1000_release_swflag_ich8lan(hw);
+        nvm->ops.release_nvm(hw);
 }
 
 /**
@@ -2229,6 +2306,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
  **/
 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
 {
+        u16 reg;
         u32 ctrl, icr, kab;
         s32 ret_val;
 
@@ -2304,6 +2382,9 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                         hw_dbg(hw, "Auto Read Done did not complete\n");
                 }
         }
+        /* Dummy read to clear the phy wakeup bit after lcd reset */
+        if (hw->mac.type == e1000_pchlan)
+                e1e_rphy(hw, BM_WUC, &reg);
 
         /*
          * For PCH, this write will make sure that any noise
@@ -2843,9 +2924,8 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
                             E1000_PHY_CTRL_GBE_DISABLE;
                 ew32(PHY_CTRL, phy_ctrl);
 
-                /* Workaround SWFLAG unexpectedly set during S0->Sx */
                 if (hw->mac.type == e1000_pchlan)
-                        udelay(500);
+                        e1000_phy_hw_reset_ich8lan(hw);
         default:
                 break;
         }
@@ -3113,9 +3193,9 @@ static struct e1000_phy_operations ich8_phy_ops = {
 };
 
 static struct e1000_nvm_operations ich8_nvm_ops = {
-        .acquire_nvm            = e1000_acquire_swflag_ich8lan,
+        .acquire_nvm            = e1000_acquire_nvm_ich8lan,
         .read_nvm               = e1000_read_nvm_ich8lan,
-        .release_nvm            = e1000_release_swflag_ich8lan,
+        .release_nvm            = e1000_release_nvm_ich8lan,
         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
         .valid_led_default      = e1000_valid_led_default_ich8lan,
         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,