aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/e1000e/ich8lan.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
-rw-r--r--drivers/net/e1000e/ich8lan.c156
1 files changed, 77 insertions, 79 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 101a2714467e..dd94fc2e4b82 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -260,12 +260,12 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
260 phy->reset_delay_us = 100; 260 phy->reset_delay_us = 100;
261 261
262 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; 262 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
263 phy->ops.read_phy_reg = e1000_read_phy_reg_hv; 263 phy->ops.read_reg = e1000_read_phy_reg_hv;
264 phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked; 264 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
265 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 265 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
266 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 266 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
267 phy->ops.write_phy_reg = e1000_write_phy_reg_hv; 267 phy->ops.write_reg = e1000_write_phy_reg_hv;
268 phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked; 268 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
269 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 269 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
270 270
271 phy->id = e1000_phy_unknown; 271 phy->id = e1000_phy_unknown;
@@ -277,8 +277,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
277 phy->ops.force_speed_duplex = 277 phy->ops.force_speed_duplex =
278 e1000_phy_force_speed_duplex_82577; 278 e1000_phy_force_speed_duplex_82577;
279 phy->ops.get_cable_length = e1000_get_cable_length_82577; 279 phy->ops.get_cable_length = e1000_get_cable_length_82577;
280 phy->ops.get_phy_info = e1000_get_phy_info_82577; 280 phy->ops.get_info = e1000_get_phy_info_82577;
281 phy->ops.commit_phy = e1000e_phy_sw_reset; 281 phy->ops.commit = e1000e_phy_sw_reset;
282 } 282 }
283 283
284 return ret_val; 284 return ret_val;
@@ -305,8 +305,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
305 */ 305 */
306 ret_val = e1000e_determine_phy_address(hw); 306 ret_val = e1000e_determine_phy_address(hw);
307 if (ret_val) { 307 if (ret_val) {
308 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; 308 phy->ops.write_reg = e1000e_write_phy_reg_bm;
309 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; 309 phy->ops.read_reg = e1000e_read_phy_reg_bm;
310 ret_val = e1000e_determine_phy_address(hw); 310 ret_val = e1000e_determine_phy_address(hw);
311 if (ret_val) 311 if (ret_val)
312 return ret_val; 312 return ret_val;
@@ -326,8 +326,8 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
326 case IGP03E1000_E_PHY_ID: 326 case IGP03E1000_E_PHY_ID:
327 phy->type = e1000_phy_igp_3; 327 phy->type = e1000_phy_igp_3;
328 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 328 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
329 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked; 329 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
330 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked; 330 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
331 break; 331 break;
332 case IFE_E_PHY_ID: 332 case IFE_E_PHY_ID:
333 case IFE_PLUS_E_PHY_ID: 333 case IFE_PLUS_E_PHY_ID:
@@ -338,9 +338,9 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
338 case BME1000_E_PHY_ID: 338 case BME1000_E_PHY_ID:
339 phy->type = e1000_phy_bm; 339 phy->type = e1000_phy_bm;
340 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 340 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
341 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; 341 phy->ops.read_reg = e1000e_read_phy_reg_bm;
342 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; 342 phy->ops.write_reg = e1000e_write_phy_reg_bm;
343 hw->phy.ops.commit_phy = e1000e_phy_sw_reset; 343 phy->ops.commit = e1000e_phy_sw_reset;
344 break; 344 break;
345 default: 345 default:
346 return -E1000_ERR_PHY; 346 return -E1000_ERR_PHY;
@@ -816,7 +816,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
816 s32 ret_val; 816 s32 ret_val;
817 u16 word_addr, reg_data, reg_addr, phy_page = 0; 817 u16 word_addr, reg_data, reg_addr, phy_page = 0;
818 818
819 ret_val = hw->phy.ops.acquire_phy(hw); 819 ret_val = hw->phy.ops.acquire(hw);
820 if (ret_val) 820 if (ret_val)
821 return ret_val; 821 return ret_val;
822 822
@@ -912,7 +912,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
912 reg_addr &= PHY_REG_MASK; 912 reg_addr &= PHY_REG_MASK;
913 reg_addr |= phy_page; 913 reg_addr |= phy_page;
914 914
915 ret_val = phy->ops.write_phy_reg_locked(hw, 915 ret_val = phy->ops.write_reg_locked(hw,
916 (u32)reg_addr, 916 (u32)reg_addr,
917 reg_data); 917 reg_data);
918 if (ret_val) 918 if (ret_val)
@@ -921,7 +921,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
921 } 921 }
922 922
923out: 923out:
924 hw->phy.ops.release_phy(hw); 924 hw->phy.ops.release(hw);
925 return ret_val; 925 return ret_val;
926} 926}
927 927
@@ -945,15 +945,14 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
945 goto out; 945 goto out;
946 946
947 /* Wrap the whole flow with the sw flag */ 947 /* Wrap the whole flow with the sw flag */
948 ret_val = hw->phy.ops.acquire_phy(hw); 948 ret_val = hw->phy.ops.acquire(hw);
949 if (ret_val) 949 if (ret_val)
950 goto out; 950 goto out;
951 951
952 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 952 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
953 if (link) { 953 if (link) {
954 if (hw->phy.type == e1000_phy_82578) { 954 if (hw->phy.type == e1000_phy_82578) {
955 ret_val = hw->phy.ops.read_phy_reg_locked(hw, 955 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
956 BM_CS_STATUS,
957 &status_reg); 956 &status_reg);
958 if (ret_val) 957 if (ret_val)
959 goto release; 958 goto release;
@@ -969,8 +968,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
969 } 968 }
970 969
971 if (hw->phy.type == e1000_phy_82577) { 970 if (hw->phy.type == e1000_phy_82577) {
972 ret_val = hw->phy.ops.read_phy_reg_locked(hw, 971 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
973 HV_M_STATUS,
974 &status_reg); 972 &status_reg);
975 if (ret_val) 973 if (ret_val)
976 goto release; 974 goto release;
@@ -986,14 +984,14 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
986 } 984 }
987 985
988 /* Link stall fix for link up */ 986 /* Link stall fix for link up */
989 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19), 987 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
990 0x0100); 988 0x0100);
991 if (ret_val) 989 if (ret_val)
992 goto release; 990 goto release;
993 991
994 } else { 992 } else {
995 /* Link stall fix for link down */ 993 /* Link stall fix for link down */
996 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19), 994 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
997 0x4100); 995 0x4100);
998 if (ret_val) 996 if (ret_val)
999 goto release; 997 goto release;
@@ -1002,7 +1000,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1002 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 1000 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1003 1001
1004release: 1002release:
1005 hw->phy.ops.release_phy(hw); 1003 hw->phy.ops.release(hw);
1006out: 1004out:
1007 return ret_val; 1005 return ret_val;
1008} 1006}
@@ -1078,7 +1076,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1078 if (hw->mac.type != e1000_pchlan) 1076 if (hw->mac.type != e1000_pchlan)
1079 return ret_val; 1077 return ret_val;
1080 1078
1081 ret_val = hw->phy.ops.acquire_phy(hw); 1079 ret_val = hw->phy.ops.acquire(hw);
1082 if (ret_val) 1080 if (ret_val)
1083 return ret_val; 1081 return ret_val;
1084 1082
@@ -1092,7 +1090,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1092 1090
1093 mac_reg = er32(PHY_CTRL); 1091 mac_reg = er32(PHY_CTRL);
1094 1092
1095 ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg); 1093 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1096 if (ret_val) 1094 if (ret_val)
1097 goto out; 1095 goto out;
1098 1096
@@ -1113,10 +1111,10 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1113 } 1111 }
1114 /* Restart auto-neg to activate the bits */ 1112 /* Restart auto-neg to activate the bits */
1115 oem_reg |= HV_OEM_BITS_RESTART_AN; 1113 oem_reg |= HV_OEM_BITS_RESTART_AN;
1116 ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg); 1114 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1117 1115
1118out: 1116out:
1119 hw->phy.ops.release_phy(hw); 1117 hw->phy.ops.release(hw);
1120 1118
1121 return ret_val; 1119 return ret_val;
1122} 1120}
@@ -1159,7 +1157,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1159 } 1157 }
1160 1158
1161 /* Select page 0 */ 1159 /* Select page 0 */
1162 ret_val = hw->phy.ops.acquire_phy(hw); 1160 ret_val = hw->phy.ops.acquire(hw);
1163 if (ret_val) 1161 if (ret_val)
1164 return ret_val; 1162 return ret_val;
1165 1163
@@ -1167,7 +1165,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1167 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 1165 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1168 if (ret_val) 1166 if (ret_val)
1169 goto out; 1167 goto out;
1170 hw->phy.ops.release_phy(hw); 1168 hw->phy.ops.release(hw);
1171 1169
1172 /* 1170 /*
1173 * Configure the K1 Si workaround during phy reset assuming there is 1171 * Configure the K1 Si workaround during phy reset assuming there is
@@ -1667,7 +1665,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1667 goto out; 1665 goto out;
1668 } 1666 }
1669 1667
1670 nvm->ops.acquire_nvm(hw); 1668 nvm->ops.acquire(hw);
1671 1669
1672 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 1670 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1673 if (ret_val) { 1671 if (ret_val) {
@@ -1693,7 +1691,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1693 } 1691 }
1694 } 1692 }
1695 1693
1696 nvm->ops.release_nvm(hw); 1694 nvm->ops.release(hw);
1697 1695
1698out: 1696out:
1699 if (ret_val) 1697 if (ret_val)
@@ -1951,14 +1949,14 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1951 return -E1000_ERR_NVM; 1949 return -E1000_ERR_NVM;
1952 } 1950 }
1953 1951
1954 nvm->ops.acquire_nvm(hw); 1952 nvm->ops.acquire(hw);
1955 1953
1956 for (i = 0; i < words; i++) { 1954 for (i = 0; i < words; i++) {
1957 dev_spec->shadow_ram[offset+i].modified = 1; 1955 dev_spec->shadow_ram[offset+i].modified = 1;
1958 dev_spec->shadow_ram[offset+i].value = data[i]; 1956 dev_spec->shadow_ram[offset+i].value = data[i];
1959 } 1957 }
1960 1958
1961 nvm->ops.release_nvm(hw); 1959 nvm->ops.release(hw);
1962 1960
1963 return 0; 1961 return 0;
1964} 1962}
@@ -1989,7 +1987,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1989 if (nvm->type != e1000_nvm_flash_sw) 1987 if (nvm->type != e1000_nvm_flash_sw)
1990 goto out; 1988 goto out;
1991 1989
1992 nvm->ops.acquire_nvm(hw); 1990 nvm->ops.acquire(hw);
1993 1991
1994 /* 1992 /*
1995 * We're writing to the opposite bank so if we're on bank 1, 1993 * We're writing to the opposite bank so if we're on bank 1,
@@ -2007,7 +2005,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2007 old_bank_offset = 0; 2005 old_bank_offset = 0;
2008 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 2006 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2009 if (ret_val) { 2007 if (ret_val) {
2010 nvm->ops.release_nvm(hw); 2008 nvm->ops.release(hw);
2011 goto out; 2009 goto out;
2012 } 2010 }
2013 } else { 2011 } else {
@@ -2015,7 +2013,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2015 new_bank_offset = 0; 2013 new_bank_offset = 0;
2016 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 2014 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2017 if (ret_val) { 2015 if (ret_val) {
2018 nvm->ops.release_nvm(hw); 2016 nvm->ops.release(hw);
2019 goto out; 2017 goto out;
2020 } 2018 }
2021 } 2019 }
@@ -2073,7 +2071,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2073 if (ret_val) { 2071 if (ret_val) {
2074 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 2072 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2075 e_dbg("Flash commit failed.\n"); 2073 e_dbg("Flash commit failed.\n");
2076 nvm->ops.release_nvm(hw); 2074 nvm->ops.release(hw);
2077 goto out; 2075 goto out;
2078 } 2076 }
2079 2077
@@ -2086,7 +2084,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2086 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 2084 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2087 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 2085 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2088 if (ret_val) { 2086 if (ret_val) {
2089 nvm->ops.release_nvm(hw); 2087 nvm->ops.release(hw);
2090 goto out; 2088 goto out;
2091 } 2089 }
2092 data &= 0xBFFF; 2090 data &= 0xBFFF;
@@ -2094,7 +2092,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2094 act_offset * 2 + 1, 2092 act_offset * 2 + 1,
2095 (u8)(data >> 8)); 2093 (u8)(data >> 8));
2096 if (ret_val) { 2094 if (ret_val) {
2097 nvm->ops.release_nvm(hw); 2095 nvm->ops.release(hw);
2098 goto out; 2096 goto out;
2099 } 2097 }
2100 2098
@@ -2107,7 +2105,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2107 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 2105 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2108 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 2106 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2109 if (ret_val) { 2107 if (ret_val) {
2110 nvm->ops.release_nvm(hw); 2108 nvm->ops.release(hw);
2111 goto out; 2109 goto out;
2112 } 2110 }
2113 2111
@@ -2117,7 +2115,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2117 dev_spec->shadow_ram[i].value = 0xFFFF; 2115 dev_spec->shadow_ram[i].value = 0xFFFF;
2118 } 2116 }
2119 2117
2120 nvm->ops.release_nvm(hw); 2118 nvm->ops.release(hw);
2121 2119
2122 /* 2120 /*
2123 * Reload the EEPROM, or else modifications will not appear 2121 * Reload the EEPROM, or else modifications will not appear
@@ -2186,7 +2184,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2186 union ich8_hws_flash_status hsfsts; 2184 union ich8_hws_flash_status hsfsts;
2187 u32 gfpreg; 2185 u32 gfpreg;
2188 2186
2189 nvm->ops.acquire_nvm(hw); 2187 nvm->ops.acquire(hw);
2190 2188
2191 gfpreg = er32flash(ICH_FLASH_GFPREG); 2189 gfpreg = er32flash(ICH_FLASH_GFPREG);
2192 2190
@@ -2207,7 +2205,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2207 hsfsts.hsf_status.flockdn = true; 2205 hsfsts.hsf_status.flockdn = true;
2208 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2206 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2209 2207
2210 nvm->ops.release_nvm(hw); 2208 nvm->ops.release(hw);
2211} 2209}
2212 2210
2213/** 2211/**
@@ -2743,7 +2741,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2743 * Reset the phy after disabling host wakeup to reset the Rx buffer. 2741 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2744 */ 2742 */
2745 if (hw->phy.type == e1000_phy_82578) { 2743 if (hw->phy.type == e1000_phy_82578) {
2746 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i); 2744 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2747 ret_val = e1000_phy_hw_reset_ich8lan(hw); 2745 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2748 if (ret_val) 2746 if (ret_val)
2749 return ret_val; 2747 return ret_val;
@@ -2890,7 +2888,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2890 ew32(FCTTV, hw->fc.pause_time); 2888 ew32(FCTTV, hw->fc.pause_time);
2891 if ((hw->phy.type == e1000_phy_82578) || 2889 if ((hw->phy.type == e1000_phy_82578) ||
2892 (hw->phy.type == e1000_phy_82577)) { 2890 (hw->phy.type == e1000_phy_82577)) {
2893 ret_val = hw->phy.ops.write_phy_reg(hw, 2891 ret_val = hw->phy.ops.write_reg(hw,
2894 PHY_REG(BM_PORT_CTRL_PAGE, 27), 2892 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2895 hw->fc.pause_time); 2893 hw->fc.pause_time);
2896 if (ret_val) 2894 if (ret_val)
@@ -2953,7 +2951,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2953 return ret_val; 2951 return ret_val;
2954 break; 2952 break;
2955 case e1000_phy_ife: 2953 case e1000_phy_ife:
2956 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, 2954 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2957 &reg_data); 2955 &reg_data);
2958 if (ret_val) 2956 if (ret_val)
2959 return ret_val; 2957 return ret_val;
@@ -2972,7 +2970,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2972 reg_data |= IFE_PMC_AUTO_MDIX; 2970 reg_data |= IFE_PMC_AUTO_MDIX;
2973 break; 2971 break;
2974 } 2972 }
2975 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, 2973 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2976 reg_data); 2974 reg_data);
2977 if (ret_val) 2975 if (ret_val)
2978 return ret_val; 2976 return ret_val;
@@ -3274,7 +3272,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3274 **/ 3272 **/
3275static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 3273static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3276{ 3274{
3277 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, 3275 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3278 (u16)hw->mac.ledctl_mode1); 3276 (u16)hw->mac.ledctl_mode1);
3279} 3277}
3280 3278
@@ -3286,7 +3284,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3286 **/ 3284 **/
3287static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 3285static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3288{ 3286{
3289 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, 3287 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3290 (u16)hw->mac.ledctl_default); 3288 (u16)hw->mac.ledctl_default);
3291} 3289}
3292 3290
@@ -3318,7 +3316,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3318 } 3316 }
3319 } 3317 }
3320 3318
3321 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); 3319 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3322} 3320}
3323 3321
3324/** 3322/**
@@ -3349,7 +3347,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3349 } 3347 }
3350 } 3348 }
3351 3349
3352 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); 3350 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3353} 3351}
3354 3352
3355/** 3353/**
@@ -3426,20 +3424,20 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3426 /* Clear PHY statistics registers */ 3424 /* Clear PHY statistics registers */
3427 if ((hw->phy.type == e1000_phy_82578) || 3425 if ((hw->phy.type == e1000_phy_82578) ||
3428 (hw->phy.type == e1000_phy_82577)) { 3426 (hw->phy.type == e1000_phy_82577)) {
3429 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 3427 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3430 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 3428 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3431 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 3429 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3432 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 3430 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3433 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 3431 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3434 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 3432 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3435 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 3433 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3436 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 3434 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3437 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 3435 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3438 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 3436 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3439 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data); 3437 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3440 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data); 3438 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3441 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 3439 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3442 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 3440 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3443 } 3441 }
3444} 3442}
3445 3443
@@ -3462,29 +3460,29 @@ static struct e1000_mac_operations ich8_mac_ops = {
3462}; 3460};
3463 3461
3464static struct e1000_phy_operations ich8_phy_ops = { 3462static struct e1000_phy_operations ich8_phy_ops = {
3465 .acquire_phy = e1000_acquire_swflag_ich8lan, 3463 .acquire = e1000_acquire_swflag_ich8lan,
3466 .check_reset_block = e1000_check_reset_block_ich8lan, 3464 .check_reset_block = e1000_check_reset_block_ich8lan,
3467 .commit_phy = NULL, 3465 .commit = NULL,
3468 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, 3466 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
3469 .get_cfg_done = e1000_get_cfg_done_ich8lan, 3467 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3470 .get_cable_length = e1000e_get_cable_length_igp_2, 3468 .get_cable_length = e1000e_get_cable_length_igp_2,
3471 .get_phy_info = e1000_get_phy_info_ich8lan, 3469 .get_info = e1000_get_phy_info_ich8lan,
3472 .read_phy_reg = e1000e_read_phy_reg_igp, 3470 .read_reg = e1000e_read_phy_reg_igp,
3473 .release_phy = e1000_release_swflag_ich8lan, 3471 .release = e1000_release_swflag_ich8lan,
3474 .reset_phy = e1000_phy_hw_reset_ich8lan, 3472 .reset = e1000_phy_hw_reset_ich8lan,
3475 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 3473 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3476 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 3474 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3477 .write_phy_reg = e1000e_write_phy_reg_igp, 3475 .write_reg = e1000e_write_phy_reg_igp,
3478}; 3476};
3479 3477
3480static struct e1000_nvm_operations ich8_nvm_ops = { 3478static struct e1000_nvm_operations ich8_nvm_ops = {
3481 .acquire_nvm = e1000_acquire_nvm_ich8lan, 3479 .acquire = e1000_acquire_nvm_ich8lan,
3482 .read_nvm = e1000_read_nvm_ich8lan, 3480 .read = e1000_read_nvm_ich8lan,
3483 .release_nvm = e1000_release_nvm_ich8lan, 3481 .release = e1000_release_nvm_ich8lan,
3484 .update_nvm = e1000_update_nvm_checksum_ich8lan, 3482 .update = e1000_update_nvm_checksum_ich8lan,
3485 .valid_led_default = e1000_valid_led_default_ich8lan, 3483 .valid_led_default = e1000_valid_led_default_ich8lan,
3486 .validate_nvm = e1000_validate_nvm_checksum_ich8lan, 3484 .validate = e1000_validate_nvm_checksum_ich8lan,
3487 .write_nvm = e1000_write_nvm_ich8lan, 3485 .write = e1000_write_nvm_ich8lan,
3488}; 3486};
3489 3487
3490struct e1000_info e1000_ich8_info = { 3488struct e1000_info e1000_ich8_info = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 10:35:10 -0500