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-rw-r--r--drivers/net/e1000e/hw.h864
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diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
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1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
32#include <linux/types.h>
33
34struct e1000_hw;
35struct e1000_adapter;
36
37#include "defines.h"
38
39#define er32(reg) __er32(hw, E1000_##reg)
40#define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41#define e1e_flush() er32(STATUS)
42
43#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
45
46#define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) << 2)))
48
49enum e1e_registers {
50 E1000_CTRL = 0x00000, /* Device Control - RW */
51 E1000_STATUS = 0x00008, /* Device Status - RO */
52 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
53 E1000_EERD = 0x00014, /* EEPROM Read - RW */
54 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
55 E1000_FLA = 0x0001C, /* Flash Access - RW */
56 E1000_MDIC = 0x00020, /* MDI Control - RW */
57 E1000_SCTL = 0x00024, /* SerDes Control - RW */
58 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
59 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
60 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
61 E1000_FCT = 0x00030, /* Flow Control Type - RW */
62 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
63 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
64 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
65 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
68 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
69 E1000_RCTL = 0x00100, /* RX Control - RW */
70 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
71 E1000_TXCW = 0x00178, /* TX Configuration Word - RW */
72 E1000_RXCW = 0x00180, /* RX Configuration Word - RO */
73 E1000_TCTL = 0x00400, /* TX Control - RW */
74 E1000_TCTL_EXT = 0x00404, /* Extended TX Control - RW */
75 E1000_TIPG = 0x00410, /* TX Inter-packet gap -RW */
76 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle - RW */
77 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
78 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
79 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
80 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
81 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
82 E1000_PBS = 0x01008, /* Packet Buffer Size */
83 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
84 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
85 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
86 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
87 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
88 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
89 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
90 E1000_RDBAL = 0x02800, /* RX Descriptor Base Address Low - RW */
91 E1000_RDBAH = 0x02804, /* RX Descriptor Base Address High - RW */
92 E1000_RDLEN = 0x02808, /* RX Descriptor Length - RW */
93 E1000_RDH = 0x02810, /* RX Descriptor Head - RW */
94 E1000_RDT = 0x02818, /* RX Descriptor Tail - RW */
95 E1000_RDTR = 0x02820, /* RX Delay Timer - RW */
96 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
97
98/* Convenience macros
99 *
100 * Note: "_n" is the queue number of the register to be written to.
101 *
102 * Example usage:
103 * E1000_RDBAL_REG(current_rx_queue)
104 *
105 */
106#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
107 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
108 E1000_TDBAL = 0x03800, /* TX Descriptor Base Address Low - RW */
109 E1000_TDBAH = 0x03804, /* TX Descriptor Base Address High - RW */
110 E1000_TDLEN = 0x03808, /* TX Descriptor Length - RW */
111 E1000_TDH = 0x03810, /* TX Descriptor Head - RW */
112 E1000_TDT = 0x03818, /* TX Descriptor Tail - RW */
113 E1000_TIDV = 0x03820, /* TX Interrupt Delay Value - RW */
114 E1000_TXDCTL = 0x03828, /* TX Descriptor Control - RW */
115 E1000_TADV = 0x0382C, /* TX Interrupt Absolute Delay Val - RW */
116 E1000_TARC0 = 0x03840, /* TX Arbitration Count (0) */
117 E1000_TXDCTL1 = 0x03928, /* TX Descriptor Control (1) - RW */
118 E1000_TARC1 = 0x03940, /* TX Arbitration Count (1) */
119 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
120 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
121 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
122 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
123 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
124 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
125 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
126 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
127 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
128 E1000_COLC = 0x04028, /* Collision Count - R/clr */
129 E1000_DC = 0x04030, /* Defer Count - R/clr */
130 E1000_TNCRS = 0x04034, /* TX-No CRS - R/clr */
131 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
132 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
133 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
134 E1000_XONRXC = 0x04048, /* XON RX Count - R/clr */
135 E1000_XONTXC = 0x0404C, /* XON TX Count - R/clr */
136 E1000_XOFFRXC = 0x04050, /* XOFF RX Count - R/clr */
137 E1000_XOFFTXC = 0x04054, /* XOFF TX Count - R/clr */
138 E1000_FCRUC = 0x04058, /* Flow Control RX Unsupported Count- R/clr */
139 E1000_PRC64 = 0x0405C, /* Packets RX (64 bytes) - R/clr */
140 E1000_PRC127 = 0x04060, /* Packets RX (65-127 bytes) - R/clr */
141 E1000_PRC255 = 0x04064, /* Packets RX (128-255 bytes) - R/clr */
142 E1000_PRC511 = 0x04068, /* Packets RX (255-511 bytes) - R/clr */
143 E1000_PRC1023 = 0x0406C, /* Packets RX (512-1023 bytes) - R/clr */
144 E1000_PRC1522 = 0x04070, /* Packets RX (1024-1522 bytes) - R/clr */
145 E1000_GPRC = 0x04074, /* Good Packets RX Count - R/clr */
146 E1000_BPRC = 0x04078, /* Broadcast Packets RX Count - R/clr */
147 E1000_MPRC = 0x0407C, /* Multicast Packets RX Count - R/clr */
148 E1000_GPTC = 0x04080, /* Good Packets TX Count - R/clr */
149 E1000_GORCL = 0x04088, /* Good Octets RX Count Low - R/clr */
150 E1000_GORCH = 0x0408C, /* Good Octets RX Count High - R/clr */
151 E1000_GOTCL = 0x04090, /* Good Octets TX Count Low - R/clr */
152 E1000_GOTCH = 0x04094, /* Good Octets TX Count High - R/clr */
153 E1000_RNBC = 0x040A0, /* RX No Buffers Count - R/clr */
154 E1000_RUC = 0x040A4, /* RX Undersize Count - R/clr */
155 E1000_RFC = 0x040A8, /* RX Fragment Count - R/clr */
156 E1000_ROC = 0x040AC, /* RX Oversize Count - R/clr */
157 E1000_RJC = 0x040B0, /* RX Jabber Count - R/clr */
158 E1000_MGTPRC = 0x040B4, /* Management Packets RX Count - R/clr */
159 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
160 E1000_MGTPTC = 0x040BC, /* Management Packets TX Count - R/clr */
161 E1000_TORL = 0x040C0, /* Total Octets RX Low - R/clr */
162 E1000_TORH = 0x040C4, /* Total Octets RX High - R/clr */
163 E1000_TOTL = 0x040C8, /* Total Octets TX Low - R/clr */
164 E1000_TOTH = 0x040CC, /* Total Octets TX High - R/clr */
165 E1000_TPR = 0x040D0, /* Total Packets RX - R/clr */
166 E1000_TPT = 0x040D4, /* Total Packets TX - R/clr */
167 E1000_PTC64 = 0x040D8, /* Packets TX (64 bytes) - R/clr */
168 E1000_PTC127 = 0x040DC, /* Packets TX (65-127 bytes) - R/clr */
169 E1000_PTC255 = 0x040E0, /* Packets TX (128-255 bytes) - R/clr */
170 E1000_PTC511 = 0x040E4, /* Packets TX (256-511 bytes) - R/clr */
171 E1000_PTC1023 = 0x040E8, /* Packets TX (512-1023 bytes) - R/clr */
172 E1000_PTC1522 = 0x040EC, /* Packets TX (1024-1522 Bytes) - R/clr */
173 E1000_MPTC = 0x040F0, /* Multicast Packets TX Count - R/clr */
174 E1000_BPTC = 0x040F4, /* Broadcast Packets TX Count - R/clr */
175 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context TX - R/clr */
176 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context TX Fail - R/clr */
177 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
178 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
179 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
180 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
181 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
182 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
183 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
184 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
185 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
186 E1000_RXCSUM = 0x05000, /* RX Checksum Control - RW */
187 E1000_RFCTL = 0x05008, /* Receive Filter Control*/
188 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
189 E1000_RA = 0x05400, /* Receive Address - RW Array */
190 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
191 E1000_WUC = 0x05800, /* Wakeup Control - RW */
192 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
193 E1000_WUS = 0x05810, /* Wakeup Status - RO */
194 E1000_MANC = 0x05820, /* Management Control - RW */
195 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
196 E1000_HOST_IF = 0x08800, /* Host Interface */
197
198 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
199 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
200 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
201 E1000_GCR = 0x05B00, /* PCI-Ex Control */
202 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
203 E1000_SWSM = 0x05B50, /* SW Semaphore */
204 E1000_FWSM = 0x05B54, /* FW Semaphore */
205 E1000_HICR = 0x08F00, /* Host Inteface Control */
206};
207
208/* RSS registers */
209
210/* IGP01E1000 Specific Registers */
211#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
212#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
213#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
214#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
215#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
216#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
217
218#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
219#define IGP01E1000_PHY_POLARITY_MASK 0x0078
220
221#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
222#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
223
224#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
225
226#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
227#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
228#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
229
230#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
231
232#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
233#define IGP01E1000_PSSR_MDIX 0x0008
234#define IGP01E1000_PSSR_SPEED_MASK 0xC000
235#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
236
237#define IGP02E1000_PHY_CHANNEL_NUM 4
238#define IGP02E1000_PHY_AGC_A 0x11B1
239#define IGP02E1000_PHY_AGC_B 0x12B1
240#define IGP02E1000_PHY_AGC_C 0x14B1
241#define IGP02E1000_PHY_AGC_D 0x18B1
242
243#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
244#define IGP02E1000_AGC_LENGTH_MASK 0x7F
245#define IGP02E1000_AGC_RANGE 15
246
247/* manage.c */
248#define E1000_VFTA_ENTRY_SHIFT 5
249#define E1000_VFTA_ENTRY_MASK 0x7F
250#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
251
252#define E1000_HICR_EN 0x01 /* Enable bit - RO */
253#define E1000_HICR_C 0x02 /* Driver sets this bit when done
254 * to put command in RAM */
255#define E1000_HICR_FW_RESET_ENABLE 0x40
256#define E1000_HICR_FW_RESET 0x80
257
258#define E1000_FWSM_MODE_MASK 0xE
259#define E1000_FWSM_MODE_SHIFT 1
260
261#define E1000_MNG_IAMT_MODE 0x3
262#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
263#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
264#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
265#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
266#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
267#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
268
269/* nvm.c */
270#define E1000_STM_OPCODE 0xDB00
271
272#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
273#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
274#define E1000_KMRNCTRLSTA_REN 0x00200000
275#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
276#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
277
278#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
279#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
280#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
281#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
282
283/* IFE PHY Extended Status Control */
284#define IFE_PESC_POLARITY_REVERSED 0x0100
285
286/* IFE PHY Special Control */
287#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
288#define IFE_PSC_FORCE_POLARITY 0x0020
289
290/* IFE PHY Special Control and LED Control */
291#define IFE_PSCL_PROBE_MODE 0x0020
292#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
293#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
294
295/* IFE PHY MDIX Control */
296#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
297#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
298#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
299
300#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
301
302#define E1000_DEV_ID_82571EB_COPPER 0x105E
303#define E1000_DEV_ID_82571EB_FIBER 0x105F
304#define E1000_DEV_ID_82571EB_SERDES 0x1060
305#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
306#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
307#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
308#define E1000_DEV_ID_82572EI_COPPER 0x107D
309#define E1000_DEV_ID_82572EI_FIBER 0x107E
310#define E1000_DEV_ID_82572EI_SERDES 0x107F
311#define E1000_DEV_ID_82572EI 0x10B9
312#define E1000_DEV_ID_82573E 0x108B
313#define E1000_DEV_ID_82573E_IAMT 0x108C
314#define E1000_DEV_ID_82573L 0x109A
315
316#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
317#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
318#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
319#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
320
321#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
322#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
323#define E1000_DEV_ID_ICH8_IGP_C 0x104B
324#define E1000_DEV_ID_ICH8_IFE 0x104C
325#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
326#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
327#define E1000_DEV_ID_ICH8_IGP_M 0x104D
328#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
329#define E1000_DEV_ID_ICH9_IGP_C 0x294C
330#define E1000_DEV_ID_ICH9_IFE 0x10C0
331#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
332#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
333
334#define E1000_FUNC_1 1
335
336enum e1000_mac_type {
337 e1000_82571,
338 e1000_82572,
339 e1000_82573,
340 e1000_80003es2lan,
341 e1000_ich8lan,
342 e1000_ich9lan,
343};
344
345enum e1000_media_type {
346 e1000_media_type_unknown = 0,
347 e1000_media_type_copper = 1,
348 e1000_media_type_fiber = 2,
349 e1000_media_type_internal_serdes = 3,
350 e1000_num_media_types
351};
352
353enum e1000_nvm_type {
354 e1000_nvm_unknown = 0,
355 e1000_nvm_none,
356 e1000_nvm_eeprom_spi,
357 e1000_nvm_flash_hw,
358 e1000_nvm_flash_sw
359};
360
361enum e1000_nvm_override {
362 e1000_nvm_override_none = 0,
363 e1000_nvm_override_spi_small,
364 e1000_nvm_override_spi_large
365};
366
367enum e1000_phy_type {
368 e1000_phy_unknown = 0,
369 e1000_phy_none,
370 e1000_phy_m88,
371 e1000_phy_igp,
372 e1000_phy_igp_2,
373 e1000_phy_gg82563,
374 e1000_phy_igp_3,
375 e1000_phy_ife,
376};
377
378enum e1000_bus_width {
379 e1000_bus_width_unknown = 0,
380 e1000_bus_width_pcie_x1,
381 e1000_bus_width_pcie_x2,
382 e1000_bus_width_pcie_x4 = 4,
383 e1000_bus_width_32,
384 e1000_bus_width_64,
385 e1000_bus_width_reserved
386};
387
388enum e1000_1000t_rx_status {
389 e1000_1000t_rx_status_not_ok = 0,
390 e1000_1000t_rx_status_ok,
391 e1000_1000t_rx_status_undefined = 0xFF
392};
393
394enum e1000_rev_polarity{
395 e1000_rev_polarity_normal = 0,
396 e1000_rev_polarity_reversed,
397 e1000_rev_polarity_undefined = 0xFF
398};
399
400enum e1000_fc_mode {
401 e1000_fc_none = 0,
402 e1000_fc_rx_pause,
403 e1000_fc_tx_pause,
404 e1000_fc_full,
405 e1000_fc_default = 0xFF
406};
407
408enum e1000_ms_type {
409 e1000_ms_hw_default = 0,
410 e1000_ms_force_master,
411 e1000_ms_force_slave,
412 e1000_ms_auto
413};
414
415enum e1000_smart_speed {
416 e1000_smart_speed_default = 0,
417 e1000_smart_speed_on,
418 e1000_smart_speed_off
419};
420
421/* Receive Descriptor */
422struct e1000_rx_desc {
423 u64 buffer_addr; /* Address of the descriptor's data buffer */
424 u16 length; /* Length of data DMAed into data buffer */
425 u16 csum; /* Packet checksum */
426 u8 status; /* Descriptor status */
427 u8 errors; /* Descriptor Errors */
428 u16 special;
429};
430
431/* Receive Descriptor - Extended */
432union e1000_rx_desc_extended {
433 struct {
434 u64 buffer_addr;
435 u64 reserved;
436 } read;
437 struct {
438 struct {
439 u32 mrq; /* Multiple Rx Queues */
440 union {
441 u32 rss; /* RSS Hash */
442 struct {
443 u16 ip_id; /* IP id */
444 u16 csum; /* Packet Checksum */
445 } csum_ip;
446 } hi_dword;
447 } lower;
448 struct {
449 u32 status_error; /* ext status/error */
450 u16 length;
451 u16 vlan; /* VLAN tag */
452 } upper;
453 } wb; /* writeback */
454};
455
456#define MAX_PS_BUFFERS 4
457/* Receive Descriptor - Packet Split */
458union e1000_rx_desc_packet_split {
459 struct {
460 /* one buffer for protocol header(s), three data buffers */
461 u64 buffer_addr[MAX_PS_BUFFERS];
462 } read;
463 struct {
464 struct {
465 u32 mrq; /* Multiple Rx Queues */
466 union {
467 u32 rss; /* RSS Hash */
468 struct {
469 u16 ip_id; /* IP id */
470 u16 csum; /* Packet Checksum */
471 } csum_ip;
472 } hi_dword;
473 } lower;
474 struct {
475 u32 status_error; /* ext status/error */
476 u16 length0; /* length of buffer 0 */
477 u16 vlan; /* VLAN tag */
478 } middle;
479 struct {
480 u16 header_status;
481 u16 length[3]; /* length of buffers 1-3 */
482 } upper;
483 u64 reserved;
484 } wb; /* writeback */
485};
486
487/* Transmit Descriptor */
488struct e1000_tx_desc {
489 u64 buffer_addr; /* Address of the descriptor's data buffer */
490 union {
491 u32 data;
492 struct {
493 u16 length; /* Data buffer length */
494 u8 cso; /* Checksum offset */
495 u8 cmd; /* Descriptor control */
496 } flags;
497 } lower;
498 union {
499 u32 data;
500 struct {
501 u8 status; /* Descriptor status */
502 u8 css; /* Checksum start */
503 u16 special;
504 } fields;
505 } upper;
506};
507
508/* Offload Context Descriptor */
509struct e1000_context_desc {
510 union {
511 u32 ip_config;
512 struct {
513 u8 ipcss; /* IP checksum start */
514 u8 ipcso; /* IP checksum offset */
515 u16 ipcse; /* IP checksum end */
516 } ip_fields;
517 } lower_setup;
518 union {
519 u32 tcp_config;
520 struct {
521 u8 tucss; /* TCP checksum start */
522 u8 tucso; /* TCP checksum offset */
523 u16 tucse; /* TCP checksum end */
524 } tcp_fields;
525 } upper_setup;
526 u32 cmd_and_length;
527 union {
528 u32 data;
529 struct {
530 u8 status; /* Descriptor status */
531 u8 hdr_len; /* Header length */
532 u16 mss; /* Maximum segment size */
533 } fields;
534 } tcp_seg_setup;
535};
536
537/* Offload data descriptor */
538struct e1000_data_desc {
539 u64 buffer_addr; /* Address of the descriptor's buffer address */
540 union {
541 u32 data;
542 struct {
543 u16 length; /* Data buffer length */
544 u8 typ_len_ext;
545 u8 cmd;
546 } flags;
547 } lower;
548 union {
549 u32 data;
550 struct {
551 u8 status; /* Descriptor status */
552 u8 popts; /* Packet Options */
553 u16 special; /* */
554 } fields;
555 } upper;
556};
557
558/* Statistics counters collected by the MAC */
559struct e1000_hw_stats {
560 u64 crcerrs;
561 u64 algnerrc;
562 u64 symerrs;
563 u64 rxerrc;
564 u64 mpc;
565 u64 scc;
566 u64 ecol;
567 u64 mcc;
568 u64 latecol;
569 u64 colc;
570 u64 dc;
571 u64 tncrs;
572 u64 sec;
573 u64 cexterr;
574 u64 rlec;
575 u64 xonrxc;
576 u64 xontxc;
577 u64 xoffrxc;
578 u64 xofftxc;
579 u64 fcruc;
580 u64 prc64;
581 u64 prc127;
582 u64 prc255;
583 u64 prc511;
584 u64 prc1023;
585 u64 prc1522;
586 u64 gprc;
587 u64 bprc;
588 u64 mprc;
589 u64 gptc;
590 u64 gorcl;
591 u64 gorch;
592 u64 gotcl;
593 u64 gotch;
594 u64 rnbc;
595 u64 ruc;
596 u64 rfc;
597 u64 roc;
598 u64 rjc;
599 u64 mgprc;
600 u64 mgpdc;
601 u64 mgptc;
602 u64 torl;
603 u64 torh;
604 u64 totl;
605 u64 toth;
606 u64 tpr;
607 u64 tpt;
608 u64 ptc64;
609 u64 ptc127;
610 u64 ptc255;
611 u64 ptc511;
612 u64 ptc1023;
613 u64 ptc1522;
614 u64 mptc;
615 u64 bptc;
616 u64 tsctc;
617 u64 tsctfc;
618 u64 iac;
619 u64 icrxptc;
620 u64 icrxatc;
621 u64 ictxptc;
622 u64 ictxatc;
623 u64 ictxqec;
624 u64 ictxqmtc;
625 u64 icrxdmtc;
626 u64 icrxoc;
627};
628
629struct e1000_phy_stats {
630 u32 idle_errors;
631 u32 receive_errors;
632};
633
634struct e1000_host_mng_dhcp_cookie {
635 u32 signature;
636 u8 status;
637 u8 reserved0;
638 u16 vlan_id;
639 u32 reserved1;
640 u16 reserved2;
641 u8 reserved3;
642 u8 checksum;
643};
644
645/* Host Interface "Rev 1" */
646struct e1000_host_command_header {
647 u8 command_id;
648 u8 command_length;
649 u8 command_options;
650 u8 checksum;
651};
652
653#define E1000_HI_MAX_DATA_LENGTH 252
654struct e1000_host_command_info {
655 struct e1000_host_command_header command_header;
656 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
657};
658
659/* Host Interface "Rev 2" */
660struct e1000_host_mng_command_header {
661 u8 command_id;
662 u8 checksum;
663 u16 reserved1;
664 u16 reserved2;
665 u16 command_length;
666};
667
668#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
669struct e1000_host_mng_command_info {
670 struct e1000_host_mng_command_header command_header;
671 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
672};
673
674/* Function pointers and static data for the MAC. */
675struct e1000_mac_operations {
676 u32 mng_mode_enab;
677
678 s32 (*check_for_link)(struct e1000_hw *);
679 s32 (*cleanup_led)(struct e1000_hw *);
680 void (*clear_hw_cntrs)(struct e1000_hw *);
681 s32 (*get_bus_info)(struct e1000_hw *);
682 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
683 s32 (*led_on)(struct e1000_hw *);
684 s32 (*led_off)(struct e1000_hw *);
685 void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32,
686 u32);
687 s32 (*reset_hw)(struct e1000_hw *);
688 s32 (*init_hw)(struct e1000_hw *);
689 s32 (*setup_link)(struct e1000_hw *);
690 s32 (*setup_physical_interface)(struct e1000_hw *);
691};
692
693/* Function pointers for the PHY. */
694struct e1000_phy_operations {
695 s32 (*acquire_phy)(struct e1000_hw *);
696 s32 (*check_reset_block)(struct e1000_hw *);
697 s32 (*commit_phy)(struct e1000_hw *);
698 s32 (*force_speed_duplex)(struct e1000_hw *);
699 s32 (*get_cfg_done)(struct e1000_hw *hw);
700 s32 (*get_cable_length)(struct e1000_hw *);
701 s32 (*get_phy_info)(struct e1000_hw *);
702 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
703 void (*release_phy)(struct e1000_hw *);
704 s32 (*reset_phy)(struct e1000_hw *);
705 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
706 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
707 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
708};
709
710/* Function pointers for the NVM. */
711struct e1000_nvm_operations {
712 s32 (*acquire_nvm)(struct e1000_hw *);
713 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
714 void (*release_nvm)(struct e1000_hw *);
715 s32 (*update_nvm)(struct e1000_hw *);
716 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
717 s32 (*validate_nvm)(struct e1000_hw *);
718 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
719};
720
721struct e1000_mac_info {
722 struct e1000_mac_operations ops;
723
724 u8 addr[6];
725 u8 perm_addr[6];
726
727 enum e1000_mac_type type;
728 enum e1000_fc_mode fc;
729 enum e1000_fc_mode original_fc;
730
731 u32 collision_delta;
732 u32 ledctl_default;
733 u32 ledctl_mode1;
734 u32 ledctl_mode2;
735 u32 max_frame_size;
736 u32 mc_filter_type;
737 u32 min_frame_size;
738 u32 tx_packet_delta;
739 u32 txcw;
740
741 u16 current_ifs_val;
742 u16 ifs_max_val;
743 u16 ifs_min_val;
744 u16 ifs_ratio;
745 u16 ifs_step_size;
746 u16 mta_reg_count;
747 u16 rar_entry_count;
748 u16 fc_high_water;
749 u16 fc_low_water;
750 u16 fc_pause_time;
751
752 u8 forced_speed_duplex;
753
754 bool arc_subsystem_valid;
755 bool autoneg;
756 bool autoneg_failed;
757 bool get_link_status;
758 bool in_ifs_mode;
759 bool serdes_has_link;
760 bool tx_pkt_filtering;
761};
762
763struct e1000_phy_info {
764 struct e1000_phy_operations ops;
765
766 enum e1000_phy_type type;
767
768 enum e1000_1000t_rx_status local_rx;
769 enum e1000_1000t_rx_status remote_rx;
770 enum e1000_ms_type ms_type;
771 enum e1000_ms_type original_ms_type;
772 enum e1000_rev_polarity cable_polarity;
773 enum e1000_smart_speed smart_speed;
774
775 u32 addr;
776 u32 id;
777 u32 reset_delay_us; /* in usec */
778 u32 revision;
779
780 u16 autoneg_advertised;
781 u16 autoneg_mask;
782 u16 cable_length;
783 u16 max_cable_length;
784 u16 min_cable_length;
785
786 u8 mdix;
787
788 bool disable_polarity_correction;
789 bool is_mdix;
790 bool polarity_correction;
791 bool speed_downgraded;
792 bool wait_for_link;
793};
794
795struct e1000_nvm_info {
796 struct e1000_nvm_operations ops;
797
798 enum e1000_nvm_type type;
799 enum e1000_nvm_override override;
800
801 u32 flash_bank_size;
802 u32 flash_base_addr;
803
804 u16 word_size;
805 u16 delay_usec;
806 u16 address_bits;
807 u16 opcode_bits;
808 u16 page_size;
809};
810
811struct e1000_bus_info {
812 enum e1000_bus_width width;
813
814 u16 func;
815};
816
817struct e1000_dev_spec_82571 {
818 bool laa_is_present;
819};
820
821struct e1000_shadow_ram {
822 u16 value;
823 bool modified;
824};
825
826#define E1000_ICH8_SHADOW_RAM_WORDS 2048
827
828struct e1000_dev_spec_ich8lan {
829 bool kmrn_lock_loss_workaround_enabled;
830 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
831};
832
833struct e1000_hw {
834 struct e1000_adapter *adapter;
835
836 u8 __iomem *hw_addr;
837 u8 __iomem *flash_address;
838
839 struct e1000_mac_info mac;
840 struct e1000_phy_info phy;
841 struct e1000_nvm_info nvm;
842 struct e1000_bus_info bus;
843 struct e1000_host_mng_dhcp_cookie mng_cookie;
844
845 union {
846 struct e1000_dev_spec_82571 e82571;
847 struct e1000_dev_spec_ich8lan ich8lan;
848 } dev_spec;
849
850 enum e1000_media_type media_type;
851};
852
853#ifdef DEBUG
854#define hw_dbg(hw, format, arg...) \
855 printk(KERN_DEBUG, "%s: " format, e1000_get_hw_dev_name(hw), ##arg);
856#else
857static inline int __attribute__ ((format (printf, 2, 3)))
858hw_dbg(struct e1000_hw *hw, const char *format, ...)
859{
860 return 0;
861}
862#endif
863
864#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 15:50:18 -0500