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-rw-r--r--drivers/net/e1000e/es2lan.c89
1 files changed, 52 insertions, 37 deletions
diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c
index 88657adf965f..265775447538 100644
--- a/drivers/net/e1000e/es2lan.c
+++ b/drivers/net/e1000e/es2lan.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/1000 Linux driver 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -92,7 +92,8 @@
92/* In-Band Control Register (Page 194, Register 18) */ 92/* In-Band Control Register (Page 194, Register 18) */
93#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 93#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
94 94
95/* A table for the GG82563 cable length where the range is defined 95/*
96 * A table for the GG82563 cable length where the range is defined
96 * with a lower bound at "index" and the upper bound at 97 * with a lower bound at "index" and the upper bound at
97 * "index + 5". 98 * "index + 5".
98 */ 99 */
@@ -167,12 +168,13 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
167 break; 168 break;
168 } 169 }
169 170
170 nvm->type = e1000_nvm_eeprom_spi; 171 nvm->type = e1000_nvm_eeprom_spi;
171 172
172 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 173 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
173 E1000_EECD_SIZE_EX_SHIFT); 174 E1000_EECD_SIZE_EX_SHIFT);
174 175
175 /* Added to a constant, "size" becomes the left-shift value 176 /*
177 * Added to a constant, "size" becomes the left-shift value
176 * for setting word_size. 178 * for setting word_size.
177 */ 179 */
178 size += NVM_WORD_SIZE_BASE_SHIFT; 180 size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -208,8 +210,7 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
208 /* Set rar entry count */ 210 /* Set rar entry count */
209 mac->rar_entry_count = E1000_RAR_ENTRIES; 211 mac->rar_entry_count = E1000_RAR_ENTRIES;
210 /* Set if manageability features are enabled. */ 212 /* Set if manageability features are enabled. */
211 mac->arc_subsystem_valid = 213 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
212 (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
213 214
214 /* check for link */ 215 /* check for link */
215 switch (hw->media_type) { 216 switch (hw->media_type) {
@@ -344,8 +345,10 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
344 if (!(swfw_sync & (fwmask | swmask))) 345 if (!(swfw_sync & (fwmask | swmask)))
345 break; 346 break;
346 347
347 /* Firmware currently using resource (fwmask) 348 /*
348 * or other software thread using resource (swmask) */ 349 * Firmware currently using resource (fwmask)
350 * or other software thread using resource (swmask)
351 */
349 e1000e_put_hw_semaphore(hw); 352 e1000e_put_hw_semaphore(hw);
350 mdelay(5); 353 mdelay(5);
351 i++; 354 i++;
@@ -407,7 +410,8 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
407 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) 410 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
408 page_select = GG82563_PHY_PAGE_SELECT; 411 page_select = GG82563_PHY_PAGE_SELECT;
409 else 412 else
410 /* Use Alternative Page Select register to access 413 /*
414 * Use Alternative Page Select register to access
411 * registers 30 and 31 415 * registers 30 and 31
412 */ 416 */
413 page_select = GG82563_PHY_PAGE_SELECT_ALT; 417 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -417,7 +421,8 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
417 if (ret_val) 421 if (ret_val)
418 return ret_val; 422 return ret_val;
419 423
420 /* The "ready" bit in the MDIC register may be incorrectly set 424 /*
425 * The "ready" bit in the MDIC register may be incorrectly set
421 * before the device has completed the "Page Select" MDI 426 * before the device has completed the "Page Select" MDI
422 * transaction. So we wait 200us after each MDI command... 427 * transaction. So we wait 200us after each MDI command...
423 */ 428 */
@@ -462,7 +467,8 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
462 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) 467 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
463 page_select = GG82563_PHY_PAGE_SELECT; 468 page_select = GG82563_PHY_PAGE_SELECT;
464 else 469 else
465 /* Use Alternative Page Select register to access 470 /*
471 * Use Alternative Page Select register to access
466 * registers 30 and 31 472 * registers 30 and 31
467 */ 473 */
468 page_select = GG82563_PHY_PAGE_SELECT_ALT; 474 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -473,7 +479,8 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
473 return ret_val; 479 return ret_val;
474 480
475 481
476 /* The "ready" bit in the MDIC register may be incorrectly set 482 /*
483 * The "ready" bit in the MDIC register may be incorrectly set
477 * before the device has completed the "Page Select" MDI 484 * before the device has completed the "Page Select" MDI
478 * transaction. So we wait 200us after each MDI command... 485 * transaction. So we wait 200us after each MDI command...
479 */ 486 */
@@ -554,7 +561,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
554 u16 phy_data; 561 u16 phy_data;
555 bool link; 562 bool link;
556 563
557 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 564 /*
565 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
558 * forced whenever speed and duplex are forced. 566 * forced whenever speed and duplex are forced.
559 */ 567 */
560 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 568 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -593,7 +601,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
593 return ret_val; 601 return ret_val;
594 602
595 if (!link) { 603 if (!link) {
596 /* We didn't get link. 604 /*
605 * We didn't get link.
597 * Reset the DSP and cross our fingers. 606 * Reset the DSP and cross our fingers.
598 */ 607 */
599 ret_val = e1000e_phy_reset_dsp(hw); 608 ret_val = e1000e_phy_reset_dsp(hw);
@@ -612,7 +621,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
612 if (ret_val) 621 if (ret_val)
613 return ret_val; 622 return ret_val;
614 623
615 /* Resetting the phy means we need to verify the TX_CLK corresponds 624 /*
625 * Resetting the phy means we need to verify the TX_CLK corresponds
616 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 626 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
617 */ 627 */
618 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 628 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
@@ -621,7 +631,8 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
621 else 631 else
622 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 632 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
623 633
624 /* In addition, we must re-enable CRS on Tx for both half and full 634 /*
635 * In addition, we must re-enable CRS on Tx for both half and full
625 * duplex. 636 * duplex.
626 */ 637 */
627 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 638 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -704,7 +715,8 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
704 u32 icr; 715 u32 icr;
705 s32 ret_val; 716 s32 ret_val;
706 717
707 /* Prevent the PCI-E bus from sticking if there is no TLP connection 718 /*
719 * Prevent the PCI-E bus from sticking if there is no TLP connection
708 * on the last TLP read/write transaction when MAC is reset. 720 * on the last TLP read/write transaction when MAC is reset.
709 */ 721 */
710 ret_val = e1000e_disable_pcie_master(hw); 722 ret_val = e1000e_disable_pcie_master(hw);
@@ -808,7 +820,8 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
808 reg_data &= ~0x00100000; 820 reg_data &= ~0x00100000;
809 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 821 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
810 822
811 /* Clear all of the statistics registers (clear on read). It is 823 /*
824 * Clear all of the statistics registers (clear on read). It is
812 * important that we do this after we have tried to establish link 825 * important that we do this after we have tried to establish link
813 * because the symbol error count will increment wildly if there 826 * because the symbol error count will increment wildly if there
814 * is no link. 827 * is no link.
@@ -881,7 +894,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
881 if (ret_val) 894 if (ret_val)
882 return ret_val; 895 return ret_val;
883 896
884 /* Options: 897 /*
898 * Options:
885 * MDI/MDI-X = 0 (default) 899 * MDI/MDI-X = 0 (default)
886 * 0 - Auto for all speeds 900 * 0 - Auto for all speeds
887 * 1 - MDI mode 901 * 1 - MDI mode
@@ -907,7 +921,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
907 break; 921 break;
908 } 922 }
909 923
910 /* Options: 924 /*
925 * Options:
911 * disable_polarity_correction = 0 (default) 926 * disable_polarity_correction = 0 (default)
912 * Automatic Correction for Reversed Cable Polarity 927 * Automatic Correction for Reversed Cable Polarity
913 * 0 - Disabled 928 * 0 - Disabled
@@ -928,10 +943,9 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
928 return ret_val; 943 return ret_val;
929 } 944 }
930 945
931 /* Bypass RX and TX FIFO's */ 946 /* Bypass Rx and Tx FIFO's */
932 ret_val = e1000e_write_kmrn_reg(hw, 947 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
933 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 948 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
934 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
935 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 949 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
936 if (ret_val) 950 if (ret_val)
937 return ret_val; 951 return ret_val;
@@ -953,7 +967,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
953 if (ret_val) 967 if (ret_val)
954 return ret_val; 968 return ret_val;
955 969
956 /* Do not init these registers when the HW is in IAMT mode, since the 970 /*
971 * Do not init these registers when the HW is in IAMT mode, since the
957 * firmware will have already initialized them. We only initialize 972 * firmware will have already initialized them. We only initialize
958 * them if the HW is not in IAMT mode. 973 * them if the HW is not in IAMT mode.
959 */ 974 */
@@ -974,7 +989,8 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
974 return ret_val; 989 return ret_val;
975 } 990 }
976 991
977 /* Workaround: Disable padding in Kumeran interface in the MAC 992 /*
993 * Workaround: Disable padding in Kumeran interface in the MAC
978 * and in the PHY to avoid CRC errors. 994 * and in the PHY to avoid CRC errors.
979 */ 995 */
980 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); 996 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
@@ -1007,9 +1023,11 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1007 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1023 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1008 ew32(CTRL, ctrl); 1024 ew32(CTRL, ctrl);
1009 1025
1010 /* Set the mac to wait the maximum time between each 1026 /*
1027 * Set the mac to wait the maximum time between each
1011 * iteration and increase the max iterations when 1028 * iteration and increase the max iterations when
1012 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 1029 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1030 */
1013 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1031 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1014 if (ret_val) 1032 if (ret_val)
1015 return ret_val; 1033 return ret_val;
@@ -1026,9 +1044,8 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1026 if (ret_val) 1044 if (ret_val)
1027 return ret_val; 1045 return ret_val;
1028 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1046 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1029 ret_val = e1000e_write_kmrn_reg(hw, 1047 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1030 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1048 reg_data);
1031 reg_data);
1032 if (ret_val) 1049 if (ret_val)
1033 return ret_val; 1050 return ret_val;
1034 1051
@@ -1056,9 +1073,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1056 u16 reg_data; 1073 u16 reg_data;
1057 1074
1058 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1075 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1059 ret_val = e1000e_write_kmrn_reg(hw, 1076 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1060 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1077 reg_data);
1061 reg_data);
1062 if (ret_val) 1078 if (ret_val)
1063 return ret_val; 1079 return ret_val;
1064 1080
@@ -1096,9 +1112,8 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1096 u32 tipg; 1112 u32 tipg;
1097 1113
1098 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1114 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1099 ret_val = e1000e_write_kmrn_reg(hw, 1115 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1100 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1116 reg_data);
1101 reg_data);
1102 if (ret_val) 1117 if (ret_val)
1103 return ret_val; 1118 return ret_val;
1104 1119