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path: root/drivers/net/e1000/e1000_hw.h
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.h')
-rw-r--r--drivers/net/e1000/e1000_hw.h512
1 files changed, 256 insertions, 256 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 572a7b6dc12e..99fce2c5dd26 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -100,7 +100,7 @@ typedef enum {
100} e1000_fc_type; 100} e1000_fc_type;
101 101
102struct e1000_shadow_ram { 102struct e1000_shadow_ram {
103 uint16_t eeprom_word; 103 u16 eeprom_word;
104 bool modified; 104 bool modified;
105}; 105};
106 106
@@ -263,17 +263,17 @@ struct e1000_phy_info {
263}; 263};
264 264
265struct e1000_phy_stats { 265struct e1000_phy_stats {
266 uint32_t idle_errors; 266 u32 idle_errors;
267 uint32_t receive_errors; 267 u32 receive_errors;
268}; 268};
269 269
270struct e1000_eeprom_info { 270struct e1000_eeprom_info {
271 e1000_eeprom_type type; 271 e1000_eeprom_type type;
272 uint16_t word_size; 272 u16 word_size;
273 uint16_t opcode_bits; 273 u16 opcode_bits;
274 uint16_t address_bits; 274 u16 address_bits;
275 uint16_t delay_usec; 275 u16 delay_usec;
276 uint16_t page_size; 276 u16 page_size;
277 bool use_eerd; 277 bool use_eerd;
278 bool use_eewr; 278 bool use_eewr;
279}; 279};
@@ -308,34 +308,34 @@ typedef enum {
308 308
309/* Function prototypes */ 309/* Function prototypes */
310/* Initialization */ 310/* Initialization */
311int32_t e1000_reset_hw(struct e1000_hw *hw); 311s32 e1000_reset_hw(struct e1000_hw *hw);
312int32_t e1000_init_hw(struct e1000_hw *hw); 312s32 e1000_init_hw(struct e1000_hw *hw);
313int32_t e1000_set_mac_type(struct e1000_hw *hw); 313s32 e1000_set_mac_type(struct e1000_hw *hw);
314void e1000_set_media_type(struct e1000_hw *hw); 314void e1000_set_media_type(struct e1000_hw *hw);
315 315
316/* Link Configuration */ 316/* Link Configuration */
317int32_t e1000_setup_link(struct e1000_hw *hw); 317s32 e1000_setup_link(struct e1000_hw *hw);
318int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw); 318s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
319void e1000_config_collision_dist(struct e1000_hw *hw); 319void e1000_config_collision_dist(struct e1000_hw *hw);
320int32_t e1000_check_for_link(struct e1000_hw *hw); 320s32 e1000_check_for_link(struct e1000_hw *hw);
321int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex); 321s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
322int32_t e1000_force_mac_fc(struct e1000_hw *hw); 322s32 e1000_force_mac_fc(struct e1000_hw *hw);
323 323
324/* PHY */ 324/* PHY */
325int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 325s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data);
326int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 326s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
327int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 327s32 e1000_phy_hw_reset(struct e1000_hw *hw);
328int32_t e1000_phy_reset(struct e1000_hw *hw); 328s32 e1000_phy_reset(struct e1000_hw *hw);
329int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 329s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
330int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 330s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
331 331
332void e1000_phy_powerdown_workaround(struct e1000_hw *hw); 332void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
333 333
334/* EEPROM Functions */ 334/* EEPROM Functions */
335int32_t e1000_init_eeprom_params(struct e1000_hw *hw); 335s32 e1000_init_eeprom_params(struct e1000_hw *hw);
336 336
337/* MNG HOST IF functions */ 337/* MNG HOST IF functions */
338uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); 338u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
339 339
340#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 340#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
341#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 341#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
@@ -354,80 +354,80 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
354#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 354#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
355 355
356struct e1000_host_mng_command_header { 356struct e1000_host_mng_command_header {
357 uint8_t command_id; 357 u8 command_id;
358 uint8_t checksum; 358 u8 checksum;
359 uint16_t reserved1; 359 u16 reserved1;
360 uint16_t reserved2; 360 u16 reserved2;
361 uint16_t command_length; 361 u16 command_length;
362}; 362};
363 363
364struct e1000_host_mng_command_info { 364struct e1000_host_mng_command_info {
365 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 365 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
366 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ 366 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
367}; 367};
368#ifdef __BIG_ENDIAN 368#ifdef __BIG_ENDIAN
369struct e1000_host_mng_dhcp_cookie{ 369struct e1000_host_mng_dhcp_cookie{
370 uint32_t signature; 370 u32 signature;
371 uint16_t vlan_id; 371 u16 vlan_id;
372 uint8_t reserved0; 372 u8 reserved0;
373 uint8_t status; 373 u8 status;
374 uint32_t reserved1; 374 u32 reserved1;
375 uint8_t checksum; 375 u8 checksum;
376 uint8_t reserved3; 376 u8 reserved3;
377 uint16_t reserved2; 377 u16 reserved2;
378}; 378};
379#else 379#else
380struct e1000_host_mng_dhcp_cookie{ 380struct e1000_host_mng_dhcp_cookie{
381 uint32_t signature; 381 u32 signature;
382 uint8_t status; 382 u8 status;
383 uint8_t reserved0; 383 u8 reserved0;
384 uint16_t vlan_id; 384 u16 vlan_id;
385 uint32_t reserved1; 385 u32 reserved1;
386 uint16_t reserved2; 386 u16 reserved2;
387 uint8_t reserved3; 387 u8 reserved3;
388 uint8_t checksum; 388 u8 checksum;
389}; 389};
390#endif 390#endif
391 391
392int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, 392s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
393 uint16_t length); 393 u16 length);
394bool e1000_check_mng_mode(struct e1000_hw *hw); 394bool e1000_check_mng_mode(struct e1000_hw *hw);
395bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 395bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
396int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 396s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
397int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); 397s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
398int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); 398s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
399int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 399s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
400int32_t e1000_read_mac_addr(struct e1000_hw * hw); 400s32 e1000_read_mac_addr(struct e1000_hw * hw);
401 401
402/* Filters (multicast, vlan, receive) */ 402/* Filters (multicast, vlan, receive) */
403uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr); 403u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
404void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value); 404void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
405void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index); 405void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);
406void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value); 406void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
407 407
408/* LED functions */ 408/* LED functions */
409int32_t e1000_setup_led(struct e1000_hw *hw); 409s32 e1000_setup_led(struct e1000_hw *hw);
410int32_t e1000_cleanup_led(struct e1000_hw *hw); 410s32 e1000_cleanup_led(struct e1000_hw *hw);
411int32_t e1000_led_on(struct e1000_hw *hw); 411s32 e1000_led_on(struct e1000_hw *hw);
412int32_t e1000_led_off(struct e1000_hw *hw); 412s32 e1000_led_off(struct e1000_hw *hw);
413int32_t e1000_blink_led_start(struct e1000_hw *hw); 413s32 e1000_blink_led_start(struct e1000_hw *hw);
414 414
415/* Adaptive IFS Functions */ 415/* Adaptive IFS Functions */
416 416
417/* Everything else */ 417/* Everything else */
418void e1000_reset_adaptive(struct e1000_hw *hw); 418void e1000_reset_adaptive(struct e1000_hw *hw);
419void e1000_update_adaptive(struct e1000_hw *hw); 419void e1000_update_adaptive(struct e1000_hw *hw);
420void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr); 420void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr);
421void e1000_get_bus_info(struct e1000_hw *hw); 421void e1000_get_bus_info(struct e1000_hw *hw);
422void e1000_pci_set_mwi(struct e1000_hw *hw); 422void e1000_pci_set_mwi(struct e1000_hw *hw);
423void e1000_pci_clear_mwi(struct e1000_hw *hw); 423void e1000_pci_clear_mwi(struct e1000_hw *hw);
424int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value); 424s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
425void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); 425void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
426int e1000_pcix_get_mmrbc(struct e1000_hw *hw); 426int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
427/* Port I/O is only supported on 82544 and newer */ 427/* Port I/O is only supported on 82544 and newer */
428void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value); 428void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
429int32_t e1000_disable_pciex_master(struct e1000_hw *hw); 429s32 e1000_disable_pciex_master(struct e1000_hw *hw);
430int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 430s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
431 431
432 432
433#define E1000_READ_REG_IO(a, reg) \ 433#define E1000_READ_REG_IO(a, reg) \
@@ -596,8 +596,8 @@ struct e1000_rx_desc {
596 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 596 __le64 buffer_addr; /* Address of the descriptor's data buffer */
597 __le16 length; /* Length of data DMAed into data buffer */ 597 __le16 length; /* Length of data DMAed into data buffer */
598 __le16 csum; /* Packet checksum */ 598 __le16 csum; /* Packet checksum */
599 uint8_t status; /* Descriptor status */ 599 u8 status; /* Descriptor status */
600 uint8_t errors; /* Descriptor Errors */ 600 u8 errors; /* Descriptor Errors */
601 __le16 special; 601 __le16 special;
602}; 602};
603 603
@@ -718,15 +718,15 @@ struct e1000_tx_desc {
718 __le32 data; 718 __le32 data;
719 struct { 719 struct {
720 __le16 length; /* Data buffer length */ 720 __le16 length; /* Data buffer length */
721 uint8_t cso; /* Checksum offset */ 721 u8 cso; /* Checksum offset */
722 uint8_t cmd; /* Descriptor control */ 722 u8 cmd; /* Descriptor control */
723 } flags; 723 } flags;
724 } lower; 724 } lower;
725 union { 725 union {
726 __le32 data; 726 __le32 data;
727 struct { 727 struct {
728 uint8_t status; /* Descriptor status */ 728 u8 status; /* Descriptor status */
729 uint8_t css; /* Checksum start */ 729 u8 css; /* Checksum start */
730 __le16 special; 730 __le16 special;
731 } fields; 731 } fields;
732 } upper; 732 } upper;
@@ -759,16 +759,16 @@ struct e1000_context_desc {
759 union { 759 union {
760 __le32 ip_config; 760 __le32 ip_config;
761 struct { 761 struct {
762 uint8_t ipcss; /* IP checksum start */ 762 u8 ipcss; /* IP checksum start */
763 uint8_t ipcso; /* IP checksum offset */ 763 u8 ipcso; /* IP checksum offset */
764 __le16 ipcse; /* IP checksum end */ 764 __le16 ipcse; /* IP checksum end */
765 } ip_fields; 765 } ip_fields;
766 } lower_setup; 766 } lower_setup;
767 union { 767 union {
768 __le32 tcp_config; 768 __le32 tcp_config;
769 struct { 769 struct {
770 uint8_t tucss; /* TCP checksum start */ 770 u8 tucss; /* TCP checksum start */
771 uint8_t tucso; /* TCP checksum offset */ 771 u8 tucso; /* TCP checksum offset */
772 __le16 tucse; /* TCP checksum end */ 772 __le16 tucse; /* TCP checksum end */
773 } tcp_fields; 773 } tcp_fields;
774 } upper_setup; 774 } upper_setup;
@@ -776,8 +776,8 @@ struct e1000_context_desc {
776 union { 776 union {
777 __le32 data; 777 __le32 data;
778 struct { 778 struct {
779 uint8_t status; /* Descriptor status */ 779 u8 status; /* Descriptor status */
780 uint8_t hdr_len; /* Header length */ 780 u8 hdr_len; /* Header length */
781 __le16 mss; /* Maximum segment size */ 781 __le16 mss; /* Maximum segment size */
782 } fields; 782 } fields;
783 } tcp_seg_setup; 783 } tcp_seg_setup;
@@ -790,15 +790,15 @@ struct e1000_data_desc {
790 __le32 data; 790 __le32 data;
791 struct { 791 struct {
792 __le16 length; /* Data buffer length */ 792 __le16 length; /* Data buffer length */
793 uint8_t typ_len_ext; /* */ 793 u8 typ_len_ext; /* */
794 uint8_t cmd; /* */ 794 u8 cmd; /* */
795 } flags; 795 } flags;
796 } lower; 796 } lower;
797 union { 797 union {
798 __le32 data; 798 __le32 data;
799 struct { 799 struct {
800 uint8_t status; /* Descriptor status */ 800 u8 status; /* Descriptor status */
801 uint8_t popts; /* Packet Options */ 801 u8 popts; /* Packet Options */
802 __le16 special; /* */ 802 __le16 special; /* */
803 } fields; 803 } fields;
804 } upper; 804 } upper;
@@ -825,8 +825,8 @@ struct e1000_rar {
825 825
826/* IPv4 Address Table Entry */ 826/* IPv4 Address Table Entry */
827struct e1000_ipv4_at_entry { 827struct e1000_ipv4_at_entry {
828 volatile uint32_t ipv4_addr; /* IP Address (RW) */ 828 volatile u32 ipv4_addr; /* IP Address (RW) */
829 volatile uint32_t reserved; 829 volatile u32 reserved;
830}; 830};
831 831
832/* Four wakeup IP addresses are supported */ 832/* Four wakeup IP addresses are supported */
@@ -837,25 +837,25 @@ struct e1000_ipv4_at_entry {
837 837
838/* IPv6 Address Table Entry */ 838/* IPv6 Address Table Entry */
839struct e1000_ipv6_at_entry { 839struct e1000_ipv6_at_entry {
840 volatile uint8_t ipv6_addr[16]; 840 volatile u8 ipv6_addr[16];
841}; 841};
842 842
843/* Flexible Filter Length Table Entry */ 843/* Flexible Filter Length Table Entry */
844struct e1000_fflt_entry { 844struct e1000_fflt_entry {
845 volatile uint32_t length; /* Flexible Filter Length (RW) */ 845 volatile u32 length; /* Flexible Filter Length (RW) */
846 volatile uint32_t reserved; 846 volatile u32 reserved;
847}; 847};
848 848
849/* Flexible Filter Mask Table Entry */ 849/* Flexible Filter Mask Table Entry */
850struct e1000_ffmt_entry { 850struct e1000_ffmt_entry {
851 volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 851 volatile u32 mask; /* Flexible Filter Mask (RW) */
852 volatile uint32_t reserved; 852 volatile u32 reserved;
853}; 853};
854 854
855/* Flexible Filter Value Table Entry */ 855/* Flexible Filter Value Table Entry */
856struct e1000_ffvt_entry { 856struct e1000_ffvt_entry {
857 volatile uint32_t value; /* Flexible Filter Value (RW) */ 857 volatile u32 value; /* Flexible Filter Value (RW) */
858 volatile uint32_t reserved; 858 volatile u32 reserved;
859}; 859};
860 860
861/* Four Flexible Filters are supported */ 861/* Four Flexible Filters are supported */
@@ -1309,89 +1309,89 @@ struct e1000_ffvt_entry {
1309 1309
1310/* Statistics counters collected by the MAC */ 1310/* Statistics counters collected by the MAC */
1311struct e1000_hw_stats { 1311struct e1000_hw_stats {
1312 uint64_t crcerrs; 1312 u64 crcerrs;
1313 uint64_t algnerrc; 1313 u64 algnerrc;
1314 uint64_t symerrs; 1314 u64 symerrs;
1315 uint64_t rxerrc; 1315 u64 rxerrc;
1316 uint64_t txerrc; 1316 u64 txerrc;
1317 uint64_t mpc; 1317 u64 mpc;
1318 uint64_t scc; 1318 u64 scc;
1319 uint64_t ecol; 1319 u64 ecol;
1320 uint64_t mcc; 1320 u64 mcc;
1321 uint64_t latecol; 1321 u64 latecol;
1322 uint64_t colc; 1322 u64 colc;
1323 uint64_t dc; 1323 u64 dc;
1324 uint64_t tncrs; 1324 u64 tncrs;
1325 uint64_t sec; 1325 u64 sec;
1326 uint64_t cexterr; 1326 u64 cexterr;
1327 uint64_t rlec; 1327 u64 rlec;
1328 uint64_t xonrxc; 1328 u64 xonrxc;
1329 uint64_t xontxc; 1329 u64 xontxc;
1330 uint64_t xoffrxc; 1330 u64 xoffrxc;
1331 uint64_t xofftxc; 1331 u64 xofftxc;
1332 uint64_t fcruc; 1332 u64 fcruc;
1333 uint64_t prc64; 1333 u64 prc64;
1334 uint64_t prc127; 1334 u64 prc127;
1335 uint64_t prc255; 1335 u64 prc255;
1336 uint64_t prc511; 1336 u64 prc511;
1337 uint64_t prc1023; 1337 u64 prc1023;
1338 uint64_t prc1522; 1338 u64 prc1522;
1339 uint64_t gprc; 1339 u64 gprc;
1340 uint64_t bprc; 1340 u64 bprc;
1341 uint64_t mprc; 1341 u64 mprc;
1342 uint64_t gptc; 1342 u64 gptc;
1343 uint64_t gorcl; 1343 u64 gorcl;
1344 uint64_t gorch; 1344 u64 gorch;
1345 uint64_t gotcl; 1345 u64 gotcl;
1346 uint64_t gotch; 1346 u64 gotch;
1347 uint64_t rnbc; 1347 u64 rnbc;
1348 uint64_t ruc; 1348 u64 ruc;
1349 uint64_t rfc; 1349 u64 rfc;
1350 uint64_t roc; 1350 u64 roc;
1351 uint64_t rlerrc; 1351 u64 rlerrc;
1352 uint64_t rjc; 1352 u64 rjc;
1353 uint64_t mgprc; 1353 u64 mgprc;
1354 uint64_t mgpdc; 1354 u64 mgpdc;
1355 uint64_t mgptc; 1355 u64 mgptc;
1356 uint64_t torl; 1356 u64 torl;
1357 uint64_t torh; 1357 u64 torh;
1358 uint64_t totl; 1358 u64 totl;
1359 uint64_t toth; 1359 u64 toth;
1360 uint64_t tpr; 1360 u64 tpr;
1361 uint64_t tpt; 1361 u64 tpt;
1362 uint64_t ptc64; 1362 u64 ptc64;
1363 uint64_t ptc127; 1363 u64 ptc127;
1364 uint64_t ptc255; 1364 u64 ptc255;
1365 uint64_t ptc511; 1365 u64 ptc511;
1366 uint64_t ptc1023; 1366 u64 ptc1023;
1367 uint64_t ptc1522; 1367 u64 ptc1522;
1368 uint64_t mptc; 1368 u64 mptc;
1369 uint64_t bptc; 1369 u64 bptc;
1370 uint64_t tsctc; 1370 u64 tsctc;
1371 uint64_t tsctfc; 1371 u64 tsctfc;
1372 uint64_t iac; 1372 u64 iac;
1373 uint64_t icrxptc; 1373 u64 icrxptc;
1374 uint64_t icrxatc; 1374 u64 icrxatc;
1375 uint64_t ictxptc; 1375 u64 ictxptc;
1376 uint64_t ictxatc; 1376 u64 ictxatc;
1377 uint64_t ictxqec; 1377 u64 ictxqec;
1378 uint64_t ictxqmtc; 1378 u64 ictxqmtc;
1379 uint64_t icrxdmtc; 1379 u64 icrxdmtc;
1380 uint64_t icrxoc; 1380 u64 icrxoc;
1381}; 1381};
1382 1382
1383/* Structure containing variables used by the shared code (e1000_hw.c) */ 1383/* Structure containing variables used by the shared code (e1000_hw.c) */
1384struct e1000_hw { 1384struct e1000_hw {
1385 uint8_t __iomem *hw_addr; 1385 u8 __iomem *hw_addr;
1386 uint8_t __iomem *flash_address; 1386 u8 __iomem *flash_address;
1387 e1000_mac_type mac_type; 1387 e1000_mac_type mac_type;
1388 e1000_phy_type phy_type; 1388 e1000_phy_type phy_type;
1389 uint32_t phy_init_script; 1389 u32 phy_init_script;
1390 e1000_media_type media_type; 1390 e1000_media_type media_type;
1391 void *back; 1391 void *back;
1392 struct e1000_shadow_ram *eeprom_shadow_ram; 1392 struct e1000_shadow_ram *eeprom_shadow_ram;
1393 uint32_t flash_bank_size; 1393 u32 flash_bank_size;
1394 uint32_t flash_base_addr; 1394 u32 flash_base_addr;
1395 e1000_fc_type fc; 1395 e1000_fc_type fc;
1396 e1000_bus_speed bus_speed; 1396 e1000_bus_speed bus_speed;
1397 e1000_bus_width bus_width; 1397 e1000_bus_width bus_width;
@@ -1400,51 +1400,51 @@ struct e1000_hw {
1400 e1000_ms_type master_slave; 1400 e1000_ms_type master_slave;
1401 e1000_ms_type original_master_slave; 1401 e1000_ms_type original_master_slave;
1402 e1000_ffe_config ffe_config_state; 1402 e1000_ffe_config ffe_config_state;
1403 uint32_t asf_firmware_present; 1403 u32 asf_firmware_present;
1404 uint32_t eeprom_semaphore_present; 1404 u32 eeprom_semaphore_present;
1405 uint32_t swfw_sync_present; 1405 u32 swfw_sync_present;
1406 uint32_t swfwhw_semaphore_present; 1406 u32 swfwhw_semaphore_present;
1407 unsigned long io_base; 1407 unsigned long io_base;
1408 uint32_t phy_id; 1408 u32 phy_id;
1409 uint32_t phy_revision; 1409 u32 phy_revision;
1410 uint32_t phy_addr; 1410 u32 phy_addr;
1411 uint32_t original_fc; 1411 u32 original_fc;
1412 uint32_t txcw; 1412 u32 txcw;
1413 uint32_t autoneg_failed; 1413 u32 autoneg_failed;
1414 uint32_t max_frame_size; 1414 u32 max_frame_size;
1415 uint32_t min_frame_size; 1415 u32 min_frame_size;
1416 uint32_t mc_filter_type; 1416 u32 mc_filter_type;
1417 uint32_t num_mc_addrs; 1417 u32 num_mc_addrs;
1418 uint32_t collision_delta; 1418 u32 collision_delta;
1419 uint32_t tx_packet_delta; 1419 u32 tx_packet_delta;
1420 uint32_t ledctl_default; 1420 u32 ledctl_default;
1421 uint32_t ledctl_mode1; 1421 u32 ledctl_mode1;
1422 uint32_t ledctl_mode2; 1422 u32 ledctl_mode2;
1423 bool tx_pkt_filtering; 1423 bool tx_pkt_filtering;
1424 struct e1000_host_mng_dhcp_cookie mng_cookie; 1424 struct e1000_host_mng_dhcp_cookie mng_cookie;
1425 uint16_t phy_spd_default; 1425 u16 phy_spd_default;
1426 uint16_t autoneg_advertised; 1426 u16 autoneg_advertised;
1427 uint16_t pci_cmd_word; 1427 u16 pci_cmd_word;
1428 uint16_t fc_high_water; 1428 u16 fc_high_water;
1429 uint16_t fc_low_water; 1429 u16 fc_low_water;
1430 uint16_t fc_pause_time; 1430 u16 fc_pause_time;
1431 uint16_t current_ifs_val; 1431 u16 current_ifs_val;
1432 uint16_t ifs_min_val; 1432 u16 ifs_min_val;
1433 uint16_t ifs_max_val; 1433 u16 ifs_max_val;
1434 uint16_t ifs_step_size; 1434 u16 ifs_step_size;
1435 uint16_t ifs_ratio; 1435 u16 ifs_ratio;
1436 uint16_t device_id; 1436 u16 device_id;
1437 uint16_t vendor_id; 1437 u16 vendor_id;
1438 uint16_t subsystem_id; 1438 u16 subsystem_id;
1439 uint16_t subsystem_vendor_id; 1439 u16 subsystem_vendor_id;
1440 uint8_t revision_id; 1440 u8 revision_id;
1441 uint8_t autoneg; 1441 u8 autoneg;
1442 uint8_t mdix; 1442 u8 mdix;
1443 uint8_t forced_speed_duplex; 1443 u8 forced_speed_duplex;
1444 uint8_t wait_autoneg_complete; 1444 u8 wait_autoneg_complete;
1445 uint8_t dma_fairness; 1445 u8 dma_fairness;
1446 uint8_t mac_addr[NODE_ADDRESS_SIZE]; 1446 u8 mac_addr[NODE_ADDRESS_SIZE];
1447 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; 1447 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1448 bool disable_polarity_correction; 1448 bool disable_polarity_correction;
1449 bool speed_downgraded; 1449 bool speed_downgraded;
1450 e1000_smart_speed smart_speed; 1450 e1000_smart_speed smart_speed;
@@ -2165,14 +2165,14 @@ typedef enum {
2165#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2165#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2166 2166
2167struct e1000_host_command_header { 2167struct e1000_host_command_header {
2168 uint8_t command_id; 2168 u8 command_id;
2169 uint8_t command_length; 2169 u8 command_length;
2170 uint8_t command_options; /* I/F bits for command, status for return */ 2170 u8 command_options; /* I/F bits for command, status for return */
2171 uint8_t checksum; 2171 u8 checksum;
2172}; 2172};
2173struct e1000_host_command_info { 2173struct e1000_host_command_info {
2174 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2174 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2175 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2175 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2176}; 2176};
2177 2177
2178/* Host SMB register #0 */ 2178/* Host SMB register #0 */
@@ -2495,7 +2495,7 @@ struct e1000_host_command_info {
2495/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2495/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2496#define PHY_CFG_TIMEOUT 100 2496#define PHY_CFG_TIMEOUT 100
2497 2497
2498#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2498#define E1000_TX_BUFFER_SIZE ((u32)1514)
2499 2499
2500/* The carrier extension symbol, as received by the NIC. */ 2500/* The carrier extension symbol, as received by the NIC. */
2501#define CARRIER_EXTENSION 0x0F 2501#define CARRIER_EXTENSION 0x0F
@@ -3312,68 +3312,68 @@ struct e1000_host_command_info {
3312/* Offset 04h HSFSTS */ 3312/* Offset 04h HSFSTS */
3313union ich8_hws_flash_status { 3313union ich8_hws_flash_status {
3314 struct ich8_hsfsts { 3314 struct ich8_hsfsts {
3315#ifdef E1000_BIG_ENDIAN 3315#ifdef __BIG_ENDIAN
3316 uint16_t reserved2 :6; 3316 u16 reserved2 :6;
3317 uint16_t fldesvalid :1; 3317 u16 fldesvalid :1;
3318 uint16_t flockdn :1; 3318 u16 flockdn :1;
3319 uint16_t flcdone :1; 3319 u16 flcdone :1;
3320 uint16_t flcerr :1; 3320 u16 flcerr :1;
3321 uint16_t dael :1; 3321 u16 dael :1;
3322 uint16_t berasesz :2; 3322 u16 berasesz :2;
3323 uint16_t flcinprog :1; 3323 u16 flcinprog :1;
3324 uint16_t reserved1 :2; 3324 u16 reserved1 :2;
3325#else 3325#else
3326 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */ 3326 u16 flcdone :1; /* bit 0 Flash Cycle Done */
3327 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */ 3327 u16 flcerr :1; /* bit 1 Flash Cycle Error */
3328 uint16_t dael :1; /* bit 2 Direct Access error Log */ 3328 u16 dael :1; /* bit 2 Direct Access error Log */
3329 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */ 3329 u16 berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3330 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */ 3330 u16 flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3331 uint16_t reserved1 :2; /* bit 13:6 Reserved */ 3331 u16 reserved1 :2; /* bit 13:6 Reserved */
3332 uint16_t reserved2 :6; /* bit 13:6 Reserved */ 3332 u16 reserved2 :6; /* bit 13:6 Reserved */
3333 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 3333 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3334 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */ 3334 u16 flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3335#endif 3335#endif
3336 } hsf_status; 3336 } hsf_status;
3337 uint16_t regval; 3337 u16 regval;
3338}; 3338};
3339 3339
3340/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 3340/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3341/* Offset 06h FLCTL */ 3341/* Offset 06h FLCTL */
3342union ich8_hws_flash_ctrl { 3342union ich8_hws_flash_ctrl {
3343 struct ich8_hsflctl { 3343 struct ich8_hsflctl {
3344#ifdef E1000_BIG_ENDIAN 3344#ifdef __BIG_ENDIAN
3345 uint16_t fldbcount :2; 3345 u16 fldbcount :2;
3346 uint16_t flockdn :6; 3346 u16 flockdn :6;
3347 uint16_t flcgo :1; 3347 u16 flcgo :1;
3348 uint16_t flcycle :2; 3348 u16 flcycle :2;
3349 uint16_t reserved :5; 3349 u16 reserved :5;
3350#else 3350#else
3351 uint16_t flcgo :1; /* 0 Flash Cycle Go */ 3351 u16 flcgo :1; /* 0 Flash Cycle Go */
3352 uint16_t flcycle :2; /* 2:1 Flash Cycle */ 3352 u16 flcycle :2; /* 2:1 Flash Cycle */
3353 uint16_t reserved :5; /* 7:3 Reserved */ 3353 u16 reserved :5; /* 7:3 Reserved */
3354 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */ 3354 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
3355 uint16_t flockdn :6; /* 15:10 Reserved */ 3355 u16 flockdn :6; /* 15:10 Reserved */
3356#endif 3356#endif
3357 } hsf_ctrl; 3357 } hsf_ctrl;
3358 uint16_t regval; 3358 u16 regval;
3359}; 3359};
3360 3360
3361/* ICH8 Flash Region Access Permissions */ 3361/* ICH8 Flash Region Access Permissions */
3362union ich8_hws_flash_regacc { 3362union ich8_hws_flash_regacc {
3363 struct ich8_flracc { 3363 struct ich8_flracc {
3364#ifdef E1000_BIG_ENDIAN 3364#ifdef __BIG_ENDIAN
3365 uint32_t gmwag :8; 3365 u32 gmwag :8;
3366 uint32_t gmrag :8; 3366 u32 gmrag :8;
3367 uint32_t grwa :8; 3367 u32 grwa :8;
3368 uint32_t grra :8; 3368 u32 grra :8;
3369#else 3369#else
3370 uint32_t grra :8; /* 0:7 GbE region Read Access */ 3370 u32 grra :8; /* 0:7 GbE region Read Access */
3371 uint32_t grwa :8; /* 8:15 GbE region Write Access */ 3371 u32 grwa :8; /* 8:15 GbE region Write Access */
3372 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */ 3372 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
3373 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */ 3373 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
3374#endif 3374#endif
3375 } hsf_flregacc; 3375 } hsf_flregacc;
3376 uint16_t regval; 3376 u16 regval;
3377}; 3377};
3378 3378
3379/* Miscellaneous PHY bit definitions. */ 3379/* Miscellaneous PHY bit definitions. */