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path: root/drivers/net/e1000/e1000_hw.h
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-rw-r--r--drivers/net/e1000/e1000_hw.h2891
1 files changed, 1440 insertions, 1451 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 1c782d2ff04e..4bfdf323b589 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -35,7 +35,6 @@
35 35
36#include "e1000_osdep.h" 36#include "e1000_osdep.h"
37 37
38
39/* Forward declarations of structures used by the shared code */ 38/* Forward declarations of structures used by the shared code */
40struct e1000_hw; 39struct e1000_hw;
41struct e1000_hw_stats; 40struct e1000_hw_stats;
@@ -43,169 +42,169 @@ struct e1000_hw_stats;
43/* Enumerated types specific to the e1000 hardware */ 42/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */ 43/* Media Access Controlers */
45typedef enum { 44typedef enum {
46 e1000_undefined = 0, 45 e1000_undefined = 0,
47 e1000_82542_rev2_0, 46 e1000_82542_rev2_0,
48 e1000_82542_rev2_1, 47 e1000_82542_rev2_1,
49 e1000_82543, 48 e1000_82543,
50 e1000_82544, 49 e1000_82544,
51 e1000_82540, 50 e1000_82540,
52 e1000_82545, 51 e1000_82545,
53 e1000_82545_rev_3, 52 e1000_82545_rev_3,
54 e1000_82546, 53 e1000_82546,
55 e1000_82546_rev_3, 54 e1000_82546_rev_3,
56 e1000_82541, 55 e1000_82541,
57 e1000_82541_rev_2, 56 e1000_82541_rev_2,
58 e1000_82547, 57 e1000_82547,
59 e1000_82547_rev_2, 58 e1000_82547_rev_2,
60 e1000_num_macs 59 e1000_num_macs
61} e1000_mac_type; 60} e1000_mac_type;
62 61
63typedef enum { 62typedef enum {
64 e1000_eeprom_uninitialized = 0, 63 e1000_eeprom_uninitialized = 0,
65 e1000_eeprom_spi, 64 e1000_eeprom_spi,
66 e1000_eeprom_microwire, 65 e1000_eeprom_microwire,
67 e1000_eeprom_flash, 66 e1000_eeprom_flash,
68 e1000_eeprom_none, /* No NVM support */ 67 e1000_eeprom_none, /* No NVM support */
69 e1000_num_eeprom_types 68 e1000_num_eeprom_types
70} e1000_eeprom_type; 69} e1000_eeprom_type;
71 70
72/* Media Types */ 71/* Media Types */
73typedef enum { 72typedef enum {
74 e1000_media_type_copper = 0, 73 e1000_media_type_copper = 0,
75 e1000_media_type_fiber = 1, 74 e1000_media_type_fiber = 1,
76 e1000_media_type_internal_serdes = 2, 75 e1000_media_type_internal_serdes = 2,
77 e1000_num_media_types 76 e1000_num_media_types
78} e1000_media_type; 77} e1000_media_type;
79 78
80typedef enum { 79typedef enum {
81 e1000_10_half = 0, 80 e1000_10_half = 0,
82 e1000_10_full = 1, 81 e1000_10_full = 1,
83 e1000_100_half = 2, 82 e1000_100_half = 2,
84 e1000_100_full = 3 83 e1000_100_full = 3
85} e1000_speed_duplex_type; 84} e1000_speed_duplex_type;
86 85
87/* Flow Control Settings */ 86/* Flow Control Settings */
88typedef enum { 87typedef enum {
89 E1000_FC_NONE = 0, 88 E1000_FC_NONE = 0,
90 E1000_FC_RX_PAUSE = 1, 89 E1000_FC_RX_PAUSE = 1,
91 E1000_FC_TX_PAUSE = 2, 90 E1000_FC_TX_PAUSE = 2,
92 E1000_FC_FULL = 3, 91 E1000_FC_FULL = 3,
93 E1000_FC_DEFAULT = 0xFF 92 E1000_FC_DEFAULT = 0xFF
94} e1000_fc_type; 93} e1000_fc_type;
95 94
96struct e1000_shadow_ram { 95struct e1000_shadow_ram {
97 u16 eeprom_word; 96 u16 eeprom_word;
98 bool modified; 97 bool modified;
99}; 98};
100 99
101/* PCI bus types */ 100/* PCI bus types */
102typedef enum { 101typedef enum {
103 e1000_bus_type_unknown = 0, 102 e1000_bus_type_unknown = 0,
104 e1000_bus_type_pci, 103 e1000_bus_type_pci,
105 e1000_bus_type_pcix, 104 e1000_bus_type_pcix,
106 e1000_bus_type_reserved 105 e1000_bus_type_reserved
107} e1000_bus_type; 106} e1000_bus_type;
108 107
109/* PCI bus speeds */ 108/* PCI bus speeds */
110typedef enum { 109typedef enum {
111 e1000_bus_speed_unknown = 0, 110 e1000_bus_speed_unknown = 0,
112 e1000_bus_speed_33, 111 e1000_bus_speed_33,
113 e1000_bus_speed_66, 112 e1000_bus_speed_66,
114 e1000_bus_speed_100, 113 e1000_bus_speed_100,
115 e1000_bus_speed_120, 114 e1000_bus_speed_120,
116 e1000_bus_speed_133, 115 e1000_bus_speed_133,
117 e1000_bus_speed_reserved 116 e1000_bus_speed_reserved
118} e1000_bus_speed; 117} e1000_bus_speed;
119 118
120/* PCI bus widths */ 119/* PCI bus widths */
121typedef enum { 120typedef enum {
122 e1000_bus_width_unknown = 0, 121 e1000_bus_width_unknown = 0,
123 e1000_bus_width_32, 122 e1000_bus_width_32,
124 e1000_bus_width_64, 123 e1000_bus_width_64,
125 e1000_bus_width_reserved 124 e1000_bus_width_reserved
126} e1000_bus_width; 125} e1000_bus_width;
127 126
128/* PHY status info structure and supporting enums */ 127/* PHY status info structure and supporting enums */
129typedef enum { 128typedef enum {
130 e1000_cable_length_50 = 0, 129 e1000_cable_length_50 = 0,
131 e1000_cable_length_50_80, 130 e1000_cable_length_50_80,
132 e1000_cable_length_80_110, 131 e1000_cable_length_80_110,
133 e1000_cable_length_110_140, 132 e1000_cable_length_110_140,
134 e1000_cable_length_140, 133 e1000_cable_length_140,
135 e1000_cable_length_undefined = 0xFF 134 e1000_cable_length_undefined = 0xFF
136} e1000_cable_length; 135} e1000_cable_length;
137 136
138typedef enum { 137typedef enum {
139 e1000_gg_cable_length_60 = 0, 138 e1000_gg_cable_length_60 = 0,
140 e1000_gg_cable_length_60_115 = 1, 139 e1000_gg_cable_length_60_115 = 1,
141 e1000_gg_cable_length_115_150 = 2, 140 e1000_gg_cable_length_115_150 = 2,
142 e1000_gg_cable_length_150 = 4 141 e1000_gg_cable_length_150 = 4
143} e1000_gg_cable_length; 142} e1000_gg_cable_length;
144 143
145typedef enum { 144typedef enum {
146 e1000_igp_cable_length_10 = 10, 145 e1000_igp_cable_length_10 = 10,
147 e1000_igp_cable_length_20 = 20, 146 e1000_igp_cable_length_20 = 20,
148 e1000_igp_cable_length_30 = 30, 147 e1000_igp_cable_length_30 = 30,
149 e1000_igp_cable_length_40 = 40, 148 e1000_igp_cable_length_40 = 40,
150 e1000_igp_cable_length_50 = 50, 149 e1000_igp_cable_length_50 = 50,
151 e1000_igp_cable_length_60 = 60, 150 e1000_igp_cable_length_60 = 60,
152 e1000_igp_cable_length_70 = 70, 151 e1000_igp_cable_length_70 = 70,
153 e1000_igp_cable_length_80 = 80, 152 e1000_igp_cable_length_80 = 80,
154 e1000_igp_cable_length_90 = 90, 153 e1000_igp_cable_length_90 = 90,
155 e1000_igp_cable_length_100 = 100, 154 e1000_igp_cable_length_100 = 100,
156 e1000_igp_cable_length_110 = 110, 155 e1000_igp_cable_length_110 = 110,
157 e1000_igp_cable_length_115 = 115, 156 e1000_igp_cable_length_115 = 115,
158 e1000_igp_cable_length_120 = 120, 157 e1000_igp_cable_length_120 = 120,
159 e1000_igp_cable_length_130 = 130, 158 e1000_igp_cable_length_130 = 130,
160 e1000_igp_cable_length_140 = 140, 159 e1000_igp_cable_length_140 = 140,
161 e1000_igp_cable_length_150 = 150, 160 e1000_igp_cable_length_150 = 150,
162 e1000_igp_cable_length_160 = 160, 161 e1000_igp_cable_length_160 = 160,
163 e1000_igp_cable_length_170 = 170, 162 e1000_igp_cable_length_170 = 170,
164 e1000_igp_cable_length_180 = 180 163 e1000_igp_cable_length_180 = 180
165} e1000_igp_cable_length; 164} e1000_igp_cable_length;
166 165
167typedef enum { 166typedef enum {
168 e1000_10bt_ext_dist_enable_normal = 0, 167 e1000_10bt_ext_dist_enable_normal = 0,
169 e1000_10bt_ext_dist_enable_lower, 168 e1000_10bt_ext_dist_enable_lower,
170 e1000_10bt_ext_dist_enable_undefined = 0xFF 169 e1000_10bt_ext_dist_enable_undefined = 0xFF
171} e1000_10bt_ext_dist_enable; 170} e1000_10bt_ext_dist_enable;
172 171
173typedef enum { 172typedef enum {
174 e1000_rev_polarity_normal = 0, 173 e1000_rev_polarity_normal = 0,
175 e1000_rev_polarity_reversed, 174 e1000_rev_polarity_reversed,
176 e1000_rev_polarity_undefined = 0xFF 175 e1000_rev_polarity_undefined = 0xFF
177} e1000_rev_polarity; 176} e1000_rev_polarity;
178 177
179typedef enum { 178typedef enum {
180 e1000_downshift_normal = 0, 179 e1000_downshift_normal = 0,
181 e1000_downshift_activated, 180 e1000_downshift_activated,
182 e1000_downshift_undefined = 0xFF 181 e1000_downshift_undefined = 0xFF
183} e1000_downshift; 182} e1000_downshift;
184 183
185typedef enum { 184typedef enum {
186 e1000_smart_speed_default = 0, 185 e1000_smart_speed_default = 0,
187 e1000_smart_speed_on, 186 e1000_smart_speed_on,
188 e1000_smart_speed_off 187 e1000_smart_speed_off
189} e1000_smart_speed; 188} e1000_smart_speed;
190 189
191typedef enum { 190typedef enum {
192 e1000_polarity_reversal_enabled = 0, 191 e1000_polarity_reversal_enabled = 0,
193 e1000_polarity_reversal_disabled, 192 e1000_polarity_reversal_disabled,
194 e1000_polarity_reversal_undefined = 0xFF 193 e1000_polarity_reversal_undefined = 0xFF
195} e1000_polarity_reversal; 194} e1000_polarity_reversal;
196 195
197typedef enum { 196typedef enum {
198 e1000_auto_x_mode_manual_mdi = 0, 197 e1000_auto_x_mode_manual_mdi = 0,
199 e1000_auto_x_mode_manual_mdix, 198 e1000_auto_x_mode_manual_mdix,
200 e1000_auto_x_mode_auto1, 199 e1000_auto_x_mode_auto1,
201 e1000_auto_x_mode_auto2, 200 e1000_auto_x_mode_auto2,
202 e1000_auto_x_mode_undefined = 0xFF 201 e1000_auto_x_mode_undefined = 0xFF
203} e1000_auto_x_mode; 202} e1000_auto_x_mode;
204 203
205typedef enum { 204typedef enum {
206 e1000_1000t_rx_status_not_ok = 0, 205 e1000_1000t_rx_status_not_ok = 0,
207 e1000_1000t_rx_status_ok, 206 e1000_1000t_rx_status_ok,
208 e1000_1000t_rx_status_undefined = 0xFF 207 e1000_1000t_rx_status_undefined = 0xFF
209} e1000_1000t_rx_status; 208} e1000_1000t_rx_status;
210 209
211typedef enum { 210typedef enum {
@@ -215,63 +214,61 @@ typedef enum {
215} e1000_phy_type; 214} e1000_phy_type;
216 215
217typedef enum { 216typedef enum {
218 e1000_ms_hw_default = 0, 217 e1000_ms_hw_default = 0,
219 e1000_ms_force_master, 218 e1000_ms_force_master,
220 e1000_ms_force_slave, 219 e1000_ms_force_slave,
221 e1000_ms_auto 220 e1000_ms_auto
222} e1000_ms_type; 221} e1000_ms_type;
223 222
224typedef enum { 223typedef enum {
225 e1000_ffe_config_enabled = 0, 224 e1000_ffe_config_enabled = 0,
226 e1000_ffe_config_active, 225 e1000_ffe_config_active,
227 e1000_ffe_config_blocked 226 e1000_ffe_config_blocked
228} e1000_ffe_config; 227} e1000_ffe_config;
229 228
230typedef enum { 229typedef enum {
231 e1000_dsp_config_disabled = 0, 230 e1000_dsp_config_disabled = 0,
232 e1000_dsp_config_enabled, 231 e1000_dsp_config_enabled,
233 e1000_dsp_config_activated, 232 e1000_dsp_config_activated,
234 e1000_dsp_config_undefined = 0xFF 233 e1000_dsp_config_undefined = 0xFF
235} e1000_dsp_config; 234} e1000_dsp_config;
236 235
237struct e1000_phy_info { 236struct e1000_phy_info {
238 e1000_cable_length cable_length; 237 e1000_cable_length cable_length;
239 e1000_10bt_ext_dist_enable extended_10bt_distance; 238 e1000_10bt_ext_dist_enable extended_10bt_distance;
240 e1000_rev_polarity cable_polarity; 239 e1000_rev_polarity cable_polarity;
241 e1000_downshift downshift; 240 e1000_downshift downshift;
242 e1000_polarity_reversal polarity_correction; 241 e1000_polarity_reversal polarity_correction;
243 e1000_auto_x_mode mdix_mode; 242 e1000_auto_x_mode mdix_mode;
244 e1000_1000t_rx_status local_rx; 243 e1000_1000t_rx_status local_rx;
245 e1000_1000t_rx_status remote_rx; 244 e1000_1000t_rx_status remote_rx;
246}; 245};
247 246
248struct e1000_phy_stats { 247struct e1000_phy_stats {
249 u32 idle_errors; 248 u32 idle_errors;
250 u32 receive_errors; 249 u32 receive_errors;
251}; 250};
252 251
253struct e1000_eeprom_info { 252struct e1000_eeprom_info {
254 e1000_eeprom_type type; 253 e1000_eeprom_type type;
255 u16 word_size; 254 u16 word_size;
256 u16 opcode_bits; 255 u16 opcode_bits;
257 u16 address_bits; 256 u16 address_bits;
258 u16 delay_usec; 257 u16 delay_usec;
259 u16 page_size; 258 u16 page_size;
260 bool use_eerd; 259 bool use_eerd;
261 bool use_eewr; 260 bool use_eewr;
262}; 261};
263 262
264/* Flex ASF Information */ 263/* Flex ASF Information */
265#define E1000_HOST_IF_MAX_SIZE 2048 264#define E1000_HOST_IF_MAX_SIZE 2048
266 265
267typedef enum { 266typedef enum {
268 e1000_byte_align = 0, 267 e1000_byte_align = 0,
269 e1000_word_align = 1, 268 e1000_word_align = 1,
270 e1000_dword_align = 2 269 e1000_dword_align = 2
271} e1000_align_type; 270} e1000_align_type;
272 271
273
274
275/* Error Codes */ 272/* Error Codes */
276#define E1000_SUCCESS 0 273#define E1000_SUCCESS 0
277#define E1000_ERR_EEPROM 1 274#define E1000_ERR_EEPROM 1
@@ -300,11 +297,11 @@ s32 e1000_setup_link(struct e1000_hw *hw);
300s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 297s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
301void e1000_config_collision_dist(struct e1000_hw *hw); 298void e1000_config_collision_dist(struct e1000_hw *hw);
302s32 e1000_check_for_link(struct e1000_hw *hw); 299s32 e1000_check_for_link(struct e1000_hw *hw);
303s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); 300s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
304s32 e1000_force_mac_fc(struct e1000_hw *hw); 301s32 e1000_force_mac_fc(struct e1000_hw *hw);
305 302
306/* PHY */ 303/* PHY */
307s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data); 304s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
308s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); 305s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
309s32 e1000_phy_hw_reset(struct e1000_hw *hw); 306s32 e1000_phy_hw_reset(struct e1000_hw *hw);
310s32 e1000_phy_reset(struct e1000_hw *hw); 307s32 e1000_phy_reset(struct e1000_hw *hw);
@@ -318,64 +315,64 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw);
318u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw); 315u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
319 316
320#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 317#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
321#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 318#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
322 319
323#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 320#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
324#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 321#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
325#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 322#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
326#define E1000_MNG_IAMT_MODE 0x3 323#define E1000_MNG_IAMT_MODE 0x3
327#define E1000_MNG_ICH_IAMT_MODE 0x2 324#define E1000_MNG_ICH_IAMT_MODE 0x2
328#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 325#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
329 326
330#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 327#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
331#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ 328#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
332#define E1000_VFTA_ENTRY_SHIFT 0x5 329#define E1000_VFTA_ENTRY_SHIFT 0x5
333#define E1000_VFTA_ENTRY_MASK 0x7F 330#define E1000_VFTA_ENTRY_MASK 0x7F
334#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 331#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
335 332
336struct e1000_host_mng_command_header { 333struct e1000_host_mng_command_header {
337 u8 command_id; 334 u8 command_id;
338 u8 checksum; 335 u8 checksum;
339 u16 reserved1; 336 u16 reserved1;
340 u16 reserved2; 337 u16 reserved2;
341 u16 command_length; 338 u16 command_length;
342}; 339};
343 340
344struct e1000_host_mng_command_info { 341struct e1000_host_mng_command_info {
345 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 342 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
346 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ 343 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */
347}; 344};
348#ifdef __BIG_ENDIAN 345#ifdef __BIG_ENDIAN
349struct e1000_host_mng_dhcp_cookie{ 346struct e1000_host_mng_dhcp_cookie {
350 u32 signature; 347 u32 signature;
351 u16 vlan_id; 348 u16 vlan_id;
352 u8 reserved0; 349 u8 reserved0;
353 u8 status; 350 u8 status;
354 u32 reserved1; 351 u32 reserved1;
355 u8 checksum; 352 u8 checksum;
356 u8 reserved3; 353 u8 reserved3;
357 u16 reserved2; 354 u16 reserved2;
358}; 355};
359#else 356#else
360struct e1000_host_mng_dhcp_cookie{ 357struct e1000_host_mng_dhcp_cookie {
361 u32 signature; 358 u32 signature;
362 u8 status; 359 u8 status;
363 u8 reserved0; 360 u8 reserved0;
364 u16 vlan_id; 361 u16 vlan_id;
365 u32 reserved1; 362 u32 reserved1;
366 u16 reserved2; 363 u16 reserved2;
367 u8 reserved3; 364 u8 reserved3;
368 u8 checksum; 365 u8 checksum;
369}; 366};
370#endif 367#endif
371 368
372bool e1000_check_mng_mode(struct e1000_hw *hw); 369bool e1000_check_mng_mode(struct e1000_hw *hw);
373bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 370bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
374s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); 371s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
375s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); 372s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
376s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); 373s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
377s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); 374s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
378s32 e1000_read_mac_addr(struct e1000_hw * hw); 375s32 e1000_read_mac_addr(struct e1000_hw *hw);
379 376
380/* Filters (multicast, vlan, receive) */ 377/* Filters (multicast, vlan, receive) */
381u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); 378u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
@@ -395,7 +392,8 @@ s32 e1000_blink_led_start(struct e1000_hw *hw);
395/* Everything else */ 392/* Everything else */
396void e1000_reset_adaptive(struct e1000_hw *hw); 393void e1000_reset_adaptive(struct e1000_hw *hw);
397void e1000_update_adaptive(struct e1000_hw *hw); 394void e1000_update_adaptive(struct e1000_hw *hw);
398void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr); 395void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
396 u32 frame_len, u8 * mac_addr);
399void e1000_get_bus_info(struct e1000_hw *hw); 397void e1000_get_bus_info(struct e1000_hw *hw);
400void e1000_pci_set_mwi(struct e1000_hw *hw); 398void e1000_pci_set_mwi(struct e1000_hw *hw);
401void e1000_pci_clear_mwi(struct e1000_hw *hw); 399void e1000_pci_clear_mwi(struct e1000_hw *hw);
@@ -404,7 +402,6 @@ int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
404/* Port I/O is only supported on 82544 and newer */ 402/* Port I/O is only supported on 82544 and newer */
405void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); 403void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
406 404
407
408#define E1000_READ_REG_IO(a, reg) \ 405#define E1000_READ_REG_IO(a, reg) \
409 e1000_read_reg_io((a), E1000_##reg) 406 e1000_read_reg_io((a), E1000_##reg)
410#define E1000_WRITE_REG_IO(a, reg, val) \ 407#define E1000_WRITE_REG_IO(a, reg, val) \
@@ -469,21 +466,20 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
469 466
470/* The sizes (in bytes) of a ethernet packet */ 467/* The sizes (in bytes) of a ethernet packet */
471#define ENET_HEADER_SIZE 14 468#define ENET_HEADER_SIZE 14
472#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 469#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
473#define ETHERNET_FCS_SIZE 4 470#define ETHERNET_FCS_SIZE 4
474#define MINIMUM_ETHERNET_PACKET_SIZE \ 471#define MINIMUM_ETHERNET_PACKET_SIZE \
475 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 472 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
476#define CRC_LENGTH ETHERNET_FCS_SIZE 473#define CRC_LENGTH ETHERNET_FCS_SIZE
477#define MAX_JUMBO_FRAME_SIZE 0x3F00 474#define MAX_JUMBO_FRAME_SIZE 0x3F00
478 475
479
480/* 802.1q VLAN Packet Sizes */ 476/* 802.1q VLAN Packet Sizes */
481#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 477#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
482 478
483/* Ethertype field values */ 479/* Ethertype field values */
484#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 480#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
485#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 481#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
486#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 482#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
487 483
488/* Packet Header defines */ 484/* Packet Header defines */
489#define IP_PROTOCOL_TCP 6 485#define IP_PROTOCOL_TCP 6
@@ -525,93 +521,93 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
525 521
526/* Receive Descriptor */ 522/* Receive Descriptor */
527struct e1000_rx_desc { 523struct e1000_rx_desc {
528 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 524 __le64 buffer_addr; /* Address of the descriptor's data buffer */
529 __le16 length; /* Length of data DMAed into data buffer */ 525 __le16 length; /* Length of data DMAed into data buffer */
530 __le16 csum; /* Packet checksum */ 526 __le16 csum; /* Packet checksum */
531 u8 status; /* Descriptor status */ 527 u8 status; /* Descriptor status */
532 u8 errors; /* Descriptor Errors */ 528 u8 errors; /* Descriptor Errors */
533 __le16 special; 529 __le16 special;
534}; 530};
535 531
536/* Receive Descriptor - Extended */ 532/* Receive Descriptor - Extended */
537union e1000_rx_desc_extended { 533union e1000_rx_desc_extended {
538 struct { 534 struct {
539 __le64 buffer_addr; 535 __le64 buffer_addr;
540 __le64 reserved; 536 __le64 reserved;
541 } read; 537 } read;
542 struct { 538 struct {
543 struct { 539 struct {
544 __le32 mrq; /* Multiple Rx Queues */ 540 __le32 mrq; /* Multiple Rx Queues */
545 union { 541 union {
546 __le32 rss; /* RSS Hash */ 542 __le32 rss; /* RSS Hash */
547 struct { 543 struct {
548 __le16 ip_id; /* IP id */ 544 __le16 ip_id; /* IP id */
549 __le16 csum; /* Packet Checksum */ 545 __le16 csum; /* Packet Checksum */
550 } csum_ip; 546 } csum_ip;
551 } hi_dword; 547 } hi_dword;
552 } lower; 548 } lower;
553 struct { 549 struct {
554 __le32 status_error; /* ext status/error */ 550 __le32 status_error; /* ext status/error */
555 __le16 length; 551 __le16 length;
556 __le16 vlan; /* VLAN tag */ 552 __le16 vlan; /* VLAN tag */
557 } upper; 553 } upper;
558 } wb; /* writeback */ 554 } wb; /* writeback */
559}; 555};
560 556
561#define MAX_PS_BUFFERS 4 557#define MAX_PS_BUFFERS 4
562/* Receive Descriptor - Packet Split */ 558/* Receive Descriptor - Packet Split */
563union e1000_rx_desc_packet_split { 559union e1000_rx_desc_packet_split {
564 struct { 560 struct {
565 /* one buffer for protocol header(s), three data buffers */ 561 /* one buffer for protocol header(s), three data buffers */
566 __le64 buffer_addr[MAX_PS_BUFFERS]; 562 __le64 buffer_addr[MAX_PS_BUFFERS];
567 } read; 563 } read;
568 struct { 564 struct {
569 struct { 565 struct {
570 __le32 mrq; /* Multiple Rx Queues */ 566 __le32 mrq; /* Multiple Rx Queues */
571 union { 567 union {
572 __le32 rss; /* RSS Hash */ 568 __le32 rss; /* RSS Hash */
573 struct { 569 struct {
574 __le16 ip_id; /* IP id */ 570 __le16 ip_id; /* IP id */
575 __le16 csum; /* Packet Checksum */ 571 __le16 csum; /* Packet Checksum */
576 } csum_ip; 572 } csum_ip;
577 } hi_dword; 573 } hi_dword;
578 } lower; 574 } lower;
579 struct { 575 struct {
580 __le32 status_error; /* ext status/error */ 576 __le32 status_error; /* ext status/error */
581 __le16 length0; /* length of buffer 0 */ 577 __le16 length0; /* length of buffer 0 */
582 __le16 vlan; /* VLAN tag */ 578 __le16 vlan; /* VLAN tag */
583 } middle; 579 } middle;
584 struct { 580 struct {
585 __le16 header_status; 581 __le16 header_status;
586 __le16 length[3]; /* length of buffers 1-3 */ 582 __le16 length[3]; /* length of buffers 1-3 */
587 } upper; 583 } upper;
588 __le64 reserved; 584 __le64 reserved;
589 } wb; /* writeback */ 585 } wb; /* writeback */
590}; 586};
591 587
592/* Receive Decriptor bit definitions */ 588/* Receive Descriptor bit definitions */
593#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 589#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
594#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 590#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
595#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 591#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
596#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 592#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
597#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 593#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
598#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 594#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
599#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 595#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
600#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 596#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
601#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 597#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
602#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 598#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
603#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 599#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
604#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 600#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
605#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 601#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
606#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 602#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
607#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 603#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
608#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 604#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
609#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 605#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
610#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 606#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
611#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 607#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
612#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 608#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
613#define E1000_RXD_SPC_PRI_SHIFT 13 609#define E1000_RXD_SPC_PRI_SHIFT 13
614#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 610#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
615#define E1000_RXD_SPC_CFI_SHIFT 12 611#define E1000_RXD_SPC_CFI_SHIFT 12
616 612
617#define E1000_RXDEXT_STATERR_CE 0x01000000 613#define E1000_RXDEXT_STATERR_CE 0x01000000
@@ -633,7 +629,6 @@ union e1000_rx_desc_packet_split {
633 E1000_RXD_ERR_CXE | \ 629 E1000_RXD_ERR_CXE | \
634 E1000_RXD_ERR_RXE) 630 E1000_RXD_ERR_RXE)
635 631
636
637/* Same mask, but for extended and packet split descriptors */ 632/* Same mask, but for extended and packet split descriptors */
638#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 633#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
639 E1000_RXDEXT_STATERR_CE | \ 634 E1000_RXDEXT_STATERR_CE | \
@@ -642,109 +637,108 @@ union e1000_rx_desc_packet_split {
642 E1000_RXDEXT_STATERR_CXE | \ 637 E1000_RXDEXT_STATERR_CXE | \
643 E1000_RXDEXT_STATERR_RXE) 638 E1000_RXDEXT_STATERR_RXE)
644 639
645
646/* Transmit Descriptor */ 640/* Transmit Descriptor */
647struct e1000_tx_desc { 641struct e1000_tx_desc {
648 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 642 __le64 buffer_addr; /* Address of the descriptor's data buffer */
649 union { 643 union {
650 __le32 data; 644 __le32 data;
651 struct { 645 struct {
652 __le16 length; /* Data buffer length */ 646 __le16 length; /* Data buffer length */
653 u8 cso; /* Checksum offset */ 647 u8 cso; /* Checksum offset */
654 u8 cmd; /* Descriptor control */ 648 u8 cmd; /* Descriptor control */
655 } flags; 649 } flags;
656 } lower; 650 } lower;
657 union { 651 union {
658 __le32 data; 652 __le32 data;
659 struct { 653 struct {
660 u8 status; /* Descriptor status */ 654 u8 status; /* Descriptor status */
661 u8 css; /* Checksum start */ 655 u8 css; /* Checksum start */
662 __le16 special; 656 __le16 special;
663 } fields; 657 } fields;
664 } upper; 658 } upper;
665}; 659};
666 660
667/* Transmit Descriptor bit definitions */ 661/* Transmit Descriptor bit definitions */
668#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 662#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
669#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 663#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
670#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 664#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
671#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 665#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
672#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 666#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
673#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 667#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
674#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 668#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
675#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 669#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
676#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 670#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
677#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 671#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
678#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 672#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
679#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 673#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
680#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 674#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
681#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 675#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
682#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 676#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
683#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 677#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
684#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 678#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
685#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 679#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
686#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 680#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
687#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 681#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
688 682
689/* Offload Context Descriptor */ 683/* Offload Context Descriptor */
690struct e1000_context_desc { 684struct e1000_context_desc {
691 union { 685 union {
692 __le32 ip_config; 686 __le32 ip_config;
693 struct { 687 struct {
694 u8 ipcss; /* IP checksum start */ 688 u8 ipcss; /* IP checksum start */
695 u8 ipcso; /* IP checksum offset */ 689 u8 ipcso; /* IP checksum offset */
696 __le16 ipcse; /* IP checksum end */ 690 __le16 ipcse; /* IP checksum end */
697 } ip_fields; 691 } ip_fields;
698 } lower_setup; 692 } lower_setup;
699 union { 693 union {
700 __le32 tcp_config; 694 __le32 tcp_config;
701 struct { 695 struct {
702 u8 tucss; /* TCP checksum start */ 696 u8 tucss; /* TCP checksum start */
703 u8 tucso; /* TCP checksum offset */ 697 u8 tucso; /* TCP checksum offset */
704 __le16 tucse; /* TCP checksum end */ 698 __le16 tucse; /* TCP checksum end */
705 } tcp_fields; 699 } tcp_fields;
706 } upper_setup; 700 } upper_setup;
707 __le32 cmd_and_length; /* */ 701 __le32 cmd_and_length; /* */
708 union { 702 union {
709 __le32 data; 703 __le32 data;
710 struct { 704 struct {
711 u8 status; /* Descriptor status */ 705 u8 status; /* Descriptor status */
712 u8 hdr_len; /* Header length */ 706 u8 hdr_len; /* Header length */
713 __le16 mss; /* Maximum segment size */ 707 __le16 mss; /* Maximum segment size */
714 } fields; 708 } fields;
715 } tcp_seg_setup; 709 } tcp_seg_setup;
716}; 710};
717 711
718/* Offload data descriptor */ 712/* Offload data descriptor */
719struct e1000_data_desc { 713struct e1000_data_desc {
720 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 714 __le64 buffer_addr; /* Address of the descriptor's buffer address */
721 union { 715 union {
722 __le32 data; 716 __le32 data;
723 struct { 717 struct {
724 __le16 length; /* Data buffer length */ 718 __le16 length; /* Data buffer length */
725 u8 typ_len_ext; /* */ 719 u8 typ_len_ext; /* */
726 u8 cmd; /* */ 720 u8 cmd; /* */
727 } flags; 721 } flags;
728 } lower; 722 } lower;
729 union { 723 union {
730 __le32 data; 724 __le32 data;
731 struct { 725 struct {
732 u8 status; /* Descriptor status */ 726 u8 status; /* Descriptor status */
733 u8 popts; /* Packet Options */ 727 u8 popts; /* Packet Options */
734 __le16 special; /* */ 728 __le16 special; /* */
735 } fields; 729 } fields;
736 } upper; 730 } upper;
737}; 731};
738 732
739/* Filters */ 733/* Filters */
740#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 734#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
741#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 735#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
742#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 736#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
743 737
744/* Receive Address Register */ 738/* Receive Address Register */
745struct e1000_rar { 739struct e1000_rar {
746 volatile __le32 low; /* receive address low */ 740 volatile __le32 low; /* receive address low */
747 volatile __le32 high; /* receive address high */ 741 volatile __le32 high; /* receive address high */
748}; 742};
749 743
750/* Number of entries in the Multicast Table Array (MTA). */ 744/* Number of entries in the Multicast Table Array (MTA). */
@@ -752,8 +746,8 @@ struct e1000_rar {
752 746
753/* IPv4 Address Table Entry */ 747/* IPv4 Address Table Entry */
754struct e1000_ipv4_at_entry { 748struct e1000_ipv4_at_entry {
755 volatile u32 ipv4_addr; /* IP Address (RW) */ 749 volatile u32 ipv4_addr; /* IP Address (RW) */
756 volatile u32 reserved; 750 volatile u32 reserved;
757}; 751};
758 752
759/* Four wakeup IP addresses are supported */ 753/* Four wakeup IP addresses are supported */
@@ -763,25 +757,25 @@ struct e1000_ipv4_at_entry {
763 757
764/* IPv6 Address Table Entry */ 758/* IPv6 Address Table Entry */
765struct e1000_ipv6_at_entry { 759struct e1000_ipv6_at_entry {
766 volatile u8 ipv6_addr[16]; 760 volatile u8 ipv6_addr[16];
767}; 761};
768 762
769/* Flexible Filter Length Table Entry */ 763/* Flexible Filter Length Table Entry */
770struct e1000_fflt_entry { 764struct e1000_fflt_entry {
771 volatile u32 length; /* Flexible Filter Length (RW) */ 765 volatile u32 length; /* Flexible Filter Length (RW) */
772 volatile u32 reserved; 766 volatile u32 reserved;
773}; 767};
774 768
775/* Flexible Filter Mask Table Entry */ 769/* Flexible Filter Mask Table Entry */
776struct e1000_ffmt_entry { 770struct e1000_ffmt_entry {
777 volatile u32 mask; /* Flexible Filter Mask (RW) */ 771 volatile u32 mask; /* Flexible Filter Mask (RW) */
778 volatile u32 reserved; 772 volatile u32 reserved;
779}; 773};
780 774
781/* Flexible Filter Value Table Entry */ 775/* Flexible Filter Value Table Entry */
782struct e1000_ffvt_entry { 776struct e1000_ffvt_entry {
783 volatile u32 value; /* Flexible Filter Value (RW) */ 777 volatile u32 value; /* Flexible Filter Value (RW) */
784 volatile u32 reserved; 778 volatile u32 reserved;
785}; 779};
786 780
787/* Four Flexible Filters are supported */ 781/* Four Flexible Filters are supported */
@@ -808,210 +802,211 @@ struct e1000_ffvt_entry {
808 * R/clr - register is read only and is cleared when read 802 * R/clr - register is read only and is cleared when read
809 * A - register array 803 * A - register array
810 */ 804 */
811#define E1000_CTRL 0x00000 /* Device Control - RW */ 805#define E1000_CTRL 0x00000 /* Device Control - RW */
812#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 806#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
813#define E1000_STATUS 0x00008 /* Device Status - RO */ 807#define E1000_STATUS 0x00008 /* Device Status - RO */
814#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 808#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
815#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 809#define E1000_EERD 0x00014 /* EEPROM Read - RW */
816#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 810#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
817#define E1000_FLA 0x0001C /* Flash Access - RW */ 811#define E1000_FLA 0x0001C /* Flash Access - RW */
818#define E1000_MDIC 0x00020 /* MDI Control - RW */ 812#define E1000_MDIC 0x00020 /* MDI Control - RW */
819#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 813#define E1000_SCTL 0x00024 /* SerDes Control - RW */
820#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ 814#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
821#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 815#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
822#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 816#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
823#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 817#define E1000_FCT 0x00030 /* Flow Control Type - RW */
824#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 818#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
825#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 819#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
826#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 820#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
827#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 821#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
828#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 822#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
829#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 823#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
830#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 824#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
831#define E1000_RCTL 0x00100 /* RX Control - RW */ 825#define E1000_RCTL 0x00100 /* RX Control - RW */
832#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ 826#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
833#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ 827#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
834#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ 828#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
835#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ 829#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
836#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ 830#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
837#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ 831#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
838#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 832#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
839#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 833#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
840#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 834#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
841#define E1000_TCTL 0x00400 /* TX Control - RW */ 835#define E1000_TCTL 0x00400 /* TX Control - RW */
842#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 836#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
843#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 837#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
844#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 838#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
845#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 839#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
846#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 840#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
847#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 841#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
848#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 842#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
849#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 843#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
850#define FEXTNVM_SW_CONFIG 0x0001 844#define FEXTNVM_SW_CONFIG 0x0001
851#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 845#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
852#define E1000_PBS 0x01008 /* Packet Buffer Size */ 846#define E1000_PBS 0x01008 /* Packet Buffer Size */
853#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 847#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
854#define E1000_FLASH_UPDATES 1000 848#define E1000_FLASH_UPDATES 1000
855#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 849#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
856#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 850#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
857#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 851#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
858#define E1000_FLSWCTL 0x01030 /* FLASH control register */ 852#define E1000_FLSWCTL 0x01030 /* FLASH control register */
859#define E1000_FLSWDATA 0x01034 /* FLASH data register */ 853#define E1000_FLSWDATA 0x01034 /* FLASH data register */
860#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 854#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
861#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 855#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
862#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 856#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
863#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 857#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
864#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 858#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
865#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 859#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
866#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 860#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
867#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 861#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
868#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 862#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
869#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 863#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
870#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 864#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
871#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 865#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
872#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ 866#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
873#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ 867#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
874#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ 868#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
875#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 869#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
876#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 870#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
877#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 871#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
878#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ 872#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
879#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ 873#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
880#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 874#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
881#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 875#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
882#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 876#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
883#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 877#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
884#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 878#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
885#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 879#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
886#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 880#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
887#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 881#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
888#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 882#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
889#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 883#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
890#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 884#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
891#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 885#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
892#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 886#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
893#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 887#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
894#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 888#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
895#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 889#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
896#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 890#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
897#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 891#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
898#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 892#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
899#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 893#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
900#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 894#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
901#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 895#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
902#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 896#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
903#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 897#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
904#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 898#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
905#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ 899#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
906#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 900#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
907#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 901#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
908#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 902#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
909#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 903#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
910#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 904#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
911#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 905#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
912#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 906#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
913#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 907#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
914#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 908#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
915#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 909#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
916#define E1000_COLC 0x04028 /* Collision Count - R/clr */ 910#define E1000_COLC 0x04028 /* Collision Count - R/clr */
917#define E1000_DC 0x04030 /* Defer Count - R/clr */ 911#define E1000_DC 0x04030 /* Defer Count - R/clr */
918#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 912#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
919#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 913#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
920#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 914#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
921#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 915#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
922#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 916#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
923#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 917#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
924#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 918#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
925#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 919#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
926#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 920#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
927#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 921#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
928#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 922#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
929#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 923#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
930#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 924#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
931#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 925#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
932#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 926#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
933#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 927#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
934#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 928#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
935#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 929#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
936#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 930#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
937#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 931#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
938#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 932#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
939#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 933#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
940#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 934#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
941#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 935#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
942#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 936#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
943#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 937#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
944#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 938#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
945#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 939#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
946#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 940#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
947#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 941#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
948#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 942#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
949#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 943#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
950#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 944#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
951#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 945#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
952#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 946#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
953#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 947#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
954#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 948#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
955#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 949#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
956#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 950#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
957#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 951#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
958#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 952#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
959#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 953#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
960#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 954#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
961#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 955#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
962#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 956#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
963#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 957#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
964#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 958#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
965#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 959#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
966#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 960#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
967#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ 961#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
968#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ 962#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
969#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ 963#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
970#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 964#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
971#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ 965#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
972#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 966#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
973#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 967#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
974#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 968#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
975#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 969#define E1000_RFCTL 0x05008 /* Receive Filter Control */
976#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 970#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
977#define E1000_RA 0x05400 /* Receive Address - RW Array */ 971#define E1000_RA 0x05400 /* Receive Address - RW Array */
978#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 972#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
979#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 973#define E1000_WUC 0x05800 /* Wakeup Control - RW */
980#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 974#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
981#define E1000_WUS 0x05810 /* Wakeup Status - RO */ 975#define E1000_WUS 0x05810 /* Wakeup Status - RO */
982#define E1000_MANC 0x05820 /* Management Control - RW */ 976#define E1000_MANC 0x05820 /* Management Control - RW */
983#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 977#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
984#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 978#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
985#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 979#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
986#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 980#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
987#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 981#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
988#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 982#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
989#define E1000_HOST_IF 0x08800 /* Host Interface */ 983#define E1000_HOST_IF 0x08800 /* Host Interface */
990#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 984#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
991#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 985#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
992 986
993#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 987#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
994#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 988#define E1000_MDPHYA 0x0003C /* PHY address - RW */
995#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 989#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
996 990#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
997#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 991
998#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 992#define E1000_GCR 0x05B00 /* PCI-Ex Control */
999#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 993#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1000#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 994#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1001#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 995#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1002#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 996#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1003#define E1000_SWSM 0x05B50 /* SW Semaphore */ 997#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1004#define E1000_FWSM 0x05B54 /* FW Semaphore */ 998#define E1000_SWSM 0x05B50 /* SW Semaphore */
1005#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 999#define E1000_FWSM 0x05B54 /* FW Semaphore */
1006#define E1000_HICR 0x08F00 /* Host Inteface Control */ 1000#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1001#define E1000_HICR 0x08F00 /* Host Interface Control */
1007 1002
1008/* RSS registers */ 1003/* RSS registers */
1009#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 1004#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1010#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 1005#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1011#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ 1006#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1012#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ 1007#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1013#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 1008#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1014#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 1009#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1015/* Register Set (82542) 1010/* Register Set (82542)
1016 * 1011 *
1017 * Some of the 82542 registers are located at different offsets than they are 1012 * Some of the 82542 registers are located at different offsets than they are
@@ -1051,19 +1046,19 @@ struct e1000_ffvt_entry {
1051#define E1000_82542_RDLEN0 E1000_82542_RDLEN 1046#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1052#define E1000_82542_RDH0 E1000_82542_RDH 1047#define E1000_82542_RDH0 E1000_82542_RDH
1053#define E1000_82542_RDT0 E1000_82542_RDT 1048#define E1000_82542_RDT0 E1000_82542_RDT
1054#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication 1049#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1055 * RX Control - RW */ 1050 * RX Control - RW */
1056#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) 1051#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1057#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ 1052#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1058#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ 1053#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1059#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ 1054#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1060#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ 1055#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1061#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ 1056#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1062#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ 1057#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1063#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ 1058#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1064#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ 1059#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1065#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ 1060#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1066#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ 1061#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1067#define E1000_82542_RDTR1 0x00130 1062#define E1000_82542_RDTR1 0x00130
1068#define E1000_82542_RDBAL1 0x00138 1063#define E1000_82542_RDBAL1 0x00138
1069#define E1000_82542_RDBAH1 0x0013C 1064#define E1000_82542_RDBAH1 0x0013C
@@ -1233,279 +1228,278 @@ struct e1000_ffvt_entry {
1233 1228
1234/* Statistics counters collected by the MAC */ 1229/* Statistics counters collected by the MAC */
1235struct e1000_hw_stats { 1230struct e1000_hw_stats {
1236 u64 crcerrs; 1231 u64 crcerrs;
1237 u64 algnerrc; 1232 u64 algnerrc;
1238 u64 symerrs; 1233 u64 symerrs;
1239 u64 rxerrc; 1234 u64 rxerrc;
1240 u64 txerrc; 1235 u64 txerrc;
1241 u64 mpc; 1236 u64 mpc;
1242 u64 scc; 1237 u64 scc;
1243 u64 ecol; 1238 u64 ecol;
1244 u64 mcc; 1239 u64 mcc;
1245 u64 latecol; 1240 u64 latecol;
1246 u64 colc; 1241 u64 colc;
1247 u64 dc; 1242 u64 dc;
1248 u64 tncrs; 1243 u64 tncrs;
1249 u64 sec; 1244 u64 sec;
1250 u64 cexterr; 1245 u64 cexterr;
1251 u64 rlec; 1246 u64 rlec;
1252 u64 xonrxc; 1247 u64 xonrxc;
1253 u64 xontxc; 1248 u64 xontxc;
1254 u64 xoffrxc; 1249 u64 xoffrxc;
1255 u64 xofftxc; 1250 u64 xofftxc;
1256 u64 fcruc; 1251 u64 fcruc;
1257 u64 prc64; 1252 u64 prc64;
1258 u64 prc127; 1253 u64 prc127;
1259 u64 prc255; 1254 u64 prc255;
1260 u64 prc511; 1255 u64 prc511;
1261 u64 prc1023; 1256 u64 prc1023;
1262 u64 prc1522; 1257 u64 prc1522;
1263 u64 gprc; 1258 u64 gprc;
1264 u64 bprc; 1259 u64 bprc;
1265 u64 mprc; 1260 u64 mprc;
1266 u64 gptc; 1261 u64 gptc;
1267 u64 gorcl; 1262 u64 gorcl;
1268 u64 gorch; 1263 u64 gorch;
1269 u64 gotcl; 1264 u64 gotcl;
1270 u64 gotch; 1265 u64 gotch;
1271 u64 rnbc; 1266 u64 rnbc;
1272 u64 ruc; 1267 u64 ruc;
1273 u64 rfc; 1268 u64 rfc;
1274 u64 roc; 1269 u64 roc;
1275 u64 rlerrc; 1270 u64 rlerrc;
1276 u64 rjc; 1271 u64 rjc;
1277 u64 mgprc; 1272 u64 mgprc;
1278 u64 mgpdc; 1273 u64 mgpdc;
1279 u64 mgptc; 1274 u64 mgptc;
1280 u64 torl; 1275 u64 torl;
1281 u64 torh; 1276 u64 torh;
1282 u64 totl; 1277 u64 totl;
1283 u64 toth; 1278 u64 toth;
1284 u64 tpr; 1279 u64 tpr;
1285 u64 tpt; 1280 u64 tpt;
1286 u64 ptc64; 1281 u64 ptc64;
1287 u64 ptc127; 1282 u64 ptc127;
1288 u64 ptc255; 1283 u64 ptc255;
1289 u64 ptc511; 1284 u64 ptc511;
1290 u64 ptc1023; 1285 u64 ptc1023;
1291 u64 ptc1522; 1286 u64 ptc1522;
1292 u64 mptc; 1287 u64 mptc;
1293 u64 bptc; 1288 u64 bptc;
1294 u64 tsctc; 1289 u64 tsctc;
1295 u64 tsctfc; 1290 u64 tsctfc;
1296 u64 iac; 1291 u64 iac;
1297 u64 icrxptc; 1292 u64 icrxptc;
1298 u64 icrxatc; 1293 u64 icrxatc;
1299 u64 ictxptc; 1294 u64 ictxptc;
1300 u64 ictxatc; 1295 u64 ictxatc;
1301 u64 ictxqec; 1296 u64 ictxqec;
1302 u64 ictxqmtc; 1297 u64 ictxqmtc;
1303 u64 icrxdmtc; 1298 u64 icrxdmtc;
1304 u64 icrxoc; 1299 u64 icrxoc;
1305}; 1300};
1306 1301
1307/* Structure containing variables used by the shared code (e1000_hw.c) */ 1302/* Structure containing variables used by the shared code (e1000_hw.c) */
1308struct e1000_hw { 1303struct e1000_hw {
1309 u8 __iomem *hw_addr; 1304 u8 __iomem *hw_addr;
1310 u8 __iomem *flash_address; 1305 u8 __iomem *flash_address;
1311 e1000_mac_type mac_type; 1306 e1000_mac_type mac_type;
1312 e1000_phy_type phy_type; 1307 e1000_phy_type phy_type;
1313 u32 phy_init_script; 1308 u32 phy_init_script;
1314 e1000_media_type media_type; 1309 e1000_media_type media_type;
1315 void *back; 1310 void *back;
1316 struct e1000_shadow_ram *eeprom_shadow_ram; 1311 struct e1000_shadow_ram *eeprom_shadow_ram;
1317 u32 flash_bank_size; 1312 u32 flash_bank_size;
1318 u32 flash_base_addr; 1313 u32 flash_base_addr;
1319 e1000_fc_type fc; 1314 e1000_fc_type fc;
1320 e1000_bus_speed bus_speed; 1315 e1000_bus_speed bus_speed;
1321 e1000_bus_width bus_width; 1316 e1000_bus_width bus_width;
1322 e1000_bus_type bus_type; 1317 e1000_bus_type bus_type;
1323 struct e1000_eeprom_info eeprom; 1318 struct e1000_eeprom_info eeprom;
1324 e1000_ms_type master_slave; 1319 e1000_ms_type master_slave;
1325 e1000_ms_type original_master_slave; 1320 e1000_ms_type original_master_slave;
1326 e1000_ffe_config ffe_config_state; 1321 e1000_ffe_config ffe_config_state;
1327 u32 asf_firmware_present; 1322 u32 asf_firmware_present;
1328 u32 eeprom_semaphore_present; 1323 u32 eeprom_semaphore_present;
1329 unsigned long io_base; 1324 unsigned long io_base;
1330 u32 phy_id; 1325 u32 phy_id;
1331 u32 phy_revision; 1326 u32 phy_revision;
1332 u32 phy_addr; 1327 u32 phy_addr;
1333 u32 original_fc; 1328 u32 original_fc;
1334 u32 txcw; 1329 u32 txcw;
1335 u32 autoneg_failed; 1330 u32 autoneg_failed;
1336 u32 max_frame_size; 1331 u32 max_frame_size;
1337 u32 min_frame_size; 1332 u32 min_frame_size;
1338 u32 mc_filter_type; 1333 u32 mc_filter_type;
1339 u32 num_mc_addrs; 1334 u32 num_mc_addrs;
1340 u32 collision_delta; 1335 u32 collision_delta;
1341 u32 tx_packet_delta; 1336 u32 tx_packet_delta;
1342 u32 ledctl_default; 1337 u32 ledctl_default;
1343 u32 ledctl_mode1; 1338 u32 ledctl_mode1;
1344 u32 ledctl_mode2; 1339 u32 ledctl_mode2;
1345 bool tx_pkt_filtering; 1340 bool tx_pkt_filtering;
1346 struct e1000_host_mng_dhcp_cookie mng_cookie; 1341 struct e1000_host_mng_dhcp_cookie mng_cookie;
1347 u16 phy_spd_default; 1342 u16 phy_spd_default;
1348 u16 autoneg_advertised; 1343 u16 autoneg_advertised;
1349 u16 pci_cmd_word; 1344 u16 pci_cmd_word;
1350 u16 fc_high_water; 1345 u16 fc_high_water;
1351 u16 fc_low_water; 1346 u16 fc_low_water;
1352 u16 fc_pause_time; 1347 u16 fc_pause_time;
1353 u16 current_ifs_val; 1348 u16 current_ifs_val;
1354 u16 ifs_min_val; 1349 u16 ifs_min_val;
1355 u16 ifs_max_val; 1350 u16 ifs_max_val;
1356 u16 ifs_step_size; 1351 u16 ifs_step_size;
1357 u16 ifs_ratio; 1352 u16 ifs_ratio;
1358 u16 device_id; 1353 u16 device_id;
1359 u16 vendor_id; 1354 u16 vendor_id;
1360 u16 subsystem_id; 1355 u16 subsystem_id;
1361 u16 subsystem_vendor_id; 1356 u16 subsystem_vendor_id;
1362 u8 revision_id; 1357 u8 revision_id;
1363 u8 autoneg; 1358 u8 autoneg;
1364 u8 mdix; 1359 u8 mdix;
1365 u8 forced_speed_duplex; 1360 u8 forced_speed_duplex;
1366 u8 wait_autoneg_complete; 1361 u8 wait_autoneg_complete;
1367 u8 dma_fairness; 1362 u8 dma_fairness;
1368 u8 mac_addr[NODE_ADDRESS_SIZE]; 1363 u8 mac_addr[NODE_ADDRESS_SIZE];
1369 u8 perm_mac_addr[NODE_ADDRESS_SIZE]; 1364 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1370 bool disable_polarity_correction; 1365 bool disable_polarity_correction;
1371 bool speed_downgraded; 1366 bool speed_downgraded;
1372 e1000_smart_speed smart_speed; 1367 e1000_smart_speed smart_speed;
1373 e1000_dsp_config dsp_config_state; 1368 e1000_dsp_config dsp_config_state;
1374 bool get_link_status; 1369 bool get_link_status;
1375 bool serdes_has_link; 1370 bool serdes_has_link;
1376 bool tbi_compatibility_en; 1371 bool tbi_compatibility_en;
1377 bool tbi_compatibility_on; 1372 bool tbi_compatibility_on;
1378 bool laa_is_present; 1373 bool laa_is_present;
1379 bool phy_reset_disable; 1374 bool phy_reset_disable;
1380 bool initialize_hw_bits_disable; 1375 bool initialize_hw_bits_disable;
1381 bool fc_send_xon; 1376 bool fc_send_xon;
1382 bool fc_strict_ieee; 1377 bool fc_strict_ieee;
1383 bool report_tx_early; 1378 bool report_tx_early;
1384 bool adaptive_ifs; 1379 bool adaptive_ifs;
1385 bool ifs_params_forced; 1380 bool ifs_params_forced;
1386 bool in_ifs_mode; 1381 bool in_ifs_mode;
1387 bool mng_reg_access_disabled; 1382 bool mng_reg_access_disabled;
1388 bool leave_av_bit_off; 1383 bool leave_av_bit_off;
1389 bool bad_tx_carr_stats_fd; 1384 bool bad_tx_carr_stats_fd;
1390 bool has_smbus; 1385 bool has_smbus;
1391}; 1386};
1392 1387
1393 1388#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1394#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1389#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1395#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1390#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1396#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 1391#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1397#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1392#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1398#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 1393#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1399#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1394#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1400#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 1395#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1401#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1402/* Register Bit Masks */ 1396/* Register Bit Masks */
1403/* Device Control */ 1397/* Device Control */
1404#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1398#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1405#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1399#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1406#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1400#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1407#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 1401#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1408#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1402#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1409#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1403#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1410#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1404#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1411#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 1405#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1412#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 1406#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1413#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 1407#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1414#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 1408#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1415#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 1409#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1416#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1410#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1417#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1411#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1418#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1412#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1419#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1413#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1420#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1414#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1421#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 1415#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1422#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 1416#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1423#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 1417#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1424#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 1418#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1425#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1419#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1426#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1420#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1427#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1421#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1428#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1422#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1429#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1423#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1430#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1424#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1431#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1425#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1432#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1426#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1433#define E1000_CTRL_RST 0x04000000 /* Global reset */ 1427#define E1000_CTRL_RST 0x04000000 /* Global reset */
1434#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1428#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1435#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1429#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1436#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1430#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1437#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1431#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1438#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1432#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1439#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 1433#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1440 1434
1441/* Device Status */ 1435/* Device Status */
1442#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1436#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1443#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1437#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1444#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1438#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1445#define E1000_STATUS_FUNC_SHIFT 2 1439#define E1000_STATUS_FUNC_SHIFT 2
1446#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1440#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1447#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1441#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1448#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1442#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1449#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1443#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1450#define E1000_STATUS_SPEED_MASK 0x000000C0 1444#define E1000_STATUS_SPEED_MASK 0x000000C0
1451#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1445#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1452#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1446#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1453#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1447#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1454#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion 1448#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1455 by EEPROM/Flash */ 1449 by EEPROM/Flash */
1456#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1450#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1457#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1451#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1458#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1452#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1459#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1453#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1460#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1454#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1461#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1455#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1462#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1456#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1463#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1457#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1464#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 1458#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1465#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 1459#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1466#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 1460#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1467#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 1461#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1468#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 1462#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1469#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 1463#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1470#define E1000_STATUS_FUSE_8 0x04000000 1464#define E1000_STATUS_FUSE_8 0x04000000
1471#define E1000_STATUS_FUSE_9 0x08000000 1465#define E1000_STATUS_FUSE_9 0x08000000
1472#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 1466#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1473#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 1467#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1474 1468
1475/* Constants used to intrepret the masked PCI-X bus speed. */ 1469/* Constants used to interpret the masked PCI-X bus speed. */
1476#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1470#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1477#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1471#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1478#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1472#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1479 1473
1480/* EEPROM/Flash Control */ 1474/* EEPROM/Flash Control */
1481#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1475#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1482#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1476#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1483#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1477#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1484#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1478#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1485#define E1000_EECD_FWE_MASK 0x00000030 1479#define E1000_EECD_FWE_MASK 0x00000030
1486#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1480#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1487#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1481#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1488#define E1000_EECD_FWE_SHIFT 4 1482#define E1000_EECD_FWE_SHIFT 4
1489#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1483#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1490#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1484#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1491#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1485#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1492#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1486#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1493#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1487#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1494 * (0-small, 1-large) */ 1488 * (0-small, 1-large) */
1495#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1489#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1496#ifndef E1000_EEPROM_GRANT_ATTEMPTS 1490#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1497#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1491#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1498#endif 1492#endif
1499#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 1493#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1500#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 1494#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1501#define E1000_EECD_SIZE_EX_SHIFT 11 1495#define E1000_EECD_SIZE_EX_SHIFT 11
1502#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1496#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1503#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1497#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1504#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1498#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1505#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1499#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1506#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1500#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1507#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1501#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1508#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1502#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1509#define E1000_EECD_SECVAL_SHIFT 22 1503#define E1000_EECD_SECVAL_SHIFT 22
1510#define E1000_STM_OPCODE 0xDB00 1504#define E1000_STM_OPCODE 0xDB00
1511#define E1000_HICR_FW_RESET 0xC0 1505#define E1000_HICR_FW_RESET 0xC0
@@ -1515,12 +1509,12 @@ struct e1000_hw {
1515#define E1000_ICH_NVM_SIG_MASK 0xC0 1509#define E1000_ICH_NVM_SIG_MASK 0xC0
1516 1510
1517/* EEPROM Read */ 1511/* EEPROM Read */
1518#define E1000_EERD_START 0x00000001 /* Start Read */ 1512#define E1000_EERD_START 0x00000001 /* Start Read */
1519#define E1000_EERD_DONE 0x00000010 /* Read Done */ 1513#define E1000_EERD_DONE 0x00000010 /* Read Done */
1520#define E1000_EERD_ADDR_SHIFT 8 1514#define E1000_EERD_ADDR_SHIFT 8
1521#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1515#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1522#define E1000_EERD_DATA_SHIFT 16 1516#define E1000_EERD_DATA_SHIFT 16
1523#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1517#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1524 1518
1525/* SPI EEPROM Status Register */ 1519/* SPI EEPROM Status Register */
1526#define EEPROM_STATUS_RDY_SPI 0x01 1520#define EEPROM_STATUS_RDY_SPI 0x01
@@ -1530,25 +1524,25 @@ struct e1000_hw {
1530#define EEPROM_STATUS_WPEN_SPI 0x80 1524#define EEPROM_STATUS_WPEN_SPI 0x80
1531 1525
1532/* Extended Device Control */ 1526/* Extended Device Control */
1533#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1527#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1534#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1528#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1535#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1529#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1536#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1530#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1537#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1531#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1538#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 1532#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1539#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 1533#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1540#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1534#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1541#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 1535#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1542#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 1536#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1543#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1537#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1544#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1538#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1545#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1539#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1546#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1540#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1547#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1541#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1548#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1542#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1549#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1543#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1550#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1544#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1551#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1545#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1552#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1546#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1553#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1547#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1554#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1548#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
@@ -1560,11 +1554,11 @@ struct e1000_hw {
1560#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1554#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1561#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1555#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1562#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1556#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1563#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1557#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1564#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1558#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1565#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1559#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1566#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 1560#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1567#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 1561#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1568#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 1562#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1569 1563
1570/* MDI Control */ 1564/* MDI Control */
@@ -1664,167 +1658,167 @@ struct e1000_hw {
1664#define E1000_LEDCTL_MODE_LED_OFF 0xF 1658#define E1000_LEDCTL_MODE_LED_OFF 0xF
1665 1659
1666/* Receive Address */ 1660/* Receive Address */
1667#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1661#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1668 1662
1669/* Interrupt Cause Read */ 1663/* Interrupt Cause Read */
1670#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1664#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1671#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1665#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1672#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1666#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1673#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1667#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1674#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1668#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1675#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1669#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1676#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1670#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1677#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1671#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1678#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1672#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1679#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1673#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1680#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1674#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1681#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1675#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1682#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1676#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1683#define E1000_ICR_TXD_LOW 0x00008000 1677#define E1000_ICR_TXD_LOW 0x00008000
1684#define E1000_ICR_SRPD 0x00010000 1678#define E1000_ICR_SRPD 0x00010000
1685#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 1679#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1686#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 1680#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1687#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 1681#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1688#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 1682#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1689#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 1683#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1690#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 1684#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1691#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 1685#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1692#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 1686#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1693#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1687#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1694#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1688#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1695#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1689#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1696#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 1690#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1697#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 1691#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1698#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 1692#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
1699 1693
1700/* Interrupt Cause Set */ 1694/* Interrupt Cause Set */
1701#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1695#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1702#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1696#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1703#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1697#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1704#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1698#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1705#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1699#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1706#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1700#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1707#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1701#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1708#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1702#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1709#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1703#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1710#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1704#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1711#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1705#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1712#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1706#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1713#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1707#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1714#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1708#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1715#define E1000_ICS_SRPD E1000_ICR_SRPD 1709#define E1000_ICS_SRPD E1000_ICR_SRPD
1716#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1710#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1717#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 1711#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1718#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1712#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1719#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1713#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1720#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1714#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1721#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1715#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1722#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1716#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1723#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1717#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1724#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1718#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1725#define E1000_ICS_DSW E1000_ICR_DSW 1719#define E1000_ICS_DSW E1000_ICR_DSW
1726#define E1000_ICS_PHYINT E1000_ICR_PHYINT 1720#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1727#define E1000_ICS_EPRST E1000_ICR_EPRST 1721#define E1000_ICS_EPRST E1000_ICR_EPRST
1728 1722
1729/* Interrupt Mask Set */ 1723/* Interrupt Mask Set */
1730#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1724#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1731#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1725#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1732#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1726#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1733#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1727#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1734#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1728#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1735#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1729#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1736#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1730#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1737#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1731#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1738#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1732#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1739#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1733#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1740#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1734#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1741#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1735#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1742#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1736#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1743#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1737#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1744#define E1000_IMS_SRPD E1000_ICR_SRPD 1738#define E1000_IMS_SRPD E1000_ICR_SRPD
1745#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1739#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1746#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 1740#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1747#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1741#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1748#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1742#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1749#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1743#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1750#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1744#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1751#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1745#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1752#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1746#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1753#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1747#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1754#define E1000_IMS_DSW E1000_ICR_DSW 1748#define E1000_IMS_DSW E1000_ICR_DSW
1755#define E1000_IMS_PHYINT E1000_ICR_PHYINT 1749#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1756#define E1000_IMS_EPRST E1000_ICR_EPRST 1750#define E1000_IMS_EPRST E1000_ICR_EPRST
1757 1751
1758/* Interrupt Mask Clear */ 1752/* Interrupt Mask Clear */
1759#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1753#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1760#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1754#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1761#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1755#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1762#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1756#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1763#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1757#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1764#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1758#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1765#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1759#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1766#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1760#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1767#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1761#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1768#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1762#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1769#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1763#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1770#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1764#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1771#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1765#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1772#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1766#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1773#define E1000_IMC_SRPD E1000_ICR_SRPD 1767#define E1000_IMC_SRPD E1000_ICR_SRPD
1774#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 1768#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1775#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 1769#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1776#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1770#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1777#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1771#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1778#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1772#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1779#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1773#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1780#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1774#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1781#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1775#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1782#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1776#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1783#define E1000_IMC_DSW E1000_ICR_DSW 1777#define E1000_IMC_DSW E1000_ICR_DSW
1784#define E1000_IMC_PHYINT E1000_ICR_PHYINT 1778#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1785#define E1000_IMC_EPRST E1000_ICR_EPRST 1779#define E1000_IMC_EPRST E1000_ICR_EPRST
1786 1780
1787/* Receive Control */ 1781/* Receive Control */
1788#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1782#define E1000_RCTL_RST 0x00000001 /* Software reset */
1789#define E1000_RCTL_EN 0x00000002 /* enable */ 1783#define E1000_RCTL_EN 0x00000002 /* enable */
1790#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1784#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1791#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1785#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1792#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1786#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1793#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1787#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1794#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1788#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1795#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1789#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1796#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1790#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1797#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1791#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1798#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 1792#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1799#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 1793#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1800#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1794#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1801#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1795#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1802#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1796#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1803#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1797#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1804#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1798#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1805#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1799#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1806#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1800#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1807#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1801#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1808#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1802#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1809#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1803#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1810/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1804/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1811#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1805#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1812#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1806#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1813#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1807#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1814#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1808#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1815/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1809/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1816#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1810#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1817#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1811#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1818#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1812#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1819#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1813#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1820#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1814#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1821#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1815#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1822#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1816#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1823#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1817#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1824#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1818#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1825#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1819#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1826#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 1820#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1827#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 1821#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1828 1822
1829/* Use byte values for the following shift parameters 1823/* Use byte values for the following shift parameters
1830 * Usage: 1824 * Usage:
@@ -1847,10 +1841,10 @@ struct e1000_hw {
1847#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 1841#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1848#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 1842#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1849 1843
1850#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 1844#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1851#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 1845#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1852#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 1846#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1853#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 1847#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1854 1848
1855/* SW_W_SYNC definitions */ 1849/* SW_W_SYNC definitions */
1856#define E1000_SWFW_EEP_SM 0x0001 1850#define E1000_SWFW_EEP_SM 0x0001
@@ -1859,17 +1853,17 @@ struct e1000_hw {
1859#define E1000_SWFW_MAC_CSR_SM 0x0008 1853#define E1000_SWFW_MAC_CSR_SM 0x0008
1860 1854
1861/* Receive Descriptor */ 1855/* Receive Descriptor */
1862#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1856#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1863#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1857#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1864#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1858#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1865#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1859#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1866#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1860#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1867 1861
1868/* Flow Control */ 1862/* Flow Control */
1869#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1863#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1870#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1864#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1871#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1865#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1872#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1866#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1873 1867
1874/* Header split receive */ 1868/* Header split receive */
1875#define E1000_RFCTL_ISCSI_DIS 0x00000001 1869#define E1000_RFCTL_ISCSI_DIS 0x00000001
@@ -1889,64 +1883,64 @@ struct e1000_hw {
1889#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1883#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1890 1884
1891/* Receive Descriptor Control */ 1885/* Receive Descriptor Control */
1892#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1886#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1893#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1887#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1894#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1888#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1895#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1889#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1896 1890
1897/* Transmit Descriptor Control */ 1891/* Transmit Descriptor Control */
1898#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 1892#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1899#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 1893#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1900#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 1894#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1901#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1895#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1902#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1896#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1903#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1897#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1904#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 1898#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1905 still to be processed. */ 1899 still to be processed. */
1906/* Transmit Configuration Word */ 1900/* Transmit Configuration Word */
1907#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1901#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1908#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1902#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1909#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1903#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1910#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1904#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1911#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1905#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1912#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1906#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1913#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1907#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1914#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1908#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1915#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1909#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1916#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1910#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1917 1911
1918/* Receive Configuration Word */ 1912/* Receive Configuration Word */
1919#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1913#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1920#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1914#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1921#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1915#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1922#define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1916#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1923#define E1000_RXCW_C 0x20000000 /* Receive config */ 1917#define E1000_RXCW_C 0x20000000 /* Receive config */
1924#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1918#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1925#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1919#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1926 1920
1927/* Transmit Control */ 1921/* Transmit Control */
1928#define E1000_TCTL_RST 0x00000001 /* software reset */ 1922#define E1000_TCTL_RST 0x00000001 /* software reset */
1929#define E1000_TCTL_EN 0x00000002 /* enable tx */ 1923#define E1000_TCTL_EN 0x00000002 /* enable tx */
1930#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 1924#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1931#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 1925#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1932#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 1926#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1933#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 1927#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1934#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 1928#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1935#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1929#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1936#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1930#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1937#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1931#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1938#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 1932#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1939/* Extended Transmit Control */ 1933/* Extended Transmit Control */
1940#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 1934#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
1941#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 1935#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
1942 1936
1943/* Receive Checksum Control */ 1937/* Receive Checksum Control */
1944#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1938#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1945#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1939#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1946#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1940#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1947#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1941#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1948#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1942#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1949#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1943#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1950 1944
1951/* Multiple Receive Queue Control */ 1945/* Multiple Receive Queue Control */
1952#define E1000_MRQC_ENABLE_MASK 0x00000003 1946#define E1000_MRQC_ENABLE_MASK 0x00000003
@@ -1962,141 +1956,141 @@ struct e1000_hw {
1962 1956
1963/* Definitions for power management and wakeup registers */ 1957/* Definitions for power management and wakeup registers */
1964/* Wake Up Control */ 1958/* Wake Up Control */
1965#define E1000_WUC_APME 0x00000001 /* APM Enable */ 1959#define E1000_WUC_APME 0x00000001 /* APM Enable */
1966#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1960#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1967#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1961#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1968#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1962#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1969#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 1963#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1970 1964
1971/* Wake Up Filter Control */ 1965/* Wake Up Filter Control */
1972#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 1966#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1973#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1967#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1974#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1968#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1975#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 1969#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1976#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1970#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1977#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1971#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1978#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1972#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1979#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1973#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1980#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 1974#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1981#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1975#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1982#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1976#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1983#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1977#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1984#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 1978#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1985#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 1979#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1986#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 1980#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1987#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1981#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1988 1982
1989/* Wake Up Status */ 1983/* Wake Up Status */
1990#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 1984#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1991#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 1985#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1992#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 1986#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1993#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 1987#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1994#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 1988#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1995#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 1989#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1996#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 1990#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1997#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 1991#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1998#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 1992#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1999#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 1993#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
2000#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 1994#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
2001#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 1995#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
2002#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1996#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2003 1997
2004/* Management Control */ 1998/* Management Control */
2005#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 1999#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2006#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 2000#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2007#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 2001#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2008#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 2002#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2009#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 2003#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2010#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 2004#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2011#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 2005#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2012#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 2006#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2013#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 2007#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2014#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 2008#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2015 * Filtering */ 2009 * Filtering */
2016#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 2010#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
2017#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 2011#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2018#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 2012#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2019#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 2013#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2020#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 2014#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2021#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 2015#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2022#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 2016#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2023 * filtering */ 2017 * filtering */
2024#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 2018#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2025 * memory */ 2019 * memory */
2026#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2020#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2027 * filtering */ 2021 * filtering */
2028#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2022#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2029#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2023#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2030#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2024#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2031#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2025#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2032#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2026#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2033#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 2027#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2034#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 2028#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2035#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 2029#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2036 2030
2037#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 2031#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2038#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 2032#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2039 2033
2040/* SW Semaphore Register */ 2034/* SW Semaphore Register */
2041#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2035#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2042#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2036#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2043#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2037#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2044#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 2038#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2045 2039
2046/* FW Semaphore Register */ 2040/* FW Semaphore Register */
2047#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ 2041#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2048#define E1000_FWSM_MODE_SHIFT 1 2042#define E1000_FWSM_MODE_SHIFT 1
2049#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2043#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2050 2044
2051#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 2045#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2052#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ 2046#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2053#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ 2047#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2054#define E1000_FWSM_SKUEL_SHIFT 29 2048#define E1000_FWSM_SKUEL_SHIFT 29
2055#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ 2049#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2056#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ 2050#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2057#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ 2051#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2058#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ 2052#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2059 2053
2060/* FFLT Debug Register */ 2054/* FFLT Debug Register */
2061#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2055#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2062 2056
2063typedef enum { 2057typedef enum {
2064 e1000_mng_mode_none = 0, 2058 e1000_mng_mode_none = 0,
2065 e1000_mng_mode_asf, 2059 e1000_mng_mode_asf,
2066 e1000_mng_mode_pt, 2060 e1000_mng_mode_pt,
2067 e1000_mng_mode_ipmi, 2061 e1000_mng_mode_ipmi,
2068 e1000_mng_mode_host_interface_only 2062 e1000_mng_mode_host_interface_only
2069} e1000_mng_mode; 2063} e1000_mng_mode;
2070 2064
2071/* Host Inteface Control Register */ 2065/* Host Interface Control Register */
2072#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ 2066#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2073#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done 2067#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2074 * to put command in RAM */ 2068 * to put command in RAM */
2075#define E1000_HICR_SV 0x00000004 /* Status Validity */ 2069#define E1000_HICR_SV 0x00000004 /* Status Validity */
2076#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ 2070#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2077 2071
2078/* Host Interface Command Interface - Address range 0x8800-0x8EFF */ 2072/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2079#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ 2073#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2080#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ 2074#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2081#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ 2075#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2082#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2076#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2083 2077
2084struct e1000_host_command_header { 2078struct e1000_host_command_header {
2085 u8 command_id; 2079 u8 command_id;
2086 u8 command_length; 2080 u8 command_length;
2087 u8 command_options; /* I/F bits for command, status for return */ 2081 u8 command_options; /* I/F bits for command, status for return */
2088 u8 checksum; 2082 u8 checksum;
2089}; 2083};
2090struct e1000_host_command_info { 2084struct e1000_host_command_info {
2091 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2085 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2092 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2086 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2093}; 2087};
2094 2088
2095/* Host SMB register #0 */ 2089/* Host SMB register #0 */
2096#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ 2090#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2097#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ 2091#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2098#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ 2092#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2099#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ 2093#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2100 2094
2101/* Host SMB register #1 */ 2095/* Host SMB register #1 */
2102#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN 2096#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
@@ -2105,10 +2099,10 @@ struct e1000_host_command_info {
2105#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT 2099#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2106 2100
2107/* FW Status Register */ 2101/* FW Status Register */
2108#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ 2102#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2109 2103
2110/* Wake Up Packet Length */ 2104/* Wake Up Packet Length */
2111#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 2105#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2112 2106
2113#define E1000_MDALIGN 4096 2107#define E1000_MDALIGN 4096
2114 2108
@@ -2162,24 +2156,24 @@ struct e1000_host_command_info {
2162#define PCI_EX_LINK_WIDTH_SHIFT 4 2156#define PCI_EX_LINK_WIDTH_SHIFT 4
2163 2157
2164/* EEPROM Commands - Microwire */ 2158/* EEPROM Commands - Microwire */
2165#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 2159#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2166#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 2160#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2167#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 2161#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2168#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 2162#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2169#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 2163#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */
2170 2164
2171/* EEPROM Commands - SPI */ 2165/* EEPROM Commands - SPI */
2172#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2166#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2173#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2167#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2174#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2168#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2175#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2169#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2176#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ 2170#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2177#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ 2171#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2178#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ 2172#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2179#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ 2173#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2180#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2174#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2181#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2175#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2182#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2176#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2183 2177
2184/* EEPROM Size definitions */ 2178/* EEPROM Size definitions */
2185#define EEPROM_WORD_SIZE_SHIFT 6 2179#define EEPROM_WORD_SIZE_SHIFT 6
@@ -2190,7 +2184,7 @@ struct e1000_host_command_info {
2190#define EEPROM_COMPAT 0x0003 2184#define EEPROM_COMPAT 0x0003
2191#define EEPROM_ID_LED_SETTINGS 0x0004 2185#define EEPROM_ID_LED_SETTINGS 0x0004
2192#define EEPROM_VERSION 0x0005 2186#define EEPROM_VERSION 0x0005
2193#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 2187#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2194#define EEPROM_PHY_CLASS_WORD 0x0007 2188#define EEPROM_PHY_CLASS_WORD 0x0007
2195#define EEPROM_INIT_CONTROL1_REG 0x000A 2189#define EEPROM_INIT_CONTROL1_REG 0x000A
2196#define EEPROM_INIT_CONTROL2_REG 0x000F 2190#define EEPROM_INIT_CONTROL2_REG 0x000F
@@ -2203,8 +2197,8 @@ struct e1000_host_command_info {
2203#define EEPROM_FLASH_VERSION 0x0032 2197#define EEPROM_FLASH_VERSION 0x0032
2204#define EEPROM_CHECKSUM_REG 0x003F 2198#define EEPROM_CHECKSUM_REG 0x003F
2205 2199
2206#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 2200#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2207#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 2201#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
2208 2202
2209/* Word definitions for ID LED Settings */ 2203/* Word definitions for ID LED Settings */
2210#define ID_LED_RESERVED_0000 0x0000 2204#define ID_LED_RESERVED_0000 0x0000
@@ -2227,7 +2221,6 @@ struct e1000_host_command_info {
2227#define IGP_ACTIVITY_LED_ENABLE 0x0300 2221#define IGP_ACTIVITY_LED_ENABLE 0x0300
2228#define IGP_LED3_MODE 0x07000000 2222#define IGP_LED3_MODE 0x07000000
2229 2223
2230
2231/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 2224/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2232#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 2225#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2233 2226
@@ -2332,9 +2325,9 @@ struct e1000_host_command_info {
2332#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 2325#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2333 2326
2334/* PBA constants */ 2327/* PBA constants */
2335#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ 2328#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2336#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2329#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2337#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2330#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2338#define E1000_PBA_20K 0x0014 2331#define E1000_PBA_20K 0x0014
2339#define E1000_PBA_22K 0x0016 2332#define E1000_PBA_22K 0x0016
2340#define E1000_PBA_24K 0x0018 2333#define E1000_PBA_24K 0x0018
@@ -2343,7 +2336,7 @@ struct e1000_host_command_info {
2343#define E1000_PBA_34K 0x0022 2336#define E1000_PBA_34K 0x0022
2344#define E1000_PBA_38K 0x0026 2337#define E1000_PBA_38K 0x0026
2345#define E1000_PBA_40K 0x0028 2338#define E1000_PBA_40K 0x0028
2346#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2339#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2347 2340
2348#define E1000_PBS_16K E1000_PBA_16K 2341#define E1000_PBS_16K E1000_PBA_16K
2349 2342
@@ -2353,9 +2346,9 @@ struct e1000_host_command_info {
2353#define FLOW_CONTROL_TYPE 0x8808 2346#define FLOW_CONTROL_TYPE 0x8808
2354 2347
2355/* The historical defaults for the flow control values are given below. */ 2348/* The historical defaults for the flow control values are given below. */
2356#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 2349#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2357#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 2350#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2358#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 2351#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2359 2352
2360/* PCIX Config space */ 2353/* PCIX Config space */
2361#define PCIX_COMMAND_REGISTER 0xE6 2354#define PCIX_COMMAND_REGISTER 0xE6
@@ -2369,7 +2362,6 @@ struct e1000_host_command_info {
2369#define PCIX_STATUS_HI_MMRBC_4K 0x3 2362#define PCIX_STATUS_HI_MMRBC_4K 0x3
2370#define PCIX_STATUS_HI_MMRBC_2K 0x2 2363#define PCIX_STATUS_HI_MMRBC_2K 0x2
2371 2364
2372
2373/* Number of bits required to shift right the "pause" bits from the 2365/* Number of bits required to shift right the "pause" bits from the
2374 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 2366 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2375 */ 2367 */
@@ -2390,7 +2382,6 @@ struct e1000_host_command_info {
2390 */ 2382 */
2391#define ILOS_SHIFT 3 2383#define ILOS_SHIFT 3
2392 2384
2393
2394#define RECEIVE_BUFFER_ALIGN_SIZE (256) 2385#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2395 2386
2396/* Number of milliseconds we wait for auto-negotiation to complete */ 2387/* Number of milliseconds we wait for auto-negotiation to complete */
@@ -2443,7 +2434,6 @@ struct e1000_host_command_info {
2443 (((length) > (adapter)->min_frame_size) && \ 2434 (((length) > (adapter)->min_frame_size) && \
2444 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 2435 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2445 2436
2446
2447/* Structures, enums, and macros for the PHY */ 2437/* Structures, enums, and macros for the PHY */
2448 2438
2449/* Bit definitions for the Management Data IO (MDIO) and Management Data 2439/* Bit definitions for the Management Data IO (MDIO) and Management Data
@@ -2460,49 +2450,49 @@ struct e1000_host_command_info {
2460 2450
2461/* PHY 1000 MII Register/Bit Definitions */ 2451/* PHY 1000 MII Register/Bit Definitions */
2462/* PHY Registers defined by IEEE */ 2452/* PHY Registers defined by IEEE */
2463#define PHY_CTRL 0x00 /* Control Register */ 2453#define PHY_CTRL 0x00 /* Control Register */
2464#define PHY_STATUS 0x01 /* Status Regiser */ 2454#define PHY_STATUS 0x01 /* Status Register */
2465#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 2455#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2466#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 2456#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2467#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 2457#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2468#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 2458#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2469#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 2459#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2470#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 2460#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2471#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 2461#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2472#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 2462#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2473#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 2463#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2474#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 2464#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2475 2465
2476#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 2466#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2477#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ 2467#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2478 2468
2479/* M88E1000 Specific Registers */ 2469/* M88E1000 Specific Registers */
2480#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 2470#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2481#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 2471#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2482#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 2472#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2483#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 2473#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2484#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 2474#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2485#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 2475#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2486 2476
2487#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 2477#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2488#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 2478#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2489#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 2479#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2490#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 2480#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2491#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 2481#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2492 2482
2493#define IGP01E1000_IEEE_REGS_PAGE 0x0000 2483#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2494#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 2484#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2495#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 2485#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2496 2486
2497/* IGP01E1000 Specific Registers */ 2487/* IGP01E1000 Specific Registers */
2498#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 2488#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2499#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 2489#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2500#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 2490#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2501#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2491#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2502#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2492#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2503#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2493#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2504#define IGP02E1000_PHY_POWER_MGMT 0x19 2494#define IGP02E1000_PHY_POWER_MGMT 0x19
2505#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2495#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2506 2496
2507/* IGP01E1000 AGC Registers - stores the cable length values*/ 2497/* IGP01E1000 AGC Registers - stores the cable length values*/
2508#define IGP01E1000_PHY_AGC_A 0x1172 2498#define IGP01E1000_PHY_AGC_A 0x1172
@@ -2546,118 +2536,118 @@ struct e1000_host_command_info {
2546#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 2536#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2547 2537
2548/* PHY Control Register */ 2538/* PHY Control Register */
2549#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2539#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2550#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 2540#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2551#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 2541#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2552#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 2542#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2553#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 2543#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2554#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 2544#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2555#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 2545#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2556#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2546#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2557#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 2547#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2558#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 2548#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2559 2549
2560/* PHY Status Register */ 2550/* PHY Status Register */
2561#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 2551#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2562#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 2552#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2563#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 2553#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2564#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 2554#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2565#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 2555#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2566#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 2556#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2567#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 2557#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2568#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 2558#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2569#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 2559#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2570#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 2560#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2571#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 2561#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2572#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 2562#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2573#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 2563#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2574#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 2564#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2575#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 2565#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2576 2566
2577/* Autoneg Advertisement Register */ 2567/* Autoneg Advertisement Register */
2578#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 2568#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2579#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 2569#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2580#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 2570#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2581#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 2571#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2582#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 2572#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2583#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 2573#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2584#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 2574#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2585#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 2575#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2586#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 2576#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2587#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2577#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2588 2578
2589/* Link Partner Ability Register (Base Page) */ 2579/* Link Partner Ability Register (Base Page) */
2590#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 2580#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2591#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 2581#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2592#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 2582#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2593#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 2583#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2594#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 2584#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2595#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 2585#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2596#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 2586#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2597#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 2587#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2598#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 2588#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2599#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 2589#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2600#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2590#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2601 2591
2602/* Autoneg Expansion Register */ 2592/* Autoneg Expansion Register */
2603#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 2593#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2604#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 2594#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2605#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 2595#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2606#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 2596#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2607#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 2597#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2608 2598
2609/* Next Page TX Register */ 2599/* Next Page TX Register */
2610#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2600#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2611#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 2601#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2612 * of different NP 2602 * of different NP
2613 */ 2603 */
2614#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2604#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2615 * 0 = cannot comply with msg 2605 * 0 = cannot comply with msg
2616 */ 2606 */
2617#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2607#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2618#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2608#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2619 * 0 = sending last NP 2609 * 0 = sending last NP
2620 */ 2610 */
2621 2611
2622/* Link Partner Next Page Register */ 2612/* Link Partner Next Page Register */
2623#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2613#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2624#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 2614#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2625 * of different NP 2615 * of different NP
2626 */ 2616 */
2627#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2617#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2628 * 0 = cannot comply with msg 2618 * 0 = cannot comply with msg
2629 */ 2619 */
2630#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2620#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2631#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 2621#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2632#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2622#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2633 * 0 = sending last NP 2623 * 0 = sending last NP
2634 */ 2624 */
2635 2625
2636/* 1000BASE-T Control Register */ 2626/* 1000BASE-T Control Register */
2637#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 2627#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2638#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 2628#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2639#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 2629#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2640#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 2630#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2641 /* 0=DTE device */ 2631 /* 0=DTE device */
2642#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 2632#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2643 /* 0=Configure PHY as Slave */ 2633 /* 0=Configure PHY as Slave */
2644#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 2634#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2645 /* 0=Automatic Master/Slave config */ 2635 /* 0=Automatic Master/Slave config */
2646#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 2636#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2647#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 2637#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2648#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 2638#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2649#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 2639#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2650#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 2640#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2651 2641
2652/* 1000BASE-T Status Register */ 2642/* 1000BASE-T Status Register */
2653#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 2643#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2654#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 2644#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2655#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 2645#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2656#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 2646#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2657#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 2647#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2658#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 2648#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2659#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 2649#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2660#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 2650#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2661#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 2651#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2662#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 2652#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2663#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 2653#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
@@ -2665,64 +2655,64 @@ struct e1000_host_command_info {
2665#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 2655#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2666 2656
2667/* Extended Status Register */ 2657/* Extended Status Register */
2668#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 2658#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2669#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 2659#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2670#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 2660#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2671#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 2661#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2672 2662
2673#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 2663#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2674#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 2664#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2675 2665
2676#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 2666#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2677 /* (0=enable, 1=disable) */ 2667 /* (0=enable, 1=disable) */
2678 2668
2679/* M88E1000 PHY Specific Control Register */ 2669/* M88E1000 PHY Specific Control Register */
2680#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 2670#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2681#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 2671#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2682#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 2672#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2683#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 2673#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2684 * 0=CLK125 toggling 2674 * 0=CLK125 toggling
2685 */ 2675 */
2686#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 2676#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2687 /* Manual MDI configuration */ 2677 /* Manual MDI configuration */
2688#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 2678#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2689#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 2679#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2690 * 100BASE-TX/10BASE-T: 2680 * 100BASE-TX/10BASE-T:
2691 * MDI Mode 2681 * MDI Mode
2692 */ 2682 */
2693#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 2683#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2694 * all speeds. 2684 * all speeds.
2695 */ 2685 */
2696#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 2686#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2697 /* 1=Enable Extended 10BASE-T distance 2687 /* 1=Enable Extended 10BASE-T distance
2698 * (Lower 10BASE-T RX Threshold) 2688 * (Lower 10BASE-T RX Threshold)
2699 * 0=Normal 10BASE-T RX Threshold */ 2689 * 0=Normal 10BASE-T RX Threshold */
2700#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 2690#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2701 /* 1=5-Bit interface in 100BASE-TX 2691 /* 1=5-Bit interface in 100BASE-TX
2702 * 0=MII interface in 100BASE-TX */ 2692 * 0=MII interface in 100BASE-TX */
2703#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 2693#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2704#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 2694#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2705#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 2695#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2706 2696
2707#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 2697#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2708#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 2698#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2709#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 2699#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2710 2700
2711/* M88E1000 PHY Specific Status Register */ 2701/* M88E1000 PHY Specific Status Register */
2712#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 2702#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2713#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 2703#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2714#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 2704#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2715#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 2705#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2716#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 2706#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2717 * 3=110-140M;4=>140M */ 2707 * 3=110-140M;4=>140M */
2718#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 2708#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2719#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 2709#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2720#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 2710#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2721#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 2711#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2722#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 2712#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2723#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 2713#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2724#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 2714#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2725#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 2715#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2726 2716
2727#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 2717#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2728#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 2718#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
@@ -2730,12 +2720,12 @@ struct e1000_host_command_info {
2730#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 2720#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2731 2721
2732/* M88E1000 Extended PHY Specific Control Register */ 2722/* M88E1000 Extended PHY Specific Control Register */
2733#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 2723#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2734#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 2724#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2735 * Will assert lost lock and bring 2725 * Will assert lost lock and bring
2736 * link down if idle not seen 2726 * link down if idle not seen
2737 * within 1ms in 1000BASE-T 2727 * within 1ms in 1000BASE-T
2738 */ 2728 */
2739/* Number of times we will attempt to autonegotiate before downshifting if we 2729/* Number of times we will attempt to autonegotiate before downshifting if we
2740 * are the master */ 2730 * are the master */
2741#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 2731#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
@@ -2750,9 +2740,9 @@ struct e1000_host_command_info {
2750#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 2740#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2751#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 2741#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2752#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 2742#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2753#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 2743#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2754#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2744#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2755#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2745#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2756 2746
2757/* M88EC018 Rev 2 specific DownShift settings */ 2747/* M88EC018 Rev 2 specific DownShift settings */
2758#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 2748#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
@@ -2774,18 +2764,18 @@ struct e1000_host_command_info {
2774#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 2764#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2775 2765
2776/* IGP01E1000 Specific Port Status Register - R/O */ 2766/* IGP01E1000 Specific Port Status Register - R/O */
2777#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 2767#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2778#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 2768#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2779#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 2769#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2780#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 2770#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2781#define IGP01E1000_PSSR_LINK_UP 0x0400 2771#define IGP01E1000_PSSR_LINK_UP 0x0400
2782#define IGP01E1000_PSSR_MDIX 0x0800 2772#define IGP01E1000_PSSR_MDIX 0x0800
2783#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 2773#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2784#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 2774#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2785#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 2775#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2786#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 2776#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2787#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 2777#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2788#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 2778#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2789 2779
2790/* IGP01E1000 Specific Port Control Register - R/W */ 2780/* IGP01E1000 Specific Port Control Register - R/W */
2791#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 2781#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
@@ -2793,16 +2783,16 @@ struct e1000_host_command_info {
2793#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 2783#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2794#define IGP01E1000_PSCR_FLIP_CHIP 0x0800 2784#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2795#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 2785#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2796#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 2786#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2797 2787
2798/* IGP01E1000 Specific Port Link Health Register */ 2788/* IGP01E1000 Specific Port Link Health Register */
2799#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 2789#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2800#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 2790#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2801#define IGP01E1000_PLHR_MASTER_FAULT 0x2000 2791#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2802#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 2792#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2803#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 2793#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2804#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 2794#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2805#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 2795#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2806#define IGP01E1000_PLHR_DATA_ERR_0 0x0100 2796#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2807#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 2797#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2808#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 2798#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
@@ -2817,9 +2807,9 @@ struct e1000_host_command_info {
2817#define IGP01E1000_MSE_CHANNEL_B 0x0F00 2807#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2818#define IGP01E1000_MSE_CHANNEL_A 0xF000 2808#define IGP01E1000_MSE_CHANNEL_A 0xF000
2819 2809
2820#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 2810#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2821#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ 2811#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2822#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ 2812#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2823 2813
2824/* IGP01E1000 DSP reset macros */ 2814/* IGP01E1000 DSP reset macros */
2825#define DSP_RESET_ENABLE 0x0 2815#define DSP_RESET_ENABLE 0x0
@@ -2828,8 +2818,8 @@ struct e1000_host_command_info {
2828 2818
2829/* IGP01E1000 & IGP02E1000 AGC Registers */ 2819/* IGP01E1000 & IGP02E1000 AGC Registers */
2830 2820
2831#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 2821#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2832#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ 2822#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2833 2823
2834/* IGP02E1000 AGC Register Length 9-bit mask */ 2824/* IGP02E1000 AGC Register Length 9-bit mask */
2835#define IGP02E1000_AGC_LENGTH_MASK 0x7F 2825#define IGP02E1000_AGC_LENGTH_MASK 0x7F
@@ -2847,9 +2837,9 @@ struct e1000_host_command_info {
2847#define IGP01E1000_PHY_POLARITY_MASK 0x0078 2837#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2848 2838
2849/* IGP01E1000 GMII FIFO Register */ 2839/* IGP01E1000 GMII FIFO Register */
2850#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 2840#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2851 * on Link-Up */ 2841 * on Link-Up */
2852#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 2842#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2853 2843
2854/* IGP01E1000 Analog Register */ 2844/* IGP01E1000 Analog Register */
2855#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 2845#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
@@ -2883,7 +2873,6 @@ struct e1000_host_command_info {
2883#define M88E1111_I_PHY_ID 0x01410CC0 2873#define M88E1111_I_PHY_ID 0x01410CC0
2884#define L1LXT971A_PHY_ID 0x001378E0 2874#define L1LXT971A_PHY_ID 0x001378E0
2885 2875
2886
2887/* Bits... 2876/* Bits...
2888 * 15-5: page 2877 * 15-5: page
2889 * 4-0: register offset 2878 * 4-0: register offset
@@ -2893,41 +2882,41 @@ struct e1000_host_command_info {
2893 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 2882 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2894 2883
2895#define IGP3_PHY_PORT_CTRL \ 2884#define IGP3_PHY_PORT_CTRL \
2896 PHY_REG(769, 17) /* Port General Configuration */ 2885 PHY_REG(769, 17) /* Port General Configuration */
2897#define IGP3_PHY_RATE_ADAPT_CTRL \ 2886#define IGP3_PHY_RATE_ADAPT_CTRL \
2898 PHY_REG(769, 25) /* Rate Adapter Control Register */ 2887 PHY_REG(769, 25) /* Rate Adapter Control Register */
2899 2888
2900#define IGP3_KMRN_FIFO_CTRL_STATS \ 2889#define IGP3_KMRN_FIFO_CTRL_STATS \
2901 PHY_REG(770, 16) /* KMRN FIFO's control/status register */ 2890 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2902#define IGP3_KMRN_POWER_MNG_CTRL \ 2891#define IGP3_KMRN_POWER_MNG_CTRL \
2903 PHY_REG(770, 17) /* KMRN Power Management Control Register */ 2892 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2904#define IGP3_KMRN_INBAND_CTRL \ 2893#define IGP3_KMRN_INBAND_CTRL \
2905 PHY_REG(770, 18) /* KMRN Inband Control Register */ 2894 PHY_REG(770, 18) /* KMRN Inband Control Register */
2906#define IGP3_KMRN_DIAG \ 2895#define IGP3_KMRN_DIAG \
2907 PHY_REG(770, 19) /* KMRN Diagnostic register */ 2896 PHY_REG(770, 19) /* KMRN Diagnostic register */
2908#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ 2897#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
2909#define IGP3_KMRN_ACK_TIMEOUT \ 2898#define IGP3_KMRN_ACK_TIMEOUT \
2910 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ 2899 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2911 2900
2912#define IGP3_VR_CTRL \ 2901#define IGP3_VR_CTRL \
2913 PHY_REG(776, 18) /* Voltage regulator control register */ 2902 PHY_REG(776, 18) /* Voltage regulator control register */
2914#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 2903#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
2915#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ 2904#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
2916 2905
2917#define IGP3_CAPABILITY \ 2906#define IGP3_CAPABILITY \
2918 PHY_REG(776, 19) /* IGP3 Capability Register */ 2907 PHY_REG(776, 19) /* IGP3 Capability Register */
2919 2908
2920/* Capabilities for SKU Control */ 2909/* Capabilities for SKU Control */
2921#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ 2910#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
2922#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ 2911#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
2923#define IGP3_CAP_ASF 0x0004 /* Support ASF */ 2912#define IGP3_CAP_ASF 0x0004 /* Support ASF */
2924#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ 2913#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
2925#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ 2914#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
2926#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ 2915#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
2927#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ 2916#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
2928#define IGP3_CAP_RSS 0x0080 /* Support RSS */ 2917#define IGP3_CAP_RSS 0x0080 /* Support RSS */
2929#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ 2918#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
2930#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ 2919#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
2931 2920
2932#define IGP3_PPC_JORDAN_EN 0x0001 2921#define IGP3_PPC_JORDAN_EN 0x0001
2933#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 2922#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
@@ -2937,69 +2926,69 @@ struct e1000_host_command_info {
2937#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 2926#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
2938#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 2927#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
2939 2928
2940#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ 2929#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
2941#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ 2930#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
2942 2931
2943#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) 2932#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
2944#define IGP3_KMRN_EC_DIS_INBAND 0x0080 2933#define IGP3_KMRN_EC_DIS_INBAND 0x0080
2945 2934
2946#define IGP03E1000_E_PHY_ID 0x02A80390 2935#define IGP03E1000_E_PHY_ID 0x02A80390
2947#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ 2936#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
2948#define IFE_PLUS_E_PHY_ID 0x02A80320 2937#define IFE_PLUS_E_PHY_ID 0x02A80320
2949#define IFE_C_E_PHY_ID 0x02A80310 2938#define IFE_C_E_PHY_ID 0x02A80310
2950 2939
2951#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ 2940#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
2952#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ 2941#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
2953#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ 2942#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
2954#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ 2943#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */
2955#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ 2944#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
2956#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ 2945#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
2957#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ 2946#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
2958#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ 2947#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
2959#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ 2948#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
2960#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ 2949#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
2961#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ 2950#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
2962#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ 2951#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
2963#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ 2952#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
2964 2953
2965#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ 2954#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */
2966#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ 2955#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
2967#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ 2956#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
2968#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ 2957#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
2969#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ 2958#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
2970#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ 2959#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
2971#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ 2960#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
2972#define IFE_PESC_POLARITY_REVERSED_SHIFT 8 2961#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
2973 2962
2974#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ 2963#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */
2975#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ 2964#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
2976#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ 2965#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
2977#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ 2966#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
2978#define IFE_PSC_FORCE_POLARITY_SHIFT 5 2967#define IFE_PSC_FORCE_POLARITY_SHIFT 5
2979#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 2968#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
2980 2969
2981#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ 2970#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
2982#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ 2971#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
2983#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 2972#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
2984#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ 2973#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */
2985#define IFE_PMC_MDIX_MODE_SHIFT 6 2974#define IFE_PMC_MDIX_MODE_SHIFT 6
2986#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ 2975#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
2987 2976
2988#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ 2977#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
2989#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ 2978#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
2990#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ 2979#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
2991#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ 2980#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
2992#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ 2981#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
2993#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ 2982#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
2994#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ 2983#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
2995#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ 2984#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
2996#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ 2985#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
2997#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 2986#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
2998#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 2987#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
2999 2988
3000#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 2989#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3001#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 2990#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3002#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 2991#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3003#define ICH_FLASH_SEG_SIZE_256 256 2992#define ICH_FLASH_SEG_SIZE_256 256
3004#define ICH_FLASH_SEG_SIZE_4K 4096 2993#define ICH_FLASH_SEG_SIZE_4K 4096
3005#define ICH_FLASH_SEG_SIZE_64K 65536 2994#define ICH_FLASH_SEG_SIZE_64K 65536
@@ -3043,10 +3032,10 @@ struct e1000_host_command_info {
3043#define MII_CR_SPEED_100 0x2000 3032#define MII_CR_SPEED_100 0x2000
3044#define MII_CR_SPEED_10 0x0000 3033#define MII_CR_SPEED_10 0x0000
3045#define E1000_PHY_ADDRESS 0x01 3034#define E1000_PHY_ADDRESS 0x01
3046#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 3035#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3047#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 3036#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3048#define PHY_REVISION_MASK 0xFFFFFFF0 3037#define PHY_REVISION_MASK 0xFFFFFFF0
3049#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 3038#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3050#define REG4_SPEED_MASK 0x01E0 3039#define REG4_SPEED_MASK 0x01E0
3051#define REG9_SPEED_MASK 0x0300 3040#define REG9_SPEED_MASK 0x0300
3052#define ADVERTISE_10_HALF 0x0001 3041#define ADVERTISE_10_HALF 0x0001
@@ -3055,8 +3044,8 @@ struct e1000_host_command_info {
3055#define ADVERTISE_100_FULL 0x0008 3044#define ADVERTISE_100_FULL 0x0008
3056#define ADVERTISE_1000_HALF 0x0010 3045#define ADVERTISE_1000_HALF 0x0010
3057#define ADVERTISE_1000_FULL 0x0020 3046#define ADVERTISE_1000_FULL 0x0020
3058#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 3047#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3059#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 3048#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
3060#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 3049#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
3061 3050
3062#endif /* _E1000_HW_H_ */ 3051#endif /* _E1000_HW_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 20:58:54 -0500