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path: root/drivers/net/e1000/e1000_hw.h
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.h')
-rw-r--r--drivers/net/e1000/e1000_hw.h386
1 files changed, 370 insertions, 16 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 467c9ed944f8..375b95518c31 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -62,6 +62,7 @@ typedef enum {
62 e1000_82572, 62 e1000_82572,
63 e1000_82573, 63 e1000_82573,
64 e1000_80003es2lan, 64 e1000_80003es2lan,
65 e1000_ich8lan,
65 e1000_num_macs 66 e1000_num_macs
66} e1000_mac_type; 67} e1000_mac_type;
67 68
@@ -70,6 +71,7 @@ typedef enum {
70 e1000_eeprom_spi, 71 e1000_eeprom_spi,
71 e1000_eeprom_microwire, 72 e1000_eeprom_microwire,
72 e1000_eeprom_flash, 73 e1000_eeprom_flash,
74 e1000_eeprom_ich8,
73 e1000_eeprom_none, /* No NVM support */ 75 e1000_eeprom_none, /* No NVM support */
74 e1000_num_eeprom_types 76 e1000_num_eeprom_types
75} e1000_eeprom_type; 77} e1000_eeprom_type;
@@ -98,6 +100,11 @@ typedef enum {
98 e1000_fc_default = 0xFF 100 e1000_fc_default = 0xFF
99} e1000_fc_type; 101} e1000_fc_type;
100 102
103struct e1000_shadow_ram {
104 uint16_t eeprom_word;
105 boolean_t modified;
106};
107
101/* PCI bus types */ 108/* PCI bus types */
102typedef enum { 109typedef enum {
103 e1000_bus_type_unknown = 0, 110 e1000_bus_type_unknown = 0,
@@ -218,6 +225,8 @@ typedef enum {
218 e1000_phy_igp, 225 e1000_phy_igp,
219 e1000_phy_igp_2, 226 e1000_phy_igp_2,
220 e1000_phy_gg82563, 227 e1000_phy_gg82563,
228 e1000_phy_igp_3,
229 e1000_phy_ife,
221 e1000_phy_undefined = 0xFF 230 e1000_phy_undefined = 0xFF
222} e1000_phy_type; 231} e1000_phy_type;
223 232
@@ -313,10 +322,9 @@ int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy
313int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 322int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
314int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 323int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
315int32_t e1000_phy_reset(struct e1000_hw *hw); 324int32_t e1000_phy_reset(struct e1000_hw *hw);
325void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
316int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 326int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
317int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 327int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
318int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
319int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
320 328
321/* EEPROM Functions */ 329/* EEPROM Functions */
322int32_t e1000_init_eeprom_params(struct e1000_hw *hw); 330int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
@@ -331,6 +339,7 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
331#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
332#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
333#define E1000_MNG_IAMT_MODE 0x3 341#define E1000_MNG_IAMT_MODE 0x3
342#define E1000_MNG_ICH_IAMT_MODE 0x2
334#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
335 344
336#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 345#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
@@ -386,11 +395,8 @@ int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
386int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 395int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
387int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num); 396int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
388int32_t e1000_read_mac_addr(struct e1000_hw * hw); 397int32_t e1000_read_mac_addr(struct e1000_hw * hw);
389int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
390void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
391 398
392/* Filters (multicast, vlan, receive) */ 399/* Filters (multicast, vlan, receive) */
393void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
394uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr); 400uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
395void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value); 401void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
396void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index); 402void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
@@ -401,6 +407,7 @@ int32_t e1000_setup_led(struct e1000_hw *hw);
401int32_t e1000_cleanup_led(struct e1000_hw *hw); 407int32_t e1000_cleanup_led(struct e1000_hw *hw);
402int32_t e1000_led_on(struct e1000_hw *hw); 408int32_t e1000_led_on(struct e1000_hw *hw);
403int32_t e1000_led_off(struct e1000_hw *hw); 409int32_t e1000_led_off(struct e1000_hw *hw);
410int32_t e1000_blink_led_start(struct e1000_hw *hw);
404 411
405/* Adaptive IFS Functions */ 412/* Adaptive IFS Functions */
406 413
@@ -414,15 +421,16 @@ void e1000_pci_clear_mwi(struct e1000_hw *hw);
414void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); 421void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
415void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); 422void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
416/* Port I/O is only supported on 82544 and newer */ 423/* Port I/O is only supported on 82544 and newer */
417uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
418uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
419void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value); 424void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
420void e1000_enable_pciex_master(struct e1000_hw *hw);
421int32_t e1000_disable_pciex_master(struct e1000_hw *hw); 425int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
422int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
423void e1000_release_software_semaphore(struct e1000_hw *hw);
424int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 426int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
425 427
428
429#define E1000_READ_REG_IO(a, reg) \
430 e1000_read_reg_io((a), E1000_##reg)
431#define E1000_WRITE_REG_IO(a, reg, val) \
432 e1000_write_reg_io((a), E1000_##reg, val)
433
426/* PCI Device IDs */ 434/* PCI Device IDs */
427#define E1000_DEV_ID_82542 0x1000 435#define E1000_DEV_ID_82542 0x1000
428#define E1000_DEV_ID_82543GC_FIBER 0x1001 436#define E1000_DEV_ID_82543GC_FIBER 0x1001
@@ -446,6 +454,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
446#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 454#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
447#define E1000_DEV_ID_82541EI 0x1013 455#define E1000_DEV_ID_82541EI 0x1013
448#define E1000_DEV_ID_82541EI_MOBILE 0x1018 456#define E1000_DEV_ID_82541EI_MOBILE 0x1018
457#define E1000_DEV_ID_82541ER_LOM 0x1014
449#define E1000_DEV_ID_82541ER 0x1078 458#define E1000_DEV_ID_82541ER 0x1078
450#define E1000_DEV_ID_82547GI 0x1075 459#define E1000_DEV_ID_82547GI 0x1075
451#define E1000_DEV_ID_82541GI 0x1076 460#define E1000_DEV_ID_82541GI 0x1076
@@ -457,18 +466,28 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
457#define E1000_DEV_ID_82546GB_PCIE 0x108A 466#define E1000_DEV_ID_82546GB_PCIE 0x108A
458#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 467#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
459#define E1000_DEV_ID_82547EI 0x1019 468#define E1000_DEV_ID_82547EI 0x1019
469#define E1000_DEV_ID_82547EI_MOBILE 0x101A
460#define E1000_DEV_ID_82571EB_COPPER 0x105E 470#define E1000_DEV_ID_82571EB_COPPER 0x105E
461#define E1000_DEV_ID_82571EB_FIBER 0x105F 471#define E1000_DEV_ID_82571EB_FIBER 0x105F
462#define E1000_DEV_ID_82571EB_SERDES 0x1060 472#define E1000_DEV_ID_82571EB_SERDES 0x1060
463#define E1000_DEV_ID_82572EI_COPPER 0x107D 473#define E1000_DEV_ID_82572EI_COPPER 0x107D
464#define E1000_DEV_ID_82572EI_FIBER 0x107E 474#define E1000_DEV_ID_82572EI_FIBER 0x107E
465#define E1000_DEV_ID_82572EI_SERDES 0x107F 475#define E1000_DEV_ID_82572EI_SERDES 0x107F
476#define E1000_DEV_ID_82572EI 0x10B9
466#define E1000_DEV_ID_82573E 0x108B 477#define E1000_DEV_ID_82573E 0x108B
467#define E1000_DEV_ID_82573E_IAMT 0x108C 478#define E1000_DEV_ID_82573E_IAMT 0x108C
468#define E1000_DEV_ID_82573L 0x109A 479#define E1000_DEV_ID_82573L 0x109A
469#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 480#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
470#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 481#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
471#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 482#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
483#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
484#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
485
486#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
487#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
488#define E1000_DEV_ID_ICH8_IGP_C 0x104B
489#define E1000_DEV_ID_ICH8_IFE 0x104C
490#define E1000_DEV_ID_ICH8_IGP_M 0x104D
472 491
473 492
474#define NODE_ADDRESS_SIZE 6 493#define NODE_ADDRESS_SIZE 6
@@ -539,6 +558,14 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
539 E1000_IMS_RXSEQ | \ 558 E1000_IMS_RXSEQ | \
540 E1000_IMS_LSC) 559 E1000_IMS_LSC)
541 560
561/* Additional interrupts need to be handled for e1000_ich8lan:
562 DSW = The FW changed the status of the DISSW bit in FWSM
563 PHYINT = The LAN connected device generates an interrupt
564 EPRST = Manageability reset event */
565#define IMS_ICH8LAN_ENABLE_MASK (\
566 E1000_IMS_DSW | \
567 E1000_IMS_PHYINT | \
568 E1000_IMS_EPRST)
542 569
543/* Number of high/low register pairs in the RAR. The RAR (Receive Address 570/* Number of high/low register pairs in the RAR. The RAR (Receive Address
544 * Registers) holds the directed and multicast addresses that we monitor. We 571 * Registers) holds the directed and multicast addresses that we monitor. We
@@ -546,6 +573,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
546 * E1000_RAR_ENTRIES - 1 multicast addresses. 573 * E1000_RAR_ENTRIES - 1 multicast addresses.
547 */ 574 */
548#define E1000_RAR_ENTRIES 15 575#define E1000_RAR_ENTRIES 15
576#define E1000_RAR_ENTRIES_ICH8LAN 7
549 577
550#define MIN_NUMBER_OF_DESCRIPTORS 8 578#define MIN_NUMBER_OF_DESCRIPTORS 8
551#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 579#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
@@ -767,6 +795,9 @@ struct e1000_data_desc {
767#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 795#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
768#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 796#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
769 797
798#define E1000_NUM_UNICAST_ICH8LAN 7
799#define E1000_MC_TBL_SIZE_ICH8LAN 32
800
770 801
771/* Receive Address Register */ 802/* Receive Address Register */
772struct e1000_rar { 803struct e1000_rar {
@@ -776,6 +807,7 @@ struct e1000_rar {
776 807
777/* Number of entries in the Multicast Table Array (MTA). */ 808/* Number of entries in the Multicast Table Array (MTA). */
778#define E1000_NUM_MTA_REGISTERS 128 809#define E1000_NUM_MTA_REGISTERS 128
810#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
779 811
780/* IPv4 Address Table Entry */ 812/* IPv4 Address Table Entry */
781struct e1000_ipv4_at_entry { 813struct e1000_ipv4_at_entry {
@@ -786,6 +818,7 @@ struct e1000_ipv4_at_entry {
786/* Four wakeup IP addresses are supported */ 818/* Four wakeup IP addresses are supported */
787#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 819#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
788#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 820#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
821#define E1000_IP4AT_SIZE_ICH8LAN 3
789#define E1000_IP6AT_SIZE 1 822#define E1000_IP6AT_SIZE 1
790 823
791/* IPv6 Address Table Entry */ 824/* IPv6 Address Table Entry */
@@ -844,6 +877,7 @@ struct e1000_ffvt_entry {
844#define E1000_FLA 0x0001C /* Flash Access - RW */ 877#define E1000_FLA 0x0001C /* Flash Access - RW */
845#define E1000_MDIC 0x00020 /* MDI Control - RW */ 878#define E1000_MDIC 0x00020 /* MDI Control - RW */
846#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 879#define E1000_SCTL 0x00024 /* SerDes Control - RW */
880#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
847#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 881#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
848#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 882#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
849#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 883#define E1000_FCT 0x00030 /* Flow Control Type - RW */
@@ -872,6 +906,8 @@ struct e1000_ffvt_entry {
872#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 906#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
873#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 907#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
874#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 908#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
909#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
910#define FEXTNVM_SW_CONFIG 0x0001
875#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 911#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
876#define E1000_PBS 0x01008 /* Packet Buffer Size */ 912#define E1000_PBS 0x01008 /* Packet Buffer Size */
877#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 913#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
@@ -899,11 +935,13 @@ struct e1000_ffvt_entry {
899#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 935#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
900#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 936#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
901#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 937#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
902#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 938#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
939#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
903#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 940#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
904#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 941#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
905#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 942#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
906#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 943#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
944#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
907#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 945#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
908#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 946#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
909#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 947#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
@@ -1050,6 +1088,7 @@ struct e1000_ffvt_entry {
1050#define E1000_82542_FLA E1000_FLA 1088#define E1000_82542_FLA E1000_FLA
1051#define E1000_82542_MDIC E1000_MDIC 1089#define E1000_82542_MDIC E1000_MDIC
1052#define E1000_82542_SCTL E1000_SCTL 1090#define E1000_82542_SCTL E1000_SCTL
1091#define E1000_82542_FEXTNVM E1000_FEXTNVM
1053#define E1000_82542_FCAL E1000_FCAL 1092#define E1000_82542_FCAL E1000_FCAL
1054#define E1000_82542_FCAH E1000_FCAH 1093#define E1000_82542_FCAH E1000_FCAH
1055#define E1000_82542_FCT E1000_FCT 1094#define E1000_82542_FCT E1000_FCT
@@ -1073,6 +1112,19 @@ struct e1000_ffvt_entry {
1073#define E1000_82542_RDLEN0 E1000_82542_RDLEN 1112#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1074#define E1000_82542_RDH0 E1000_82542_RDH 1113#define E1000_82542_RDH0 E1000_82542_RDH
1075#define E1000_82542_RDT0 E1000_82542_RDT 1114#define E1000_82542_RDT0 E1000_82542_RDT
1115#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1116 * RX Control - RW */
1117#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1118#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1119#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1120#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1121#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1122#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1123#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1124#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1125#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1126#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1127#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1076#define E1000_82542_RDTR1 0x00130 1128#define E1000_82542_RDTR1 0x00130
1077#define E1000_82542_RDBAL1 0x00138 1129#define E1000_82542_RDBAL1 0x00138
1078#define E1000_82542_RDBAH1 0x0013C 1130#define E1000_82542_RDBAH1 0x0013C
@@ -1110,11 +1162,14 @@ struct e1000_ffvt_entry {
1110#define E1000_82542_FLOP E1000_FLOP 1162#define E1000_82542_FLOP E1000_FLOP
1111#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL 1163#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1112#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE 1164#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1165#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1113#define E1000_82542_ERT E1000_ERT 1166#define E1000_82542_ERT E1000_ERT
1114#define E1000_82542_RXDCTL E1000_RXDCTL 1167#define E1000_82542_RXDCTL E1000_RXDCTL
1168#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1115#define E1000_82542_RADV E1000_RADV 1169#define E1000_82542_RADV E1000_RADV
1116#define E1000_82542_RSRPD E1000_RSRPD 1170#define E1000_82542_RSRPD E1000_RSRPD
1117#define E1000_82542_TXDMAC E1000_TXDMAC 1171#define E1000_82542_TXDMAC E1000_TXDMAC
1172#define E1000_82542_KABGTXD E1000_KABGTXD
1118#define E1000_82542_TDFHS E1000_TDFHS 1173#define E1000_82542_TDFHS E1000_TDFHS
1119#define E1000_82542_TDFTS E1000_TDFTS 1174#define E1000_82542_TDFTS E1000_TDFTS
1120#define E1000_82542_TDFPC E1000_TDFPC 1175#define E1000_82542_TDFPC E1000_TDFPC
@@ -1310,13 +1365,16 @@ struct e1000_hw_stats {
1310 1365
1311/* Structure containing variables used by the shared code (e1000_hw.c) */ 1366/* Structure containing variables used by the shared code (e1000_hw.c) */
1312struct e1000_hw { 1367struct e1000_hw {
1313 uint8_t __iomem *hw_addr; 1368 uint8_t *hw_addr;
1314 uint8_t *flash_address; 1369 uint8_t *flash_address;
1315 e1000_mac_type mac_type; 1370 e1000_mac_type mac_type;
1316 e1000_phy_type phy_type; 1371 e1000_phy_type phy_type;
1317 uint32_t phy_init_script; 1372 uint32_t phy_init_script;
1318 e1000_media_type media_type; 1373 e1000_media_type media_type;
1319 void *back; 1374 void *back;
1375 struct e1000_shadow_ram *eeprom_shadow_ram;
1376 uint32_t flash_bank_size;
1377 uint32_t flash_base_addr;
1320 e1000_fc_type fc; 1378 e1000_fc_type fc;
1321 e1000_bus_speed bus_speed; 1379 e1000_bus_speed bus_speed;
1322 e1000_bus_width bus_width; 1380 e1000_bus_width bus_width;
@@ -1328,6 +1386,7 @@ struct e1000_hw {
1328 uint32_t asf_firmware_present; 1386 uint32_t asf_firmware_present;
1329 uint32_t eeprom_semaphore_present; 1387 uint32_t eeprom_semaphore_present;
1330 uint32_t swfw_sync_present; 1388 uint32_t swfw_sync_present;
1389 uint32_t swfwhw_semaphore_present;
1331 unsigned long io_base; 1390 unsigned long io_base;
1332 uint32_t phy_id; 1391 uint32_t phy_id;
1333 uint32_t phy_revision; 1392 uint32_t phy_revision;
@@ -1387,6 +1446,7 @@ struct e1000_hw {
1387 boolean_t in_ifs_mode; 1446 boolean_t in_ifs_mode;
1388 boolean_t mng_reg_access_disabled; 1447 boolean_t mng_reg_access_disabled;
1389 boolean_t leave_av_bit_off; 1448 boolean_t leave_av_bit_off;
1449 boolean_t kmrn_lock_loss_workaround_disabled;
1390}; 1450};
1391 1451
1392 1452
@@ -1435,6 +1495,7 @@ struct e1000_hw {
1435#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1495#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1436#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1496#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1437#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1497#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1498#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1438 1499
1439/* Device Status */ 1500/* Device Status */
1440#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1501#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
@@ -1449,6 +1510,8 @@ struct e1000_hw {
1449#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1510#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1450#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1511#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1451#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1512#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1513#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1514 by EEPROM/Flash */
1452#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1515#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1453#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1516#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1454#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1517#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
@@ -1506,6 +1569,10 @@ struct e1000_hw {
1506#define E1000_STM_OPCODE 0xDB00 1569#define E1000_STM_OPCODE 0xDB00
1507#define E1000_HICR_FW_RESET 0xC0 1570#define E1000_HICR_FW_RESET 0xC0
1508 1571
1572#define E1000_SHADOW_RAM_WORDS 2048
1573#define E1000_ICH8_NVM_SIG_WORD 0x13
1574#define E1000_ICH8_NVM_SIG_MASK 0xC0
1575
1509/* EEPROM Read */ 1576/* EEPROM Read */
1510#define E1000_EERD_START 0x00000001 /* Start Read */ 1577#define E1000_EERD_START 0x00000001 /* Start Read */
1511#define E1000_EERD_DONE 0x00000010 /* Read Done */ 1578#define E1000_EERD_DONE 0x00000010 /* Read Done */
@@ -1551,7 +1618,6 @@ struct e1000_hw {
1551#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1618#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1552#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1619#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1553#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1620#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1554#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1555#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1621#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1556#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1622#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1557#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1623#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
@@ -1591,12 +1657,31 @@ struct e1000_hw {
1591#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 1657#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1592 1658
1593/* In-Band Control */ 1659/* In-Band Control */
1660#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1594#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 1661#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1595 1662
1596/* Half-Duplex Control */ 1663/* Half-Duplex Control */
1597#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 1664#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1598#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 1665#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1599 1666
1667#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1668
1669#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1670#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1671
1672#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1673#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1674#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1675
1676#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1677
1678#define E1000_PHY_CTRL_SPD_EN 0x00000001
1679#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1680#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1681#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1682#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1683#define E1000_PHY_CTRL_B2B_EN 0x00000080
1684
1600/* LED Control */ 1685/* LED Control */
1601#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1686#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1602#define E1000_LEDCTL_LED0_MODE_SHIFT 0 1687#define E1000_LEDCTL_LED0_MODE_SHIFT 0
@@ -1666,6 +1751,9 @@ struct e1000_hw {
1666#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1751#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1667#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1752#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1668#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1753#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1754#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1755#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1756#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
1669 1757
1670/* Interrupt Cause Set */ 1758/* Interrupt Cause Set */
1671#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1759#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1692,6 +1780,9 @@ struct e1000_hw {
1692#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1780#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1693#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1781#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1694#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1782#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1783#define E1000_ICS_DSW E1000_ICR_DSW
1784#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1785#define E1000_ICS_EPRST E1000_ICR_EPRST
1695 1786
1696/* Interrupt Mask Set */ 1787/* Interrupt Mask Set */
1697#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1788#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1718,6 +1809,9 @@ struct e1000_hw {
1718#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1809#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1719#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1810#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1720#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1811#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1812#define E1000_IMS_DSW E1000_ICR_DSW
1813#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1814#define E1000_IMS_EPRST E1000_ICR_EPRST
1721 1815
1722/* Interrupt Mask Clear */ 1816/* Interrupt Mask Clear */
1723#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1817#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1744,6 +1838,9 @@ struct e1000_hw {
1744#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1838#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1745#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1839#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1746#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1840#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1841#define E1000_IMC_DSW E1000_ICR_DSW
1842#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1843#define E1000_IMC_EPRST E1000_ICR_EPRST
1747 1844
1748/* Receive Control */ 1845/* Receive Control */
1749#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1846#define E1000_RCTL_RST 0x00000001 /* Software reset */
@@ -1918,9 +2015,10 @@ struct e1000_hw {
1918#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 2015#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1919#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2016#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1920#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 2017#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1921#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000 2018#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
1922#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2019#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1923#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 2020#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2021#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1924 2022
1925/* Definitions for power management and wakeup registers */ 2023/* Definitions for power management and wakeup registers */
1926/* Wake Up Control */ 2024/* Wake Up Control */
@@ -2010,6 +2108,15 @@ struct e1000_hw {
2010#define E1000_FWSM_MODE_SHIFT 1 2108#define E1000_FWSM_MODE_SHIFT 1
2011#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2109#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2012 2110
2111#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2112#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2113#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2114#define E1000_FWSM_SKUEL_SHIFT 29
2115#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2116#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2117#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2118#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2119
2013/* FFLT Debug Register */ 2120/* FFLT Debug Register */
2014#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2121#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2015 2122
@@ -2082,6 +2189,8 @@ struct e1000_host_command_info {
2082 E1000_GCR_TXDSCW_NO_SNOOP | \ 2189 E1000_GCR_TXDSCW_NO_SNOOP | \
2083 E1000_GCR_TXDSCR_NO_SNOOP) 2190 E1000_GCR_TXDSCR_NO_SNOOP)
2084 2191
2192#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2193
2085#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2194#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2086/* Function Active and Power State to MNG */ 2195/* Function Active and Power State to MNG */
2087#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 2196#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
@@ -2140,8 +2249,10 @@ struct e1000_host_command_info {
2140#define EEPROM_PHY_CLASS_WORD 0x0007 2249#define EEPROM_PHY_CLASS_WORD 0x0007
2141#define EEPROM_INIT_CONTROL1_REG 0x000A 2250#define EEPROM_INIT_CONTROL1_REG 0x000A
2142#define EEPROM_INIT_CONTROL2_REG 0x000F 2251#define EEPROM_INIT_CONTROL2_REG 0x000F
2252#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2143#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 2253#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2144#define EEPROM_INIT_3GIO_3 0x001A 2254#define EEPROM_INIT_3GIO_3 0x001A
2255#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2145#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 2256#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2146#define EEPROM_CFG 0x0012 2257#define EEPROM_CFG 0x0012
2147#define EEPROM_FLASH_VERSION 0x0032 2258#define EEPROM_FLASH_VERSION 0x0032
@@ -2153,10 +2264,16 @@ struct e1000_host_command_info {
2153/* Word definitions for ID LED Settings */ 2264/* Word definitions for ID LED Settings */
2154#define ID_LED_RESERVED_0000 0x0000 2265#define ID_LED_RESERVED_0000 0x0000
2155#define ID_LED_RESERVED_FFFF 0xFFFF 2266#define ID_LED_RESERVED_FFFF 0xFFFF
2267#define ID_LED_RESERVED_82573 0xF746
2268#define ID_LED_DEFAULT_82573 0x1811
2156#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2269#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2157 (ID_LED_OFF1_OFF2 << 8) | \ 2270 (ID_LED_OFF1_OFF2 << 8) | \
2158 (ID_LED_DEF1_DEF2 << 4) | \ 2271 (ID_LED_DEF1_DEF2 << 4) | \
2159 (ID_LED_DEF1_DEF2)) 2272 (ID_LED_DEF1_DEF2))
2273#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2274 (ID_LED_DEF1_OFF2 << 8) | \
2275 (ID_LED_DEF1_ON2 << 4) | \
2276 (ID_LED_DEF1_DEF2))
2160#define ID_LED_DEF1_DEF2 0x1 2277#define ID_LED_DEF1_DEF2 0x1
2161#define ID_LED_DEF1_ON2 0x2 2278#define ID_LED_DEF1_ON2 0x2
2162#define ID_LED_DEF1_OFF2 0x3 2279#define ID_LED_DEF1_OFF2 0x3
@@ -2191,6 +2308,11 @@ struct e1000_host_command_info {
2191#define EEPROM_WORD0F_ASM_DIR 0x2000 2308#define EEPROM_WORD0F_ASM_DIR 0x2000
2192#define EEPROM_WORD0F_ANE 0x0800 2309#define EEPROM_WORD0F_ANE 0x0800
2193#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 2310#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2311#define EEPROM_WORD0F_LPLU 0x0001
2312
2313/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2314#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2315#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2194 2316
2195/* Mask bits for fields in Word 0x1a of the EEPROM */ 2317/* Mask bits for fields in Word 0x1a of the EEPROM */
2196#define EEPROM_WORD1A_ASPM_MASK 0x000C 2318#define EEPROM_WORD1A_ASPM_MASK 0x000C
@@ -2265,23 +2387,29 @@ struct e1000_host_command_info {
2265#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 2387#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2266#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 2388#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2267#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 2389#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2268#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000 2390#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2269 2391
2270#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF 2392#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2271#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 2393#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2272#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 2394#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2395#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2396#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2273 2397
2274/* PBA constants */ 2398/* PBA constants */
2399#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2275#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2400#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2276#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2401#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2277#define E1000_PBA_22K 0x0016 2402#define E1000_PBA_22K 0x0016
2278#define E1000_PBA_24K 0x0018 2403#define E1000_PBA_24K 0x0018
2279#define E1000_PBA_30K 0x001E 2404#define E1000_PBA_30K 0x001E
2280#define E1000_PBA_32K 0x0020 2405#define E1000_PBA_32K 0x0020
2406#define E1000_PBA_34K 0x0022
2281#define E1000_PBA_38K 0x0026 2407#define E1000_PBA_38K 0x0026
2282#define E1000_PBA_40K 0x0028 2408#define E1000_PBA_40K 0x0028
2283#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2409#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2284 2410
2411#define E1000_PBS_16K E1000_PBA_16K
2412
2285/* Flow Control Constants */ 2413/* Flow Control Constants */
2286#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 2414#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2287#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 2415#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
@@ -2336,7 +2464,7 @@ struct e1000_host_command_info {
2336/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2464/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2337#define AUTO_READ_DONE_TIMEOUT 10 2465#define AUTO_READ_DONE_TIMEOUT 10
2338/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2466/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2339#define PHY_CFG_TIMEOUT 40 2467#define PHY_CFG_TIMEOUT 100
2340 2468
2341#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2469#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2342 2470
@@ -2764,6 +2892,17 @@ struct e1000_host_command_info {
2764#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2892#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2765#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2893#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2766 2894
2895/* M88EC018 Rev 2 specific DownShift settings */
2896#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2897#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2898#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2899#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2900#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2901#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2902#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2903#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2904#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2905
2767/* IGP01E1000 Specific Port Config Register - R/W */ 2906/* IGP01E1000 Specific Port Config Register - R/W */
2768#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 2907#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2769#define IGP01E1000_PSCFR_PRE_EN 0x0020 2908#define IGP01E1000_PSCFR_PRE_EN 0x0020
@@ -2990,6 +3129,221 @@ struct e1000_host_command_info {
2990#define L1LXT971A_PHY_ID 0x001378E0 3129#define L1LXT971A_PHY_ID 0x001378E0
2991#define GG82563_E_PHY_ID 0x01410CA0 3130#define GG82563_E_PHY_ID 0x01410CA0
2992 3131
3132
3133/* Bits...
3134 * 15-5: page
3135 * 4-0: register offset
3136 */
3137#define PHY_PAGE_SHIFT 5
3138#define PHY_REG(page, reg) \
3139 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3140
3141#define IGP3_PHY_PORT_CTRL \
3142 PHY_REG(769, 17) /* Port General Configuration */
3143#define IGP3_PHY_RATE_ADAPT_CTRL \
3144 PHY_REG(769, 25) /* Rate Adapter Control Register */
3145
3146#define IGP3_KMRN_FIFO_CTRL_STATS \
3147 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3148#define IGP3_KMRN_POWER_MNG_CTRL \
3149 PHY_REG(770, 17) /* KMRN Power Management Control Register */
3150#define IGP3_KMRN_INBAND_CTRL \
3151 PHY_REG(770, 18) /* KMRN Inband Control Register */
3152#define IGP3_KMRN_DIAG \
3153 PHY_REG(770, 19) /* KMRN Diagnostic register */
3154#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3155#define IGP3_KMRN_ACK_TIMEOUT \
3156 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3157
3158#define IGP3_VR_CTRL \
3159 PHY_REG(776, 18) /* Voltage regulator control register */
3160#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3161
3162#define IGP3_CAPABILITY \
3163 PHY_REG(776, 19) /* IGP3 Capability Register */
3164
3165/* Capabilities for SKU Control */
3166#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3167#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3168#define IGP3_CAP_ASF 0x0004 /* Support ASF */
3169#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3170#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3171#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3172#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3173#define IGP3_CAP_RSS 0x0080 /* Support RSS */
3174#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3175#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3176
3177#define IGP3_PPC_JORDAN_EN 0x0001
3178#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
3179
3180#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
3181#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
3182#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3183#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3184
3185#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3186#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3187
3188#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3189#define IGP3_KMRN_EC_DIS_INBAND 0x0080
3190
3191#define IGP03E1000_E_PHY_ID 0x02A80390
3192#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3193#define IFE_PLUS_E_PHY_ID 0x02A80320
3194#define IFE_C_E_PHY_ID 0x02A80310
3195
3196#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3197#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3198#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3199#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
3200#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3201#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3202#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3203#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3204#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3205#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3206#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3207#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3208#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3209
3210#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
3211#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3212#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3213#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3214#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3215#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3216#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3217#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3218
3219#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
3220#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3221#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3222#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3223#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3224#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3225
3226#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3227#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3228#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3229#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */
3230#define IFE_PMC_MDIX_MODE_SHIFT 6
3231#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3232
3233#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3234#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3235#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3236#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3237#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3238#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3239#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3240#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3241#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3242#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3243#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3244
3245#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
3246#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
3247#define ICH8_FLASH_SEG_SIZE_256 256
3248#define ICH8_FLASH_SEG_SIZE_4K 4096
3249#define ICH8_FLASH_SEG_SIZE_64K 65536
3250
3251#define ICH8_CYCLE_READ 0x0
3252#define ICH8_CYCLE_RESERVED 0x1
3253#define ICH8_CYCLE_WRITE 0x2
3254#define ICH8_CYCLE_ERASE 0x3
3255
3256#define ICH8_FLASH_GFPREG 0x0000
3257#define ICH8_FLASH_HSFSTS 0x0004
3258#define ICH8_FLASH_HSFCTL 0x0006
3259#define ICH8_FLASH_FADDR 0x0008
3260#define ICH8_FLASH_FDATA0 0x0010
3261#define ICH8_FLASH_FRACC 0x0050
3262#define ICH8_FLASH_FREG0 0x0054
3263#define ICH8_FLASH_FREG1 0x0058
3264#define ICH8_FLASH_FREG2 0x005C
3265#define ICH8_FLASH_FREG3 0x0060
3266#define ICH8_FLASH_FPR0 0x0074
3267#define ICH8_FLASH_FPR1 0x0078
3268#define ICH8_FLASH_SSFSTS 0x0090
3269#define ICH8_FLASH_SSFCTL 0x0092
3270#define ICH8_FLASH_PREOP 0x0094
3271#define ICH8_FLASH_OPTYPE 0x0096
3272#define ICH8_FLASH_OPMENU 0x0098
3273
3274#define ICH8_FLASH_REG_MAPSIZE 0x00A0
3275#define ICH8_FLASH_SECTOR_SIZE 4096
3276#define ICH8_GFPREG_BASE_MASK 0x1FFF
3277#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3278
3279/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3280/* Offset 04h HSFSTS */
3281union ich8_hws_flash_status {
3282 struct ich8_hsfsts {
3283#ifdef E1000_BIG_ENDIAN
3284 uint16_t reserved2 :6;
3285 uint16_t fldesvalid :1;
3286 uint16_t flockdn :1;
3287 uint16_t flcdone :1;
3288 uint16_t flcerr :1;
3289 uint16_t dael :1;
3290 uint16_t berasesz :2;
3291 uint16_t flcinprog :1;
3292 uint16_t reserved1 :2;
3293#else
3294 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */
3295 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */
3296 uint16_t dael :1; /* bit 2 Direct Access error Log */
3297 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3298 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3299 uint16_t reserved1 :2; /* bit 13:6 Reserved */
3300 uint16_t reserved2 :6; /* bit 13:6 Reserved */
3301 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3302 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3303#endif
3304 } hsf_status;
3305 uint16_t regval;
3306};
3307
3308/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3309/* Offset 06h FLCTL */
3310union ich8_hws_flash_ctrl {
3311 struct ich8_hsflctl {
3312#ifdef E1000_BIG_ENDIAN
3313 uint16_t fldbcount :2;
3314 uint16_t flockdn :6;
3315 uint16_t flcgo :1;
3316 uint16_t flcycle :2;
3317 uint16_t reserved :5;
3318#else
3319 uint16_t flcgo :1; /* 0 Flash Cycle Go */
3320 uint16_t flcycle :2; /* 2:1 Flash Cycle */
3321 uint16_t reserved :5; /* 7:3 Reserved */
3322 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */
3323 uint16_t flockdn :6; /* 15:10 Reserved */
3324#endif
3325 } hsf_ctrl;
3326 uint16_t regval;
3327};
3328
3329/* ICH8 Flash Region Access Permissions */
3330union ich8_hws_flash_regacc {
3331 struct ich8_flracc {
3332#ifdef E1000_BIG_ENDIAN
3333 uint32_t gmwag :8;
3334 uint32_t gmrag :8;
3335 uint32_t grwa :8;
3336 uint32_t grra :8;
3337#else
3338 uint32_t grra :8; /* 0:7 GbE region Read Access */
3339 uint32_t grwa :8; /* 8:15 GbE region Write Access */
3340 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */
3341 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */
3342#endif
3343 } hsf_flregacc;
3344 uint16_t regval;
3345};
3346
2993/* Miscellaneous PHY bit definitions. */ 3347/* Miscellaneous PHY bit definitions. */
2994#define PHY_PREAMBLE 0xFFFFFFFF 3348#define PHY_PREAMBLE 0xFFFFFFFF
2995#define PHY_SOF 0x01 3349#define PHY_SOF 0x01