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path: root/drivers/net/e1000/e1000_hw.c
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c356
1 files changed, 177 insertions, 179 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 8d7d87f12827..c7e242b69a18 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -30,7 +30,7 @@
30 * Shared functions for accessing and configuring the MAC 30 * Shared functions for accessing and configuring the MAC
31 */ 31 */
32 32
33#include "e1000_hw.h" 33#include "e1000.h"
34 34
35static s32 e1000_check_downshift(struct e1000_hw *hw); 35static s32 e1000_check_downshift(struct e1000_hw *hw);
36static s32 e1000_check_polarity(struct e1000_hw *hw, 36static s32 e1000_check_polarity(struct e1000_hw *hw,
@@ -114,7 +114,7 @@ static DEFINE_SPINLOCK(e1000_eeprom_lock);
114 */ 114 */
115static s32 e1000_set_phy_type(struct e1000_hw *hw) 115static s32 e1000_set_phy_type(struct e1000_hw *hw)
116{ 116{
117 DEBUGFUNC("e1000_set_phy_type"); 117 e_dbg("e1000_set_phy_type");
118 118
119 if (hw->mac_type == e1000_undefined) 119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE; 120 return -E1000_ERR_PHY_TYPE;
@@ -152,7 +152,7 @@ static void e1000_phy_init_script(struct e1000_hw *hw)
152 u32 ret_val; 152 u32 ret_val;
153 u16 phy_saved_data; 153 u16 phy_saved_data;
154 154
155 DEBUGFUNC("e1000_phy_init_script"); 155 e_dbg("e1000_phy_init_script");
156 156
157 if (hw->phy_init_script) { 157 if (hw->phy_init_script) {
158 msleep(20); 158 msleep(20);
@@ -245,7 +245,7 @@ static void e1000_phy_init_script(struct e1000_hw *hw)
245 */ 245 */
246s32 e1000_set_mac_type(struct e1000_hw *hw) 246s32 e1000_set_mac_type(struct e1000_hw *hw)
247{ 247{
248 DEBUGFUNC("e1000_set_mac_type"); 248 e_dbg("e1000_set_mac_type");
249 249
250 switch (hw->device_id) { 250 switch (hw->device_id) {
251 case E1000_DEV_ID_82542: 251 case E1000_DEV_ID_82542:
@@ -354,7 +354,7 @@ void e1000_set_media_type(struct e1000_hw *hw)
354{ 354{
355 u32 status; 355 u32 status;
356 356
357 DEBUGFUNC("e1000_set_media_type"); 357 e_dbg("e1000_set_media_type");
358 358
359 if (hw->mac_type != e1000_82543) { 359 if (hw->mac_type != e1000_82543) {
360 /* tbi_compatibility is only valid on 82543 */ 360 /* tbi_compatibility is only valid on 82543 */
@@ -401,16 +401,16 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
401 u32 led_ctrl; 401 u32 led_ctrl;
402 s32 ret_val; 402 s32 ret_val;
403 403
404 DEBUGFUNC("e1000_reset_hw"); 404 e_dbg("e1000_reset_hw");
405 405
406 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 406 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
407 if (hw->mac_type == e1000_82542_rev2_0) { 407 if (hw->mac_type == e1000_82542_rev2_0) {
408 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 408 e_dbg("Disabling MWI on 82542 rev 2.0\n");
409 e1000_pci_clear_mwi(hw); 409 e1000_pci_clear_mwi(hw);
410 } 410 }
411 411
412 /* Clear interrupt mask to stop board from generating interrupts */ 412 /* Clear interrupt mask to stop board from generating interrupts */
413 DEBUGOUT("Masking off all interrupts\n"); 413 e_dbg("Masking off all interrupts\n");
414 ew32(IMC, 0xffffffff); 414 ew32(IMC, 0xffffffff);
415 415
416 /* Disable the Transmit and Receive units. Then delay to allow 416 /* Disable the Transmit and Receive units. Then delay to allow
@@ -442,7 +442,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
442 * the current PCI configuration. The global reset bit is self- 442 * the current PCI configuration. The global reset bit is self-
443 * clearing, and should clear within a microsecond. 443 * clearing, and should clear within a microsecond.
444 */ 444 */
445 DEBUGOUT("Issuing a global reset to MAC\n"); 445 e_dbg("Issuing a global reset to MAC\n");
446 446
447 switch (hw->mac_type) { 447 switch (hw->mac_type) {
448 case e1000_82544: 448 case e1000_82544:
@@ -516,7 +516,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
516 } 516 }
517 517
518 /* Clear interrupt mask to stop board from generating interrupts */ 518 /* Clear interrupt mask to stop board from generating interrupts */
519 DEBUGOUT("Masking off all interrupts\n"); 519 e_dbg("Masking off all interrupts\n");
520 ew32(IMC, 0xffffffff); 520 ew32(IMC, 0xffffffff);
521 521
522 /* Clear any pending interrupt events. */ 522 /* Clear any pending interrupt events. */
@@ -549,12 +549,12 @@ s32 e1000_init_hw(struct e1000_hw *hw)
549 u32 mta_size; 549 u32 mta_size;
550 u32 ctrl_ext; 550 u32 ctrl_ext;
551 551
552 DEBUGFUNC("e1000_init_hw"); 552 e_dbg("e1000_init_hw");
553 553
554 /* Initialize Identification LED */ 554 /* Initialize Identification LED */
555 ret_val = e1000_id_led_init(hw); 555 ret_val = e1000_id_led_init(hw);
556 if (ret_val) { 556 if (ret_val) {
557 DEBUGOUT("Error Initializing Identification LED\n"); 557 e_dbg("Error Initializing Identification LED\n");
558 return ret_val; 558 return ret_val;
559 } 559 }
560 560
@@ -562,14 +562,14 @@ s32 e1000_init_hw(struct e1000_hw *hw)
562 e1000_set_media_type(hw); 562 e1000_set_media_type(hw);
563 563
564 /* Disabling VLAN filtering. */ 564 /* Disabling VLAN filtering. */
565 DEBUGOUT("Initializing the IEEE VLAN\n"); 565 e_dbg("Initializing the IEEE VLAN\n");
566 if (hw->mac_type < e1000_82545_rev_3) 566 if (hw->mac_type < e1000_82545_rev_3)
567 ew32(VET, 0); 567 ew32(VET, 0);
568 e1000_clear_vfta(hw); 568 e1000_clear_vfta(hw);
569 569
570 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 570 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
571 if (hw->mac_type == e1000_82542_rev2_0) { 571 if (hw->mac_type == e1000_82542_rev2_0) {
572 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 572 e_dbg("Disabling MWI on 82542 rev 2.0\n");
573 e1000_pci_clear_mwi(hw); 573 e1000_pci_clear_mwi(hw);
574 ew32(RCTL, E1000_RCTL_RST); 574 ew32(RCTL, E1000_RCTL_RST);
575 E1000_WRITE_FLUSH(); 575 E1000_WRITE_FLUSH();
@@ -591,7 +591,7 @@ s32 e1000_init_hw(struct e1000_hw *hw)
591 } 591 }
592 592
593 /* Zero out the Multicast HASH table */ 593 /* Zero out the Multicast HASH table */
594 DEBUGOUT("Zeroing the MTA\n"); 594 e_dbg("Zeroing the MTA\n");
595 mta_size = E1000_MC_TBL_SIZE; 595 mta_size = E1000_MC_TBL_SIZE;
596 for (i = 0; i < mta_size; i++) { 596 for (i = 0; i < mta_size; i++) {
597 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 597 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
@@ -662,7 +662,7 @@ static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
662 u16 eeprom_data; 662 u16 eeprom_data;
663 s32 ret_val; 663 s32 ret_val;
664 664
665 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 665 e_dbg("e1000_adjust_serdes_amplitude");
666 666
667 if (hw->media_type != e1000_media_type_internal_serdes) 667 if (hw->media_type != e1000_media_type_internal_serdes)
668 return E1000_SUCCESS; 668 return E1000_SUCCESS;
@@ -709,7 +709,7 @@ s32 e1000_setup_link(struct e1000_hw *hw)
709 s32 ret_val; 709 s32 ret_val;
710 u16 eeprom_data; 710 u16 eeprom_data;
711 711
712 DEBUGFUNC("e1000_setup_link"); 712 e_dbg("e1000_setup_link");
713 713
714 /* Read and store word 0x0F of the EEPROM. This word contains bits 714 /* Read and store word 0x0F of the EEPROM. This word contains bits
715 * that determine the hardware's default PAUSE (flow control) mode, 715 * that determine the hardware's default PAUSE (flow control) mode,
@@ -723,7 +723,7 @@ s32 e1000_setup_link(struct e1000_hw *hw)
723 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 723 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
724 1, &eeprom_data); 724 1, &eeprom_data);
725 if (ret_val) { 725 if (ret_val) {
726 DEBUGOUT("EEPROM Read Error\n"); 726 e_dbg("EEPROM Read Error\n");
727 return -E1000_ERR_EEPROM; 727 return -E1000_ERR_EEPROM;
728 } 728 }
729 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 729 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
@@ -747,7 +747,7 @@ s32 e1000_setup_link(struct e1000_hw *hw)
747 747
748 hw->original_fc = hw->fc; 748 hw->original_fc = hw->fc;
749 749
750 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 750 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
751 751
752 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 752 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
753 * polarity value for the SW controlled pins, and setup the 753 * polarity value for the SW controlled pins, and setup the
@@ -760,7 +760,7 @@ s32 e1000_setup_link(struct e1000_hw *hw)
760 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 760 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
761 1, &eeprom_data); 761 1, &eeprom_data);
762 if (ret_val) { 762 if (ret_val) {
763 DEBUGOUT("EEPROM Read Error\n"); 763 e_dbg("EEPROM Read Error\n");
764 return -E1000_ERR_EEPROM; 764 return -E1000_ERR_EEPROM;
765 } 765 }
766 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 766 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
@@ -777,8 +777,7 @@ s32 e1000_setup_link(struct e1000_hw *hw)
777 * control is disabled, because it does not hurt anything to 777 * control is disabled, because it does not hurt anything to
778 * initialize these registers. 778 * initialize these registers.
779 */ 779 */
780 DEBUGOUT 780 e_dbg("Initializing the Flow Control address, type and timer regs\n");
781 ("Initializing the Flow Control address, type and timer regs\n");
782 781
783 ew32(FCT, FLOW_CONTROL_TYPE); 782 ew32(FCT, FLOW_CONTROL_TYPE);
784 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 783 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
@@ -827,7 +826,7 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
827 u32 signal = 0; 826 u32 signal = 0;
828 s32 ret_val; 827 s32 ret_val;
829 828
830 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 829 e_dbg("e1000_setup_fiber_serdes_link");
831 830
832 /* On adapters with a MAC newer than 82544, SWDP 1 will be 831 /* On adapters with a MAC newer than 82544, SWDP 1 will be
833 * set when the optics detect a signal. On older adapters, it will be 832 * set when the optics detect a signal. On older adapters, it will be
@@ -893,7 +892,7 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
893 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 892 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
894 break; 893 break;
895 default: 894 default:
896 DEBUGOUT("Flow control param set incorrectly\n"); 895 e_dbg("Flow control param set incorrectly\n");
897 return -E1000_ERR_CONFIG; 896 return -E1000_ERR_CONFIG;
898 break; 897 break;
899 } 898 }
@@ -904,7 +903,7 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
904 * link-up status bit will be set and the flow control enable bits (RFCE 903 * link-up status bit will be set and the flow control enable bits (RFCE
905 * and TFCE) will be set according to their negotiated value. 904 * and TFCE) will be set according to their negotiated value.
906 */ 905 */
907 DEBUGOUT("Auto-negotiation enabled\n"); 906 e_dbg("Auto-negotiation enabled\n");
908 907
909 ew32(TXCW, txcw); 908 ew32(TXCW, txcw);
910 ew32(CTRL, ctrl); 909 ew32(CTRL, ctrl);
@@ -921,7 +920,7 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
921 */ 920 */
922 if (hw->media_type == e1000_media_type_internal_serdes || 921 if (hw->media_type == e1000_media_type_internal_serdes ||
923 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 922 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
924 DEBUGOUT("Looking for Link\n"); 923 e_dbg("Looking for Link\n");
925 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 924 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
926 msleep(10); 925 msleep(10);
927 status = er32(STATUS); 926 status = er32(STATUS);
@@ -929,7 +928,7 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
929 break; 928 break;
930 } 929 }
931 if (i == (LINK_UP_TIMEOUT / 10)) { 930 if (i == (LINK_UP_TIMEOUT / 10)) {
932 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 931 e_dbg("Never got a valid link from auto-neg!!!\n");
933 hw->autoneg_failed = 1; 932 hw->autoneg_failed = 1;
934 /* AutoNeg failed to achieve a link, so we'll call 933 /* AutoNeg failed to achieve a link, so we'll call
935 * e1000_check_for_link. This routine will force the link up if 934 * e1000_check_for_link. This routine will force the link up if
@@ -938,16 +937,16 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
938 */ 937 */
939 ret_val = e1000_check_for_link(hw); 938 ret_val = e1000_check_for_link(hw);
940 if (ret_val) { 939 if (ret_val) {
941 DEBUGOUT("Error while checking for link\n"); 940 e_dbg("Error while checking for link\n");
942 return ret_val; 941 return ret_val;
943 } 942 }
944 hw->autoneg_failed = 0; 943 hw->autoneg_failed = 0;
945 } else { 944 } else {
946 hw->autoneg_failed = 0; 945 hw->autoneg_failed = 0;
947 DEBUGOUT("Valid Link Found\n"); 946 e_dbg("Valid Link Found\n");
948 } 947 }
949 } else { 948 } else {
950 DEBUGOUT("No Signal Detected\n"); 949 e_dbg("No Signal Detected\n");
951 } 950 }
952 return E1000_SUCCESS; 951 return E1000_SUCCESS;
953} 952}
@@ -964,7 +963,7 @@ static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
964 s32 ret_val; 963 s32 ret_val;
965 u16 phy_data; 964 u16 phy_data;
966 965
967 DEBUGFUNC("e1000_copper_link_preconfig"); 966 e_dbg("e1000_copper_link_preconfig");
968 967
969 ctrl = er32(CTRL); 968 ctrl = er32(CTRL);
970 /* With 82543, we need to force speed and duplex on the MAC equal to what 969 /* With 82543, we need to force speed and duplex on the MAC equal to what
@@ -987,10 +986,10 @@ static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
987 /* Make sure we have a valid PHY */ 986 /* Make sure we have a valid PHY */
988 ret_val = e1000_detect_gig_phy(hw); 987 ret_val = e1000_detect_gig_phy(hw);
989 if (ret_val) { 988 if (ret_val) {
990 DEBUGOUT("Error, did not detect valid phy.\n"); 989 e_dbg("Error, did not detect valid phy.\n");
991 return ret_val; 990 return ret_val;
992 } 991 }
993 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 992 e_dbg("Phy ID = %x\n", hw->phy_id);
994 993
995 /* Set PHY to class A mode (if necessary) */ 994 /* Set PHY to class A mode (if necessary) */
996 ret_val = e1000_set_phy_mode(hw); 995 ret_val = e1000_set_phy_mode(hw);
@@ -1025,14 +1024,14 @@ static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1025 s32 ret_val; 1024 s32 ret_val;
1026 u16 phy_data; 1025 u16 phy_data;
1027 1026
1028 DEBUGFUNC("e1000_copper_link_igp_setup"); 1027 e_dbg("e1000_copper_link_igp_setup");
1029 1028
1030 if (hw->phy_reset_disable) 1029 if (hw->phy_reset_disable)
1031 return E1000_SUCCESS; 1030 return E1000_SUCCESS;
1032 1031
1033 ret_val = e1000_phy_reset(hw); 1032 ret_val = e1000_phy_reset(hw);
1034 if (ret_val) { 1033 if (ret_val) {
1035 DEBUGOUT("Error Resetting the PHY\n"); 1034 e_dbg("Error Resetting the PHY\n");
1036 return ret_val; 1035 return ret_val;
1037 } 1036 }
1038 1037
@@ -1049,7 +1048,7 @@ static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1049 /* disable lplu d3 during driver init */ 1048 /* disable lplu d3 during driver init */
1050 ret_val = e1000_set_d3_lplu_state(hw, false); 1049 ret_val = e1000_set_d3_lplu_state(hw, false);
1051 if (ret_val) { 1050 if (ret_val) {
1052 DEBUGOUT("Error Disabling LPLU D3\n"); 1051 e_dbg("Error Disabling LPLU D3\n");
1053 return ret_val; 1052 return ret_val;
1054 } 1053 }
1055 } 1054 }
@@ -1166,7 +1165,7 @@ static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1166 s32 ret_val; 1165 s32 ret_val;
1167 u16 phy_data; 1166 u16 phy_data;
1168 1167
1169 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1168 e_dbg("e1000_copper_link_mgp_setup");
1170 1169
1171 if (hw->phy_reset_disable) 1170 if (hw->phy_reset_disable)
1172 return E1000_SUCCESS; 1171 return E1000_SUCCESS;
@@ -1255,7 +1254,7 @@ static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1255 /* SW Reset the PHY so all changes take effect */ 1254 /* SW Reset the PHY so all changes take effect */
1256 ret_val = e1000_phy_reset(hw); 1255 ret_val = e1000_phy_reset(hw);
1257 if (ret_val) { 1256 if (ret_val) {
1258 DEBUGOUT("Error Resetting the PHY\n"); 1257 e_dbg("Error Resetting the PHY\n");
1259 return ret_val; 1258 return ret_val;
1260 } 1259 }
1261 1260
@@ -1274,7 +1273,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1274 s32 ret_val; 1273 s32 ret_val;
1275 u16 phy_data; 1274 u16 phy_data;
1276 1275
1277 DEBUGFUNC("e1000_copper_link_autoneg"); 1276 e_dbg("e1000_copper_link_autoneg");
1278 1277
1279 /* Perform some bounds checking on the hw->autoneg_advertised 1278 /* Perform some bounds checking on the hw->autoneg_advertised
1280 * parameter. If this variable is zero, then set it to the default. 1279 * parameter. If this variable is zero, then set it to the default.
@@ -1287,13 +1286,13 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1287 if (hw->autoneg_advertised == 0) 1286 if (hw->autoneg_advertised == 0)
1288 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1287 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1289 1288
1290 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1289 e_dbg("Reconfiguring auto-neg advertisement params\n");
1291 ret_val = e1000_phy_setup_autoneg(hw); 1290 ret_val = e1000_phy_setup_autoneg(hw);
1292 if (ret_val) { 1291 if (ret_val) {
1293 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1292 e_dbg("Error Setting up Auto-Negotiation\n");
1294 return ret_val; 1293 return ret_val;
1295 } 1294 }
1296 DEBUGOUT("Restarting Auto-Neg\n"); 1295 e_dbg("Restarting Auto-Neg\n");
1297 1296
1298 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1297 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1299 * the Auto Neg Restart bit in the PHY control register. 1298 * the Auto Neg Restart bit in the PHY control register.
@@ -1313,7 +1312,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1313 if (hw->wait_autoneg_complete) { 1312 if (hw->wait_autoneg_complete) {
1314 ret_val = e1000_wait_autoneg(hw); 1313 ret_val = e1000_wait_autoneg(hw);
1315 if (ret_val) { 1314 if (ret_val) {
1316 DEBUGOUT 1315 e_dbg
1317 ("Error while waiting for autoneg to complete\n"); 1316 ("Error while waiting for autoneg to complete\n");
1318 return ret_val; 1317 return ret_val;
1319 } 1318 }
@@ -1340,20 +1339,20 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1340static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1339static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1341{ 1340{
1342 s32 ret_val; 1341 s32 ret_val;
1343 DEBUGFUNC("e1000_copper_link_postconfig"); 1342 e_dbg("e1000_copper_link_postconfig");
1344 1343
1345 if (hw->mac_type >= e1000_82544) { 1344 if (hw->mac_type >= e1000_82544) {
1346 e1000_config_collision_dist(hw); 1345 e1000_config_collision_dist(hw);
1347 } else { 1346 } else {
1348 ret_val = e1000_config_mac_to_phy(hw); 1347 ret_val = e1000_config_mac_to_phy(hw);
1349 if (ret_val) { 1348 if (ret_val) {
1350 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1349 e_dbg("Error configuring MAC to PHY settings\n");
1351 return ret_val; 1350 return ret_val;
1352 } 1351 }
1353 } 1352 }
1354 ret_val = e1000_config_fc_after_link_up(hw); 1353 ret_val = e1000_config_fc_after_link_up(hw);
1355 if (ret_val) { 1354 if (ret_val) {
1356 DEBUGOUT("Error Configuring Flow Control\n"); 1355 e_dbg("Error Configuring Flow Control\n");
1357 return ret_val; 1356 return ret_val;
1358 } 1357 }
1359 1358
@@ -1361,7 +1360,7 @@ static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1361 if (hw->phy_type == e1000_phy_igp) { 1360 if (hw->phy_type == e1000_phy_igp) {
1362 ret_val = e1000_config_dsp_after_link_change(hw, true); 1361 ret_val = e1000_config_dsp_after_link_change(hw, true);
1363 if (ret_val) { 1362 if (ret_val) {
1364 DEBUGOUT("Error Configuring DSP after link up\n"); 1363 e_dbg("Error Configuring DSP after link up\n");
1365 return ret_val; 1364 return ret_val;
1366 } 1365 }
1367 } 1366 }
@@ -1381,7 +1380,7 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1381 u16 i; 1380 u16 i;
1382 u16 phy_data; 1381 u16 phy_data;
1383 1382
1384 DEBUGFUNC("e1000_setup_copper_link"); 1383 e_dbg("e1000_setup_copper_link");
1385 1384
1386 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1385 /* Check if it is a valid PHY and set PHY mode if necessary. */
1387 ret_val = e1000_copper_link_preconfig(hw); 1386 ret_val = e1000_copper_link_preconfig(hw);
@@ -1407,10 +1406,10 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1407 } else { 1406 } else {
1408 /* PHY will be set to 10H, 10F, 100H,or 100F 1407 /* PHY will be set to 10H, 10F, 100H,or 100F
1409 * depending on value from forced_speed_duplex. */ 1408 * depending on value from forced_speed_duplex. */
1410 DEBUGOUT("Forcing speed and duplex\n"); 1409 e_dbg("Forcing speed and duplex\n");
1411 ret_val = e1000_phy_force_speed_duplex(hw); 1410 ret_val = e1000_phy_force_speed_duplex(hw);
1412 if (ret_val) { 1411 if (ret_val) {
1413 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1412 e_dbg("Error Forcing Speed and Duplex\n");
1414 return ret_val; 1413 return ret_val;
1415 } 1414 }
1416 } 1415 }
@@ -1432,13 +1431,13 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1432 if (ret_val) 1431 if (ret_val)
1433 return ret_val; 1432 return ret_val;
1434 1433
1435 DEBUGOUT("Valid link established!!!\n"); 1434 e_dbg("Valid link established!!!\n");
1436 return E1000_SUCCESS; 1435 return E1000_SUCCESS;
1437 } 1436 }
1438 udelay(10); 1437 udelay(10);
1439 } 1438 }
1440 1439
1441 DEBUGOUT("Unable to establish link!!!\n"); 1440 e_dbg("Unable to establish link!!!\n");
1442 return E1000_SUCCESS; 1441 return E1000_SUCCESS;
1443} 1442}
1444 1443
@@ -1454,7 +1453,7 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1454 u16 mii_autoneg_adv_reg; 1453 u16 mii_autoneg_adv_reg;
1455 u16 mii_1000t_ctrl_reg; 1454 u16 mii_1000t_ctrl_reg;
1456 1455
1457 DEBUGFUNC("e1000_phy_setup_autoneg"); 1456 e_dbg("e1000_phy_setup_autoneg");
1458 1457
1459 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1458 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1460 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1459 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
@@ -1481,41 +1480,41 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1481 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1480 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1482 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1481 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1483 1482
1484 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 1483 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1485 1484
1486 /* Do we want to advertise 10 Mb Half Duplex? */ 1485 /* Do we want to advertise 10 Mb Half Duplex? */
1487 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1486 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1488 DEBUGOUT("Advertise 10mb Half duplex\n"); 1487 e_dbg("Advertise 10mb Half duplex\n");
1489 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1488 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1490 } 1489 }
1491 1490
1492 /* Do we want to advertise 10 Mb Full Duplex? */ 1491 /* Do we want to advertise 10 Mb Full Duplex? */
1493 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1492 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1494 DEBUGOUT("Advertise 10mb Full duplex\n"); 1493 e_dbg("Advertise 10mb Full duplex\n");
1495 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1494 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1496 } 1495 }
1497 1496
1498 /* Do we want to advertise 100 Mb Half Duplex? */ 1497 /* Do we want to advertise 100 Mb Half Duplex? */
1499 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1498 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1500 DEBUGOUT("Advertise 100mb Half duplex\n"); 1499 e_dbg("Advertise 100mb Half duplex\n");
1501 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1500 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1502 } 1501 }
1503 1502
1504 /* Do we want to advertise 100 Mb Full Duplex? */ 1503 /* Do we want to advertise 100 Mb Full Duplex? */
1505 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1504 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1506 DEBUGOUT("Advertise 100mb Full duplex\n"); 1505 e_dbg("Advertise 100mb Full duplex\n");
1507 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1506 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1508 } 1507 }
1509 1508
1510 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1509 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1511 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1510 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1512 DEBUGOUT 1511 e_dbg
1513 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1512 ("Advertise 1000mb Half duplex requested, request denied!\n");
1514 } 1513 }
1515 1514
1516 /* Do we want to advertise 1000 Mb Full Duplex? */ 1515 /* Do we want to advertise 1000 Mb Full Duplex? */
1517 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1516 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1518 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1517 e_dbg("Advertise 1000mb Full duplex\n");
1519 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1518 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1520 } 1519 }
1521 1520
@@ -1568,7 +1567,7 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1568 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1567 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1569 break; 1568 break;
1570 default: 1569 default:
1571 DEBUGOUT("Flow control param set incorrectly\n"); 1570 e_dbg("Flow control param set incorrectly\n");
1572 return -E1000_ERR_CONFIG; 1571 return -E1000_ERR_CONFIG;
1573 } 1572 }
1574 1573
@@ -1576,7 +1575,7 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1576 if (ret_val) 1575 if (ret_val)
1577 return ret_val; 1576 return ret_val;
1578 1577
1579 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1578 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1580 1579
1581 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1580 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1582 if (ret_val) 1581 if (ret_val)
@@ -1600,12 +1599,12 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1600 u16 phy_data; 1599 u16 phy_data;
1601 u16 i; 1600 u16 i;
1602 1601
1603 DEBUGFUNC("e1000_phy_force_speed_duplex"); 1602 e_dbg("e1000_phy_force_speed_duplex");
1604 1603
1605 /* Turn off Flow control if we are forcing speed and duplex. */ 1604 /* Turn off Flow control if we are forcing speed and duplex. */
1606 hw->fc = E1000_FC_NONE; 1605 hw->fc = E1000_FC_NONE;
1607 1606
1608 DEBUGOUT1("hw->fc = %d\n", hw->fc); 1607 e_dbg("hw->fc = %d\n", hw->fc);
1609 1608
1610 /* Read the Device Control Register. */ 1609 /* Read the Device Control Register. */
1611 ctrl = er32(CTRL); 1610 ctrl = er32(CTRL);
@@ -1634,14 +1633,14 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1634 */ 1633 */
1635 ctrl |= E1000_CTRL_FD; 1634 ctrl |= E1000_CTRL_FD;
1636 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1635 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1637 DEBUGOUT("Full Duplex\n"); 1636 e_dbg("Full Duplex\n");
1638 } else { 1637 } else {
1639 /* We want to force half duplex so we CLEAR the full duplex bits in 1638 /* We want to force half duplex so we CLEAR the full duplex bits in
1640 * the Device and MII Control Registers. 1639 * the Device and MII Control Registers.
1641 */ 1640 */
1642 ctrl &= ~E1000_CTRL_FD; 1641 ctrl &= ~E1000_CTRL_FD;
1643 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1642 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1644 DEBUGOUT("Half Duplex\n"); 1643 e_dbg("Half Duplex\n");
1645 } 1644 }
1646 1645
1647 /* Are we forcing 100Mbps??? */ 1646 /* Are we forcing 100Mbps??? */
@@ -1651,13 +1650,13 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1651 ctrl |= E1000_CTRL_SPD_100; 1650 ctrl |= E1000_CTRL_SPD_100;
1652 mii_ctrl_reg |= MII_CR_SPEED_100; 1651 mii_ctrl_reg |= MII_CR_SPEED_100;
1653 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1652 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1654 DEBUGOUT("Forcing 100mb "); 1653 e_dbg("Forcing 100mb ");
1655 } else { 1654 } else {
1656 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1655 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1657 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1656 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1658 mii_ctrl_reg |= MII_CR_SPEED_10; 1657 mii_ctrl_reg |= MII_CR_SPEED_10;
1659 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1658 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1660 DEBUGOUT("Forcing 10mb "); 1659 e_dbg("Forcing 10mb ");
1661 } 1660 }
1662 1661
1663 e1000_config_collision_dist(hw); 1662 e1000_config_collision_dist(hw);
@@ -1680,7 +1679,7 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1680 if (ret_val) 1679 if (ret_val)
1681 return ret_val; 1680 return ret_val;
1682 1681
1683 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 1682 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1684 1683
1685 /* Need to reset the PHY or these changes will be ignored */ 1684 /* Need to reset the PHY or these changes will be ignored */
1686 mii_ctrl_reg |= MII_CR_RESET; 1685 mii_ctrl_reg |= MII_CR_RESET;
@@ -1720,7 +1719,7 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1720 */ 1719 */
1721 if (hw->wait_autoneg_complete) { 1720 if (hw->wait_autoneg_complete) {
1722 /* We will wait for autoneg to complete. */ 1721 /* We will wait for autoneg to complete. */
1723 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 1722 e_dbg("Waiting for forced speed/duplex link.\n");
1724 mii_status_reg = 0; 1723 mii_status_reg = 0;
1725 1724
1726 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1725 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
@@ -1746,7 +1745,7 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1746 /* We didn't get link. Reset the DSP and wait again for link. */ 1745 /* We didn't get link. Reset the DSP and wait again for link. */
1747 ret_val = e1000_phy_reset_dsp(hw); 1746 ret_val = e1000_phy_reset_dsp(hw);
1748 if (ret_val) { 1747 if (ret_val) {
1749 DEBUGOUT("Error Resetting PHY DSP\n"); 1748 e_dbg("Error Resetting PHY DSP\n");
1750 return ret_val; 1749 return ret_val;
1751 } 1750 }
1752 } 1751 }
@@ -1826,7 +1825,7 @@ void e1000_config_collision_dist(struct e1000_hw *hw)
1826{ 1825{
1827 u32 tctl, coll_dist; 1826 u32 tctl, coll_dist;
1828 1827
1829 DEBUGFUNC("e1000_config_collision_dist"); 1828 e_dbg("e1000_config_collision_dist");
1830 1829
1831 if (hw->mac_type < e1000_82543) 1830 if (hw->mac_type < e1000_82543)
1832 coll_dist = E1000_COLLISION_DISTANCE_82542; 1831 coll_dist = E1000_COLLISION_DISTANCE_82542;
@@ -1857,7 +1856,7 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1857 s32 ret_val; 1856 s32 ret_val;
1858 u16 phy_data; 1857 u16 phy_data;
1859 1858
1860 DEBUGFUNC("e1000_config_mac_to_phy"); 1859 e_dbg("e1000_config_mac_to_phy");
1861 1860
1862 /* 82544 or newer MAC, Auto Speed Detection takes care of 1861 /* 82544 or newer MAC, Auto Speed Detection takes care of
1863 * MAC speed/duplex configuration.*/ 1862 * MAC speed/duplex configuration.*/
@@ -1913,7 +1912,7 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw)
1913{ 1912{
1914 u32 ctrl; 1913 u32 ctrl;
1915 1914
1916 DEBUGFUNC("e1000_force_mac_fc"); 1915 e_dbg("e1000_force_mac_fc");
1917 1916
1918 /* Get the current configuration of the Device Control Register */ 1917 /* Get the current configuration of the Device Control Register */
1919 ctrl = er32(CTRL); 1918 ctrl = er32(CTRL);
@@ -1952,7 +1951,7 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw)
1952 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1951 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1953 break; 1952 break;
1954 default: 1953 default:
1955 DEBUGOUT("Flow control param set incorrectly\n"); 1954 e_dbg("Flow control param set incorrectly\n");
1956 return -E1000_ERR_CONFIG; 1955 return -E1000_ERR_CONFIG;
1957 } 1956 }
1958 1957
@@ -1984,7 +1983,7 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1984 u16 speed; 1983 u16 speed;
1985 u16 duplex; 1984 u16 duplex;
1986 1985
1987 DEBUGFUNC("e1000_config_fc_after_link_up"); 1986 e_dbg("e1000_config_fc_after_link_up");
1988 1987
1989 /* Check for the case where we have fiber media and auto-neg failed 1988 /* Check for the case where we have fiber media and auto-neg failed
1990 * so we had to force link. In this case, we need to force the 1989 * so we had to force link. In this case, we need to force the
@@ -1997,7 +1996,7 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1997 && (!hw->autoneg))) { 1996 && (!hw->autoneg))) {
1998 ret_val = e1000_force_mac_fc(hw); 1997 ret_val = e1000_force_mac_fc(hw);
1999 if (ret_val) { 1998 if (ret_val) {
2000 DEBUGOUT("Error forcing flow control settings\n"); 1999 e_dbg("Error forcing flow control settings\n");
2001 return ret_val; 2000 return ret_val;
2002 } 2001 }
2003 } 2002 }
@@ -2079,10 +2078,10 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2079 */ 2078 */
2080 if (hw->original_fc == E1000_FC_FULL) { 2079 if (hw->original_fc == E1000_FC_FULL) {
2081 hw->fc = E1000_FC_FULL; 2080 hw->fc = E1000_FC_FULL;
2082 DEBUGOUT("Flow Control = FULL.\n"); 2081 e_dbg("Flow Control = FULL.\n");
2083 } else { 2082 } else {
2084 hw->fc = E1000_FC_RX_PAUSE; 2083 hw->fc = E1000_FC_RX_PAUSE;
2085 DEBUGOUT 2084 e_dbg
2086 ("Flow Control = RX PAUSE frames only.\n"); 2085 ("Flow Control = RX PAUSE frames only.\n");
2087 } 2086 }
2088 } 2087 }
@@ -2100,7 +2099,7 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2100 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2099 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2101 { 2100 {
2102 hw->fc = E1000_FC_TX_PAUSE; 2101 hw->fc = E1000_FC_TX_PAUSE;
2103 DEBUGOUT 2102 e_dbg
2104 ("Flow Control = TX PAUSE frames only.\n"); 2103 ("Flow Control = TX PAUSE frames only.\n");
2105 } 2104 }
2106 /* For transmitting PAUSE frames ONLY. 2105 /* For transmitting PAUSE frames ONLY.
@@ -2117,7 +2116,7 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2117 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2116 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2118 { 2117 {
2119 hw->fc = E1000_FC_RX_PAUSE; 2118 hw->fc = E1000_FC_RX_PAUSE;
2120 DEBUGOUT 2119 e_dbg
2121 ("Flow Control = RX PAUSE frames only.\n"); 2120 ("Flow Control = RX PAUSE frames only.\n");
2122 } 2121 }
2123 /* Per the IEEE spec, at this point flow control should be 2122 /* Per the IEEE spec, at this point flow control should be
@@ -2144,10 +2143,10 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2144 hw->original_fc == E1000_FC_TX_PAUSE) || 2143 hw->original_fc == E1000_FC_TX_PAUSE) ||
2145 hw->fc_strict_ieee) { 2144 hw->fc_strict_ieee) {
2146 hw->fc = E1000_FC_NONE; 2145 hw->fc = E1000_FC_NONE;
2147 DEBUGOUT("Flow Control = NONE.\n"); 2146 e_dbg("Flow Control = NONE.\n");
2148 } else { 2147 } else {
2149 hw->fc = E1000_FC_RX_PAUSE; 2148 hw->fc = E1000_FC_RX_PAUSE;
2150 DEBUGOUT 2149 e_dbg
2151 ("Flow Control = RX PAUSE frames only.\n"); 2150 ("Flow Control = RX PAUSE frames only.\n");
2152 } 2151 }
2153 2152
@@ -2158,7 +2157,7 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2158 ret_val = 2157 ret_val =
2159 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2158 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2160 if (ret_val) { 2159 if (ret_val) {
2161 DEBUGOUT 2160 e_dbg
2162 ("Error getting link speed and duplex\n"); 2161 ("Error getting link speed and duplex\n");
2163 return ret_val; 2162 return ret_val;
2164 } 2163 }
@@ -2171,12 +2170,12 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2171 */ 2170 */
2172 ret_val = e1000_force_mac_fc(hw); 2171 ret_val = e1000_force_mac_fc(hw);
2173 if (ret_val) { 2172 if (ret_val) {
2174 DEBUGOUT 2173 e_dbg
2175 ("Error forcing flow control settings\n"); 2174 ("Error forcing flow control settings\n");
2176 return ret_val; 2175 return ret_val;
2177 } 2176 }
2178 } else { 2177 } else {
2179 DEBUGOUT 2178 e_dbg
2180 ("Copper PHY and Auto Neg has not completed.\n"); 2179 ("Copper PHY and Auto Neg has not completed.\n");
2181 } 2180 }
2182 } 2181 }
@@ -2197,7 +2196,7 @@ static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2197 u32 status; 2196 u32 status;
2198 s32 ret_val = E1000_SUCCESS; 2197 s32 ret_val = E1000_SUCCESS;
2199 2198
2200 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 2199 e_dbg("e1000_check_for_serdes_link_generic");
2201 2200
2202 ctrl = er32(CTRL); 2201 ctrl = er32(CTRL);
2203 status = er32(STATUS); 2202 status = er32(STATUS);
@@ -2216,7 +2215,7 @@ static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2216 hw->autoneg_failed = 1; 2215 hw->autoneg_failed = 1;
2217 goto out; 2216 goto out;
2218 } 2217 }
2219 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 2218 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2220 2219
2221 /* Disable auto-negotiation in the TXCW register */ 2220 /* Disable auto-negotiation in the TXCW register */
2222 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2221 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
@@ -2229,7 +2228,7 @@ static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2229 /* Configure Flow Control after forcing link up. */ 2228 /* Configure Flow Control after forcing link up. */
2230 ret_val = e1000_config_fc_after_link_up(hw); 2229 ret_val = e1000_config_fc_after_link_up(hw);
2231 if (ret_val) { 2230 if (ret_val) {
2232 DEBUGOUT("Error configuring flow control\n"); 2231 e_dbg("Error configuring flow control\n");
2233 goto out; 2232 goto out;
2234 } 2233 }
2235 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2234 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
@@ -2239,7 +2238,7 @@ static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2239 * and disable forced link in the Device Control register 2238 * and disable forced link in the Device Control register
2240 * in an attempt to auto-negotiate with our link partner. 2239 * in an attempt to auto-negotiate with our link partner.
2241 */ 2240 */
2242 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2241 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2243 ew32(TXCW, hw->txcw); 2242 ew32(TXCW, hw->txcw);
2244 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 2243 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2245 2244
@@ -2256,11 +2255,11 @@ static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2256 if (rxcw & E1000_RXCW_SYNCH) { 2255 if (rxcw & E1000_RXCW_SYNCH) {
2257 if (!(rxcw & E1000_RXCW_IV)) { 2256 if (!(rxcw & E1000_RXCW_IV)) {
2258 hw->serdes_has_link = true; 2257 hw->serdes_has_link = true;
2259 DEBUGOUT("SERDES: Link up - forced.\n"); 2258 e_dbg("SERDES: Link up - forced.\n");
2260 } 2259 }
2261 } else { 2260 } else {
2262 hw->serdes_has_link = false; 2261 hw->serdes_has_link = false;
2263 DEBUGOUT("SERDES: Link down - force failed.\n"); 2262 e_dbg("SERDES: Link down - force failed.\n");
2264 } 2263 }
2265 } 2264 }
2266 2265
@@ -2273,20 +2272,20 @@ static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2273 if (rxcw & E1000_RXCW_SYNCH) { 2272 if (rxcw & E1000_RXCW_SYNCH) {
2274 if (!(rxcw & E1000_RXCW_IV)) { 2273 if (!(rxcw & E1000_RXCW_IV)) {
2275 hw->serdes_has_link = true; 2274 hw->serdes_has_link = true;
2276 DEBUGOUT("SERDES: Link up - autoneg " 2275 e_dbg("SERDES: Link up - autoneg "
2277 "completed successfully.\n"); 2276 "completed successfully.\n");
2278 } else { 2277 } else {
2279 hw->serdes_has_link = false; 2278 hw->serdes_has_link = false;
2280 DEBUGOUT("SERDES: Link down - invalid" 2279 e_dbg("SERDES: Link down - invalid"
2281 "codewords detected in autoneg.\n"); 2280 "codewords detected in autoneg.\n");
2282 } 2281 }
2283 } else { 2282 } else {
2284 hw->serdes_has_link = false; 2283 hw->serdes_has_link = false;
2285 DEBUGOUT("SERDES: Link down - no sync.\n"); 2284 e_dbg("SERDES: Link down - no sync.\n");
2286 } 2285 }
2287 } else { 2286 } else {
2288 hw->serdes_has_link = false; 2287 hw->serdes_has_link = false;
2289 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 2288 e_dbg("SERDES: Link down - autoneg failed\n");
2290 } 2289 }
2291 } 2290 }
2292 2291
@@ -2312,7 +2311,7 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
2312 s32 ret_val; 2311 s32 ret_val;
2313 u16 phy_data; 2312 u16 phy_data;
2314 2313
2315 DEBUGFUNC("e1000_check_for_link"); 2314 e_dbg("e1000_check_for_link");
2316 2315
2317 ctrl = er32(CTRL); 2316 ctrl = er32(CTRL);
2318 status = er32(STATUS); 2317 status = er32(STATUS);
@@ -2407,7 +2406,7 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
2407 else { 2406 else {
2408 ret_val = e1000_config_mac_to_phy(hw); 2407 ret_val = e1000_config_mac_to_phy(hw);
2409 if (ret_val) { 2408 if (ret_val) {
2410 DEBUGOUT 2409 e_dbg
2411 ("Error configuring MAC to PHY settings\n"); 2410 ("Error configuring MAC to PHY settings\n");
2412 return ret_val; 2411 return ret_val;
2413 } 2412 }
@@ -2419,7 +2418,7 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
2419 */ 2418 */
2420 ret_val = e1000_config_fc_after_link_up(hw); 2419 ret_val = e1000_config_fc_after_link_up(hw);
2421 if (ret_val) { 2420 if (ret_val) {
2422 DEBUGOUT("Error configuring flow control\n"); 2421 e_dbg("Error configuring flow control\n");
2423 return ret_val; 2422 return ret_val;
2424 } 2423 }
2425 2424
@@ -2435,7 +2434,7 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
2435 ret_val = 2434 ret_val =
2436 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2435 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2437 if (ret_val) { 2436 if (ret_val) {
2438 DEBUGOUT 2437 e_dbg
2439 ("Error getting link speed and duplex\n"); 2438 ("Error getting link speed and duplex\n");
2440 return ret_val; 2439 return ret_val;
2441 } 2440 }
@@ -2487,30 +2486,30 @@ s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2487 s32 ret_val; 2486 s32 ret_val;
2488 u16 phy_data; 2487 u16 phy_data;
2489 2488
2490 DEBUGFUNC("e1000_get_speed_and_duplex"); 2489 e_dbg("e1000_get_speed_and_duplex");
2491 2490
2492 if (hw->mac_type >= e1000_82543) { 2491 if (hw->mac_type >= e1000_82543) {
2493 status = er32(STATUS); 2492 status = er32(STATUS);
2494 if (status & E1000_STATUS_SPEED_1000) { 2493 if (status & E1000_STATUS_SPEED_1000) {
2495 *speed = SPEED_1000; 2494 *speed = SPEED_1000;
2496 DEBUGOUT("1000 Mbs, "); 2495 e_dbg("1000 Mbs, ");
2497 } else if (status & E1000_STATUS_SPEED_100) { 2496 } else if (status & E1000_STATUS_SPEED_100) {
2498 *speed = SPEED_100; 2497 *speed = SPEED_100;
2499 DEBUGOUT("100 Mbs, "); 2498 e_dbg("100 Mbs, ");
2500 } else { 2499 } else {
2501 *speed = SPEED_10; 2500 *speed = SPEED_10;
2502 DEBUGOUT("10 Mbs, "); 2501 e_dbg("10 Mbs, ");
2503 } 2502 }
2504 2503
2505 if (status & E1000_STATUS_FD) { 2504 if (status & E1000_STATUS_FD) {
2506 *duplex = FULL_DUPLEX; 2505 *duplex = FULL_DUPLEX;
2507 DEBUGOUT("Full Duplex\n"); 2506 e_dbg("Full Duplex\n");
2508 } else { 2507 } else {
2509 *duplex = HALF_DUPLEX; 2508 *duplex = HALF_DUPLEX;
2510 DEBUGOUT(" Half Duplex\n"); 2509 e_dbg(" Half Duplex\n");
2511 } 2510 }
2512 } else { 2511 } else {
2513 DEBUGOUT("1000 Mbs, Full Duplex\n"); 2512 e_dbg("1000 Mbs, Full Duplex\n");
2514 *speed = SPEED_1000; 2513 *speed = SPEED_1000;
2515 *duplex = FULL_DUPLEX; 2514 *duplex = FULL_DUPLEX;
2516 } 2515 }
@@ -2554,8 +2553,8 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2554 u16 i; 2553 u16 i;
2555 u16 phy_data; 2554 u16 phy_data;
2556 2555
2557 DEBUGFUNC("e1000_wait_autoneg"); 2556 e_dbg("e1000_wait_autoneg");
2558 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2557 e_dbg("Waiting for Auto-Neg to complete.\n");
2559 2558
2560 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2559 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2561 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2560 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
@@ -2718,7 +2717,7 @@ s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2718{ 2717{
2719 u32 ret_val; 2718 u32 ret_val;
2720 2719
2721 DEBUGFUNC("e1000_read_phy_reg"); 2720 e_dbg("e1000_read_phy_reg");
2722 2721
2723 if ((hw->phy_type == e1000_phy_igp) && 2722 if ((hw->phy_type == e1000_phy_igp) &&
2724 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2723 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
@@ -2741,10 +2740,10 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2741 u32 mdic = 0; 2740 u32 mdic = 0;
2742 const u32 phy_addr = 1; 2741 const u32 phy_addr = 1;
2743 2742
2744 DEBUGFUNC("e1000_read_phy_reg_ex"); 2743 e_dbg("e1000_read_phy_reg_ex");
2745 2744
2746 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2745 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2747 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2746 e_dbg("PHY Address %d is out of range\n", reg_addr);
2748 return -E1000_ERR_PARAM; 2747 return -E1000_ERR_PARAM;
2749 } 2748 }
2750 2749
@@ -2767,11 +2766,11 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2767 break; 2766 break;
2768 } 2767 }
2769 if (!(mdic & E1000_MDIC_READY)) { 2768 if (!(mdic & E1000_MDIC_READY)) {
2770 DEBUGOUT("MDI Read did not complete\n"); 2769 e_dbg("MDI Read did not complete\n");
2771 return -E1000_ERR_PHY; 2770 return -E1000_ERR_PHY;
2772 } 2771 }
2773 if (mdic & E1000_MDIC_ERROR) { 2772 if (mdic & E1000_MDIC_ERROR) {
2774 DEBUGOUT("MDI Error\n"); 2773 e_dbg("MDI Error\n");
2775 return -E1000_ERR_PHY; 2774 return -E1000_ERR_PHY;
2776 } 2775 }
2777 *phy_data = (u16) mdic; 2776 *phy_data = (u16) mdic;
@@ -2820,7 +2819,7 @@ s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2820{ 2819{
2821 u32 ret_val; 2820 u32 ret_val;
2822 2821
2823 DEBUGFUNC("e1000_write_phy_reg"); 2822 e_dbg("e1000_write_phy_reg");
2824 2823
2825 if ((hw->phy_type == e1000_phy_igp) && 2824 if ((hw->phy_type == e1000_phy_igp) &&
2826 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2825 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
@@ -2843,10 +2842,10 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2843 u32 mdic = 0; 2842 u32 mdic = 0;
2844 const u32 phy_addr = 1; 2843 const u32 phy_addr = 1;
2845 2844
2846 DEBUGFUNC("e1000_write_phy_reg_ex"); 2845 e_dbg("e1000_write_phy_reg_ex");
2847 2846
2848 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2847 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2849 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2848 e_dbg("PHY Address %d is out of range\n", reg_addr);
2850 return -E1000_ERR_PARAM; 2849 return -E1000_ERR_PARAM;
2851 } 2850 }
2852 2851
@@ -2870,7 +2869,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2870 break; 2869 break;
2871 } 2870 }
2872 if (!(mdic & E1000_MDIC_READY)) { 2871 if (!(mdic & E1000_MDIC_READY)) {
2873 DEBUGOUT("MDI Write did not complete\n"); 2872 e_dbg("MDI Write did not complete\n");
2874 return -E1000_ERR_PHY; 2873 return -E1000_ERR_PHY;
2875 } 2874 }
2876 } else { 2875 } else {
@@ -2910,9 +2909,9 @@ s32 e1000_phy_hw_reset(struct e1000_hw *hw)
2910 u32 led_ctrl; 2909 u32 led_ctrl;
2911 s32 ret_val; 2910 s32 ret_val;
2912 2911
2913 DEBUGFUNC("e1000_phy_hw_reset"); 2912 e_dbg("e1000_phy_hw_reset");
2914 2913
2915 DEBUGOUT("Resetting Phy...\n"); 2914 e_dbg("Resetting Phy...\n");
2916 2915
2917 if (hw->mac_type > e1000_82543) { 2916 if (hw->mac_type > e1000_82543) {
2918 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2917 /* Read the device control register and assert the E1000_CTRL_PHY_RST
@@ -2973,7 +2972,7 @@ s32 e1000_phy_reset(struct e1000_hw *hw)
2973 s32 ret_val; 2972 s32 ret_val;
2974 u16 phy_data; 2973 u16 phy_data;
2975 2974
2976 DEBUGFUNC("e1000_phy_reset"); 2975 e_dbg("e1000_phy_reset");
2977 2976
2978 switch (hw->phy_type) { 2977 switch (hw->phy_type) {
2979 case e1000_phy_igp: 2978 case e1000_phy_igp:
@@ -3013,7 +3012,7 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3013 u16 phy_id_high, phy_id_low; 3012 u16 phy_id_high, phy_id_low;
3014 bool match = false; 3013 bool match = false;
3015 3014
3016 DEBUGFUNC("e1000_detect_gig_phy"); 3015 e_dbg("e1000_detect_gig_phy");
3017 3016
3018 if (hw->phy_id != 0) 3017 if (hw->phy_id != 0)
3019 return E1000_SUCCESS; 3018 return E1000_SUCCESS;
@@ -3057,16 +3056,16 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3057 match = true; 3056 match = true;
3058 break; 3057 break;
3059 default: 3058 default:
3060 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3059 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3061 return -E1000_ERR_CONFIG; 3060 return -E1000_ERR_CONFIG;
3062 } 3061 }
3063 phy_init_status = e1000_set_phy_type(hw); 3062 phy_init_status = e1000_set_phy_type(hw);
3064 3063
3065 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3064 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3066 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 3065 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3067 return E1000_SUCCESS; 3066 return E1000_SUCCESS;
3068 } 3067 }
3069 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 3068 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3070 return -E1000_ERR_PHY; 3069 return -E1000_ERR_PHY;
3071} 3070}
3072 3071
@@ -3079,7 +3078,7 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3079static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3078static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3080{ 3079{
3081 s32 ret_val; 3080 s32 ret_val;
3082 DEBUGFUNC("e1000_phy_reset_dsp"); 3081 e_dbg("e1000_phy_reset_dsp");
3083 3082
3084 do { 3083 do {
3085 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3084 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
@@ -3111,7 +3110,7 @@ static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3111 u16 phy_data, min_length, max_length, average; 3110 u16 phy_data, min_length, max_length, average;
3112 e1000_rev_polarity polarity; 3111 e1000_rev_polarity polarity;
3113 3112
3114 DEBUGFUNC("e1000_phy_igp_get_info"); 3113 e_dbg("e1000_phy_igp_get_info");
3115 3114
3116 /* The downshift status is checked only once, after link is established, 3115 /* The downshift status is checked only once, after link is established,
3117 * and it stored in the hw->speed_downgraded parameter. */ 3116 * and it stored in the hw->speed_downgraded parameter. */
@@ -3189,7 +3188,7 @@ static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3189 u16 phy_data; 3188 u16 phy_data;
3190 e1000_rev_polarity polarity; 3189 e1000_rev_polarity polarity;
3191 3190
3192 DEBUGFUNC("e1000_phy_m88_get_info"); 3191 e_dbg("e1000_phy_m88_get_info");
3193 3192
3194 /* The downshift status is checked only once, after link is established, 3193 /* The downshift status is checked only once, after link is established,
3195 * and it stored in the hw->speed_downgraded parameter. */ 3194 * and it stored in the hw->speed_downgraded parameter. */
@@ -3261,7 +3260,7 @@ s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3261 s32 ret_val; 3260 s32 ret_val;
3262 u16 phy_data; 3261 u16 phy_data;
3263 3262
3264 DEBUGFUNC("e1000_phy_get_info"); 3263 e_dbg("e1000_phy_get_info");
3265 3264
3266 phy_info->cable_length = e1000_cable_length_undefined; 3265 phy_info->cable_length = e1000_cable_length_undefined;
3267 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3266 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
@@ -3273,7 +3272,7 @@ s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3273 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3272 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3274 3273
3275 if (hw->media_type != e1000_media_type_copper) { 3274 if (hw->media_type != e1000_media_type_copper) {
3276 DEBUGOUT("PHY info is only valid for copper media\n"); 3275 e_dbg("PHY info is only valid for copper media\n");
3277 return -E1000_ERR_CONFIG; 3276 return -E1000_ERR_CONFIG;
3278 } 3277 }
3279 3278
@@ -3286,7 +3285,7 @@ s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3286 return ret_val; 3285 return ret_val;
3287 3286
3288 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3287 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3289 DEBUGOUT("PHY info is only valid if link is up\n"); 3288 e_dbg("PHY info is only valid if link is up\n");
3290 return -E1000_ERR_CONFIG; 3289 return -E1000_ERR_CONFIG;
3291 } 3290 }
3292 3291
@@ -3298,10 +3297,10 @@ s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3298 3297
3299s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3298s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3300{ 3299{
3301 DEBUGFUNC("e1000_validate_mdi_settings"); 3300 e_dbg("e1000_validate_mdi_settings");
3302 3301
3303 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 3302 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3304 DEBUGOUT("Invalid MDI setting detected\n"); 3303 e_dbg("Invalid MDI setting detected\n");
3305 hw->mdix = 1; 3304 hw->mdix = 1;
3306 return -E1000_ERR_CONFIG; 3305 return -E1000_ERR_CONFIG;
3307 } 3306 }
@@ -3322,7 +3321,7 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3322 s32 ret_val = E1000_SUCCESS; 3321 s32 ret_val = E1000_SUCCESS;
3323 u16 eeprom_size; 3322 u16 eeprom_size;
3324 3323
3325 DEBUGFUNC("e1000_init_eeprom_params"); 3324 e_dbg("e1000_init_eeprom_params");
3326 3325
3327 switch (hw->mac_type) { 3326 switch (hw->mac_type) {
3328 case e1000_82542_rev2_0: 3327 case e1000_82542_rev2_0:
@@ -3539,7 +3538,7 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3539 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3538 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3540 u32 eecd, i = 0; 3539 u32 eecd, i = 0;
3541 3540
3542 DEBUGFUNC("e1000_acquire_eeprom"); 3541 e_dbg("e1000_acquire_eeprom");
3543 3542
3544 eecd = er32(EECD); 3543 eecd = er32(EECD);
3545 3544
@@ -3557,7 +3556,7 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3557 if (!(eecd & E1000_EECD_GNT)) { 3556 if (!(eecd & E1000_EECD_GNT)) {
3558 eecd &= ~E1000_EECD_REQ; 3557 eecd &= ~E1000_EECD_REQ;
3559 ew32(EECD, eecd); 3558 ew32(EECD, eecd);
3560 DEBUGOUT("Could not acquire EEPROM grant\n"); 3559 e_dbg("Could not acquire EEPROM grant\n");
3561 return -E1000_ERR_EEPROM; 3560 return -E1000_ERR_EEPROM;
3562 } 3561 }
3563 } 3562 }
@@ -3639,7 +3638,7 @@ static void e1000_release_eeprom(struct e1000_hw *hw)
3639{ 3638{
3640 u32 eecd; 3639 u32 eecd;
3641 3640
3642 DEBUGFUNC("e1000_release_eeprom"); 3641 e_dbg("e1000_release_eeprom");
3643 3642
3644 eecd = er32(EECD); 3643 eecd = er32(EECD);
3645 3644
@@ -3687,7 +3686,7 @@ static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3687 u16 retry_count = 0; 3686 u16 retry_count = 0;
3688 u8 spi_stat_reg; 3687 u8 spi_stat_reg;
3689 3688
3690 DEBUGFUNC("e1000_spi_eeprom_ready"); 3689 e_dbg("e1000_spi_eeprom_ready");
3691 3690
3692 /* Read "Status Register" repeatedly until the LSB is cleared. The 3691 /* Read "Status Register" repeatedly until the LSB is cleared. The
3693 * EEPROM will signal that the command has been completed by clearing 3692 * EEPROM will signal that the command has been completed by clearing
@@ -3712,7 +3711,7 @@ static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3712 * only 0-5mSec on 5V devices) 3711 * only 0-5mSec on 5V devices)
3713 */ 3712 */
3714 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 3713 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3715 DEBUGOUT("SPI EEPROM Status error\n"); 3714 e_dbg("SPI EEPROM Status error\n");
3716 return -E1000_ERR_EEPROM; 3715 return -E1000_ERR_EEPROM;
3717 } 3716 }
3718 3717
@@ -3741,7 +3740,7 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3741 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3740 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3742 u32 i = 0; 3741 u32 i = 0;
3743 3742
3744 DEBUGFUNC("e1000_read_eeprom"); 3743 e_dbg("e1000_read_eeprom");
3745 3744
3746 /* If eeprom is not yet detected, do so now */ 3745 /* If eeprom is not yet detected, do so now */
3747 if (eeprom->word_size == 0) 3746 if (eeprom->word_size == 0)
@@ -3752,9 +3751,8 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3752 */ 3751 */
3753 if ((offset >= eeprom->word_size) 3752 if ((offset >= eeprom->word_size)
3754 || (words > eeprom->word_size - offset) || (words == 0)) { 3753 || (words > eeprom->word_size - offset) || (words == 0)) {
3755 DEBUGOUT2 3754 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3756 ("\"words\" parameter out of bounds. Words = %d, size = %d\n", 3755 "size = %d\n", offset, eeprom->word_size);
3757 offset, eeprom->word_size);
3758 return -E1000_ERR_EEPROM; 3756 return -E1000_ERR_EEPROM;
3759 } 3757 }
3760 3758
@@ -3832,11 +3830,11 @@ s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3832 u16 checksum = 0; 3830 u16 checksum = 0;
3833 u16 i, eeprom_data; 3831 u16 i, eeprom_data;
3834 3832
3835 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3833 e_dbg("e1000_validate_eeprom_checksum");
3836 3834
3837 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3835 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3838 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3836 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3839 DEBUGOUT("EEPROM Read Error\n"); 3837 e_dbg("EEPROM Read Error\n");
3840 return -E1000_ERR_EEPROM; 3838 return -E1000_ERR_EEPROM;
3841 } 3839 }
3842 checksum += eeprom_data; 3840 checksum += eeprom_data;
@@ -3845,7 +3843,7 @@ s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3845 if (checksum == (u16) EEPROM_SUM) 3843 if (checksum == (u16) EEPROM_SUM)
3846 return E1000_SUCCESS; 3844 return E1000_SUCCESS;
3847 else { 3845 else {
3848 DEBUGOUT("EEPROM Checksum Invalid\n"); 3846 e_dbg("EEPROM Checksum Invalid\n");
3849 return -E1000_ERR_EEPROM; 3847 return -E1000_ERR_EEPROM;
3850 } 3848 }
3851} 3849}
@@ -3862,18 +3860,18 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3862 u16 checksum = 0; 3860 u16 checksum = 0;
3863 u16 i, eeprom_data; 3861 u16 i, eeprom_data;
3864 3862
3865 DEBUGFUNC("e1000_update_eeprom_checksum"); 3863 e_dbg("e1000_update_eeprom_checksum");
3866 3864
3867 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 3865 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3868 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3866 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3869 DEBUGOUT("EEPROM Read Error\n"); 3867 e_dbg("EEPROM Read Error\n");
3870 return -E1000_ERR_EEPROM; 3868 return -E1000_ERR_EEPROM;
3871 } 3869 }
3872 checksum += eeprom_data; 3870 checksum += eeprom_data;
3873 } 3871 }
3874 checksum = (u16) EEPROM_SUM - checksum; 3872 checksum = (u16) EEPROM_SUM - checksum;
3875 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 3873 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3876 DEBUGOUT("EEPROM Write Error\n"); 3874 e_dbg("EEPROM Write Error\n");
3877 return -E1000_ERR_EEPROM; 3875 return -E1000_ERR_EEPROM;
3878 } 3876 }
3879 return E1000_SUCCESS; 3877 return E1000_SUCCESS;
@@ -3904,7 +3902,7 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3904 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3902 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3905 s32 status = 0; 3903 s32 status = 0;
3906 3904
3907 DEBUGFUNC("e1000_write_eeprom"); 3905 e_dbg("e1000_write_eeprom");
3908 3906
3909 /* If eeprom is not yet detected, do so now */ 3907 /* If eeprom is not yet detected, do so now */
3910 if (eeprom->word_size == 0) 3908 if (eeprom->word_size == 0)
@@ -3915,7 +3913,7 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3915 */ 3913 */
3916 if ((offset >= eeprom->word_size) 3914 if ((offset >= eeprom->word_size)
3917 || (words > eeprom->word_size - offset) || (words == 0)) { 3915 || (words > eeprom->word_size - offset) || (words == 0)) {
3918 DEBUGOUT("\"words\" parameter out of bounds\n"); 3916 e_dbg("\"words\" parameter out of bounds\n");
3919 return -E1000_ERR_EEPROM; 3917 return -E1000_ERR_EEPROM;
3920 } 3918 }
3921 3919
@@ -3949,7 +3947,7 @@ static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
3949 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3947 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3950 u16 widx = 0; 3948 u16 widx = 0;
3951 3949
3952 DEBUGFUNC("e1000_write_eeprom_spi"); 3950 e_dbg("e1000_write_eeprom_spi");
3953 3951
3954 while (widx < words) { 3952 while (widx < words) {
3955 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 3953 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
@@ -4013,7 +4011,7 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4013 u16 words_written = 0; 4011 u16 words_written = 0;
4014 u16 i = 0; 4012 u16 i = 0;
4015 4013
4016 DEBUGFUNC("e1000_write_eeprom_microwire"); 4014 e_dbg("e1000_write_eeprom_microwire");
4017 4015
4018 /* Send the write enable command to the EEPROM (3-bit opcode plus 4016 /* Send the write enable command to the EEPROM (3-bit opcode plus
4019 * 6/8-bit dummy address beginning with 11). It's less work to include 4017 * 6/8-bit dummy address beginning with 11). It's less work to include
@@ -4056,7 +4054,7 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4056 udelay(50); 4054 udelay(50);
4057 } 4055 }
4058 if (i == 200) { 4056 if (i == 200) {
4059 DEBUGOUT("EEPROM Write did not complete\n"); 4057 e_dbg("EEPROM Write did not complete\n");
4060 return -E1000_ERR_EEPROM; 4058 return -E1000_ERR_EEPROM;
4061 } 4059 }
4062 4060
@@ -4092,12 +4090,12 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw)
4092 u16 offset; 4090 u16 offset;
4093 u16 eeprom_data, i; 4091 u16 eeprom_data, i;
4094 4092
4095 DEBUGFUNC("e1000_read_mac_addr"); 4093 e_dbg("e1000_read_mac_addr");
4096 4094
4097 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4095 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4098 offset = i >> 1; 4096 offset = i >> 1;
4099 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4097 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4100 DEBUGOUT("EEPROM Read Error\n"); 4098 e_dbg("EEPROM Read Error\n");
4101 return -E1000_ERR_EEPROM; 4099 return -E1000_ERR_EEPROM;
4102 } 4100 }
4103 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); 4101 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
@@ -4132,17 +4130,17 @@ static void e1000_init_rx_addrs(struct e1000_hw *hw)
4132 u32 i; 4130 u32 i;
4133 u32 rar_num; 4131 u32 rar_num;
4134 4132
4135 DEBUGFUNC("e1000_init_rx_addrs"); 4133 e_dbg("e1000_init_rx_addrs");
4136 4134
4137 /* Setup the receive address. */ 4135 /* Setup the receive address. */
4138 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 4136 e_dbg("Programming MAC Address into RAR[0]\n");
4139 4137
4140 e1000_rar_set(hw, hw->mac_addr, 0); 4138 e1000_rar_set(hw, hw->mac_addr, 0);
4141 4139
4142 rar_num = E1000_RAR_ENTRIES; 4140 rar_num = E1000_RAR_ENTRIES;
4143 4141
4144 /* Zero out the other 15 receive addresses. */ 4142 /* Zero out the other 15 receive addresses. */
4145 DEBUGOUT("Clearing RAR[1-15]\n"); 4143 e_dbg("Clearing RAR[1-15]\n");
4146 for (i = 1; i < rar_num; i++) { 4144 for (i = 1; i < rar_num; i++) {
4147 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4145 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4148 E1000_WRITE_FLUSH(); 4146 E1000_WRITE_FLUSH();
@@ -4290,7 +4288,7 @@ static s32 e1000_id_led_init(struct e1000_hw *hw)
4290 u16 eeprom_data, i, temp; 4288 u16 eeprom_data, i, temp;
4291 const u16 led_mask = 0x0F; 4289 const u16 led_mask = 0x0F;
4292 4290
4293 DEBUGFUNC("e1000_id_led_init"); 4291 e_dbg("e1000_id_led_init");
4294 4292
4295 if (hw->mac_type < e1000_82540) { 4293 if (hw->mac_type < e1000_82540) {
4296 /* Nothing to do */ 4294 /* Nothing to do */
@@ -4303,7 +4301,7 @@ static s32 e1000_id_led_init(struct e1000_hw *hw)
4303 hw->ledctl_mode2 = hw->ledctl_default; 4301 hw->ledctl_mode2 = hw->ledctl_default;
4304 4302
4305 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4303 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4306 DEBUGOUT("EEPROM Read Error\n"); 4304 e_dbg("EEPROM Read Error\n");
4307 return -E1000_ERR_EEPROM; 4305 return -E1000_ERR_EEPROM;
4308 } 4306 }
4309 4307
@@ -4363,7 +4361,7 @@ s32 e1000_setup_led(struct e1000_hw *hw)
4363 u32 ledctl; 4361 u32 ledctl;
4364 s32 ret_val = E1000_SUCCESS; 4362 s32 ret_val = E1000_SUCCESS;
4365 4363
4366 DEBUGFUNC("e1000_setup_led"); 4364 e_dbg("e1000_setup_led");
4367 4365
4368 switch (hw->mac_type) { 4366 switch (hw->mac_type) {
4369 case e1000_82542_rev2_0: 4367 case e1000_82542_rev2_0:
@@ -4415,7 +4413,7 @@ s32 e1000_cleanup_led(struct e1000_hw *hw)
4415{ 4413{
4416 s32 ret_val = E1000_SUCCESS; 4414 s32 ret_val = E1000_SUCCESS;
4417 4415
4418 DEBUGFUNC("e1000_cleanup_led"); 4416 e_dbg("e1000_cleanup_led");
4419 4417
4420 switch (hw->mac_type) { 4418 switch (hw->mac_type) {
4421 case e1000_82542_rev2_0: 4419 case e1000_82542_rev2_0:
@@ -4451,7 +4449,7 @@ s32 e1000_led_on(struct e1000_hw *hw)
4451{ 4449{
4452 u32 ctrl = er32(CTRL); 4450 u32 ctrl = er32(CTRL);
4453 4451
4454 DEBUGFUNC("e1000_led_on"); 4452 e_dbg("e1000_led_on");
4455 4453
4456 switch (hw->mac_type) { 4454 switch (hw->mac_type) {
4457 case e1000_82542_rev2_0: 4455 case e1000_82542_rev2_0:
@@ -4497,7 +4495,7 @@ s32 e1000_led_off(struct e1000_hw *hw)
4497{ 4495{
4498 u32 ctrl = er32(CTRL); 4496 u32 ctrl = er32(CTRL);
4499 4497
4500 DEBUGFUNC("e1000_led_off"); 4498 e_dbg("e1000_led_off");
4501 4499
4502 switch (hw->mac_type) { 4500 switch (hw->mac_type) {
4503 case e1000_82542_rev2_0: 4501 case e1000_82542_rev2_0:
@@ -4626,7 +4624,7 @@ static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4626 */ 4624 */
4627void e1000_reset_adaptive(struct e1000_hw *hw) 4625void e1000_reset_adaptive(struct e1000_hw *hw)
4628{ 4626{
4629 DEBUGFUNC("e1000_reset_adaptive"); 4627 e_dbg("e1000_reset_adaptive");
4630 4628
4631 if (hw->adaptive_ifs) { 4629 if (hw->adaptive_ifs) {
4632 if (!hw->ifs_params_forced) { 4630 if (!hw->ifs_params_forced) {
@@ -4639,7 +4637,7 @@ void e1000_reset_adaptive(struct e1000_hw *hw)
4639 hw->in_ifs_mode = false; 4637 hw->in_ifs_mode = false;
4640 ew32(AIT, 0); 4638 ew32(AIT, 0);
4641 } else { 4639 } else {
4642 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4640 e_dbg("Not in Adaptive IFS mode!\n");
4643 } 4641 }
4644} 4642}
4645 4643
@@ -4654,7 +4652,7 @@ void e1000_reset_adaptive(struct e1000_hw *hw)
4654 */ 4652 */
4655void e1000_update_adaptive(struct e1000_hw *hw) 4653void e1000_update_adaptive(struct e1000_hw *hw)
4656{ 4654{
4657 DEBUGFUNC("e1000_update_adaptive"); 4655 e_dbg("e1000_update_adaptive");
4658 4656
4659 if (hw->adaptive_ifs) { 4657 if (hw->adaptive_ifs) {
4660 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { 4658 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
@@ -4679,7 +4677,7 @@ void e1000_update_adaptive(struct e1000_hw *hw)
4679 } 4677 }
4680 } 4678 }
4681 } else { 4679 } else {
4682 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4680 e_dbg("Not in Adaptive IFS mode!\n");
4683 } 4681 }
4684} 4682}
4685 4683
@@ -4851,7 +4849,7 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4851 u16 i, phy_data; 4849 u16 i, phy_data;
4852 u16 cable_length; 4850 u16 cable_length;
4853 4851
4854 DEBUGFUNC("e1000_get_cable_length"); 4852 e_dbg("e1000_get_cable_length");
4855 4853
4856 *min_length = *max_length = 0; 4854 *min_length = *max_length = 0;
4857 4855
@@ -4968,7 +4966,7 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
4968 s32 ret_val; 4966 s32 ret_val;
4969 u16 phy_data; 4967 u16 phy_data;
4970 4968
4971 DEBUGFUNC("e1000_check_polarity"); 4969 e_dbg("e1000_check_polarity");
4972 4970
4973 if (hw->phy_type == e1000_phy_m88) { 4971 if (hw->phy_type == e1000_phy_m88) {
4974 /* return the Polarity bit in the Status register. */ 4972 /* return the Polarity bit in the Status register. */
@@ -5034,7 +5032,7 @@ static s32 e1000_check_downshift(struct e1000_hw *hw)
5034 s32 ret_val; 5032 s32 ret_val;
5035 u16 phy_data; 5033 u16 phy_data;
5036 5034
5037 DEBUGFUNC("e1000_check_downshift"); 5035 e_dbg("e1000_check_downshift");
5038 5036
5039 if (hw->phy_type == e1000_phy_igp) { 5037 if (hw->phy_type == e1000_phy_igp) {
5040 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5038 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
@@ -5081,7 +5079,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5081 }; 5079 };
5082 u16 min_length, max_length; 5080 u16 min_length, max_length;
5083 5081
5084 DEBUGFUNC("e1000_config_dsp_after_link_change"); 5082 e_dbg("e1000_config_dsp_after_link_change");
5085 5083
5086 if (hw->phy_type != e1000_phy_igp) 5084 if (hw->phy_type != e1000_phy_igp)
5087 return E1000_SUCCESS; 5085 return E1000_SUCCESS;
@@ -5089,7 +5087,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5089 if (link_up) { 5087 if (link_up) {
5090 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 5088 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5091 if (ret_val) { 5089 if (ret_val) {
5092 DEBUGOUT("Error getting link speed and duplex\n"); 5090 e_dbg("Error getting link speed and duplex\n");
5093 return ret_val; 5091 return ret_val;
5094 } 5092 }
5095 5093
@@ -5289,7 +5287,7 @@ static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5289 s32 ret_val; 5287 s32 ret_val;
5290 u16 eeprom_data; 5288 u16 eeprom_data;
5291 5289
5292 DEBUGFUNC("e1000_set_phy_mode"); 5290 e_dbg("e1000_set_phy_mode");
5293 5291
5294 if ((hw->mac_type == e1000_82545_rev_3) && 5292 if ((hw->mac_type == e1000_82545_rev_3) &&
5295 (hw->media_type == e1000_media_type_copper)) { 5293 (hw->media_type == e1000_media_type_copper)) {
@@ -5337,7 +5335,7 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5337{ 5335{
5338 s32 ret_val; 5336 s32 ret_val;
5339 u16 phy_data; 5337 u16 phy_data;
5340 DEBUGFUNC("e1000_set_d3_lplu_state"); 5338 e_dbg("e1000_set_d3_lplu_state");
5341 5339
5342 if (hw->phy_type != e1000_phy_igp) 5340 if (hw->phy_type != e1000_phy_igp)
5343 return E1000_SUCCESS; 5341 return E1000_SUCCESS;
@@ -5440,7 +5438,7 @@ static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5440 u16 default_page = 0; 5438 u16 default_page = 0;
5441 u16 phy_data; 5439 u16 phy_data;
5442 5440
5443 DEBUGFUNC("e1000_set_vco_speed"); 5441 e_dbg("e1000_set_vco_speed");
5444 5442
5445 switch (hw->mac_type) { 5443 switch (hw->mac_type) {
5446 case e1000_82545_rev_3: 5444 case e1000_82545_rev_3:
@@ -5613,7 +5611,7 @@ static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5613 */ 5611 */
5614static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5612static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5615{ 5613{
5616 DEBUGFUNC("e1000_get_auto_rd_done"); 5614 e_dbg("e1000_get_auto_rd_done");
5617 msleep(5); 5615 msleep(5);
5618 return E1000_SUCCESS; 5616 return E1000_SUCCESS;
5619} 5617}
@@ -5628,7 +5626,7 @@ static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5628 */ 5626 */
5629static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5627static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5630{ 5628{
5631 DEBUGFUNC("e1000_get_phy_cfg_done"); 5629 e_dbg("e1000_get_phy_cfg_done");
5632 mdelay(10); 5630 mdelay(10);
5633 return E1000_SUCCESS; 5631 return E1000_SUCCESS;
5634} 5632}