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path: root/drivers/net/e1000/e1000_hw.c
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c219
1 files changed, 186 insertions, 33 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 045f5426ab9a..7d627dd89a3d 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -83,14 +83,14 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
83 83
84static const 84static const
85uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 85uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
86 { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 86 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
87 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58, 87 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
88 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74, 88 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
89 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90, 89 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
90 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108, 90 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
91 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124, 91 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
92 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128, 92 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
93 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128}; 93 104, 109, 114, 118, 121, 124};
94 94
95 95
96/****************************************************************************** 96/******************************************************************************
@@ -286,7 +286,6 @@ e1000_set_mac_type(struct e1000_hw *hw)
286 case E1000_DEV_ID_82546GB_FIBER: 286 case E1000_DEV_ID_82546GB_FIBER:
287 case E1000_DEV_ID_82546GB_SERDES: 287 case E1000_DEV_ID_82546GB_SERDES:
288 case E1000_DEV_ID_82546GB_PCIE: 288 case E1000_DEV_ID_82546GB_PCIE:
289 case E1000_DEV_ID_82546GB_QUAD_COPPER:
290 hw->mac_type = e1000_82546_rev_3; 289 hw->mac_type = e1000_82546_rev_3;
291 break; 290 break;
292 case E1000_DEV_ID_82541EI: 291 case E1000_DEV_ID_82541EI:
@@ -305,8 +304,19 @@ e1000_set_mac_type(struct e1000_hw *hw)
305 case E1000_DEV_ID_82547GI: 304 case E1000_DEV_ID_82547GI:
306 hw->mac_type = e1000_82547_rev_2; 305 hw->mac_type = e1000_82547_rev_2;
307 break; 306 break;
307 case E1000_DEV_ID_82571EB_COPPER:
308 case E1000_DEV_ID_82571EB_FIBER:
309 case E1000_DEV_ID_82571EB_SERDES:
310 hw->mac_type = e1000_82571;
311 break;
312 case E1000_DEV_ID_82572EI_COPPER:
313 case E1000_DEV_ID_82572EI_FIBER:
314 case E1000_DEV_ID_82572EI_SERDES:
315 hw->mac_type = e1000_82572;
316 break;
308 case E1000_DEV_ID_82573E: 317 case E1000_DEV_ID_82573E:
309 case E1000_DEV_ID_82573E_IAMT: 318 case E1000_DEV_ID_82573E_IAMT:
319 case E1000_DEV_ID_82573L:
310 hw->mac_type = e1000_82573; 320 hw->mac_type = e1000_82573;
311 break; 321 break;
312 default: 322 default:
@@ -315,6 +325,8 @@ e1000_set_mac_type(struct e1000_hw *hw)
315 } 325 }
316 326
317 switch(hw->mac_type) { 327 switch(hw->mac_type) {
328 case e1000_82571:
329 case e1000_82572:
318 case e1000_82573: 330 case e1000_82573:
319 hw->eeprom_semaphore_present = TRUE; 331 hw->eeprom_semaphore_present = TRUE;
320 /* fall through */ 332 /* fall through */
@@ -351,6 +363,8 @@ e1000_set_media_type(struct e1000_hw *hw)
351 switch (hw->device_id) { 363 switch (hw->device_id) {
352 case E1000_DEV_ID_82545GM_SERDES: 364 case E1000_DEV_ID_82545GM_SERDES:
353 case E1000_DEV_ID_82546GB_SERDES: 365 case E1000_DEV_ID_82546GB_SERDES:
366 case E1000_DEV_ID_82571EB_SERDES:
367 case E1000_DEV_ID_82572EI_SERDES:
354 hw->media_type = e1000_media_type_internal_serdes; 368 hw->media_type = e1000_media_type_internal_serdes;
355 break; 369 break;
356 default: 370 default:
@@ -523,6 +537,8 @@ e1000_reset_hw(struct e1000_hw *hw)
523 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 537 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
524 E1000_WRITE_FLUSH(hw); 538 E1000_WRITE_FLUSH(hw);
525 /* fall through */ 539 /* fall through */
540 case e1000_82571:
541 case e1000_82572:
526 ret_val = e1000_get_auto_rd_done(hw); 542 ret_val = e1000_get_auto_rd_done(hw);
527 if(ret_val) 543 if(ret_val)
528 /* We don't want to continue accessing MAC registers. */ 544 /* We don't want to continue accessing MAC registers. */
@@ -683,6 +699,9 @@ e1000_init_hw(struct e1000_hw *hw)
683 switch (hw->mac_type) { 699 switch (hw->mac_type) {
684 default: 700 default:
685 break; 701 break;
702 case e1000_82571:
703 case e1000_82572:
704 ctrl |= (1 << 22);
686 case e1000_82573: 705 case e1000_82573:
687 ctrl |= E1000_TXDCTL_COUNT_DESC; 706 ctrl |= E1000_TXDCTL_COUNT_DESC;
688 break; 707 break;
@@ -694,6 +713,25 @@ e1000_init_hw(struct e1000_hw *hw)
694 e1000_enable_tx_pkt_filtering(hw); 713 e1000_enable_tx_pkt_filtering(hw);
695 } 714 }
696 715
716 switch (hw->mac_type) {
717 default:
718 break;
719 case e1000_82571:
720 ctrl = E1000_READ_REG(hw, TXDCTL1);
721 ctrl &= ~E1000_TXDCTL_WTHRESH;
722 ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB;
723 ctrl |= (1 << 22);
724 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
725 break;
726 }
727
728
729
730 if (hw->mac_type == e1000_82573) {
731 uint32_t gcr = E1000_READ_REG(hw, GCR);
732 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
733 E1000_WRITE_REG(hw, GCR, gcr);
734 }
697 735
698 /* Clear all of the statistics registers (clear on read). It is 736 /* Clear all of the statistics registers (clear on read). It is
699 * important that we do this after we have tried to establish link 737 * important that we do this after we have tried to establish link
@@ -878,6 +916,14 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
878 916
879 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 917 DEBUGFUNC("e1000_setup_fiber_serdes_link");
880 918
919 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
920 * until explicitly turned off or a power cycle is performed. A read to
921 * the register does not indicate its status. Therefore, we ensure
922 * loopback mode is disabled during initialization.
923 */
924 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
925 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
926
881 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 927 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
882 * set when the optics detect a signal. On older adapters, it will be 928 * set when the optics detect a signal. On older adapters, it will be
883 * cleared when there is a signal. This applies to fiber media only. 929 * cleared when there is a signal. This applies to fiber media only.
@@ -2943,6 +2989,8 @@ e1000_phy_reset(struct e1000_hw *hw)
2943 2989
2944 switch (hw->mac_type) { 2990 switch (hw->mac_type) {
2945 case e1000_82541_rev_2: 2991 case e1000_82541_rev_2:
2992 case e1000_82571:
2993 case e1000_82572:
2946 ret_val = e1000_phy_hw_reset(hw); 2994 ret_val = e1000_phy_hw_reset(hw);
2947 if(ret_val) 2995 if(ret_val)
2948 return ret_val; 2996 return ret_val;
@@ -2981,6 +3029,16 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
2981 3029
2982 DEBUGFUNC("e1000_detect_gig_phy"); 3030 DEBUGFUNC("e1000_detect_gig_phy");
2983 3031
3032 /* The 82571 firmware may still be configuring the PHY. In this
3033 * case, we cannot access the PHY until the configuration is done. So
3034 * we explicitly set the PHY values. */
3035 if(hw->mac_type == e1000_82571 ||
3036 hw->mac_type == e1000_82572) {
3037 hw->phy_id = IGP01E1000_I_PHY_ID;
3038 hw->phy_type = e1000_phy_igp_2;
3039 return E1000_SUCCESS;
3040 }
3041
2984 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3042 /* Read the PHY ID Registers to identify which PHY is onboard. */
2985 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3043 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2986 if(ret_val) 3044 if(ret_val)
@@ -3334,6 +3392,21 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3334 eeprom->use_eerd = FALSE; 3392 eeprom->use_eerd = FALSE;
3335 eeprom->use_eewr = FALSE; 3393 eeprom->use_eewr = FALSE;
3336 break; 3394 break;
3395 case e1000_82571:
3396 case e1000_82572:
3397 eeprom->type = e1000_eeprom_spi;
3398 eeprom->opcode_bits = 8;
3399 eeprom->delay_usec = 1;
3400 if (eecd & E1000_EECD_ADDR_BITS) {
3401 eeprom->page_size = 32;
3402 eeprom->address_bits = 16;
3403 } else {
3404 eeprom->page_size = 8;
3405 eeprom->address_bits = 8;
3406 }
3407 eeprom->use_eerd = FALSE;
3408 eeprom->use_eewr = FALSE;
3409 break;
3337 case e1000_82573: 3410 case e1000_82573:
3338 eeprom->type = e1000_eeprom_spi; 3411 eeprom->type = e1000_eeprom_spi;
3339 eeprom->opcode_bits = 8; 3412 eeprom->opcode_bits = 8;
@@ -3543,25 +3616,26 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3543 eecd = E1000_READ_REG(hw, EECD); 3616 eecd = E1000_READ_REG(hw, EECD);
3544 3617
3545 if (hw->mac_type != e1000_82573) { 3618 if (hw->mac_type != e1000_82573) {
3546 /* Request EEPROM Access */ 3619 /* Request EEPROM Access */
3547 if(hw->mac_type > e1000_82544) { 3620 if(hw->mac_type > e1000_82544) {
3548 eecd |= E1000_EECD_REQ; 3621 eecd |= E1000_EECD_REQ;
3549 E1000_WRITE_REG(hw, EECD, eecd);
3550 eecd = E1000_READ_REG(hw, EECD);
3551 while((!(eecd & E1000_EECD_GNT)) &&
3552 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3553 i++;
3554 udelay(5);
3555 eecd = E1000_READ_REG(hw, EECD);
3556 }
3557 if(!(eecd & E1000_EECD_GNT)) {
3558 eecd &= ~E1000_EECD_REQ;
3559 E1000_WRITE_REG(hw, EECD, eecd); 3622 E1000_WRITE_REG(hw, EECD, eecd);
3560 DEBUGOUT("Could not acquire EEPROM grant\n"); 3623 eecd = E1000_READ_REG(hw, EECD);
3561 return -E1000_ERR_EEPROM; 3624 while((!(eecd & E1000_EECD_GNT)) &&
3625 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3626 i++;
3627 udelay(5);
3628 eecd = E1000_READ_REG(hw, EECD);
3629 }
3630 if(!(eecd & E1000_EECD_GNT)) {
3631 eecd &= ~E1000_EECD_REQ;
3632 E1000_WRITE_REG(hw, EECD, eecd);
3633 DEBUGOUT("Could not acquire EEPROM grant\n");
3634 e1000_put_hw_eeprom_semaphore(hw);
3635 return -E1000_ERR_EEPROM;
3636 }
3562 } 3637 }
3563 } 3638 }
3564 }
3565 3639
3566 /* Setup EEPROM for Read/Write */ 3640 /* Setup EEPROM for Read/Write */
3567 3641
@@ -4064,7 +4138,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
4064 return -E1000_ERR_EEPROM; 4138 return -E1000_ERR_EEPROM;
4065 } 4139 }
4066 4140
4067 /* 82573 reads only through eerd */ 4141 /* 82573 writes only through eewr */
4068 if(eeprom->use_eewr == TRUE) 4142 if(eeprom->use_eewr == TRUE)
4069 return e1000_write_eeprom_eewr(hw, offset, words, data); 4143 return e1000_write_eeprom_eewr(hw, offset, words, data);
4070 4144
@@ -4353,9 +4427,16 @@ e1000_read_mac_addr(struct e1000_hw * hw)
4353 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 4427 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
4354 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); 4428 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
4355 } 4429 }
4356 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) && 4430 switch (hw->mac_type) {
4357 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) 4431 default:
4432 break;
4433 case e1000_82546:
4434 case e1000_82546_rev_3:
4435 case e1000_82571:
4436 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4358 hw->perm_mac_addr[5] ^= 0x01; 4437 hw->perm_mac_addr[5] ^= 0x01;
4438 break;
4439 }
4359 4440
4360 for(i = 0; i < NODE_ADDRESS_SIZE; i++) 4441 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
4361 hw->mac_addr[i] = hw->perm_mac_addr[i]; 4442 hw->mac_addr[i] = hw->perm_mac_addr[i];
@@ -4385,6 +4466,12 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
4385 e1000_rar_set(hw, hw->mac_addr, 0); 4466 e1000_rar_set(hw, hw->mac_addr, 0);
4386 4467
4387 rar_num = E1000_RAR_ENTRIES; 4468 rar_num = E1000_RAR_ENTRIES;
4469
4470 /* Reserve a spot for the Locally Administered Address to work around
4471 * an 82571 issue in which a reset on one port will reload the MAC on
4472 * the other port. */
4473 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
4474 rar_num -= 1;
4388 /* Zero out the other 15 receive addresses. */ 4475 /* Zero out the other 15 receive addresses. */
4389 DEBUGOUT("Clearing RAR[1-15]\n"); 4476 DEBUGOUT("Clearing RAR[1-15]\n");
4390 for(i = 1; i < rar_num; i++) { 4477 for(i = 1; i < rar_num; i++) {
@@ -4427,6 +4514,12 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
4427 /* Clear RAR[1-15] */ 4514 /* Clear RAR[1-15] */
4428 DEBUGOUT(" Clearing RAR[1-15]\n"); 4515 DEBUGOUT(" Clearing RAR[1-15]\n");
4429 num_rar_entry = E1000_RAR_ENTRIES; 4516 num_rar_entry = E1000_RAR_ENTRIES;
4517 /* Reserve a spot for the Locally Administered Address to work around
4518 * an 82571 issue in which a reset on one port will reload the MAC on
4519 * the other port. */
4520 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
4521 num_rar_entry -= 1;
4522
4430 for(i = rar_used_count; i < num_rar_entry; i++) { 4523 for(i = rar_used_count; i < num_rar_entry; i++) {
4431 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4524 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4432 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4525 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -4984,7 +5077,6 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
4984 temp = E1000_READ_REG(hw, ICTXQEC); 5077 temp = E1000_READ_REG(hw, ICTXQEC);
4985 temp = E1000_READ_REG(hw, ICTXQMTC); 5078 temp = E1000_READ_REG(hw, ICTXQMTC);
4986 temp = E1000_READ_REG(hw, ICRXDMTC); 5079 temp = E1000_READ_REG(hw, ICRXDMTC);
4987
4988} 5080}
4989 5081
4990/****************************************************************************** 5082/******************************************************************************
@@ -5151,6 +5243,8 @@ e1000_get_bus_info(struct e1000_hw *hw)
5151 hw->bus_speed = e1000_bus_speed_unknown; 5243 hw->bus_speed = e1000_bus_speed_unknown;
5152 hw->bus_width = e1000_bus_width_unknown; 5244 hw->bus_width = e1000_bus_width_unknown;
5153 break; 5245 break;
5246 case e1000_82571:
5247 case e1000_82572:
5154 case e1000_82573: 5248 case e1000_82573:
5155 hw->bus_type = e1000_bus_type_pci_express; 5249 hw->bus_type = e1000_bus_type_pci_express;
5156 hw->bus_speed = e1000_bus_speed_2500; 5250 hw->bus_speed = e1000_bus_speed_2500;
@@ -5250,6 +5344,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
5250 int32_t ret_val; 5344 int32_t ret_val;
5251 uint16_t agc_value = 0; 5345 uint16_t agc_value = 0;
5252 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 5346 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5347 uint16_t max_agc = 0;
5253 uint16_t i, phy_data; 5348 uint16_t i, phy_data;
5254 uint16_t cable_length; 5349 uint16_t cable_length;
5255 5350
@@ -5338,6 +5433,40 @@ e1000_get_cable_length(struct e1000_hw *hw,
5338 IGP01E1000_AGC_RANGE) : 0; 5433 IGP01E1000_AGC_RANGE) : 0;
5339 *max_length = e1000_igp_cable_length_table[agc_value] + 5434 *max_length = e1000_igp_cable_length_table[agc_value] +
5340 IGP01E1000_AGC_RANGE; 5435 IGP01E1000_AGC_RANGE;
5436 } else if (hw->phy_type == e1000_phy_igp_2) {
5437 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
5438 {IGP02E1000_PHY_AGC_A,
5439 IGP02E1000_PHY_AGC_B,
5440 IGP02E1000_PHY_AGC_C,
5441 IGP02E1000_PHY_AGC_D};
5442 /* Read the AGC registers for all channels */
5443 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
5444 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5445 if (ret_val)
5446 return ret_val;
5447
5448 /* Getting bits 15:9, which represent the combination of course and
5449 * fine gain values. The result is a number that can be put into
5450 * the lookup table to obtain the approximate cable length. */
5451 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
5452 IGP02E1000_AGC_LENGTH_MASK;
5453
5454 /* Remove min & max AGC values from calculation. */
5455 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc])
5456 min_agc = cur_agc;
5457 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc])
5458 max_agc = cur_agc;
5459
5460 agc_value += e1000_igp_2_cable_length_table[cur_agc];
5461 }
5462
5463 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]);
5464 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
5465
5466 /* Calculate cable length with the error range of +/- 10 meters. */
5467 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
5468 (agc_value - IGP02E1000_AGC_RANGE) : 0;
5469 *max_length = agc_value + IGP02E1000_AGC_RANGE;
5341 } 5470 }
5342 5471
5343 return E1000_SUCCESS; 5472 return E1000_SUCCESS;
@@ -6465,6 +6594,8 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
6465 default: 6594 default:
6466 msec_delay(5); 6595 msec_delay(5);
6467 break; 6596 break;
6597 case e1000_82571:
6598 case e1000_82572:
6468 case e1000_82573: 6599 case e1000_82573:
6469 while(timeout) { 6600 while(timeout) {
6470 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; 6601 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
@@ -6494,10 +6625,31 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
6494int32_t 6625int32_t
6495e1000_get_phy_cfg_done(struct e1000_hw *hw) 6626e1000_get_phy_cfg_done(struct e1000_hw *hw)
6496{ 6627{
6628 int32_t timeout = PHY_CFG_TIMEOUT;
6629 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
6630
6497 DEBUGFUNC("e1000_get_phy_cfg_done"); 6631 DEBUGFUNC("e1000_get_phy_cfg_done");
6498 6632
6499 /* Simply wait for 10ms */ 6633 switch (hw->mac_type) {
6500 msec_delay(10); 6634 default:
6635 msec_delay(10);
6636 break;
6637 case e1000_82571:
6638 case e1000_82572:
6639 while (timeout) {
6640 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
6641 break;
6642 else
6643 msec_delay(1);
6644 timeout--;
6645 }
6646
6647 if (!timeout) {
6648 DEBUGOUT("MNG configuration cycle has not completed.\n");
6649 return -E1000_ERR_RESET;
6650 }
6651 break;
6652 }
6501 6653
6502 return E1000_SUCCESS; 6654 return E1000_SUCCESS;
6503} 6655}
@@ -6569,8 +6721,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
6569 return; 6721 return;
6570 6722
6571 swsm = E1000_READ_REG(hw, SWSM); 6723 swsm = E1000_READ_REG(hw, SWSM);
6572 /* Release both semaphores. */ 6724 swsm &= ~(E1000_SWSM_SWESMBI);
6573 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
6574 E1000_WRITE_REG(hw, SWSM, swsm); 6725 E1000_WRITE_REG(hw, SWSM, swsm);
6575} 6726}
6576 6727
@@ -6606,6 +6757,8 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
6606 * if this is the case. We read FWSM to determine the manageability mode. 6757 * if this is the case. We read FWSM to determine the manageability mode.
6607 */ 6758 */
6608 switch (hw->mac_type) { 6759 switch (hw->mac_type) {
6760 case e1000_82571:
6761 case e1000_82572:
6609 case e1000_82573: 6762 case e1000_82573:
6610 fwsm = E1000_READ_REG(hw, FWSM); 6763 fwsm = E1000_READ_REG(hw, FWSM);
6611 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 6764 if((fwsm & E1000_FWSM_MODE_MASK) != 0)