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path: root/drivers/net/e1000/e1000_hw.c
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-rw-r--r--drivers/net/e1000/e1000_hw.c1324
1 files changed, 662 insertions, 662 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index b64203458e9a..9a4b6cbddf2c 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -33,107 +33,107 @@
33 33
34#include "e1000_hw.h" 34#include "e1000_hw.h"
35 35
36static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); 36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); 37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
38static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); 38static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
39static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 39static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
40static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); 40static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw); 41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42 42
43static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); 43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static int32_t e1000_check_downshift(struct e1000_hw *hw); 44static s32 e1000_check_downshift(struct e1000_hw *hw);
45static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); 45static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 46static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47static void e1000_clear_vfta(struct e1000_hw *hw); 47static void e1000_clear_vfta(struct e1000_hw *hw);
48static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); 48static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
49static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, 49static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
50 bool link_up); 50 bool link_up);
51static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); 51static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
52static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); 52static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
53static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); 53static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
54static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); 54static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
55static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); 55static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, u16 *max_length);
56static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); 56static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
57static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); 57static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
58static int32_t e1000_get_software_flag(struct e1000_hw *hw); 58static s32 e1000_get_software_flag(struct e1000_hw *hw);
59static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); 59static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
60static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); 60static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
61static int32_t e1000_id_led_init(struct e1000_hw *hw); 61static s32 e1000_id_led_init(struct e1000_hw *hw);
62static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); 62static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, u32 cnf_base_addr, u32 cnf_size);
63static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); 63static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
64static void e1000_init_rx_addrs(struct e1000_hw *hw); 64static void e1000_init_rx_addrs(struct e1000_hw *hw);
65static void e1000_initialize_hardware_bits(struct e1000_hw *hw); 65static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
66static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); 66static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
67static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); 67static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
68static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); 68static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
69static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); 69static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum);
70static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); 70static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
71static int32_t e1000_mng_write_commit(struct e1000_hw *hw); 71static s32 e1000_mng_write_commit(struct e1000_hw *hw);
72static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 72static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 73static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
74static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 74static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
75static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 75static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
76static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); 76static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
77static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 77static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
78static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 78static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
79static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); 79static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
80static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); 80static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
81static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); 81static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
82static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); 82static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
83static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); 83static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 *data);
84static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); 84static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 data);
85static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 85static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
86static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 86static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
87static void e1000_release_software_flag(struct e1000_hw *hw); 87static void e1000_release_software_flag(struct e1000_hw *hw);
88static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 88static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
89static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); 89static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
90static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); 90static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
91static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); 91static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
92static int32_t e1000_wait_autoneg(struct e1000_hw *hw); 92static s32 e1000_wait_autoneg(struct e1000_hw *hw);
93static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); 93static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
94static int32_t e1000_set_phy_type(struct e1000_hw *hw); 94static s32 e1000_set_phy_type(struct e1000_hw *hw);
95static void e1000_phy_init_script(struct e1000_hw *hw); 95static void e1000_phy_init_script(struct e1000_hw *hw);
96static int32_t e1000_setup_copper_link(struct e1000_hw *hw); 96static s32 e1000_setup_copper_link(struct e1000_hw *hw);
97static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 97static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
98static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 98static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
99static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); 99static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
100static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); 100static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
101static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); 101static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
102static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); 102static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
103static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, 103static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
104 uint16_t count); 104 u16 count);
105static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); 105static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
106static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); 106static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
107static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, 107static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
108 uint16_t words, uint16_t *data); 108 u16 words, u16 *data);
109static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, 109static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw,
110 uint16_t offset, uint16_t words, 110 u16 offset, u16 words,
111 uint16_t *data); 111 u16 *data);
112static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); 112static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
113static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 113static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
114static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 114static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
115static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, 115static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data,
116 uint16_t count); 116 u16 count);
117static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 117static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
118 uint16_t phy_data); 118 u16 phy_data);
119static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, 119static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
120 uint16_t *phy_data); 120 u16 *phy_data);
121static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); 121static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
122static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 122static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
123static void e1000_release_eeprom(struct e1000_hw *hw); 123static void e1000_release_eeprom(struct e1000_hw *hw);
124static void e1000_standby_eeprom(struct e1000_hw *hw); 124static void e1000_standby_eeprom(struct e1000_hw *hw);
125static int32_t e1000_set_vco_speed(struct e1000_hw *hw); 125static s32 e1000_set_vco_speed(struct e1000_hw *hw);
126static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); 126static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
127static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 127static s32 e1000_set_phy_mode(struct e1000_hw *hw);
128static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); 128static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
129static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); 129static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
130static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, 130static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
131 uint16_t duplex); 131 u16 duplex);
132static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 132static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
133 133
134/* IGP cable length table */ 134/* IGP cable length table */
135static const 135static const
136uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 136u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
137 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 137 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
138 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 138 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
139 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 139 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
@@ -144,7 +144,7 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
144 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 144 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
145 145
146static const 146static const
147uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 147u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
148 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 148 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
149 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 149 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
150 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 150 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
@@ -159,7 +159,7 @@ uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
159 * 159 *
160 * hw - Struct containing variables accessed by shared code 160 * hw - Struct containing variables accessed by shared code
161 *****************************************************************************/ 161 *****************************************************************************/
162static int32_t 162static s32
163e1000_set_phy_type(struct e1000_hw *hw) 163e1000_set_phy_type(struct e1000_hw *hw)
164{ 164{
165 DEBUGFUNC("e1000_set_phy_type"); 165 DEBUGFUNC("e1000_set_phy_type");
@@ -213,8 +213,8 @@ e1000_set_phy_type(struct e1000_hw *hw)
213static void 213static void
214e1000_phy_init_script(struct e1000_hw *hw) 214e1000_phy_init_script(struct e1000_hw *hw)
215{ 215{
216 uint32_t ret_val; 216 u32 ret_val;
217 uint16_t phy_saved_data; 217 u16 phy_saved_data;
218 218
219 DEBUGFUNC("e1000_phy_init_script"); 219 DEBUGFUNC("e1000_phy_init_script");
220 220
@@ -272,7 +272,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
272 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 272 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
273 273
274 if (hw->mac_type == e1000_82547) { 274 if (hw->mac_type == e1000_82547) {
275 uint16_t fused, fine, coarse; 275 u16 fused, fine, coarse;
276 276
277 /* Move to analog registers page */ 277 /* Move to analog registers page */
278 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 278 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
@@ -306,7 +306,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
306 * 306 *
307 * hw - Struct containing variables accessed by shared code 307 * hw - Struct containing variables accessed by shared code
308 *****************************************************************************/ 308 *****************************************************************************/
309int32_t 309s32
310e1000_set_mac_type(struct e1000_hw *hw) 310e1000_set_mac_type(struct e1000_hw *hw)
311{ 311{
312 DEBUGFUNC("e1000_set_mac_type"); 312 DEBUGFUNC("e1000_set_mac_type");
@@ -477,7 +477,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
477void 477void
478e1000_set_media_type(struct e1000_hw *hw) 478e1000_set_media_type(struct e1000_hw *hw)
479{ 479{
480 uint32_t status; 480 u32 status;
481 481
482 DEBUGFUNC("e1000_set_media_type"); 482 DEBUGFUNC("e1000_set_media_type");
483 483
@@ -528,17 +528,17 @@ e1000_set_media_type(struct e1000_hw *hw)
528 * 528 *
529 * hw - Struct containing variables accessed by shared code 529 * hw - Struct containing variables accessed by shared code
530 *****************************************************************************/ 530 *****************************************************************************/
531int32_t 531s32
532e1000_reset_hw(struct e1000_hw *hw) 532e1000_reset_hw(struct e1000_hw *hw)
533{ 533{
534 uint32_t ctrl; 534 u32 ctrl;
535 uint32_t ctrl_ext; 535 u32 ctrl_ext;
536 uint32_t icr; 536 u32 icr;
537 uint32_t manc; 537 u32 manc;
538 uint32_t led_ctrl; 538 u32 led_ctrl;
539 uint32_t timeout; 539 u32 timeout;
540 uint32_t extcnf_ctrl; 540 u32 extcnf_ctrl;
541 int32_t ret_val; 541 s32 ret_val;
542 542
543 DEBUGFUNC("e1000_reset_hw"); 543 DEBUGFUNC("e1000_reset_hw");
544 544
@@ -730,7 +730,7 @@ e1000_reset_hw(struct e1000_hw *hw)
730 } 730 }
731 731
732 if (hw->mac_type == e1000_ich8lan) { 732 if (hw->mac_type == e1000_ich8lan) {
733 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 733 u32 kab = E1000_READ_REG(hw, KABGTXD);
734 kab |= E1000_KABGTXD_BGSQLBIAS; 734 kab |= E1000_KABGTXD_BGSQLBIAS;
735 E1000_WRITE_REG(hw, KABGTXD, kab); 735 E1000_WRITE_REG(hw, KABGTXD, kab);
736 } 736 }
@@ -752,10 +752,10 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
752{ 752{
753 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { 753 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
754 /* Settings common to all PCI-express silicon */ 754 /* Settings common to all PCI-express silicon */
755 uint32_t reg_ctrl, reg_ctrl_ext; 755 u32 reg_ctrl, reg_ctrl_ext;
756 uint32_t reg_tarc0, reg_tarc1; 756 u32 reg_tarc0, reg_tarc1;
757 uint32_t reg_tctl; 757 u32 reg_tctl;
758 uint32_t reg_txdctl, reg_txdctl1; 758 u32 reg_txdctl, reg_txdctl1;
759 759
760 /* link autonegotiation/sync workarounds */ 760 /* link autonegotiation/sync workarounds */
761 reg_tarc0 = E1000_READ_REG(hw, TARC0); 761 reg_tarc0 = E1000_READ_REG(hw, TARC0);
@@ -866,15 +866,15 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
866 * configuration and flow control settings. Clears all on-chip counters. Leaves 866 * configuration and flow control settings. Clears all on-chip counters. Leaves
867 * the transmit and receive units disabled and uninitialized. 867 * the transmit and receive units disabled and uninitialized.
868 *****************************************************************************/ 868 *****************************************************************************/
869int32_t 869s32
870e1000_init_hw(struct e1000_hw *hw) 870e1000_init_hw(struct e1000_hw *hw)
871{ 871{
872 uint32_t ctrl; 872 u32 ctrl;
873 uint32_t i; 873 u32 i;
874 int32_t ret_val; 874 s32 ret_val;
875 uint32_t mta_size; 875 u32 mta_size;
876 uint32_t reg_data; 876 u32 reg_data;
877 uint32_t ctrl_ext; 877 u32 ctrl_ext;
878 878
879 DEBUGFUNC("e1000_init_hw"); 879 DEBUGFUNC("e1000_init_hw");
880 880
@@ -1020,7 +1020,7 @@ e1000_init_hw(struct e1000_hw *hw)
1020 1020
1021 1021
1022 if (hw->mac_type == e1000_82573) { 1022 if (hw->mac_type == e1000_82573) {
1023 uint32_t gcr = E1000_READ_REG(hw, GCR); 1023 u32 gcr = E1000_READ_REG(hw, GCR);
1024 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1024 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1025 E1000_WRITE_REG(hw, GCR, gcr); 1025 E1000_WRITE_REG(hw, GCR, gcr);
1026 } 1026 }
@@ -1054,11 +1054,11 @@ e1000_init_hw(struct e1000_hw *hw)
1054 * 1054 *
1055 * hw - Struct containing variables accessed by shared code. 1055 * hw - Struct containing variables accessed by shared code.
1056 *****************************************************************************/ 1056 *****************************************************************************/
1057static int32_t 1057static s32
1058e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 1058e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1059{ 1059{
1060 uint16_t eeprom_data; 1060 u16 eeprom_data;
1061 int32_t ret_val; 1061 s32 ret_val;
1062 1062
1063 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 1063 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1064 1064
@@ -1100,12 +1100,12 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1100 * established. Assumes the hardware has previously been reset and the 1100 * established. Assumes the hardware has previously been reset and the
1101 * transmitter and receiver are not enabled. 1101 * transmitter and receiver are not enabled.
1102 *****************************************************************************/ 1102 *****************************************************************************/
1103int32_t 1103s32
1104e1000_setup_link(struct e1000_hw *hw) 1104e1000_setup_link(struct e1000_hw *hw)
1105{ 1105{
1106 uint32_t ctrl_ext; 1106 u32 ctrl_ext;
1107 int32_t ret_val; 1107 s32 ret_val;
1108 uint16_t eeprom_data; 1108 u16 eeprom_data;
1109 1109
1110 DEBUGFUNC("e1000_setup_link"); 1110 DEBUGFUNC("e1000_setup_link");
1111 1111
@@ -1233,15 +1233,15 @@ e1000_setup_link(struct e1000_hw *hw)
1233 * link. Assumes the hardware has been previously reset and the transmitter 1233 * link. Assumes the hardware has been previously reset and the transmitter
1234 * and receiver are not enabled. 1234 * and receiver are not enabled.
1235 *****************************************************************************/ 1235 *****************************************************************************/
1236static int32_t 1236static s32
1237e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 1237e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1238{ 1238{
1239 uint32_t ctrl; 1239 u32 ctrl;
1240 uint32_t status; 1240 u32 status;
1241 uint32_t txcw = 0; 1241 u32 txcw = 0;
1242 uint32_t i; 1242 u32 i;
1243 uint32_t signal = 0; 1243 u32 signal = 0;
1244 int32_t ret_val; 1244 s32 ret_val;
1245 1245
1246 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 1246 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1247 1247
@@ -1380,12 +1380,12 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1380* 1380*
1381* hw - Struct containing variables accessed by shared code 1381* hw - Struct containing variables accessed by shared code
1382******************************************************************************/ 1382******************************************************************************/
1383static int32_t 1383static s32
1384e1000_copper_link_preconfig(struct e1000_hw *hw) 1384e1000_copper_link_preconfig(struct e1000_hw *hw)
1385{ 1385{
1386 uint32_t ctrl; 1386 u32 ctrl;
1387 int32_t ret_val; 1387 s32 ret_val;
1388 uint16_t phy_data; 1388 u16 phy_data;
1389 1389
1390 DEBUGFUNC("e1000_copper_link_preconfig"); 1390 DEBUGFUNC("e1000_copper_link_preconfig");
1391 1391
@@ -1440,12 +1440,12 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1440* 1440*
1441* hw - Struct containing variables accessed by shared code 1441* hw - Struct containing variables accessed by shared code
1442*********************************************************************/ 1442*********************************************************************/
1443static int32_t 1443static s32
1444e1000_copper_link_igp_setup(struct e1000_hw *hw) 1444e1000_copper_link_igp_setup(struct e1000_hw *hw)
1445{ 1445{
1446 uint32_t led_ctrl; 1446 u32 led_ctrl;
1447 int32_t ret_val; 1447 s32 ret_val;
1448 uint16_t phy_data; 1448 u16 phy_data;
1449 1449
1450 DEBUGFUNC("e1000_copper_link_igp_setup"); 1450 DEBUGFUNC("e1000_copper_link_igp_setup");
1451 1451
@@ -1587,12 +1587,12 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1587* 1587*
1588* hw - Struct containing variables accessed by shared code 1588* hw - Struct containing variables accessed by shared code
1589*********************************************************************/ 1589*********************************************************************/
1590static int32_t 1590static s32
1591e1000_copper_link_ggp_setup(struct e1000_hw *hw) 1591e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1592{ 1592{
1593 int32_t ret_val; 1593 s32 ret_val;
1594 uint16_t phy_data; 1594 u16 phy_data;
1595 uint32_t reg_data; 1595 u32 reg_data;
1596 1596
1597 DEBUGFUNC("e1000_copper_link_ggp_setup"); 1597 DEBUGFUNC("e1000_copper_link_ggp_setup");
1598 1598
@@ -1735,11 +1735,11 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1735* 1735*
1736* hw - Struct containing variables accessed by shared code 1736* hw - Struct containing variables accessed by shared code
1737*********************************************************************/ 1737*********************************************************************/
1738static int32_t 1738static s32
1739e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1739e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1740{ 1740{
1741 int32_t ret_val; 1741 s32 ret_val;
1742 uint16_t phy_data; 1742 u16 phy_data;
1743 1743
1744 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1744 DEBUGFUNC("e1000_copper_link_mgp_setup");
1745 1745
@@ -1839,11 +1839,11 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1839* 1839*
1840* hw - Struct containing variables accessed by shared code 1840* hw - Struct containing variables accessed by shared code
1841*********************************************************************/ 1841*********************************************************************/
1842static int32_t 1842static s32
1843e1000_copper_link_autoneg(struct e1000_hw *hw) 1843e1000_copper_link_autoneg(struct e1000_hw *hw)
1844{ 1844{
1845 int32_t ret_val; 1845 s32 ret_val;
1846 uint16_t phy_data; 1846 u16 phy_data;
1847 1847
1848 DEBUGFUNC("e1000_copper_link_autoneg"); 1848 DEBUGFUNC("e1000_copper_link_autoneg");
1849 1849
@@ -1910,10 +1910,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1910* 1910*
1911* hw - Struct containing variables accessed by shared code 1911* hw - Struct containing variables accessed by shared code
1912******************************************************************************/ 1912******************************************************************************/
1913static int32_t 1913static s32
1914e1000_copper_link_postconfig(struct e1000_hw *hw) 1914e1000_copper_link_postconfig(struct e1000_hw *hw)
1915{ 1915{
1916 int32_t ret_val; 1916 s32 ret_val;
1917 DEBUGFUNC("e1000_copper_link_postconfig"); 1917 DEBUGFUNC("e1000_copper_link_postconfig");
1918 1918
1919 if (hw->mac_type >= e1000_82544) { 1919 if (hw->mac_type >= e1000_82544) {
@@ -1948,13 +1948,13 @@ e1000_copper_link_postconfig(struct e1000_hw *hw)
1948* 1948*
1949* hw - Struct containing variables accessed by shared code 1949* hw - Struct containing variables accessed by shared code
1950******************************************************************************/ 1950******************************************************************************/
1951static int32_t 1951static s32
1952e1000_setup_copper_link(struct e1000_hw *hw) 1952e1000_setup_copper_link(struct e1000_hw *hw)
1953{ 1953{
1954 int32_t ret_val; 1954 s32 ret_val;
1955 uint16_t i; 1955 u16 i;
1956 uint16_t phy_data; 1956 u16 phy_data;
1957 uint16_t reg_data; 1957 u16 reg_data;
1958 1958
1959 DEBUGFUNC("e1000_setup_copper_link"); 1959 DEBUGFUNC("e1000_setup_copper_link");
1960 1960
@@ -2062,12 +2062,12 @@ e1000_setup_copper_link(struct e1000_hw *hw)
2062* 2062*
2063* hw - Struct containing variables accessed by shared code 2063* hw - Struct containing variables accessed by shared code
2064******************************************************************************/ 2064******************************************************************************/
2065static int32_t 2065static s32
2066e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) 2066e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2067{ 2067{
2068 int32_t ret_val = E1000_SUCCESS; 2068 s32 ret_val = E1000_SUCCESS;
2069 uint32_t tipg; 2069 u32 tipg;
2070 uint16_t reg_data; 2070 u16 reg_data;
2071 2071
2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2073 2073
@@ -2098,12 +2098,12 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2098 return ret_val; 2098 return ret_val;
2099} 2099}
2100 2100
2101static int32_t 2101static s32
2102e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 2102e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2103{ 2103{
2104 int32_t ret_val = E1000_SUCCESS; 2104 s32 ret_val = E1000_SUCCESS;
2105 uint16_t reg_data; 2105 u16 reg_data;
2106 uint32_t tipg; 2106 u32 tipg;
2107 2107
2108 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 2108 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2109 2109
@@ -2135,12 +2135,12 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2135* 2135*
2136* hw - Struct containing variables accessed by shared code 2136* hw - Struct containing variables accessed by shared code
2137******************************************************************************/ 2137******************************************************************************/
2138int32_t 2138s32
2139e1000_phy_setup_autoneg(struct e1000_hw *hw) 2139e1000_phy_setup_autoneg(struct e1000_hw *hw)
2140{ 2140{
2141 int32_t ret_val; 2141 s32 ret_val;
2142 uint16_t mii_autoneg_adv_reg; 2142 u16 mii_autoneg_adv_reg;
2143 uint16_t mii_1000t_ctrl_reg; 2143 u16 mii_1000t_ctrl_reg;
2144 2144
2145 DEBUGFUNC("e1000_phy_setup_autoneg"); 2145 DEBUGFUNC("e1000_phy_setup_autoneg");
2146 2146
@@ -2284,15 +2284,15 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2284* 2284*
2285* hw - Struct containing variables accessed by shared code 2285* hw - Struct containing variables accessed by shared code
2286******************************************************************************/ 2286******************************************************************************/
2287static int32_t 2287static s32
2288e1000_phy_force_speed_duplex(struct e1000_hw *hw) 2288e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2289{ 2289{
2290 uint32_t ctrl; 2290 u32 ctrl;
2291 int32_t ret_val; 2291 s32 ret_val;
2292 uint16_t mii_ctrl_reg; 2292 u16 mii_ctrl_reg;
2293 uint16_t mii_status_reg; 2293 u16 mii_status_reg;
2294 uint16_t phy_data; 2294 u16 phy_data;
2295 uint16_t i; 2295 u16 i;
2296 2296
2297 DEBUGFUNC("e1000_phy_force_speed_duplex"); 2297 DEBUGFUNC("e1000_phy_force_speed_duplex");
2298 2298
@@ -2538,7 +2538,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2538void 2538void
2539e1000_config_collision_dist(struct e1000_hw *hw) 2539e1000_config_collision_dist(struct e1000_hw *hw)
2540{ 2540{
2541 uint32_t tctl, coll_dist; 2541 u32 tctl, coll_dist;
2542 2542
2543 DEBUGFUNC("e1000_config_collision_dist"); 2543 DEBUGFUNC("e1000_config_collision_dist");
2544 2544
@@ -2565,12 +2565,12 @@ e1000_config_collision_dist(struct e1000_hw *hw)
2565* The contents of the PHY register containing the needed information need to 2565* The contents of the PHY register containing the needed information need to
2566* be passed in. 2566* be passed in.
2567******************************************************************************/ 2567******************************************************************************/
2568static int32_t 2568static s32
2569e1000_config_mac_to_phy(struct e1000_hw *hw) 2569e1000_config_mac_to_phy(struct e1000_hw *hw)
2570{ 2570{
2571 uint32_t ctrl; 2571 u32 ctrl;
2572 int32_t ret_val; 2572 s32 ret_val;
2573 uint16_t phy_data; 2573 u16 phy_data;
2574 2574
2575 DEBUGFUNC("e1000_config_mac_to_phy"); 2575 DEBUGFUNC("e1000_config_mac_to_phy");
2576 2576
@@ -2624,10 +2624,10 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2624 * by the PHY rather than the MAC. Software must also configure these 2624 * by the PHY rather than the MAC. Software must also configure these
2625 * bits when link is forced on a fiber connection. 2625 * bits when link is forced on a fiber connection.
2626 *****************************************************************************/ 2626 *****************************************************************************/
2627int32_t 2627s32
2628e1000_force_mac_fc(struct e1000_hw *hw) 2628e1000_force_mac_fc(struct e1000_hw *hw)
2629{ 2629{
2630 uint32_t ctrl; 2630 u32 ctrl;
2631 2631
2632 DEBUGFUNC("e1000_force_mac_fc"); 2632 DEBUGFUNC("e1000_force_mac_fc");
2633 2633
@@ -2691,15 +2691,15 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2691 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2691 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2692 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 2692 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2693 *****************************************************************************/ 2693 *****************************************************************************/
2694static int32_t 2694static s32
2695e1000_config_fc_after_link_up(struct e1000_hw *hw) 2695e1000_config_fc_after_link_up(struct e1000_hw *hw)
2696{ 2696{
2697 int32_t ret_val; 2697 s32 ret_val;
2698 uint16_t mii_status_reg; 2698 u16 mii_status_reg;
2699 uint16_t mii_nway_adv_reg; 2699 u16 mii_nway_adv_reg;
2700 uint16_t mii_nway_lp_ability_reg; 2700 u16 mii_nway_lp_ability_reg;
2701 uint16_t speed; 2701 u16 speed;
2702 uint16_t duplex; 2702 u16 duplex;
2703 2703
2704 DEBUGFUNC("e1000_config_fc_after_link_up"); 2704 DEBUGFUNC("e1000_config_fc_after_link_up");
2705 2705
@@ -2896,17 +2896,17 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2896 * 2896 *
2897 * Called by any function that needs to check the link status of the adapter. 2897 * Called by any function that needs to check the link status of the adapter.
2898 *****************************************************************************/ 2898 *****************************************************************************/
2899int32_t 2899s32
2900e1000_check_for_link(struct e1000_hw *hw) 2900e1000_check_for_link(struct e1000_hw *hw)
2901{ 2901{
2902 uint32_t rxcw = 0; 2902 u32 rxcw = 0;
2903 uint32_t ctrl; 2903 u32 ctrl;
2904 uint32_t status; 2904 u32 status;
2905 uint32_t rctl; 2905 u32 rctl;
2906 uint32_t icr; 2906 u32 icr;
2907 uint32_t signal = 0; 2907 u32 signal = 0;
2908 int32_t ret_val; 2908 s32 ret_val;
2909 uint16_t phy_data; 2909 u16 phy_data;
2910 2910
2911 DEBUGFUNC("e1000_check_for_link"); 2911 DEBUGFUNC("e1000_check_for_link");
2912 2912
@@ -3022,7 +3022,7 @@ e1000_check_for_link(struct e1000_hw *hw)
3022 * at gigabit speed, we turn on TBI compatibility. 3022 * at gigabit speed, we turn on TBI compatibility.
3023 */ 3023 */
3024 if (hw->tbi_compatibility_en) { 3024 if (hw->tbi_compatibility_en) {
3025 uint16_t speed, duplex; 3025 u16 speed, duplex;
3026 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 3026 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3027 if (ret_val) { 3027 if (ret_val) {
3028 DEBUGOUT("Error getting link speed and duplex\n"); 3028 DEBUGOUT("Error getting link speed and duplex\n");
@@ -3132,14 +3132,14 @@ e1000_check_for_link(struct e1000_hw *hw)
3132 * speed - Speed of the connection 3132 * speed - Speed of the connection
3133 * duplex - Duplex setting of the connection 3133 * duplex - Duplex setting of the connection
3134 *****************************************************************************/ 3134 *****************************************************************************/
3135int32_t 3135s32
3136e1000_get_speed_and_duplex(struct e1000_hw *hw, 3136e1000_get_speed_and_duplex(struct e1000_hw *hw,
3137 uint16_t *speed, 3137 u16 *speed,
3138 uint16_t *duplex) 3138 u16 *duplex)
3139{ 3139{
3140 uint32_t status; 3140 u32 status;
3141 int32_t ret_val; 3141 s32 ret_val;
3142 uint16_t phy_data; 3142 u16 phy_data;
3143 3143
3144 DEBUGFUNC("e1000_get_speed_and_duplex"); 3144 DEBUGFUNC("e1000_get_speed_and_duplex");
3145 3145
@@ -3214,12 +3214,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3214* 3214*
3215* hw - Struct containing variables accessed by shared code 3215* hw - Struct containing variables accessed by shared code
3216******************************************************************************/ 3216******************************************************************************/
3217static int32_t 3217static s32
3218e1000_wait_autoneg(struct e1000_hw *hw) 3218e1000_wait_autoneg(struct e1000_hw *hw)
3219{ 3219{
3220 int32_t ret_val; 3220 s32 ret_val;
3221 uint16_t i; 3221 u16 i;
3222 uint16_t phy_data; 3222 u16 phy_data;
3223 3223
3224 DEBUGFUNC("e1000_wait_autoneg"); 3224 DEBUGFUNC("e1000_wait_autoneg");
3225 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3225 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
@@ -3251,7 +3251,7 @@ e1000_wait_autoneg(struct e1000_hw *hw)
3251******************************************************************************/ 3251******************************************************************************/
3252static void 3252static void
3253e1000_raise_mdi_clk(struct e1000_hw *hw, 3253e1000_raise_mdi_clk(struct e1000_hw *hw,
3254 uint32_t *ctrl) 3254 u32 *ctrl)
3255{ 3255{
3256 /* Raise the clock input to the Management Data Clock (by setting the MDC 3256 /* Raise the clock input to the Management Data Clock (by setting the MDC
3257 * bit), and then delay 10 microseconds. 3257 * bit), and then delay 10 microseconds.
@@ -3269,7 +3269,7 @@ e1000_raise_mdi_clk(struct e1000_hw *hw,
3269******************************************************************************/ 3269******************************************************************************/
3270static void 3270static void
3271e1000_lower_mdi_clk(struct e1000_hw *hw, 3271e1000_lower_mdi_clk(struct e1000_hw *hw,
3272 uint32_t *ctrl) 3272 u32 *ctrl)
3273{ 3273{
3274 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3274 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3275 * bit), and then delay 10 microseconds. 3275 * bit), and then delay 10 microseconds.
@@ -3290,11 +3290,11 @@ e1000_lower_mdi_clk(struct e1000_hw *hw,
3290******************************************************************************/ 3290******************************************************************************/
3291static void 3291static void
3292e1000_shift_out_mdi_bits(struct e1000_hw *hw, 3292e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3293 uint32_t data, 3293 u32 data,
3294 uint16_t count) 3294 u16 count)
3295{ 3295{
3296 uint32_t ctrl; 3296 u32 ctrl;
3297 uint32_t mask; 3297 u32 mask;
3298 3298
3299 /* We need to shift "count" number of bits out to the PHY. So, the value 3299 /* We need to shift "count" number of bits out to the PHY. So, the value
3300 * in the "data" parameter will be shifted out to the PHY one bit at a 3300 * in the "data" parameter will be shifted out to the PHY one bit at a
@@ -3338,12 +3338,12 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3338* 3338*
3339* Bits are shifted in in MSB to LSB order. 3339* Bits are shifted in in MSB to LSB order.
3340******************************************************************************/ 3340******************************************************************************/
3341static uint16_t 3341static u16
3342e1000_shift_in_mdi_bits(struct e1000_hw *hw) 3342e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3343{ 3343{
3344 uint32_t ctrl; 3344 u32 ctrl;
3345 uint16_t data = 0; 3345 u16 data = 0;
3346 uint8_t i; 3346 u8 i;
3347 3347
3348 /* In order to read a register from the PHY, we need to shift in a total 3348 /* In order to read a register from the PHY, we need to shift in a total
3349 * of 18 bits from the PHY. The first two bit (turnaround) times are used 3349 * of 18 bits from the PHY. The first two bit (turnaround) times are used
@@ -3384,13 +3384,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3384 return data; 3384 return data;
3385} 3385}
3386 3386
3387static int32_t 3387static s32
3388e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 3388e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3389{ 3389{
3390 uint32_t swfw_sync = 0; 3390 u32 swfw_sync = 0;
3391 uint32_t swmask = mask; 3391 u32 swmask = mask;
3392 uint32_t fwmask = mask << 16; 3392 u32 fwmask = mask << 16;
3393 int32_t timeout = 200; 3393 s32 timeout = 200;
3394 3394
3395 DEBUGFUNC("e1000_swfw_sync_acquire"); 3395 DEBUGFUNC("e1000_swfw_sync_acquire");
3396 3396
@@ -3429,10 +3429,10 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3429} 3429}
3430 3430
3431static void 3431static void
3432e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 3432e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3433{ 3433{
3434 uint32_t swfw_sync; 3434 u32 swfw_sync;
3435 uint32_t swmask = mask; 3435 u32 swmask = mask;
3436 3436
3437 DEBUGFUNC("e1000_swfw_sync_release"); 3437 DEBUGFUNC("e1000_swfw_sync_release");
3438 3438
@@ -3464,13 +3464,13 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3464* hw - Struct containing variables accessed by shared code 3464* hw - Struct containing variables accessed by shared code
3465* reg_addr - address of the PHY register to read 3465* reg_addr - address of the PHY register to read
3466******************************************************************************/ 3466******************************************************************************/
3467int32_t 3467s32
3468e1000_read_phy_reg(struct e1000_hw *hw, 3468e1000_read_phy_reg(struct e1000_hw *hw,
3469 uint32_t reg_addr, 3469 u32 reg_addr,
3470 uint16_t *phy_data) 3470 u16 *phy_data)
3471{ 3471{
3472 uint32_t ret_val; 3472 u32 ret_val;
3473 uint16_t swfw; 3473 u16 swfw;
3474 3474
3475 DEBUGFUNC("e1000_read_phy_reg"); 3475 DEBUGFUNC("e1000_read_phy_reg");
3476 3476
@@ -3488,7 +3488,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3488 hw->phy_type == e1000_phy_igp_2) && 3488 hw->phy_type == e1000_phy_igp_2) &&
3489 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3489 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3490 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3490 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3491 (uint16_t)reg_addr); 3491 (u16)reg_addr);
3492 if (ret_val) { 3492 if (ret_val) {
3493 e1000_swfw_sync_release(hw, swfw); 3493 e1000_swfw_sync_release(hw, swfw);
3494 return ret_val; 3494 return ret_val;
@@ -3499,14 +3499,14 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3499 /* Select Configuration Page */ 3499 /* Select Configuration Page */
3500 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3500 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3501 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3501 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3502 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3502 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3503 } else { 3503 } else {
3504 /* Use Alternative Page Select register to access 3504 /* Use Alternative Page Select register to access
3505 * registers 30 and 31 3505 * registers 30 and 31
3506 */ 3506 */
3507 ret_val = e1000_write_phy_reg_ex(hw, 3507 ret_val = e1000_write_phy_reg_ex(hw,
3508 GG82563_PHY_PAGE_SELECT_ALT, 3508 GG82563_PHY_PAGE_SELECT_ALT,
3509 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3509 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3510 } 3510 }
3511 3511
3512 if (ret_val) { 3512 if (ret_val) {
@@ -3523,13 +3523,13 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3523 return ret_val; 3523 return ret_val;
3524} 3524}
3525 3525
3526static int32_t 3526static s32
3527e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 3527e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3528 uint16_t *phy_data) 3528 u16 *phy_data)
3529{ 3529{
3530 uint32_t i; 3530 u32 i;
3531 uint32_t mdic = 0; 3531 u32 mdic = 0;
3532 const uint32_t phy_addr = 1; 3532 const u32 phy_addr = 1;
3533 3533
3534 DEBUGFUNC("e1000_read_phy_reg_ex"); 3534 DEBUGFUNC("e1000_read_phy_reg_ex");
3535 3535
@@ -3563,7 +3563,7 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3563 DEBUGOUT("MDI Error\n"); 3563 DEBUGOUT("MDI Error\n");
3564 return -E1000_ERR_PHY; 3564 return -E1000_ERR_PHY;
3565 } 3565 }
3566 *phy_data = (uint16_t) mdic; 3566 *phy_data = (u16) mdic;
3567 } else { 3567 } else {
3568 /* We must first send a preamble through the MDIO pin to signal the 3568 /* We must first send a preamble through the MDIO pin to signal the
3569 * beginning of an MII instruction. This is done by sending 32 3569 * beginning of an MII instruction. This is done by sending 32
@@ -3603,12 +3603,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3603* reg_addr - address of the PHY register to write 3603* reg_addr - address of the PHY register to write
3604* data - data to write to the PHY 3604* data - data to write to the PHY
3605******************************************************************************/ 3605******************************************************************************/
3606int32_t 3606s32
3607e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, 3607e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr,
3608 uint16_t phy_data) 3608 u16 phy_data)
3609{ 3609{
3610 uint32_t ret_val; 3610 u32 ret_val;
3611 uint16_t swfw; 3611 u16 swfw;
3612 3612
3613 DEBUGFUNC("e1000_write_phy_reg"); 3613 DEBUGFUNC("e1000_write_phy_reg");
3614 3614
@@ -3626,7 +3626,7 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3626 hw->phy_type == e1000_phy_igp_2) && 3626 hw->phy_type == e1000_phy_igp_2) &&
3627 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3627 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3628 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3628 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3629 (uint16_t)reg_addr); 3629 (u16)reg_addr);
3630 if (ret_val) { 3630 if (ret_val) {
3631 e1000_swfw_sync_release(hw, swfw); 3631 e1000_swfw_sync_release(hw, swfw);
3632 return ret_val; 3632 return ret_val;
@@ -3637,14 +3637,14 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3637 /* Select Configuration Page */ 3637 /* Select Configuration Page */
3638 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3638 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3639 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3639 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3640 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3640 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3641 } else { 3641 } else {
3642 /* Use Alternative Page Select register to access 3642 /* Use Alternative Page Select register to access
3643 * registers 30 and 31 3643 * registers 30 and 31
3644 */ 3644 */
3645 ret_val = e1000_write_phy_reg_ex(hw, 3645 ret_val = e1000_write_phy_reg_ex(hw,
3646 GG82563_PHY_PAGE_SELECT_ALT, 3646 GG82563_PHY_PAGE_SELECT_ALT,
3647 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3647 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3648 } 3648 }
3649 3649
3650 if (ret_val) { 3650 if (ret_val) {
@@ -3661,13 +3661,13 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3661 return ret_val; 3661 return ret_val;
3662} 3662}
3663 3663
3664static int32_t 3664static s32
3665e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, 3665e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3666 uint16_t phy_data) 3666 u16 phy_data)
3667{ 3667{
3668 uint32_t i; 3668 u32 i;
3669 uint32_t mdic = 0; 3669 u32 mdic = 0;
3670 const uint32_t phy_addr = 1; 3670 const u32 phy_addr = 1;
3671 3671
3672 DEBUGFUNC("e1000_write_phy_reg_ex"); 3672 DEBUGFUNC("e1000_write_phy_reg_ex");
3673 3673
@@ -3681,7 +3681,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3681 * for the PHY register in the MDI Control register. The MAC will take 3681 * for the PHY register in the MDI Control register. The MAC will take
3682 * care of interfacing with the PHY to send the desired data. 3682 * care of interfacing with the PHY to send the desired data.
3683 */ 3683 */
3684 mdic = (((uint32_t) phy_data) | 3684 mdic = (((u32) phy_data) |
3685 (reg_addr << E1000_MDIC_REG_SHIFT) | 3685 (reg_addr << E1000_MDIC_REG_SHIFT) |
3686 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3686 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3687 (E1000_MDIC_OP_WRITE)); 3687 (E1000_MDIC_OP_WRITE));
@@ -3715,7 +3715,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3715 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3715 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3716 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3716 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3717 mdic <<= 16; 3717 mdic <<= 16;
3718 mdic |= (uint32_t) phy_data; 3718 mdic |= (u32) phy_data;
3719 3719
3720 e1000_shift_out_mdi_bits(hw, mdic, 32); 3720 e1000_shift_out_mdi_bits(hw, mdic, 32);
3721 } 3721 }
@@ -3723,13 +3723,13 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3723 return E1000_SUCCESS; 3723 return E1000_SUCCESS;
3724} 3724}
3725 3725
3726static int32_t 3726static s32
3727e1000_read_kmrn_reg(struct e1000_hw *hw, 3727e1000_read_kmrn_reg(struct e1000_hw *hw,
3728 uint32_t reg_addr, 3728 u32 reg_addr,
3729 uint16_t *data) 3729 u16 *data)
3730{ 3730{
3731 uint32_t reg_val; 3731 u32 reg_val;
3732 uint16_t swfw; 3732 u16 swfw;
3733 DEBUGFUNC("e1000_read_kmrn_reg"); 3733 DEBUGFUNC("e1000_read_kmrn_reg");
3734 3734
3735 if ((hw->mac_type == e1000_80003es2lan) && 3735 if ((hw->mac_type == e1000_80003es2lan) &&
@@ -3750,19 +3750,19 @@ e1000_read_kmrn_reg(struct e1000_hw *hw,
3750 3750
3751 /* Read the data returned */ 3751 /* Read the data returned */
3752 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 3752 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3753 *data = (uint16_t)reg_val; 3753 *data = (u16)reg_val;
3754 3754
3755 e1000_swfw_sync_release(hw, swfw); 3755 e1000_swfw_sync_release(hw, swfw);
3756 return E1000_SUCCESS; 3756 return E1000_SUCCESS;
3757} 3757}
3758 3758
3759static int32_t 3759static s32
3760e1000_write_kmrn_reg(struct e1000_hw *hw, 3760e1000_write_kmrn_reg(struct e1000_hw *hw,
3761 uint32_t reg_addr, 3761 u32 reg_addr,
3762 uint16_t data) 3762 u16 data)
3763{ 3763{
3764 uint32_t reg_val; 3764 u32 reg_val;
3765 uint16_t swfw; 3765 u16 swfw;
3766 DEBUGFUNC("e1000_write_kmrn_reg"); 3766 DEBUGFUNC("e1000_write_kmrn_reg");
3767 3767
3768 if ((hw->mac_type == e1000_80003es2lan) && 3768 if ((hw->mac_type == e1000_80003es2lan) &&
@@ -3788,13 +3788,13 @@ e1000_write_kmrn_reg(struct e1000_hw *hw,
3788* 3788*
3789* hw - Struct containing variables accessed by shared code 3789* hw - Struct containing variables accessed by shared code
3790******************************************************************************/ 3790******************************************************************************/
3791int32_t 3791s32
3792e1000_phy_hw_reset(struct e1000_hw *hw) 3792e1000_phy_hw_reset(struct e1000_hw *hw)
3793{ 3793{
3794 uint32_t ctrl, ctrl_ext; 3794 u32 ctrl, ctrl_ext;
3795 uint32_t led_ctrl; 3795 u32 led_ctrl;
3796 int32_t ret_val; 3796 s32 ret_val;
3797 uint16_t swfw; 3797 u16 swfw;
3798 3798
3799 DEBUGFUNC("e1000_phy_hw_reset"); 3799 DEBUGFUNC("e1000_phy_hw_reset");
3800 3800
@@ -3882,11 +3882,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3882* 3882*
3883* Sets bit 15 of the MII Control register 3883* Sets bit 15 of the MII Control register
3884******************************************************************************/ 3884******************************************************************************/
3885int32_t 3885s32
3886e1000_phy_reset(struct e1000_hw *hw) 3886e1000_phy_reset(struct e1000_hw *hw)
3887{ 3887{
3888 int32_t ret_val; 3888 s32 ret_val;
3889 uint16_t phy_data; 3889 u16 phy_data;
3890 3890
3891 DEBUGFUNC("e1000_phy_reset"); 3891 DEBUGFUNC("e1000_phy_reset");
3892 3892
@@ -3937,9 +3937,9 @@ e1000_phy_reset(struct e1000_hw *hw)
3937void 3937void
3938e1000_phy_powerdown_workaround(struct e1000_hw *hw) 3938e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3939{ 3939{
3940 int32_t reg; 3940 s32 reg;
3941 uint16_t phy_data; 3941 u16 phy_data;
3942 int32_t retry = 0; 3942 s32 retry = 0;
3943 3943
3944 DEBUGFUNC("e1000_phy_powerdown_workaround"); 3944 DEBUGFUNC("e1000_phy_powerdown_workaround");
3945 3945
@@ -3987,13 +3987,13 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3987* 3987*
3988* hw - struct containing variables accessed by shared code 3988* hw - struct containing variables accessed by shared code
3989******************************************************************************/ 3989******************************************************************************/
3990static int32_t 3990static s32
3991e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) 3991e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3992{ 3992{
3993 int32_t ret_val; 3993 s32 ret_val;
3994 int32_t reg; 3994 s32 reg;
3995 int32_t cnt; 3995 s32 cnt;
3996 uint16_t phy_data; 3996 u16 phy_data;
3997 3997
3998 if (hw->kmrn_lock_loss_workaround_disabled) 3998 if (hw->kmrn_lock_loss_workaround_disabled)
3999 return E1000_SUCCESS; 3999 return E1000_SUCCESS;
@@ -4040,11 +4040,11 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4040* 4040*
4041* hw - Struct containing variables accessed by shared code 4041* hw - Struct containing variables accessed by shared code
4042******************************************************************************/ 4042******************************************************************************/
4043static int32_t 4043static s32
4044e1000_detect_gig_phy(struct e1000_hw *hw) 4044e1000_detect_gig_phy(struct e1000_hw *hw)
4045{ 4045{
4046 int32_t phy_init_status, ret_val; 4046 s32 phy_init_status, ret_val;
4047 uint16_t phy_id_high, phy_id_low; 4047 u16 phy_id_high, phy_id_low;
4048 bool match = false; 4048 bool match = false;
4049 4049
4050 DEBUGFUNC("e1000_detect_gig_phy"); 4050 DEBUGFUNC("e1000_detect_gig_phy");
@@ -4076,14 +4076,14 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
4076 if (ret_val) 4076 if (ret_val)
4077 return ret_val; 4077 return ret_val;
4078 4078
4079 hw->phy_id = (uint32_t) (phy_id_high << 16); 4079 hw->phy_id = (u32) (phy_id_high << 16);
4080 udelay(20); 4080 udelay(20);
4081 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4081 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4082 if (ret_val) 4082 if (ret_val)
4083 return ret_val; 4083 return ret_val;
4084 4084
4085 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4085 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
4086 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4086 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
4087 4087
4088 switch (hw->mac_type) { 4088 switch (hw->mac_type) {
4089 case e1000_82543: 4089 case e1000_82543:
@@ -4136,10 +4136,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
4136* 4136*
4137* hw - Struct containing variables accessed by shared code 4137* hw - Struct containing variables accessed by shared code
4138******************************************************************************/ 4138******************************************************************************/
4139static int32_t 4139static s32
4140e1000_phy_reset_dsp(struct e1000_hw *hw) 4140e1000_phy_reset_dsp(struct e1000_hw *hw)
4141{ 4141{
4142 int32_t ret_val; 4142 s32 ret_val;
4143 DEBUGFUNC("e1000_phy_reset_dsp"); 4143 DEBUGFUNC("e1000_phy_reset_dsp");
4144 4144
4145 do { 4145 do {
@@ -4163,12 +4163,12 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
4163* hw - Struct containing variables accessed by shared code 4163* hw - Struct containing variables accessed by shared code
4164* phy_info - PHY information structure 4164* phy_info - PHY information structure
4165******************************************************************************/ 4165******************************************************************************/
4166static int32_t 4166static s32
4167e1000_phy_igp_get_info(struct e1000_hw *hw, 4167e1000_phy_igp_get_info(struct e1000_hw *hw,
4168 struct e1000_phy_info *phy_info) 4168 struct e1000_phy_info *phy_info)
4169{ 4169{
4170 int32_t ret_val; 4170 s32 ret_val;
4171 uint16_t phy_data, min_length, max_length, average; 4171 u16 phy_data, min_length, max_length, average;
4172 e1000_rev_polarity polarity; 4172 e1000_rev_polarity polarity;
4173 4173
4174 DEBUGFUNC("e1000_phy_igp_get_info"); 4174 DEBUGFUNC("e1000_phy_igp_get_info");
@@ -4240,12 +4240,12 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4240* hw - Struct containing variables accessed by shared code 4240* hw - Struct containing variables accessed by shared code
4241* phy_info - PHY information structure 4241* phy_info - PHY information structure
4242******************************************************************************/ 4242******************************************************************************/
4243static int32_t 4243static s32
4244e1000_phy_ife_get_info(struct e1000_hw *hw, 4244e1000_phy_ife_get_info(struct e1000_hw *hw,
4245 struct e1000_phy_info *phy_info) 4245 struct e1000_phy_info *phy_info)
4246{ 4246{
4247 int32_t ret_val; 4247 s32 ret_val;
4248 uint16_t phy_data; 4248 u16 phy_data;
4249 e1000_rev_polarity polarity; 4249 e1000_rev_polarity polarity;
4250 4250
4251 DEBUGFUNC("e1000_phy_ife_get_info"); 4251 DEBUGFUNC("e1000_phy_ife_get_info");
@@ -4290,12 +4290,12 @@ e1000_phy_ife_get_info(struct e1000_hw *hw,
4290* hw - Struct containing variables accessed by shared code 4290* hw - Struct containing variables accessed by shared code
4291* phy_info - PHY information structure 4291* phy_info - PHY information structure
4292******************************************************************************/ 4292******************************************************************************/
4293static int32_t 4293static s32
4294e1000_phy_m88_get_info(struct e1000_hw *hw, 4294e1000_phy_m88_get_info(struct e1000_hw *hw,
4295 struct e1000_phy_info *phy_info) 4295 struct e1000_phy_info *phy_info)
4296{ 4296{
4297 int32_t ret_val; 4297 s32 ret_val;
4298 uint16_t phy_data; 4298 u16 phy_data;
4299 e1000_rev_polarity polarity; 4299 e1000_rev_polarity polarity;
4300 4300
4301 DEBUGFUNC("e1000_phy_m88_get_info"); 4301 DEBUGFUNC("e1000_phy_m88_get_info");
@@ -4369,12 +4369,12 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4369* hw - Struct containing variables accessed by shared code 4369* hw - Struct containing variables accessed by shared code
4370* phy_info - PHY information structure 4370* phy_info - PHY information structure
4371******************************************************************************/ 4371******************************************************************************/
4372int32_t 4372s32
4373e1000_phy_get_info(struct e1000_hw *hw, 4373e1000_phy_get_info(struct e1000_hw *hw,
4374 struct e1000_phy_info *phy_info) 4374 struct e1000_phy_info *phy_info)
4375{ 4375{
4376 int32_t ret_val; 4376 s32 ret_val;
4377 uint16_t phy_data; 4377 u16 phy_data;
4378 4378
4379 DEBUGFUNC("e1000_phy_get_info"); 4379 DEBUGFUNC("e1000_phy_get_info");
4380 4380
@@ -4415,7 +4415,7 @@ e1000_phy_get_info(struct e1000_hw *hw,
4415 return e1000_phy_m88_get_info(hw, phy_info); 4415 return e1000_phy_m88_get_info(hw, phy_info);
4416} 4416}
4417 4417
4418int32_t 4418s32
4419e1000_validate_mdi_setting(struct e1000_hw *hw) 4419e1000_validate_mdi_setting(struct e1000_hw *hw)
4420{ 4420{
4421 DEBUGFUNC("e1000_validate_mdi_settings"); 4421 DEBUGFUNC("e1000_validate_mdi_settings");
@@ -4436,13 +4436,13 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
4436 * 4436 *
4437 * hw - Struct containing variables accessed by shared code 4437 * hw - Struct containing variables accessed by shared code
4438 *****************************************************************************/ 4438 *****************************************************************************/
4439int32_t 4439s32
4440e1000_init_eeprom_params(struct e1000_hw *hw) 4440e1000_init_eeprom_params(struct e1000_hw *hw)
4441{ 4441{
4442 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4442 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4443 uint32_t eecd = E1000_READ_REG(hw, EECD); 4443 u32 eecd = E1000_READ_REG(hw, EECD);
4444 int32_t ret_val = E1000_SUCCESS; 4444 s32 ret_val = E1000_SUCCESS;
4445 uint16_t eeprom_size; 4445 u16 eeprom_size;
4446 4446
4447 DEBUGFUNC("e1000_init_eeprom_params"); 4447 DEBUGFUNC("e1000_init_eeprom_params");
4448 4448
@@ -4561,8 +4561,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4561 break; 4561 break;
4562 case e1000_ich8lan: 4562 case e1000_ich8lan:
4563 { 4563 {
4564 int32_t i = 0; 4564 s32 i = 0;
4565 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 4565 u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4566 4566
4567 eeprom->type = e1000_eeprom_ich8; 4567 eeprom->type = e1000_eeprom_ich8;
4568 eeprom->use_eerd = false; 4568 eeprom->use_eerd = false;
@@ -4586,7 +4586,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4586 4586
4587 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 4587 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4588 4588
4589 hw->flash_bank_size /= 2 * sizeof(uint16_t); 4589 hw->flash_bank_size /= 2 * sizeof(u16);
4590 4590
4591 break; 4591 break;
4592 } 4592 }
@@ -4611,7 +4611,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4611 if (eeprom_size) 4611 if (eeprom_size)
4612 eeprom_size++; 4612 eeprom_size++;
4613 } else { 4613 } else {
4614 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> 4614 eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4615 E1000_EECD_SIZE_EX_SHIFT); 4615 E1000_EECD_SIZE_EX_SHIFT);
4616 } 4616 }
4617 4617
@@ -4628,7 +4628,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4628 *****************************************************************************/ 4628 *****************************************************************************/
4629static void 4629static void
4630e1000_raise_ee_clk(struct e1000_hw *hw, 4630e1000_raise_ee_clk(struct e1000_hw *hw,
4631 uint32_t *eecd) 4631 u32 *eecd)
4632{ 4632{
4633 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 4633 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4634 * wait <delay> microseconds. 4634 * wait <delay> microseconds.
@@ -4647,7 +4647,7 @@ e1000_raise_ee_clk(struct e1000_hw *hw,
4647 *****************************************************************************/ 4647 *****************************************************************************/
4648static void 4648static void
4649e1000_lower_ee_clk(struct e1000_hw *hw, 4649e1000_lower_ee_clk(struct e1000_hw *hw,
4650 uint32_t *eecd) 4650 u32 *eecd)
4651{ 4651{
4652 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 4652 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4653 * wait 50 microseconds. 4653 * wait 50 microseconds.
@@ -4667,12 +4667,12 @@ e1000_lower_ee_clk(struct e1000_hw *hw,
4667 *****************************************************************************/ 4667 *****************************************************************************/
4668static void 4668static void
4669e1000_shift_out_ee_bits(struct e1000_hw *hw, 4669e1000_shift_out_ee_bits(struct e1000_hw *hw,
4670 uint16_t data, 4670 u16 data,
4671 uint16_t count) 4671 u16 count)
4672{ 4672{
4673 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4673 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4674 uint32_t eecd; 4674 u32 eecd;
4675 uint32_t mask; 4675 u32 mask;
4676 4676
4677 /* We need to shift "count" bits out to the EEPROM. So, value in the 4677 /* We need to shift "count" bits out to the EEPROM. So, value in the
4678 * "data" parameter will be shifted out to the EEPROM one bit at a time. 4678 * "data" parameter will be shifted out to the EEPROM one bit at a time.
@@ -4718,13 +4718,13 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4718 * 4718 *
4719 * hw - Struct containing variables accessed by shared code 4719 * hw - Struct containing variables accessed by shared code
4720 *****************************************************************************/ 4720 *****************************************************************************/
4721static uint16_t 4721static u16
4722e1000_shift_in_ee_bits(struct e1000_hw *hw, 4722e1000_shift_in_ee_bits(struct e1000_hw *hw,
4723 uint16_t count) 4723 u16 count)
4724{ 4724{
4725 uint32_t eecd; 4725 u32 eecd;
4726 uint32_t i; 4726 u32 i;
4727 uint16_t data; 4727 u16 data;
4728 4728
4729 /* In order to read a register from the EEPROM, we need to shift 'count' 4729 /* In order to read a register from the EEPROM, we need to shift 'count'
4730 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 4730 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
@@ -4762,11 +4762,11 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4762 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 4762 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4763 * function should be called before issuing a command to the EEPROM. 4763 * function should be called before issuing a command to the EEPROM.
4764 *****************************************************************************/ 4764 *****************************************************************************/
4765static int32_t 4765static s32
4766e1000_acquire_eeprom(struct e1000_hw *hw) 4766e1000_acquire_eeprom(struct e1000_hw *hw)
4767{ 4767{
4768 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4768 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4769 uint32_t eecd, i=0; 4769 u32 eecd, i=0;
4770 4770
4771 DEBUGFUNC("e1000_acquire_eeprom"); 4771 DEBUGFUNC("e1000_acquire_eeprom");
4772 4772
@@ -4825,7 +4825,7 @@ static void
4825e1000_standby_eeprom(struct e1000_hw *hw) 4825e1000_standby_eeprom(struct e1000_hw *hw)
4826{ 4826{
4827 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4827 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4828 uint32_t eecd; 4828 u32 eecd;
4829 4829
4830 eecd = E1000_READ_REG(hw, EECD); 4830 eecd = E1000_READ_REG(hw, EECD);
4831 4831
@@ -4873,7 +4873,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4873static void 4873static void
4874e1000_release_eeprom(struct e1000_hw *hw) 4874e1000_release_eeprom(struct e1000_hw *hw)
4875{ 4875{
4876 uint32_t eecd; 4876 u32 eecd;
4877 4877
4878 DEBUGFUNC("e1000_release_eeprom"); 4878 DEBUGFUNC("e1000_release_eeprom");
4879 4879
@@ -4921,11 +4921,11 @@ e1000_release_eeprom(struct e1000_hw *hw)
4921 * 4921 *
4922 * hw - Struct containing variables accessed by shared code 4922 * hw - Struct containing variables accessed by shared code
4923 *****************************************************************************/ 4923 *****************************************************************************/
4924static int32_t 4924static s32
4925e1000_spi_eeprom_ready(struct e1000_hw *hw) 4925e1000_spi_eeprom_ready(struct e1000_hw *hw)
4926{ 4926{
4927 uint16_t retry_count = 0; 4927 u16 retry_count = 0;
4928 uint8_t spi_stat_reg; 4928 u8 spi_stat_reg;
4929 4929
4930 DEBUGFUNC("e1000_spi_eeprom_ready"); 4930 DEBUGFUNC("e1000_spi_eeprom_ready");
4931 4931
@@ -4938,7 +4938,7 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4938 do { 4938 do {
4939 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 4939 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4940 hw->eeprom.opcode_bits); 4940 hw->eeprom.opcode_bits);
4941 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); 4941 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
4942 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 4942 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4943 break; 4943 break;
4944 4944
@@ -4967,14 +4967,14 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4967 * data - word read from the EEPROM 4967 * data - word read from the EEPROM
4968 * words - number of words to read 4968 * words - number of words to read
4969 *****************************************************************************/ 4969 *****************************************************************************/
4970int32_t 4970s32
4971e1000_read_eeprom(struct e1000_hw *hw, 4971e1000_read_eeprom(struct e1000_hw *hw,
4972 uint16_t offset, 4972 u16 offset,
4973 uint16_t words, 4973 u16 words,
4974 uint16_t *data) 4974 u16 *data)
4975{ 4975{
4976 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4976 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4977 uint32_t i = 0; 4977 u32 i = 0;
4978 4978
4979 DEBUGFUNC("e1000_read_eeprom"); 4979 DEBUGFUNC("e1000_read_eeprom");
4980 4980
@@ -5012,8 +5012,8 @@ e1000_read_eeprom(struct e1000_hw *hw,
5012 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 5012 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5013 * acquired the EEPROM at this point, so any returns should relase it */ 5013 * acquired the EEPROM at this point, so any returns should relase it */
5014 if (eeprom->type == e1000_eeprom_spi) { 5014 if (eeprom->type == e1000_eeprom_spi) {
5015 uint16_t word_in; 5015 u16 word_in;
5016 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 5016 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
5017 5017
5018 if (e1000_spi_eeprom_ready(hw)) { 5018 if (e1000_spi_eeprom_ready(hw)) {
5019 e1000_release_eeprom(hw); 5019 e1000_release_eeprom(hw);
@@ -5028,7 +5028,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
5028 5028
5029 /* Send the READ command (opcode + addr) */ 5029 /* Send the READ command (opcode + addr) */
5030 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 5030 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5031 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); 5031 e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
5032 5032
5033 /* Read the data. The address of the eeprom internally increments with 5033 /* Read the data. The address of the eeprom internally increments with
5034 * each byte (spi) being read, saving on the overhead of eeprom setup 5034 * each byte (spi) being read, saving on the overhead of eeprom setup
@@ -5044,7 +5044,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
5044 /* Send the READ command (opcode + addr) */ 5044 /* Send the READ command (opcode + addr) */
5045 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 5045 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5046 eeprom->opcode_bits); 5046 eeprom->opcode_bits);
5047 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), 5047 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
5048 eeprom->address_bits); 5048 eeprom->address_bits);
5049 5049
5050 /* Read the data. For microwire, each word requires the overhead 5050 /* Read the data. For microwire, each word requires the overhead
@@ -5068,14 +5068,14 @@ e1000_read_eeprom(struct e1000_hw *hw,
5068 * data - word read from the EEPROM 5068 * data - word read from the EEPROM
5069 * words - number of words to read 5069 * words - number of words to read
5070 *****************************************************************************/ 5070 *****************************************************************************/
5071static int32_t 5071static s32
5072e1000_read_eeprom_eerd(struct e1000_hw *hw, 5072e1000_read_eeprom_eerd(struct e1000_hw *hw,
5073 uint16_t offset, 5073 u16 offset,
5074 uint16_t words, 5074 u16 words,
5075 uint16_t *data) 5075 u16 *data)
5076{ 5076{
5077 uint32_t i, eerd = 0; 5077 u32 i, eerd = 0;
5078 int32_t error = 0; 5078 s32 error = 0;
5079 5079
5080 for (i = 0; i < words; i++) { 5080 for (i = 0; i < words; i++) {
5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
@@ -5102,15 +5102,15 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
5102 * data - word read from the EEPROM 5102 * data - word read from the EEPROM
5103 * words - number of words to read 5103 * words - number of words to read
5104 *****************************************************************************/ 5104 *****************************************************************************/
5105static int32_t 5105static s32
5106e1000_write_eeprom_eewr(struct e1000_hw *hw, 5106e1000_write_eeprom_eewr(struct e1000_hw *hw,
5107 uint16_t offset, 5107 u16 offset,
5108 uint16_t words, 5108 u16 words,
5109 uint16_t *data) 5109 u16 *data)
5110{ 5110{
5111 uint32_t register_value = 0; 5111 u32 register_value = 0;
5112 uint32_t i = 0; 5112 u32 i = 0;
5113 int32_t error = 0; 5113 s32 error = 0;
5114 5114
5115 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5115 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5116 return -E1000_ERR_SWFW_SYNC; 5116 return -E1000_ERR_SWFW_SYNC;
@@ -5143,12 +5143,12 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
5143 * 5143 *
5144 * hw - Struct containing variables accessed by shared code 5144 * hw - Struct containing variables accessed by shared code
5145 *****************************************************************************/ 5145 *****************************************************************************/
5146static int32_t 5146static s32
5147e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 5147e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5148{ 5148{
5149 uint32_t attempts = 100000; 5149 u32 attempts = 100000;
5150 uint32_t i, reg = 0; 5150 u32 i, reg = 0;
5151 int32_t done = E1000_ERR_EEPROM; 5151 s32 done = E1000_ERR_EEPROM;
5152 5152
5153 for (i = 0; i < attempts; i++) { 5153 for (i = 0; i < attempts; i++) {
5154 if (eerd == E1000_EEPROM_POLL_READ) 5154 if (eerd == E1000_EEPROM_POLL_READ)
@@ -5174,7 +5174,7 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5174static bool 5174static bool
5175e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) 5175e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5176{ 5176{
5177 uint32_t eecd = 0; 5177 u32 eecd = 0;
5178 5178
5179 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5179 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5180 5180
@@ -5204,11 +5204,11 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5205 * valid. 5205 * valid.
5206 *****************************************************************************/ 5206 *****************************************************************************/
5207int32_t 5207s32
5208e1000_validate_eeprom_checksum(struct e1000_hw *hw) 5208e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5209{ 5209{
5210 uint16_t checksum = 0; 5210 u16 checksum = 0;
5211 uint16_t i, eeprom_data; 5211 u16 i, eeprom_data;
5212 5212
5213 DEBUGFUNC("e1000_validate_eeprom_checksum"); 5213 DEBUGFUNC("e1000_validate_eeprom_checksum");
5214 5214
@@ -5252,7 +5252,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5252 checksum += eeprom_data; 5252 checksum += eeprom_data;
5253 } 5253 }
5254 5254
5255 if (checksum == (uint16_t) EEPROM_SUM) 5255 if (checksum == (u16) EEPROM_SUM)
5256 return E1000_SUCCESS; 5256 return E1000_SUCCESS;
5257 else { 5257 else {
5258 DEBUGOUT("EEPROM Checksum Invalid\n"); 5258 DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -5268,12 +5268,12 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5268 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 5268 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5269 * Writes the difference to word offset 63 of the EEPROM. 5269 * Writes the difference to word offset 63 of the EEPROM.
5270 *****************************************************************************/ 5270 *****************************************************************************/
5271int32_t 5271s32
5272e1000_update_eeprom_checksum(struct e1000_hw *hw) 5272e1000_update_eeprom_checksum(struct e1000_hw *hw)
5273{ 5273{
5274 uint32_t ctrl_ext; 5274 u32 ctrl_ext;
5275 uint16_t checksum = 0; 5275 u16 checksum = 0;
5276 uint16_t i, eeprom_data; 5276 u16 i, eeprom_data;
5277 5277
5278 DEBUGFUNC("e1000_update_eeprom_checksum"); 5278 DEBUGFUNC("e1000_update_eeprom_checksum");
5279 5279
@@ -5284,7 +5284,7 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5284 } 5284 }
5285 checksum += eeprom_data; 5285 checksum += eeprom_data;
5286 } 5286 }
5287 checksum = (uint16_t) EEPROM_SUM - checksum; 5287 checksum = (u16) EEPROM_SUM - checksum;
5288 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5288 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5289 DEBUGOUT("EEPROM Write Error\n"); 5289 DEBUGOUT("EEPROM Write Error\n");
5290 return -E1000_ERR_EEPROM; 5290 return -E1000_ERR_EEPROM;
@@ -5313,14 +5313,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5313 * If e1000_update_eeprom_checksum is not called after this function, the 5313 * If e1000_update_eeprom_checksum is not called after this function, the
5314 * EEPROM will most likely contain an invalid checksum. 5314 * EEPROM will most likely contain an invalid checksum.
5315 *****************************************************************************/ 5315 *****************************************************************************/
5316int32_t 5316s32
5317e1000_write_eeprom(struct e1000_hw *hw, 5317e1000_write_eeprom(struct e1000_hw *hw,
5318 uint16_t offset, 5318 u16 offset,
5319 uint16_t words, 5319 u16 words,
5320 uint16_t *data) 5320 u16 *data)
5321{ 5321{
5322 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5322 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5323 int32_t status = 0; 5323 s32 status = 0;
5324 5324
5325 DEBUGFUNC("e1000_write_eeprom"); 5325 DEBUGFUNC("e1000_write_eeprom");
5326 5326
@@ -5370,19 +5370,19 @@ e1000_write_eeprom(struct e1000_hw *hw,
5370 * data - pointer to array of 8 bit words to be written to the EEPROM 5370 * data - pointer to array of 8 bit words to be written to the EEPROM
5371 * 5371 *
5372 *****************************************************************************/ 5372 *****************************************************************************/
5373static int32_t 5373static s32
5374e1000_write_eeprom_spi(struct e1000_hw *hw, 5374e1000_write_eeprom_spi(struct e1000_hw *hw,
5375 uint16_t offset, 5375 u16 offset,
5376 uint16_t words, 5376 u16 words,
5377 uint16_t *data) 5377 u16 *data)
5378{ 5378{
5379 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5379 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5380 uint16_t widx = 0; 5380 u16 widx = 0;
5381 5381
5382 DEBUGFUNC("e1000_write_eeprom_spi"); 5382 DEBUGFUNC("e1000_write_eeprom_spi");
5383 5383
5384 while (widx < words) { 5384 while (widx < words) {
5385 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 5385 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
5386 5386
5387 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 5387 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5388 5388
@@ -5401,14 +5401,14 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5401 /* Send the Write command (8-bit opcode + addr) */ 5401 /* Send the Write command (8-bit opcode + addr) */
5402 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 5402 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5403 5403
5404 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), 5404 e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
5405 eeprom->address_bits); 5405 eeprom->address_bits);
5406 5406
5407 /* Send the data */ 5407 /* Send the data */
5408 5408
5409 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 5409 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5410 while (widx < words) { 5410 while (widx < words) {
5411 uint16_t word_out = data[widx]; 5411 u16 word_out = data[widx];
5412 word_out = (word_out >> 8) | (word_out << 8); 5412 word_out = (word_out >> 8) | (word_out << 8);
5413 e1000_shift_out_ee_bits(hw, word_out, 16); 5413 e1000_shift_out_ee_bits(hw, word_out, 16);
5414 widx++; 5414 widx++;
@@ -5436,16 +5436,16 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5436 * data - pointer to array of 16 bit words to be written to the EEPROM 5436 * data - pointer to array of 16 bit words to be written to the EEPROM
5437 * 5437 *
5438 *****************************************************************************/ 5438 *****************************************************************************/
5439static int32_t 5439static s32
5440e1000_write_eeprom_microwire(struct e1000_hw *hw, 5440e1000_write_eeprom_microwire(struct e1000_hw *hw,
5441 uint16_t offset, 5441 u16 offset,
5442 uint16_t words, 5442 u16 words,
5443 uint16_t *data) 5443 u16 *data)
5444{ 5444{
5445 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5445 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5446 uint32_t eecd; 5446 u32 eecd;
5447 uint16_t words_written = 0; 5447 u16 words_written = 0;
5448 uint16_t i = 0; 5448 u16 i = 0;
5449 5449
5450 DEBUGFUNC("e1000_write_eeprom_microwire"); 5450 DEBUGFUNC("e1000_write_eeprom_microwire");
5451 5451
@@ -5456,9 +5456,9 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5456 * EEPROM into write/erase mode. 5456 * EEPROM into write/erase mode.
5457 */ 5457 */
5458 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 5458 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5459 (uint16_t)(eeprom->opcode_bits + 2)); 5459 (u16)(eeprom->opcode_bits + 2));
5460 5460
5461 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5461 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5462 5462
5463 /* Prepare the EEPROM */ 5463 /* Prepare the EEPROM */
5464 e1000_standby_eeprom(hw); 5464 e1000_standby_eeprom(hw);
@@ -5468,7 +5468,7 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5468 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 5468 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5469 eeprom->opcode_bits); 5469 eeprom->opcode_bits);
5470 5470
5471 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), 5471 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
5472 eeprom->address_bits); 5472 eeprom->address_bits);
5473 5473
5474 /* Send the data */ 5474 /* Send the data */
@@ -5506,9 +5506,9 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5506 * EEPROM out of write/erase mode. 5506 * EEPROM out of write/erase mode.
5507 */ 5507 */
5508 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 5508 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5509 (uint16_t)(eeprom->opcode_bits + 2)); 5509 (u16)(eeprom->opcode_bits + 2));
5510 5510
5511 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5511 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5512 5512
5513 return E1000_SUCCESS; 5513 return E1000_SUCCESS;
5514} 5514}
@@ -5523,18 +5523,18 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5523 * data - word read from the EEPROM 5523 * data - word read from the EEPROM
5524 * words - number of words to read 5524 * words - number of words to read
5525 *****************************************************************************/ 5525 *****************************************************************************/
5526static int32_t 5526static s32
5527e1000_commit_shadow_ram(struct e1000_hw *hw) 5527e1000_commit_shadow_ram(struct e1000_hw *hw)
5528{ 5528{
5529 uint32_t attempts = 100000; 5529 u32 attempts = 100000;
5530 uint32_t eecd = 0; 5530 u32 eecd = 0;
5531 uint32_t flop = 0; 5531 u32 flop = 0;
5532 uint32_t i = 0; 5532 u32 i = 0;
5533 int32_t error = E1000_SUCCESS; 5533 s32 error = E1000_SUCCESS;
5534 uint32_t old_bank_offset = 0; 5534 u32 old_bank_offset = 0;
5535 uint32_t new_bank_offset = 0; 5535 u32 new_bank_offset = 0;
5536 uint8_t low_byte = 0; 5536 u8 low_byte = 0;
5537 uint8_t high_byte = 0; 5537 u8 high_byte = 0;
5538 bool sector_write_failed = false; 5538 bool sector_write_failed = false;
5539 5539
5540 if (hw->mac_type == e1000_82573) { 5540 if (hw->mac_type == e1000_82573) {
@@ -5595,7 +5595,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5595 * in the other NVM bank or a modified value stored 5595 * in the other NVM bank or a modified value stored
5596 * in the shadow RAM */ 5596 * in the shadow RAM */
5597 if (hw->eeprom_shadow_ram[i].modified) { 5597 if (hw->eeprom_shadow_ram[i].modified) {
5598 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; 5598 low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
5599 udelay(100); 5599 udelay(100);
5600 error = e1000_verify_write_ich8_byte(hw, 5600 error = e1000_verify_write_ich8_byte(hw,
5601 (i << 1) + new_bank_offset, low_byte); 5601 (i << 1) + new_bank_offset, low_byte);
@@ -5604,7 +5604,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5604 sector_write_failed = true; 5604 sector_write_failed = true;
5605 else { 5605 else {
5606 high_byte = 5606 high_byte =
5607 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); 5607 (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5608 udelay(100); 5608 udelay(100);
5609 } 5609 }
5610 } else { 5610 } else {
@@ -5687,11 +5687,11 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5687 * 5687 *
5688 * hw - Struct containing variables accessed by shared code 5688 * hw - Struct containing variables accessed by shared code
5689 *****************************************************************************/ 5689 *****************************************************************************/
5690int32_t 5690s32
5691e1000_read_mac_addr(struct e1000_hw * hw) 5691e1000_read_mac_addr(struct e1000_hw * hw)
5692{ 5692{
5693 uint16_t offset; 5693 u16 offset;
5694 uint16_t eeprom_data, i; 5694 u16 eeprom_data, i;
5695 5695
5696 DEBUGFUNC("e1000_read_mac_addr"); 5696 DEBUGFUNC("e1000_read_mac_addr");
5697 5697
@@ -5701,8 +5701,8 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5701 DEBUGOUT("EEPROM Read Error\n"); 5701 DEBUGOUT("EEPROM Read Error\n");
5702 return -E1000_ERR_EEPROM; 5702 return -E1000_ERR_EEPROM;
5703 } 5703 }
5704 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 5704 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
5705 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); 5705 hw->perm_mac_addr[i+1] = (u8) (eeprom_data >> 8);
5706 } 5706 }
5707 5707
5708 switch (hw->mac_type) { 5708 switch (hw->mac_type) {
@@ -5734,8 +5734,8 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5734static void 5734static void
5735e1000_init_rx_addrs(struct e1000_hw *hw) 5735e1000_init_rx_addrs(struct e1000_hw *hw)
5736{ 5736{
5737 uint32_t i; 5737 u32 i;
5738 uint32_t rar_num; 5738 u32 rar_num;
5739 5739
5740 DEBUGFUNC("e1000_init_rx_addrs"); 5740 DEBUGFUNC("e1000_init_rx_addrs");
5741 5741
@@ -5770,11 +5770,11 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5770 * hw - Struct containing variables accessed by shared code 5770 * hw - Struct containing variables accessed by shared code
5771 * mc_addr - the multicast address to hash 5771 * mc_addr - the multicast address to hash
5772 *****************************************************************************/ 5772 *****************************************************************************/
5773uint32_t 5773u32
5774e1000_hash_mc_addr(struct e1000_hw *hw, 5774e1000_hash_mc_addr(struct e1000_hw *hw,
5775 uint8_t *mc_addr) 5775 u8 *mc_addr)
5776{ 5776{
5777 uint32_t hash_value = 0; 5777 u32 hash_value = 0;
5778 5778
5779 /* The portion of the address that is used for the hash table is 5779 /* The portion of the address that is used for the hash table is
5780 * determined by the mc_filter_type setting. 5780 * determined by the mc_filter_type setting.
@@ -5787,37 +5787,37 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5787 case 0: 5787 case 0:
5788 if (hw->mac_type == e1000_ich8lan) { 5788 if (hw->mac_type == e1000_ich8lan) {
5789 /* [47:38] i.e. 0x158 for above example address */ 5789 /* [47:38] i.e. 0x158 for above example address */
5790 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); 5790 hash_value = ((mc_addr[4] >> 6) | (((u16) mc_addr[5]) << 2));
5791 } else { 5791 } else {
5792 /* [47:36] i.e. 0x563 for above example address */ 5792 /* [47:36] i.e. 0x563 for above example address */
5793 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5793 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
5794 } 5794 }
5795 break; 5795 break;
5796 case 1: 5796 case 1:
5797 if (hw->mac_type == e1000_ich8lan) { 5797 if (hw->mac_type == e1000_ich8lan) {
5798 /* [46:37] i.e. 0x2B1 for above example address */ 5798 /* [46:37] i.e. 0x2B1 for above example address */
5799 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); 5799 hash_value = ((mc_addr[4] >> 5) | (((u16) mc_addr[5]) << 3));
5800 } else { 5800 } else {
5801 /* [46:35] i.e. 0xAC6 for above example address */ 5801 /* [46:35] i.e. 0xAC6 for above example address */
5802 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5802 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
5803 } 5803 }
5804 break; 5804 break;
5805 case 2: 5805 case 2:
5806 if (hw->mac_type == e1000_ich8lan) { 5806 if (hw->mac_type == e1000_ich8lan) {
5807 /*[45:36] i.e. 0x163 for above example address */ 5807 /*[45:36] i.e. 0x163 for above example address */
5808 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5808 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
5809 } else { 5809 } else {
5810 /* [45:34] i.e. 0x5D8 for above example address */ 5810 /* [45:34] i.e. 0x5D8 for above example address */
5811 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5811 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
5812 } 5812 }
5813 break; 5813 break;
5814 case 3: 5814 case 3:
5815 if (hw->mac_type == e1000_ich8lan) { 5815 if (hw->mac_type == e1000_ich8lan) {
5816 /* [43:34] i.e. 0x18D for above example address */ 5816 /* [43:34] i.e. 0x18D for above example address */
5817 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5817 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
5818 } else { 5818 } else {
5819 /* [43:32] i.e. 0x634 for above example address */ 5819 /* [43:32] i.e. 0x634 for above example address */
5820 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5820 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
5821 } 5821 }
5822 break; 5822 break;
5823 } 5823 }
@@ -5837,11 +5837,11 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5837 *****************************************************************************/ 5837 *****************************************************************************/
5838void 5838void
5839e1000_mta_set(struct e1000_hw *hw, 5839e1000_mta_set(struct e1000_hw *hw,
5840 uint32_t hash_value) 5840 u32 hash_value)
5841{ 5841{
5842 uint32_t hash_bit, hash_reg; 5842 u32 hash_bit, hash_reg;
5843 uint32_t mta; 5843 u32 mta;
5844 uint32_t temp; 5844 u32 temp;
5845 5845
5846 /* The MTA is a register array of 128 32-bit registers. 5846 /* The MTA is a register array of 128 32-bit registers.
5847 * It is treated like an array of 4096 bits. We want to set 5847 * It is treated like an array of 4096 bits. We want to set
@@ -5886,18 +5886,18 @@ e1000_mta_set(struct e1000_hw *hw,
5886 *****************************************************************************/ 5886 *****************************************************************************/
5887void 5887void
5888e1000_rar_set(struct e1000_hw *hw, 5888e1000_rar_set(struct e1000_hw *hw,
5889 uint8_t *addr, 5889 u8 *addr,
5890 uint32_t index) 5890 u32 index)
5891{ 5891{
5892 uint32_t rar_low, rar_high; 5892 u32 rar_low, rar_high;
5893 5893
5894 /* HW expects these in little endian so we reverse the byte order 5894 /* HW expects these in little endian so we reverse the byte order
5895 * from network order (big endian) to little endian 5895 * from network order (big endian) to little endian
5896 */ 5896 */
5897 rar_low = ((uint32_t) addr[0] | 5897 rar_low = ((u32) addr[0] |
5898 ((uint32_t) addr[1] << 8) | 5898 ((u32) addr[1] << 8) |
5899 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 5899 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5900 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 5900 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5901 5901
5902 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 5902 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5903 * unit hang. 5903 * unit hang.
@@ -5944,10 +5944,10 @@ e1000_rar_set(struct e1000_hw *hw,
5944 *****************************************************************************/ 5944 *****************************************************************************/
5945void 5945void
5946e1000_write_vfta(struct e1000_hw *hw, 5946e1000_write_vfta(struct e1000_hw *hw,
5947 uint32_t offset, 5947 u32 offset,
5948 uint32_t value) 5948 u32 value)
5949{ 5949{
5950 uint32_t temp; 5950 u32 temp;
5951 5951
5952 if (hw->mac_type == e1000_ich8lan) 5952 if (hw->mac_type == e1000_ich8lan)
5953 return; 5953 return;
@@ -5972,10 +5972,10 @@ e1000_write_vfta(struct e1000_hw *hw,
5972static void 5972static void
5973e1000_clear_vfta(struct e1000_hw *hw) 5973e1000_clear_vfta(struct e1000_hw *hw)
5974{ 5974{
5975 uint32_t offset; 5975 u32 offset;
5976 uint32_t vfta_value = 0; 5976 u32 vfta_value = 0;
5977 uint32_t vfta_offset = 0; 5977 u32 vfta_offset = 0;
5978 uint32_t vfta_bit_in_reg = 0; 5978 u32 vfta_bit_in_reg = 0;
5979 5979
5980 if (hw->mac_type == e1000_ich8lan) 5980 if (hw->mac_type == e1000_ich8lan)
5981 return; 5981 return;
@@ -6003,15 +6003,15 @@ e1000_clear_vfta(struct e1000_hw *hw)
6003 } 6003 }
6004} 6004}
6005 6005
6006static int32_t 6006static s32
6007e1000_id_led_init(struct e1000_hw * hw) 6007e1000_id_led_init(struct e1000_hw * hw)
6008{ 6008{
6009 uint32_t ledctl; 6009 u32 ledctl;
6010 const uint32_t ledctl_mask = 0x000000FF; 6010 const u32 ledctl_mask = 0x000000FF;
6011 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 6011 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6012 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 6012 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6013 uint16_t eeprom_data, i, temp; 6013 u16 eeprom_data, i, temp;
6014 const uint16_t led_mask = 0x0F; 6014 const u16 led_mask = 0x0F;
6015 6015
6016 DEBUGFUNC("e1000_id_led_init"); 6016 DEBUGFUNC("e1000_id_led_init");
6017 6017
@@ -6086,11 +6086,11 @@ e1000_id_led_init(struct e1000_hw * hw)
6086 * 6086 *
6087 * hw - Struct containing variables accessed by shared code 6087 * hw - Struct containing variables accessed by shared code
6088 *****************************************************************************/ 6088 *****************************************************************************/
6089int32_t 6089s32
6090e1000_setup_led(struct e1000_hw *hw) 6090e1000_setup_led(struct e1000_hw *hw)
6091{ 6091{
6092 uint32_t ledctl; 6092 u32 ledctl;
6093 int32_t ret_val = E1000_SUCCESS; 6093 s32 ret_val = E1000_SUCCESS;
6094 6094
6095 DEBUGFUNC("e1000_setup_led"); 6095 DEBUGFUNC("e1000_setup_led");
6096 6096
@@ -6111,7 +6111,7 @@ e1000_setup_led(struct e1000_hw *hw)
6111 if (ret_val) 6111 if (ret_val)
6112 return ret_val; 6112 return ret_val;
6113 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6113 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6114 (uint16_t)(hw->phy_spd_default & 6114 (u16)(hw->phy_spd_default &
6115 ~IGP01E1000_GMII_SPD)); 6115 ~IGP01E1000_GMII_SPD));
6116 if (ret_val) 6116 if (ret_val)
6117 return ret_val; 6117 return ret_val;
@@ -6145,11 +6145,11 @@ e1000_setup_led(struct e1000_hw *hw)
6145 * 6145 *
6146 * hw - Struct containing variables accessed by shared code 6146 * hw - Struct containing variables accessed by shared code
6147 *****************************************************************************/ 6147 *****************************************************************************/
6148int32_t 6148s32
6149e1000_blink_led_start(struct e1000_hw *hw) 6149e1000_blink_led_start(struct e1000_hw *hw)
6150{ 6150{
6151 int16_t i; 6151 s16 i;
6152 uint32_t ledctl_blink = 0; 6152 u32 ledctl_blink = 0;
6153 6153
6154 DEBUGFUNC("e1000_id_led_blink_on"); 6154 DEBUGFUNC("e1000_id_led_blink_on");
6155 6155
@@ -6180,10 +6180,10 @@ e1000_blink_led_start(struct e1000_hw *hw)
6180 * 6180 *
6181 * hw - Struct containing variables accessed by shared code 6181 * hw - Struct containing variables accessed by shared code
6182 *****************************************************************************/ 6182 *****************************************************************************/
6183int32_t 6183s32
6184e1000_cleanup_led(struct e1000_hw *hw) 6184e1000_cleanup_led(struct e1000_hw *hw)
6185{ 6185{
6186 int32_t ret_val = E1000_SUCCESS; 6186 s32 ret_val = E1000_SUCCESS;
6187 6187
6188 DEBUGFUNC("e1000_cleanup_led"); 6188 DEBUGFUNC("e1000_cleanup_led");
6189 6189
@@ -6222,10 +6222,10 @@ e1000_cleanup_led(struct e1000_hw *hw)
6222 * 6222 *
6223 * hw - Struct containing variables accessed by shared code 6223 * hw - Struct containing variables accessed by shared code
6224 *****************************************************************************/ 6224 *****************************************************************************/
6225int32_t 6225s32
6226e1000_led_on(struct e1000_hw *hw) 6226e1000_led_on(struct e1000_hw *hw)
6227{ 6227{
6228 uint32_t ctrl = E1000_READ_REG(hw, CTRL); 6228 u32 ctrl = E1000_READ_REG(hw, CTRL);
6229 6229
6230 DEBUGFUNC("e1000_led_on"); 6230 DEBUGFUNC("e1000_led_on");
6231 6231
@@ -6273,10 +6273,10 @@ e1000_led_on(struct e1000_hw *hw)
6273 * 6273 *
6274 * hw - Struct containing variables accessed by shared code 6274 * hw - Struct containing variables accessed by shared code
6275 *****************************************************************************/ 6275 *****************************************************************************/
6276int32_t 6276s32
6277e1000_led_off(struct e1000_hw *hw) 6277e1000_led_off(struct e1000_hw *hw)
6278{ 6278{
6279 uint32_t ctrl = E1000_READ_REG(hw, CTRL); 6279 u32 ctrl = E1000_READ_REG(hw, CTRL);
6280 6280
6281 DEBUGFUNC("e1000_led_off"); 6281 DEBUGFUNC("e1000_led_off");
6282 6282
@@ -6327,7 +6327,7 @@ e1000_led_off(struct e1000_hw *hw)
6327static void 6327static void
6328e1000_clear_hw_cntrs(struct e1000_hw *hw) 6328e1000_clear_hw_cntrs(struct e1000_hw *hw)
6329{ 6329{
6330 volatile uint32_t temp; 6330 volatile u32 temp;
6331 6331
6332 temp = E1000_READ_REG(hw, CRCERRS); 6332 temp = E1000_READ_REG(hw, CRCERRS);
6333 temp = E1000_READ_REG(hw, SYMERRS); 6333 temp = E1000_READ_REG(hw, SYMERRS);
@@ -6495,10 +6495,10 @@ e1000_update_adaptive(struct e1000_hw *hw)
6495void 6495void
6496e1000_tbi_adjust_stats(struct e1000_hw *hw, 6496e1000_tbi_adjust_stats(struct e1000_hw *hw,
6497 struct e1000_hw_stats *stats, 6497 struct e1000_hw_stats *stats,
6498 uint32_t frame_len, 6498 u32 frame_len,
6499 uint8_t *mac_addr) 6499 u8 *mac_addr)
6500{ 6500{
6501 uint64_t carry_bit; 6501 u64 carry_bit;
6502 6502
6503 /* First adjust the frame length. */ 6503 /* First adjust the frame length. */
6504 frame_len--; 6504 frame_len--;
@@ -6527,7 +6527,7 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6527 * since the test for a multicast frame will test positive on 6527 * since the test for a multicast frame will test positive on
6528 * a broadcast frame. 6528 * a broadcast frame.
6529 */ 6529 */
6530 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 6530 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
6531 /* Broadcast packet */ 6531 /* Broadcast packet */
6532 stats->bprc++; 6532 stats->bprc++;
6533 else if (*mac_addr & 0x01) 6533 else if (*mac_addr & 0x01)
@@ -6573,9 +6573,9 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6573void 6573void
6574e1000_get_bus_info(struct e1000_hw *hw) 6574e1000_get_bus_info(struct e1000_hw *hw)
6575{ 6575{
6576 int32_t ret_val; 6576 s32 ret_val;
6577 uint16_t pci_ex_link_status; 6577 u16 pci_ex_link_status;
6578 uint32_t status; 6578 u32 status;
6579 6579
6580 switch (hw->mac_type) { 6580 switch (hw->mac_type) {
6581 case e1000_82542_rev2_0: 6581 case e1000_82542_rev2_0:
@@ -6647,8 +6647,8 @@ e1000_get_bus_info(struct e1000_hw *hw)
6647 *****************************************************************************/ 6647 *****************************************************************************/
6648static void 6648static void
6649e1000_write_reg_io(struct e1000_hw *hw, 6649e1000_write_reg_io(struct e1000_hw *hw,
6650 uint32_t offset, 6650 u32 offset,
6651 uint32_t value) 6651 u32 value)
6652{ 6652{
6653 unsigned long io_addr = hw->io_base; 6653 unsigned long io_addr = hw->io_base;
6654 unsigned long io_data = hw->io_base + 4; 6654 unsigned long io_data = hw->io_base + 4;
@@ -6672,15 +6672,15 @@ e1000_write_reg_io(struct e1000_hw *hw,
6672 * register to the minimum and maximum range. 6672 * register to the minimum and maximum range.
6673 * For IGP phy's, the function calculates the range by the AGC registers. 6673 * For IGP phy's, the function calculates the range by the AGC registers.
6674 *****************************************************************************/ 6674 *****************************************************************************/
6675static int32_t 6675static s32
6676e1000_get_cable_length(struct e1000_hw *hw, 6676e1000_get_cable_length(struct e1000_hw *hw,
6677 uint16_t *min_length, 6677 u16 *min_length,
6678 uint16_t *max_length) 6678 u16 *max_length)
6679{ 6679{
6680 int32_t ret_val; 6680 s32 ret_val;
6681 uint16_t agc_value = 0; 6681 u16 agc_value = 0;
6682 uint16_t i, phy_data; 6682 u16 i, phy_data;
6683 uint16_t cable_length; 6683 u16 cable_length;
6684 6684
6685 DEBUGFUNC("e1000_get_cable_length"); 6685 DEBUGFUNC("e1000_get_cable_length");
6686 6686
@@ -6751,9 +6751,9 @@ e1000_get_cable_length(struct e1000_hw *hw,
6751 break; 6751 break;
6752 } 6752 }
6753 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6753 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6754 uint16_t cur_agc_value; 6754 u16 cur_agc_value;
6755 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 6755 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6756 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6756 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6757 {IGP01E1000_PHY_AGC_A, 6757 {IGP01E1000_PHY_AGC_A,
6758 IGP01E1000_PHY_AGC_B, 6758 IGP01E1000_PHY_AGC_B,
6759 IGP01E1000_PHY_AGC_C, 6759 IGP01E1000_PHY_AGC_C,
@@ -6799,9 +6799,9 @@ e1000_get_cable_length(struct e1000_hw *hw,
6799 IGP01E1000_AGC_RANGE; 6799 IGP01E1000_AGC_RANGE;
6800 } else if (hw->phy_type == e1000_phy_igp_2 || 6800 } else if (hw->phy_type == e1000_phy_igp_2 ||
6801 hw->phy_type == e1000_phy_igp_3) { 6801 hw->phy_type == e1000_phy_igp_3) {
6802 uint16_t cur_agc_index, max_agc_index = 0; 6802 u16 cur_agc_index, max_agc_index = 0;
6803 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 6803 u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6804 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6804 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6805 {IGP02E1000_PHY_AGC_A, 6805 {IGP02E1000_PHY_AGC_A,
6806 IGP02E1000_PHY_AGC_B, 6806 IGP02E1000_PHY_AGC_B,
6807 IGP02E1000_PHY_AGC_C, 6807 IGP02E1000_PHY_AGC_C,
@@ -6863,12 +6863,12 @@ e1000_get_cable_length(struct e1000_hw *hw,
6863 * return 0. If the link speed is 1000 Mbps the polarity status is in the 6863 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6864 * IGP01E1000_PHY_PCS_INIT_REG. 6864 * IGP01E1000_PHY_PCS_INIT_REG.
6865 *****************************************************************************/ 6865 *****************************************************************************/
6866static int32_t 6866static s32
6867e1000_check_polarity(struct e1000_hw *hw, 6867e1000_check_polarity(struct e1000_hw *hw,
6868 e1000_rev_polarity *polarity) 6868 e1000_rev_polarity *polarity)
6869{ 6869{
6870 int32_t ret_val; 6870 s32 ret_val;
6871 uint16_t phy_data; 6871 u16 phy_data;
6872 6872
6873 DEBUGFUNC("e1000_check_polarity"); 6873 DEBUGFUNC("e1000_check_polarity");
6874 6874
@@ -6939,11 +6939,11 @@ e1000_check_polarity(struct e1000_hw *hw,
6939 * Link Health register. In IGP this bit is latched high, so the driver must 6939 * Link Health register. In IGP this bit is latched high, so the driver must
6940 * read it immediately after link is established. 6940 * read it immediately after link is established.
6941 *****************************************************************************/ 6941 *****************************************************************************/
6942static int32_t 6942static s32
6943e1000_check_downshift(struct e1000_hw *hw) 6943e1000_check_downshift(struct e1000_hw *hw)
6944{ 6944{
6945 int32_t ret_val; 6945 s32 ret_val;
6946 uint16_t phy_data; 6946 u16 phy_data;
6947 6947
6948 DEBUGFUNC("e1000_check_downshift"); 6948 DEBUGFUNC("e1000_check_downshift");
6949 6949
@@ -6985,18 +6985,18 @@ e1000_check_downshift(struct e1000_hw *hw)
6985 * 6985 *
6986 ****************************************************************************/ 6986 ****************************************************************************/
6987 6987
6988static int32_t 6988static s32
6989e1000_config_dsp_after_link_change(struct e1000_hw *hw, 6989e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6990 bool link_up) 6990 bool link_up)
6991{ 6991{
6992 int32_t ret_val; 6992 s32 ret_val;
6993 uint16_t phy_data, phy_saved_data, speed, duplex, i; 6993 u16 phy_data, phy_saved_data, speed, duplex, i;
6994 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6994 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6995 {IGP01E1000_PHY_AGC_PARAM_A, 6995 {IGP01E1000_PHY_AGC_PARAM_A,
6996 IGP01E1000_PHY_AGC_PARAM_B, 6996 IGP01E1000_PHY_AGC_PARAM_B,
6997 IGP01E1000_PHY_AGC_PARAM_C, 6997 IGP01E1000_PHY_AGC_PARAM_C,
6998 IGP01E1000_PHY_AGC_PARAM_D}; 6998 IGP01E1000_PHY_AGC_PARAM_D};
6999 uint16_t min_length, max_length; 6999 u16 min_length, max_length;
7000 7000
7001 DEBUGFUNC("e1000_config_dsp_after_link_change"); 7001 DEBUGFUNC("e1000_config_dsp_after_link_change");
7002 7002
@@ -7038,8 +7038,8 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7038 if ((hw->ffe_config_state == e1000_ffe_config_enabled) && 7038 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7039 (min_length < e1000_igp_cable_length_50)) { 7039 (min_length < e1000_igp_cable_length_50)) {
7040 7040
7041 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7041 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7042 uint32_t idle_errs = 0; 7042 u32 idle_errs = 0;
7043 7043
7044 /* clear previous idle error counts */ 7044 /* clear previous idle error counts */
7045 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7045 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
@@ -7173,11 +7173,11 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7173 * 7173 *
7174 * hw - Struct containing variables accessed by shared code 7174 * hw - Struct containing variables accessed by shared code
7175 ****************************************************************************/ 7175 ****************************************************************************/
7176static int32_t 7176static s32
7177e1000_set_phy_mode(struct e1000_hw *hw) 7177e1000_set_phy_mode(struct e1000_hw *hw)
7178{ 7178{
7179 int32_t ret_val; 7179 s32 ret_val;
7180 uint16_t eeprom_data; 7180 u16 eeprom_data;
7181 7181
7182 DEBUGFUNC("e1000_set_phy_mode"); 7182 DEBUGFUNC("e1000_set_phy_mode");
7183 7183
@@ -7218,13 +7218,13 @@ e1000_set_phy_mode(struct e1000_hw *hw)
7218 * 7218 *
7219 ****************************************************************************/ 7219 ****************************************************************************/
7220 7220
7221static int32_t 7221static s32
7222e1000_set_d3_lplu_state(struct e1000_hw *hw, 7222e1000_set_d3_lplu_state(struct e1000_hw *hw,
7223 bool active) 7223 bool active)
7224{ 7224{
7225 uint32_t phy_ctrl = 0; 7225 u32 phy_ctrl = 0;
7226 int32_t ret_val; 7226 s32 ret_val;
7227 uint16_t phy_data; 7227 u16 phy_data;
7228 DEBUGFUNC("e1000_set_d3_lplu_state"); 7228 DEBUGFUNC("e1000_set_d3_lplu_state");
7229 7229
7230 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 7230 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
@@ -7348,13 +7348,13 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7348 * 7348 *
7349 ****************************************************************************/ 7349 ****************************************************************************/
7350 7350
7351static int32_t 7351static s32
7352e1000_set_d0_lplu_state(struct e1000_hw *hw, 7352e1000_set_d0_lplu_state(struct e1000_hw *hw,
7353 bool active) 7353 bool active)
7354{ 7354{
7355 uint32_t phy_ctrl = 0; 7355 u32 phy_ctrl = 0;
7356 int32_t ret_val; 7356 s32 ret_val;
7357 uint16_t phy_data; 7357 u16 phy_data;
7358 DEBUGFUNC("e1000_set_d0_lplu_state"); 7358 DEBUGFUNC("e1000_set_d0_lplu_state");
7359 7359
7360 if (hw->mac_type <= e1000_82547_rev_2) 7360 if (hw->mac_type <= e1000_82547_rev_2)
@@ -7439,12 +7439,12 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7439 * 7439 *
7440 * hw - Struct containing variables accessed by shared code 7440 * hw - Struct containing variables accessed by shared code
7441 *****************************************************************************/ 7441 *****************************************************************************/
7442static int32_t 7442static s32
7443e1000_set_vco_speed(struct e1000_hw *hw) 7443e1000_set_vco_speed(struct e1000_hw *hw)
7444{ 7444{
7445 int32_t ret_val; 7445 s32 ret_val;
7446 uint16_t default_page = 0; 7446 u16 default_page = 0;
7447 uint16_t phy_data; 7447 u16 phy_data;
7448 7448
7449 DEBUGFUNC("e1000_set_vco_speed"); 7449 DEBUGFUNC("e1000_set_vco_speed");
7450 7450
@@ -7503,18 +7503,18 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7503 * 7503 *
7504 * returns: - E1000_SUCCESS . 7504 * returns: - E1000_SUCCESS .
7505 ****************************************************************************/ 7505 ****************************************************************************/
7506static int32_t 7506static s32
7507e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) 7507e1000_host_if_read_cookie(struct e1000_hw * hw, u8 *buffer)
7508{ 7508{
7509 uint8_t i; 7509 u8 i;
7510 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 7510 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7511 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 7511 u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
7512 7512
7513 length = (length >> 2); 7513 length = (length >> 2);
7514 offset = (offset >> 2); 7514 offset = (offset >> 2);
7515 7515
7516 for (i = 0; i < length; i++) { 7516 for (i = 0; i < length; i++) {
7517 *((uint32_t *) buffer + i) = 7517 *((u32 *) buffer + i) =
7518 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 7518 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7519 } 7519 }
7520 return E1000_SUCCESS; 7520 return E1000_SUCCESS;
@@ -7530,11 +7530,11 @@ e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7530 * timeout 7530 * timeout
7531 * - E1000_SUCCESS for success. 7531 * - E1000_SUCCESS for success.
7532 ****************************************************************************/ 7532 ****************************************************************************/
7533static int32_t 7533static s32
7534e1000_mng_enable_host_if(struct e1000_hw * hw) 7534e1000_mng_enable_host_if(struct e1000_hw * hw)
7535{ 7535{
7536 uint32_t hicr; 7536 u32 hicr;
7537 uint8_t i; 7537 u8 i;
7538 7538
7539 /* Check that the host interface is enabled. */ 7539 /* Check that the host interface is enabled. */
7540 hicr = E1000_READ_REG(hw, HICR); 7540 hicr = E1000_READ_REG(hw, HICR);
@@ -7564,14 +7564,14 @@ e1000_mng_enable_host_if(struct e1000_hw * hw)
7564 * 7564 *
7565 * returns - E1000_SUCCESS for success. 7565 * returns - E1000_SUCCESS for success.
7566 ****************************************************************************/ 7566 ****************************************************************************/
7567static int32_t 7567static s32
7568e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, 7568e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer,
7569 uint16_t length, uint16_t offset, uint8_t *sum) 7569 u16 length, u16 offset, u8 *sum)
7570{ 7570{
7571 uint8_t *tmp; 7571 u8 *tmp;
7572 uint8_t *bufptr = buffer; 7572 u8 *bufptr = buffer;
7573 uint32_t data = 0; 7573 u32 data = 0;
7574 uint16_t remaining, i, j, prev_bytes; 7574 u16 remaining, i, j, prev_bytes;
7575 7575
7576 /* sum = only sum of the data and it is not checksum */ 7576 /* sum = only sum of the data and it is not checksum */
7577 7577
@@ -7579,14 +7579,14 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7579 return -E1000_ERR_PARAM; 7579 return -E1000_ERR_PARAM;
7580 } 7580 }
7581 7581
7582 tmp = (uint8_t *)&data; 7582 tmp = (u8 *)&data;
7583 prev_bytes = offset & 0x3; 7583 prev_bytes = offset & 0x3;
7584 offset &= 0xFFFC; 7584 offset &= 0xFFFC;
7585 offset >>= 2; 7585 offset >>= 2;
7586 7586
7587 if (prev_bytes) { 7587 if (prev_bytes) {
7588 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); 7588 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7589 for (j = prev_bytes; j < sizeof(uint32_t); j++) { 7589 for (j = prev_bytes; j < sizeof(u32); j++) {
7590 *(tmp + j) = *bufptr++; 7590 *(tmp + j) = *bufptr++;
7591 *sum += *(tmp + j); 7591 *sum += *(tmp + j);
7592 } 7592 }
@@ -7604,7 +7604,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7604 /* The device driver writes the relevant command block into the 7604 /* The device driver writes the relevant command block into the
7605 * ram area. */ 7605 * ram area. */
7606 for (i = 0; i < length; i++) { 7606 for (i = 0; i < length; i++) {
7607 for (j = 0; j < sizeof(uint32_t); j++) { 7607 for (j = 0; j < sizeof(u32); j++) {
7608 *(tmp + j) = *bufptr++; 7608 *(tmp + j) = *bufptr++;
7609 *sum += *(tmp + j); 7609 *sum += *(tmp + j);
7610 } 7610 }
@@ -7612,7 +7612,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7612 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); 7612 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7613 } 7613 }
7614 if (remaining) { 7614 if (remaining) {
7615 for (j = 0; j < sizeof(uint32_t); j++) { 7615 for (j = 0; j < sizeof(u32); j++) {
7616 if (j < remaining) 7616 if (j < remaining)
7617 *(tmp + j) = *bufptr++; 7617 *(tmp + j) = *bufptr++;
7618 else 7618 else
@@ -7632,23 +7632,23 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7632 * 7632 *
7633 * returns - E1000_SUCCESS for success. 7633 * returns - E1000_SUCCESS for success.
7634 ****************************************************************************/ 7634 ****************************************************************************/
7635static int32_t 7635static s32
7636e1000_mng_write_cmd_header(struct e1000_hw * hw, 7636e1000_mng_write_cmd_header(struct e1000_hw * hw,
7637 struct e1000_host_mng_command_header * hdr) 7637 struct e1000_host_mng_command_header * hdr)
7638{ 7638{
7639 uint16_t i; 7639 u16 i;
7640 uint8_t sum; 7640 u8 sum;
7641 uint8_t *buffer; 7641 u8 *buffer;
7642 7642
7643 /* Write the whole command header structure which includes sum of 7643 /* Write the whole command header structure which includes sum of
7644 * the buffer */ 7644 * the buffer */
7645 7645
7646 uint16_t length = sizeof(struct e1000_host_mng_command_header); 7646 u16 length = sizeof(struct e1000_host_mng_command_header);
7647 7647
7648 sum = hdr->checksum; 7648 sum = hdr->checksum;
7649 hdr->checksum = 0; 7649 hdr->checksum = 0;
7650 7650
7651 buffer = (uint8_t *) hdr; 7651 buffer = (u8 *) hdr;
7652 i = length; 7652 i = length;
7653 while (i--) 7653 while (i--)
7654 sum += buffer[i]; 7654 sum += buffer[i];
@@ -7658,7 +7658,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7658 length >>= 2; 7658 length >>= 2;
7659 /* The device driver writes the relevant command block into the ram area. */ 7659 /* The device driver writes the relevant command block into the ram area. */
7660 for (i = 0; i < length; i++) { 7660 for (i = 0; i < length; i++) {
7661 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); 7661 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *) hdr + i));
7662 E1000_WRITE_FLUSH(hw); 7662 E1000_WRITE_FLUSH(hw);
7663 } 7663 }
7664 7664
@@ -7672,10 +7672,10 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7672 * 7672 *
7673 * returns - E1000_SUCCESS for success. 7673 * returns - E1000_SUCCESS for success.
7674 ****************************************************************************/ 7674 ****************************************************************************/
7675static int32_t 7675static s32
7676e1000_mng_write_commit(struct e1000_hw * hw) 7676e1000_mng_write_commit(struct e1000_hw * hw)
7677{ 7677{
7678 uint32_t hicr; 7678 u32 hicr;
7679 7679
7680 hicr = E1000_READ_REG(hw, HICR); 7680 hicr = E1000_READ_REG(hw, HICR);
7681 /* Setting this bit tells the ARC that a new command is pending. */ 7681 /* Setting this bit tells the ARC that a new command is pending. */
@@ -7693,7 +7693,7 @@ e1000_mng_write_commit(struct e1000_hw * hw)
7693bool 7693bool
7694e1000_check_mng_mode(struct e1000_hw *hw) 7694e1000_check_mng_mode(struct e1000_hw *hw)
7695{ 7695{
7696 uint32_t fwsm; 7696 u32 fwsm;
7697 7697
7698 fwsm = E1000_READ_REG(hw, FWSM); 7698 fwsm = E1000_READ_REG(hw, FWSM);
7699 7699
@@ -7712,11 +7712,11 @@ e1000_check_mng_mode(struct e1000_hw *hw)
7712/***************************************************************************** 7712/*****************************************************************************
7713 * This function writes the dhcp info . 7713 * This function writes the dhcp info .
7714 ****************************************************************************/ 7714 ****************************************************************************/
7715int32_t 7715s32
7716e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, 7716e1000_mng_write_dhcp_info(struct e1000_hw * hw, u8 *buffer,
7717 uint16_t length) 7717 u16 length)
7718{ 7718{
7719 int32_t ret_val; 7719 s32 ret_val;
7720 struct e1000_host_mng_command_header hdr; 7720 struct e1000_host_mng_command_header hdr;
7721 7721
7722 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; 7722 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
@@ -7744,11 +7744,11 @@ e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7744 * 7744 *
7745 * returns - checksum of buffer contents. 7745 * returns - checksum of buffer contents.
7746 ****************************************************************************/ 7746 ****************************************************************************/
7747static uint8_t 7747static u8
7748e1000_calculate_mng_checksum(char *buffer, uint32_t length) 7748e1000_calculate_mng_checksum(char *buffer, u32 length)
7749{ 7749{
7750 uint8_t sum = 0; 7750 u8 sum = 0;
7751 uint32_t i; 7751 u32 i;
7752 7752
7753 if (!buffer) 7753 if (!buffer)
7754 return 0; 7754 return 0;
@@ -7756,7 +7756,7 @@ e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7756 for (i=0; i < length; i++) 7756 for (i=0; i < length; i++)
7757 sum += buffer[i]; 7757 sum += buffer[i];
7758 7758
7759 return (uint8_t) (0 - sum); 7759 return (u8) (0 - sum);
7760} 7760}
7761 7761
7762/***************************************************************************** 7762/*****************************************************************************
@@ -7769,10 +7769,10 @@ e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7769{ 7769{
7770 /* called in init as well as watchdog timer functions */ 7770 /* called in init as well as watchdog timer functions */
7771 7771
7772 int32_t ret_val, checksum; 7772 s32 ret_val, checksum;
7773 bool tx_filter = false; 7773 bool tx_filter = false;
7774 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 7774 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7775 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); 7775 u8 *buffer = (u8 *) &(hw->mng_cookie);
7776 7776
7777 if (e1000_check_mng_mode(hw)) { 7777 if (e1000_check_mng_mode(hw)) {
7778 ret_val = e1000_mng_enable_host_if(hw); 7778 ret_val = e1000_mng_enable_host_if(hw);
@@ -7806,11 +7806,11 @@ e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7806 * returns: - true/false 7806 * returns: - true/false
7807 * 7807 *
7808 *****************************************************************************/ 7808 *****************************************************************************/
7809uint32_t 7809u32
7810e1000_enable_mng_pass_thru(struct e1000_hw *hw) 7810e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7811{ 7811{
7812 uint32_t manc; 7812 u32 manc;
7813 uint32_t fwsm, factps; 7813 u32 fwsm, factps;
7814 7814
7815 if (hw->asf_firmware_present) { 7815 if (hw->asf_firmware_present) {
7816 manc = E1000_READ_REG(hw, MANC); 7816 manc = E1000_READ_REG(hw, MANC);
@@ -7832,12 +7832,12 @@ e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7832 return false; 7832 return false;
7833} 7833}
7834 7834
7835static int32_t 7835static s32
7836e1000_polarity_reversal_workaround(struct e1000_hw *hw) 7836e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7837{ 7837{
7838 int32_t ret_val; 7838 s32 ret_val;
7839 uint16_t mii_status_reg; 7839 u16 mii_status_reg;
7840 uint16_t i; 7840 u16 i;
7841 7841
7842 /* Polarity reversal workaround for forced 10F/10H links. */ 7842 /* Polarity reversal workaround for forced 10F/10H links. */
7843 7843
@@ -7929,7 +7929,7 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7929static void 7929static void
7930e1000_set_pci_express_master_disable(struct e1000_hw *hw) 7930e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7931{ 7931{
7932 uint32_t ctrl; 7932 u32 ctrl;
7933 7933
7934 DEBUGFUNC("e1000_set_pci_express_master_disable"); 7934 DEBUGFUNC("e1000_set_pci_express_master_disable");
7935 7935
@@ -7952,10 +7952,10 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7952 * E1000_SUCCESS master requests disabled. 7952 * E1000_SUCCESS master requests disabled.
7953 * 7953 *
7954 ******************************************************************************/ 7954 ******************************************************************************/
7955int32_t 7955s32
7956e1000_disable_pciex_master(struct e1000_hw *hw) 7956e1000_disable_pciex_master(struct e1000_hw *hw)
7957{ 7957{
7958 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 7958 s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7959 7959
7960 DEBUGFUNC("e1000_disable_pciex_master"); 7960 DEBUGFUNC("e1000_disable_pciex_master");
7961 7961
@@ -7990,10 +7990,10 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
7990 * E1000_SUCCESS at any other case. 7990 * E1000_SUCCESS at any other case.
7991 * 7991 *
7992 ******************************************************************************/ 7992 ******************************************************************************/
7993static int32_t 7993static s32
7994e1000_get_auto_rd_done(struct e1000_hw *hw) 7994e1000_get_auto_rd_done(struct e1000_hw *hw)
7995{ 7995{
7996 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 7996 s32 timeout = AUTO_READ_DONE_TIMEOUT;
7997 7997
7998 DEBUGFUNC("e1000_get_auto_rd_done"); 7998 DEBUGFUNC("e1000_get_auto_rd_done");
7999 7999
@@ -8038,11 +8038,11 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8038 * E1000_SUCCESS at any other case. 8038 * E1000_SUCCESS at any other case.
8039 * 8039 *
8040 ***************************************************************************/ 8040 ***************************************************************************/
8041static int32_t 8041static s32
8042e1000_get_phy_cfg_done(struct e1000_hw *hw) 8042e1000_get_phy_cfg_done(struct e1000_hw *hw)
8043{ 8043{
8044 int32_t timeout = PHY_CFG_TIMEOUT; 8044 s32 timeout = PHY_CFG_TIMEOUT;
8045 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 8045 u32 cfg_mask = E1000_EEPROM_CFG_DONE;
8046 8046
8047 DEBUGFUNC("e1000_get_phy_cfg_done"); 8047 DEBUGFUNC("e1000_get_phy_cfg_done");
8048 8048
@@ -8085,11 +8085,11 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
8085 * E1000_SUCCESS at any other case. 8085 * E1000_SUCCESS at any other case.
8086 * 8086 *
8087 ***************************************************************************/ 8087 ***************************************************************************/
8088static int32_t 8088static s32
8089e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) 8089e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8090{ 8090{
8091 int32_t timeout; 8091 s32 timeout;
8092 uint32_t swsm; 8092 u32 swsm;
8093 8093
8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); 8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8095 8095
@@ -8138,7 +8138,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8138static void 8138static void
8139e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) 8139e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8140{ 8140{
8141 uint32_t swsm; 8141 u32 swsm;
8142 8142
8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); 8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8144 8144
@@ -8164,11 +8164,11 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8164 * E1000_SUCCESS at any other case. 8164 * E1000_SUCCESS at any other case.
8165 * 8165 *
8166 ***************************************************************************/ 8166 ***************************************************************************/
8167static int32_t 8167static s32
8168e1000_get_software_semaphore(struct e1000_hw *hw) 8168e1000_get_software_semaphore(struct e1000_hw *hw)
8169{ 8169{
8170 int32_t timeout = hw->eeprom.word_size + 1; 8170 s32 timeout = hw->eeprom.word_size + 1;
8171 uint32_t swsm; 8171 u32 swsm;
8172 8172
8173 DEBUGFUNC("e1000_get_software_semaphore"); 8173 DEBUGFUNC("e1000_get_software_semaphore");
8174 8174
@@ -8203,7 +8203,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8203static void 8203static void
8204e1000_release_software_semaphore(struct e1000_hw *hw) 8204e1000_release_software_semaphore(struct e1000_hw *hw)
8205{ 8205{
8206 uint32_t swsm; 8206 u32 swsm;
8207 8207
8208 DEBUGFUNC("e1000_release_software_semaphore"); 8208 DEBUGFUNC("e1000_release_software_semaphore");
8209 8209
@@ -8228,11 +8228,11 @@ e1000_release_software_semaphore(struct e1000_hw *hw)
8228 * E1000_SUCCESS 8228 * E1000_SUCCESS
8229 * 8229 *
8230 *****************************************************************************/ 8230 *****************************************************************************/
8231int32_t 8231s32
8232e1000_check_phy_reset_block(struct e1000_hw *hw) 8232e1000_check_phy_reset_block(struct e1000_hw *hw)
8233{ 8233{
8234 uint32_t manc = 0; 8234 u32 manc = 0;
8235 uint32_t fwsm = 0; 8235 u32 fwsm = 0;
8236 8236
8237 if (hw->mac_type == e1000_ich8lan) { 8237 if (hw->mac_type == e1000_ich8lan) {
8238 fwsm = E1000_READ_REG(hw, FWSM); 8238 fwsm = E1000_READ_REG(hw, FWSM);
@@ -8246,10 +8246,10 @@ e1000_check_phy_reset_block(struct e1000_hw *hw)
8246 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8246 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8247} 8247}
8248 8248
8249static uint8_t 8249static u8
8250e1000_arc_subsystem_valid(struct e1000_hw *hw) 8250e1000_arc_subsystem_valid(struct e1000_hw *hw)
8251{ 8251{
8252 uint32_t fwsm; 8252 u32 fwsm;
8253 8253
8254 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC 8254 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8255 * may not be provided a DMA clock when no manageability features are 8255 * may not be provided a DMA clock when no manageability features are
@@ -8283,10 +8283,10 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
8283 * returns: E1000_SUCCESS 8283 * returns: E1000_SUCCESS
8284 * 8284 *
8285 *****************************************************************************/ 8285 *****************************************************************************/
8286static int32_t 8286static s32
8287e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) 8287e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8288{ 8288{
8289 uint32_t gcr_reg = 0; 8289 u32 gcr_reg = 0;
8290 8290
8291 DEBUGFUNC("e1000_set_pci_ex_no_snoop"); 8291 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8292 8292
@@ -8303,7 +8303,7 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8303 E1000_WRITE_REG(hw, GCR, gcr_reg); 8303 E1000_WRITE_REG(hw, GCR, gcr_reg);
8304 } 8304 }
8305 if (hw->mac_type == e1000_ich8lan) { 8305 if (hw->mac_type == e1000_ich8lan) {
8306 uint32_t ctrl_ext; 8306 u32 ctrl_ext;
8307 8307
8308 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); 8308 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8309 8309
@@ -8324,11 +8324,11 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8324 * hw: Struct containing variables accessed by shared code 8324 * hw: Struct containing variables accessed by shared code
8325 * 8325 *
8326 ***************************************************************************/ 8326 ***************************************************************************/
8327static int32_t 8327static s32
8328e1000_get_software_flag(struct e1000_hw *hw) 8328e1000_get_software_flag(struct e1000_hw *hw)
8329{ 8329{
8330 int32_t timeout = PHY_CFG_TIMEOUT; 8330 s32 timeout = PHY_CFG_TIMEOUT;
8331 uint32_t extcnf_ctrl; 8331 u32 extcnf_ctrl;
8332 8332
8333 DEBUGFUNC("e1000_get_software_flag"); 8333 DEBUGFUNC("e1000_get_software_flag");
8334 8334
@@ -8366,7 +8366,7 @@ e1000_get_software_flag(struct e1000_hw *hw)
8366static void 8366static void
8367e1000_release_software_flag(struct e1000_hw *hw) 8367e1000_release_software_flag(struct e1000_hw *hw)
8368{ 8368{
8369 uint32_t extcnf_ctrl; 8369 u32 extcnf_ctrl;
8370 8370
8371 DEBUGFUNC("e1000_release_software_flag"); 8371 DEBUGFUNC("e1000_release_software_flag");
8372 8372
@@ -8388,16 +8388,16 @@ e1000_release_software_flag(struct e1000_hw *hw)
8388 * data - word read from the EEPROM 8388 * data - word read from the EEPROM
8389 * words - number of words to read 8389 * words - number of words to read
8390 *****************************************************************************/ 8390 *****************************************************************************/
8391static int32_t 8391static s32
8392e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, 8392e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8393 uint16_t *data) 8393 u16 *data)
8394{ 8394{
8395 int32_t error = E1000_SUCCESS; 8395 s32 error = E1000_SUCCESS;
8396 uint32_t flash_bank = 0; 8396 u32 flash_bank = 0;
8397 uint32_t act_offset = 0; 8397 u32 act_offset = 0;
8398 uint32_t bank_offset = 0; 8398 u32 bank_offset = 0;
8399 uint16_t word = 0; 8399 u16 word = 0;
8400 uint16_t i = 0; 8400 u16 i = 0;
8401 8401
8402 /* We need to know which is the valid flash bank. In the event 8402 /* We need to know which is the valid flash bank. In the event
8403 * that we didn't allocate eeprom_shadow_ram, we may not be 8403 * that we didn't allocate eeprom_shadow_ram, we may not be
@@ -8444,12 +8444,12 @@ e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8444 * words - number of words to write 8444 * words - number of words to write
8445 * data - words to write to the EEPROM 8445 * data - words to write to the EEPROM
8446 *****************************************************************************/ 8446 *****************************************************************************/
8447static int32_t 8447static s32
8448e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, 8448e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8449 uint16_t *data) 8449 u16 *data)
8450{ 8450{
8451 uint32_t i = 0; 8451 u32 i = 0;
8452 int32_t error = E1000_SUCCESS; 8452 s32 error = E1000_SUCCESS;
8453 8453
8454 error = e1000_get_software_flag(hw); 8454 error = e1000_get_software_flag(hw);
8455 if (error != E1000_SUCCESS) 8455 if (error != E1000_SUCCESS)
@@ -8491,12 +8491,12 @@ e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8491 * 8491 *
8492 * hw - The pointer to the hw structure 8492 * hw - The pointer to the hw structure
8493 ****************************************************************************/ 8493 ****************************************************************************/
8494static int32_t 8494static s32
8495e1000_ich8_cycle_init(struct e1000_hw *hw) 8495e1000_ich8_cycle_init(struct e1000_hw *hw)
8496{ 8496{
8497 union ich8_hws_flash_status hsfsts; 8497 union ich8_hws_flash_status hsfsts;
8498 int32_t error = E1000_ERR_EEPROM; 8498 s32 error = E1000_ERR_EEPROM;
8499 int32_t i = 0; 8499 s32 i = 0;
8500 8500
8501 DEBUGFUNC("e1000_ich8_cycle_init"); 8501 DEBUGFUNC("e1000_ich8_cycle_init");
8502 8502
@@ -8558,13 +8558,13 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8558 * 8558 *
8559 * hw - The pointer to the hw structure 8559 * hw - The pointer to the hw structure
8560 ****************************************************************************/ 8560 ****************************************************************************/
8561static int32_t 8561static s32
8562e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) 8562e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8563{ 8563{
8564 union ich8_hws_flash_ctrl hsflctl; 8564 union ich8_hws_flash_ctrl hsflctl;
8565 union ich8_hws_flash_status hsfsts; 8565 union ich8_hws_flash_status hsfsts;
8566 int32_t error = E1000_ERR_EEPROM; 8566 s32 error = E1000_ERR_EEPROM;
8567 uint32_t i = 0; 8567 u32 i = 0;
8568 8568
8569 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 8569 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8570 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 8570 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
@@ -8593,16 +8593,16 @@ e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8593 * size - Size of data to read, 1=byte 2=word 8593 * size - Size of data to read, 1=byte 2=word
8594 * data - Pointer to the word to store the value read. 8594 * data - Pointer to the word to store the value read.
8595 *****************************************************************************/ 8595 *****************************************************************************/
8596static int32_t 8596static s32
8597e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, 8597e1000_read_ich8_data(struct e1000_hw *hw, u32 index,
8598 uint32_t size, uint16_t* data) 8598 u32 size, u16* data)
8599{ 8599{
8600 union ich8_hws_flash_status hsfsts; 8600 union ich8_hws_flash_status hsfsts;
8601 union ich8_hws_flash_ctrl hsflctl; 8601 union ich8_hws_flash_ctrl hsflctl;
8602 uint32_t flash_linear_address; 8602 u32 flash_linear_address;
8603 uint32_t flash_data = 0; 8603 u32 flash_data = 0;
8604 int32_t error = -E1000_ERR_EEPROM; 8604 s32 error = -E1000_ERR_EEPROM;
8605 int32_t count = 0; 8605 s32 count = 0;
8606 8606
8607 DEBUGFUNC("e1000_read_ich8_data"); 8607 DEBUGFUNC("e1000_read_ich8_data");
8608 8608
@@ -8640,9 +8640,9 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8640 if (error == E1000_SUCCESS) { 8640 if (error == E1000_SUCCESS) {
8641 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); 8641 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8642 if (size == 1) { 8642 if (size == 1) {
8643 *data = (uint8_t)(flash_data & 0x000000FF); 8643 *data = (u8)(flash_data & 0x000000FF);
8644 } else if (size == 2) { 8644 } else if (size == 2) {
8645 *data = (uint16_t)(flash_data & 0x0000FFFF); 8645 *data = (u16)(flash_data & 0x0000FFFF);
8646 } 8646 }
8647 break; 8647 break;
8648 } else { 8648 } else {
@@ -8672,16 +8672,16 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8672 * size - Size of data to read, 1=byte 2=word 8672 * size - Size of data to read, 1=byte 2=word
8673 * data - The byte(s) to write to the NVM. 8673 * data - The byte(s) to write to the NVM.
8674 *****************************************************************************/ 8674 *****************************************************************************/
8675static int32_t 8675static s32
8676e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, 8676e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8677 uint16_t data) 8677 u16 data)
8678{ 8678{
8679 union ich8_hws_flash_status hsfsts; 8679 union ich8_hws_flash_status hsfsts;
8680 union ich8_hws_flash_ctrl hsflctl; 8680 union ich8_hws_flash_ctrl hsflctl;
8681 uint32_t flash_linear_address; 8681 u32 flash_linear_address;
8682 uint32_t flash_data = 0; 8682 u32 flash_data = 0;
8683 int32_t error = -E1000_ERR_EEPROM; 8683 s32 error = -E1000_ERR_EEPROM;
8684 int32_t count = 0; 8684 s32 count = 0;
8685 8685
8686 DEBUGFUNC("e1000_write_ich8_data"); 8686 DEBUGFUNC("e1000_write_ich8_data");
8687 8687
@@ -8710,9 +8710,9 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8710 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 8710 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8711 8711
8712 if (size == 1) 8712 if (size == 1)
8713 flash_data = (uint32_t)data & 0x00FF; 8713 flash_data = (u32)data & 0x00FF;
8714 else 8714 else
8715 flash_data = (uint32_t)data; 8715 flash_data = (u32)data;
8716 8716
8717 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 8717 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8718 8718
@@ -8747,15 +8747,15 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8747 * index - The index of the byte to read. 8747 * index - The index of the byte to read.
8748 * data - Pointer to a byte to store the value read. 8748 * data - Pointer to a byte to store the value read.
8749 *****************************************************************************/ 8749 *****************************************************************************/
8750static int32_t 8750static s32
8751e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) 8751e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8* data)
8752{ 8752{
8753 int32_t status = E1000_SUCCESS; 8753 s32 status = E1000_SUCCESS;
8754 uint16_t word = 0; 8754 u16 word = 0;
8755 8755
8756 status = e1000_read_ich8_data(hw, index, 1, &word); 8756 status = e1000_read_ich8_data(hw, index, 1, &word);
8757 if (status == E1000_SUCCESS) { 8757 if (status == E1000_SUCCESS) {
8758 *data = (uint8_t)word; 8758 *data = (u8)word;
8759 } 8759 }
8760 8760
8761 return status; 8761 return status;
@@ -8770,11 +8770,11 @@ e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8770 * index - The index of the byte to write. 8770 * index - The index of the byte to write.
8771 * byte - The byte to write to the NVM. 8771 * byte - The byte to write to the NVM.
8772 *****************************************************************************/ 8772 *****************************************************************************/
8773static int32_t 8773static s32
8774e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) 8774e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8775{ 8775{
8776 int32_t error = E1000_SUCCESS; 8776 s32 error = E1000_SUCCESS;
8777 int32_t program_retries = 0; 8777 s32 program_retries = 0;
8778 8778
8779 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 8779 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8780 8780
@@ -8803,11 +8803,11 @@ e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8803 * index - The index of the byte to read. 8803 * index - The index of the byte to read.
8804 * data - The byte to write to the NVM. 8804 * data - The byte to write to the NVM.
8805 *****************************************************************************/ 8805 *****************************************************************************/
8806static int32_t 8806static s32
8807e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) 8807e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8808{ 8808{
8809 int32_t status = E1000_SUCCESS; 8809 s32 status = E1000_SUCCESS;
8810 uint16_t word = (uint16_t)data; 8810 u16 word = (u16)data;
8811 8811
8812 status = e1000_write_ich8_data(hw, index, 1, word); 8812 status = e1000_write_ich8_data(hw, index, 1, word);
8813 8813
@@ -8821,10 +8821,10 @@ e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8821 * index - The starting byte index of the word to read. 8821 * index - The starting byte index of the word to read.
8822 * data - Pointer to a word to store the value read. 8822 * data - Pointer to a word to store the value read.
8823 *****************************************************************************/ 8823 *****************************************************************************/
8824static int32_t 8824static s32
8825e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) 8825e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8826{ 8826{
8827 int32_t status = E1000_SUCCESS; 8827 s32 status = E1000_SUCCESS;
8828 status = e1000_read_ich8_data(hw, index, 2, data); 8828 status = e1000_read_ich8_data(hw, index, 2, data);
8829 return status; 8829 return status;
8830} 8830}
@@ -8840,19 +8840,19 @@ e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8840 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 8840 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8841 * bank size may be 4, 8 or 64 KBytes 8841 * bank size may be 4, 8 or 64 KBytes
8842 *****************************************************************************/ 8842 *****************************************************************************/
8843static int32_t 8843static s32
8844e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) 8844e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8845{ 8845{
8846 union ich8_hws_flash_status hsfsts; 8846 union ich8_hws_flash_status hsfsts;
8847 union ich8_hws_flash_ctrl hsflctl; 8847 union ich8_hws_flash_ctrl hsflctl;
8848 uint32_t flash_linear_address; 8848 u32 flash_linear_address;
8849 int32_t count = 0; 8849 s32 count = 0;
8850 int32_t error = E1000_ERR_EEPROM; 8850 s32 error = E1000_ERR_EEPROM;
8851 int32_t iteration; 8851 s32 iteration;
8852 int32_t sub_sector_size = 0; 8852 s32 sub_sector_size = 0;
8853 int32_t bank_size; 8853 s32 bank_size;
8854 int32_t j = 0; 8854 s32 j = 0;
8855 int32_t error_flag = 0; 8855 s32 error_flag = 0;
8856 8856
8857 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8857 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8858 8858
@@ -8930,16 +8930,16 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8930 return error; 8930 return error;
8931} 8931}
8932 8932
8933static int32_t 8933static s32
8934e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, 8934e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8935 uint32_t cnf_base_addr, uint32_t cnf_size) 8935 u32 cnf_base_addr, u32 cnf_size)
8936{ 8936{
8937 uint32_t ret_val = E1000_SUCCESS; 8937 u32 ret_val = E1000_SUCCESS;
8938 uint16_t word_addr, reg_data, reg_addr; 8938 u16 word_addr, reg_data, reg_addr;
8939 uint16_t i; 8939 u16 i;
8940 8940
8941 /* cnf_base_addr is in DWORD */ 8941 /* cnf_base_addr is in DWORD */
8942 word_addr = (uint16_t)(cnf_base_addr << 1); 8942 word_addr = (u16)(cnf_base_addr << 1);
8943 8943
8944 /* cnf_size is returned in size of dwords */ 8944 /* cnf_size is returned in size of dwords */
8945 for (i = 0; i < cnf_size; i++) { 8945 for (i = 0; i < cnf_size; i++) {
@@ -8955,7 +8955,7 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8955 if (ret_val != E1000_SUCCESS) 8955 if (ret_val != E1000_SUCCESS)
8956 return ret_val; 8956 return ret_val;
8957 8957
8958 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); 8958 ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
8959 8959
8960 e1000_release_software_flag(hw); 8960 e1000_release_software_flag(hw);
8961 } 8961 }
@@ -8972,10 +8972,10 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8972 * 8972 *
8973 * hw: Struct containing variables accessed by shared code 8973 * hw: Struct containing variables accessed by shared code
8974 *****************************************************************************/ 8974 *****************************************************************************/
8975static int32_t 8975static s32
8976e1000_init_lcd_from_nvm(struct e1000_hw *hw) 8976e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8977{ 8977{
8978 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; 8978 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8979 8979
8980 if (hw->phy_type != e1000_phy_igp_3) 8980 if (hw->phy_type != e1000_phy_igp_3)
8981 return E1000_SUCCESS; 8981 return E1000_SUCCESS;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-05 13:23:45 -0500