diff options
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r-- | drivers/net/e1000/e1000_hw.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 2437d362ff63..beeec0fbbeac 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -1600,10 +1600,10 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw) | |||
1600 | if(ret_val) | 1600 | if(ret_val) |
1601 | return ret_val; | 1601 | return ret_val; |
1602 | 1602 | ||
1603 | /* Read the MII 1000Base-T Control Register (Address 9). */ | 1603 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
1604 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | 1604 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
1605 | if(ret_val) | 1605 | if(ret_val) |
1606 | return ret_val; | 1606 | return ret_val; |
1607 | 1607 | ||
1608 | /* Need to parse both autoneg_advertised and fc and set up | 1608 | /* Need to parse both autoneg_advertised and fc and set up |
1609 | * the appropriate PHY registers. First we will parse for | 1609 | * the appropriate PHY registers. First we will parse for |
@@ -3916,7 +3916,7 @@ e1000_read_eeprom(struct e1000_hw *hw, | |||
3916 | } | 3916 | } |
3917 | } | 3917 | } |
3918 | 3918 | ||
3919 | if(eeprom->use_eerd == TRUE) { | 3919 | if (eeprom->use_eerd == TRUE) { |
3920 | ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); | 3920 | ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); |
3921 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || | 3921 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || |
3922 | (hw->mac_type != e1000_82573)) | 3922 | (hw->mac_type != e1000_82573)) |
@@ -4423,7 +4423,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) | |||
4423 | return -E1000_ERR_EEPROM; | 4423 | return -E1000_ERR_EEPROM; |
4424 | } | 4424 | } |
4425 | 4425 | ||
4426 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ | 4426 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
4427 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { | 4427 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
4428 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); | 4428 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); |
4429 | } | 4429 | } |
@@ -4431,7 +4431,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) | |||
4431 | /* Perform the flash update */ | 4431 | /* Perform the flash update */ |
4432 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); | 4432 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); |
4433 | 4433 | ||
4434 | for (i=0; i < attempts; i++) { | 4434 | for (i=0; i < attempts; i++) { |
4435 | eecd = E1000_READ_REG(hw, EECD); | 4435 | eecd = E1000_READ_REG(hw, EECD); |
4436 | if ((eecd & E1000_EECD_FLUPD) == 0) { | 4436 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
4437 | break; | 4437 | break; |
@@ -4504,6 +4504,7 @@ e1000_read_mac_addr(struct e1000_hw * hw) | |||
4504 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); | 4504 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); |
4505 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); | 4505 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); |
4506 | } | 4506 | } |
4507 | |||
4507 | switch (hw->mac_type) { | 4508 | switch (hw->mac_type) { |
4508 | default: | 4509 | default: |
4509 | break; | 4510 | break; |
@@ -6840,7 +6841,8 @@ int32_t | |||
6840 | e1000_check_phy_reset_block(struct e1000_hw *hw) | 6841 | e1000_check_phy_reset_block(struct e1000_hw *hw) |
6841 | { | 6842 | { |
6842 | uint32_t manc = 0; | 6843 | uint32_t manc = 0; |
6843 | if(hw->mac_type > e1000_82547_rev_2) | 6844 | |
6845 | if (hw->mac_type > e1000_82547_rev_2) | ||
6844 | manc = E1000_READ_REG(hw, MANC); | 6846 | manc = E1000_READ_REG(hw, MANC); |
6845 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | 6847 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
6846 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | 6848 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |