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-rw-r--r--drivers/net/e1000/e1000_hw.c12914
1 files changed, 4858 insertions, 8056 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 45ac225a7aaa..8d7d87f12827 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -24,88 +24,34 @@
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 26
27*******************************************************************************/ 27 */
28 28
29/* e1000_hw.c 29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC 30 * Shared functions for accessing and configuring the MAC
31 */ 31 */
32 32
33
34#include "e1000_hw.h" 33#include "e1000_hw.h"
35 34
36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
38static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
39static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
40static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static s32 e1000_check_downshift(struct e1000_hw *hw); 35static s32 e1000_check_downshift(struct e1000_hw *hw);
45static s32 e1000_check_polarity(struct e1000_hw *hw, 36static s32 e1000_check_polarity(struct e1000_hw *hw,
46 e1000_rev_polarity *polarity); 37 e1000_rev_polarity *polarity);
47static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 38static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
48static void e1000_clear_vfta(struct e1000_hw *hw); 39static void e1000_clear_vfta(struct e1000_hw *hw);
49static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
50static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
51 bool link_up); 41 bool link_up);
52static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
53static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 43static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
54static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
55static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
56static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
57 u16 *max_length); 46 u16 *max_length);
58static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
59static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
60static s32 e1000_get_software_flag(struct e1000_hw *hw);
61static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
62static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
63static s32 e1000_id_led_init(struct e1000_hw *hw); 48static s32 e1000_id_led_init(struct e1000_hw *hw);
64static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
65 u32 cnf_base_addr,
66 u32 cnf_size);
67static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
68static void e1000_init_rx_addrs(struct e1000_hw *hw); 49static void e1000_init_rx_addrs(struct e1000_hw *hw);
69static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
70static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
71static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
72static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
73static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
74 u16 offset, u8 *sum);
75static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
76 struct e1000_host_mng_command_header
77 *hdr);
78static s32 e1000_mng_write_commit(struct e1000_hw *hw);
79static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
80 struct e1000_phy_info *phy_info);
81static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
82 struct e1000_phy_info *phy_info); 51 struct e1000_phy_info *phy_info);
83static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
84 u16 *data);
85static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
86 u16 *data);
87static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
88static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
89 struct e1000_phy_info *phy_info); 53 struct e1000_phy_info *phy_info);
90static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
91static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
92static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
93 u8 byte);
94static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
95static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
96static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
97 u16 *data);
98static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
99 u16 data);
100static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
101 u16 *data);
102static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
103 u16 *data);
104static void e1000_release_software_flag(struct e1000_hw *hw);
105static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
106static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
107static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
108static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
109static s32 e1000_wait_autoneg(struct e1000_hw *hw); 55static s32 e1000_wait_autoneg(struct e1000_hw *hw);
110static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); 56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
111static s32 e1000_set_phy_type(struct e1000_hw *hw); 57static s32 e1000_set_phy_type(struct e1000_hw *hw);
@@ -117,12 +63,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
117static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); 63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
118static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
119static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
120static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, 66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
121 u16 count);
122static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
123static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
124static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
125 u16 words, u16 *data); 70 u16 words, u16 *data);
126static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
127 u16 words, u16 *data); 72 u16 words, u16 *data);
128static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
@@ -131,7 +76,7 @@ static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
131static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); 76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
132static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
133 u16 phy_data); 78 u16 phy_data);
134static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr, 79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
135 u16 *phy_data); 80 u16 *phy_data);
136static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
137static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 82static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
@@ -140,188 +85,164 @@ static void e1000_standby_eeprom(struct e1000_hw *hw);
140static s32 e1000_set_vco_speed(struct e1000_hw *hw); 85static s32 e1000_set_vco_speed(struct e1000_hw *hw);
141static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
142static s32 e1000_set_phy_mode(struct e1000_hw *hw); 87static s32 e1000_set_phy_mode(struct e1000_hw *hw);
143static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer); 88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
144static u8 e1000_calculate_mng_checksum(char *buffer, u32 length); 89 u16 *data);
145static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex); 90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
146static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 91 u16 *data);
147static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
148static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
149 92
150/* IGP cable length table */ 93/* IGP cable length table */
151static const 94static const
152u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
153 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
154 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
155 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
156 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
157 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
158 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
159 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 102 100,
160 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
161 104 110, 110,
162static const 105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
163u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 106 120, 120
164 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 107};
165 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
166 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
167 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
168 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
169 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
170 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
171 104, 109, 114, 118, 121, 124};
172 108
173static DEFINE_SPINLOCK(e1000_eeprom_lock); 109static DEFINE_SPINLOCK(e1000_eeprom_lock);
174 110
175/****************************************************************************** 111/**
176 * Set the phy type member in the hw struct. 112 * e1000_set_phy_type - Set the phy type member in the hw struct.
177 * 113 * @hw: Struct containing variables accessed by shared code
178 * hw - Struct containing variables accessed by shared code 114 */
179 *****************************************************************************/
180static s32 e1000_set_phy_type(struct e1000_hw *hw) 115static s32 e1000_set_phy_type(struct e1000_hw *hw)
181{ 116{
182 DEBUGFUNC("e1000_set_phy_type"); 117 DEBUGFUNC("e1000_set_phy_type");
183
184 if (hw->mac_type == e1000_undefined)
185 return -E1000_ERR_PHY_TYPE;
186
187 switch (hw->phy_id) {
188 case M88E1000_E_PHY_ID:
189 case M88E1000_I_PHY_ID:
190 case M88E1011_I_PHY_ID:
191 case M88E1111_I_PHY_ID:
192 hw->phy_type = e1000_phy_m88;
193 break;
194 case IGP01E1000_I_PHY_ID:
195 if (hw->mac_type == e1000_82541 ||
196 hw->mac_type == e1000_82541_rev_2 ||
197 hw->mac_type == e1000_82547 ||
198 hw->mac_type == e1000_82547_rev_2) {
199 hw->phy_type = e1000_phy_igp;
200 break;
201 }
202 case IGP03E1000_E_PHY_ID:
203 hw->phy_type = e1000_phy_igp_3;
204 break;
205 case IFE_E_PHY_ID:
206 case IFE_PLUS_E_PHY_ID:
207 case IFE_C_E_PHY_ID:
208 hw->phy_type = e1000_phy_ife;
209 break;
210 case GG82563_E_PHY_ID:
211 if (hw->mac_type == e1000_80003es2lan) {
212 hw->phy_type = e1000_phy_gg82563;
213 break;
214 }
215 /* Fall Through */
216 default:
217 /* Should never have loaded on this device */
218 hw->phy_type = e1000_phy_undefined;
219 return -E1000_ERR_PHY_TYPE;
220 }
221
222 return E1000_SUCCESS;
223}
224
225/******************************************************************************
226 * IGP phy init script - initializes the GbE PHY
227 *
228 * hw - Struct containing variables accessed by shared code
229 *****************************************************************************/
230static void e1000_phy_init_script(struct e1000_hw *hw)
231{
232 u32 ret_val;
233 u16 phy_saved_data;
234
235 DEBUGFUNC("e1000_phy_init_script");
236
237 if (hw->phy_init_script) {
238 msleep(20);
239
240 /* Save off the current value of register 0x2F5B to be restored at
241 * the end of this routine. */
242 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
243
244 /* Disabled the PHY transmitter */
245 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
246 118
247 msleep(20); 119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE;
248 121
249 e1000_write_phy_reg(hw,0x0000,0x0140); 122 switch (hw->phy_id) {
250 123 case M88E1000_E_PHY_ID:
251 msleep(5); 124 case M88E1000_I_PHY_ID:
252 125 case M88E1011_I_PHY_ID:
253 switch (hw->mac_type) { 126 case M88E1111_I_PHY_ID:
254 case e1000_82541: 127 hw->phy_type = e1000_phy_m88;
255 case e1000_82547: 128 break;
256 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 129 case IGP01E1000_I_PHY_ID:
257 130 if (hw->mac_type == e1000_82541 ||
258 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 131 hw->mac_type == e1000_82541_rev_2 ||
259 132 hw->mac_type == e1000_82547 ||
260 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 133 hw->mac_type == e1000_82547_rev_2) {
261 134 hw->phy_type = e1000_phy_igp;
262 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 135 break;
263 136 }
264 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 137 default:
265 138 /* Should never have loaded on this device */
266 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 139 hw->phy_type = e1000_phy_undefined;
267 140 return -E1000_ERR_PHY_TYPE;
268 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 141 }
269
270 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
271
272 e1000_write_phy_reg(hw, 0x2010, 0x0008);
273 break;
274
275 case e1000_82541_rev_2:
276 case e1000_82547_rev_2:
277 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
278 break;
279 default:
280 break;
281 }
282
283 e1000_write_phy_reg(hw, 0x0000, 0x3300);
284
285 msleep(20);
286
287 /* Now enable the transmitter */
288 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
289
290 if (hw->mac_type == e1000_82547) {
291 u16 fused, fine, coarse;
292
293 /* Move to analog registers page */
294 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
295
296 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
297 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
298 142
299 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 143 return E1000_SUCCESS;
300 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 144}
301 145
302 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 146/**
303 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 147 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
304 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 148 * @hw: Struct containing variables accessed by shared code
305 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 149 */
306 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 150static void e1000_phy_init_script(struct e1000_hw *hw)
151{
152 u32 ret_val;
153 u16 phy_saved_data;
154
155 DEBUGFUNC("e1000_phy_init_script");
156
157 if (hw->phy_init_script) {
158 msleep(20);
159
160 /* Save off the current value of register 0x2F5B to be restored at
161 * the end of this routine. */
162 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
163
164 /* Disabled the PHY transmitter */
165 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
166 msleep(20);
167
168 e1000_write_phy_reg(hw, 0x0000, 0x0140);
169 msleep(5);
170
171 switch (hw->mac_type) {
172 case e1000_82541:
173 case e1000_82547:
174 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
175 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
176 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
177 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
178 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
179 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
180 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
181 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
182 e1000_write_phy_reg(hw, 0x2010, 0x0008);
183 break;
307 184
308 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 185 case e1000_82541_rev_2:
309 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 186 case e1000_82547_rev_2:
310 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 187 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
188 break;
189 default:
190 break;
191 }
311 192
312 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); 193 e1000_write_phy_reg(hw, 0x0000, 0x3300);
313 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, 194 msleep(20);
314 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 195
315 } 196 /* Now enable the transmitter */
316 } 197 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
317 } 198
199 if (hw->mac_type == e1000_82547) {
200 u16 fused, fine, coarse;
201
202 /* Move to analog registers page */
203 e1000_read_phy_reg(hw,
204 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
205 &fused);
206
207 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
208 e1000_read_phy_reg(hw,
209 IGP01E1000_ANALOG_FUSE_STATUS,
210 &fused);
211
212 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
213 coarse =
214 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
215
216 if (coarse >
217 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
218 coarse -=
219 IGP01E1000_ANALOG_FUSE_COARSE_10;
220 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
221 } else if (coarse ==
222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
223 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
224
225 fused =
226 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
227 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
228 (coarse &
229 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
230
231 e1000_write_phy_reg(hw,
232 IGP01E1000_ANALOG_FUSE_CONTROL,
233 fused);
234 e1000_write_phy_reg(hw,
235 IGP01E1000_ANALOG_FUSE_BYPASS,
236 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
237 }
238 }
239 }
318} 240}
319 241
320/****************************************************************************** 242/**
321 * Set the mac type member in the hw struct. 243 * e1000_set_mac_type - Set the mac type member in the hw struct.
322 * 244 * @hw: Struct containing variables accessed by shared code
323 * hw - Struct containing variables accessed by shared code 245 */
324 *****************************************************************************/
325s32 e1000_set_mac_type(struct e1000_hw *hw) 246s32 e1000_set_mac_type(struct e1000_hw *hw)
326{ 247{
327 DEBUGFUNC("e1000_set_mac_type"); 248 DEBUGFUNC("e1000_set_mac_type");
@@ -397,61 +318,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
397 case E1000_DEV_ID_82547GI: 318 case E1000_DEV_ID_82547GI:
398 hw->mac_type = e1000_82547_rev_2; 319 hw->mac_type = e1000_82547_rev_2;
399 break; 320 break;
400 case E1000_DEV_ID_82571EB_COPPER:
401 case E1000_DEV_ID_82571EB_FIBER:
402 case E1000_DEV_ID_82571EB_SERDES:
403 case E1000_DEV_ID_82571EB_SERDES_DUAL:
404 case E1000_DEV_ID_82571EB_SERDES_QUAD:
405 case E1000_DEV_ID_82571EB_QUAD_COPPER:
406 case E1000_DEV_ID_82571PT_QUAD_COPPER:
407 case E1000_DEV_ID_82571EB_QUAD_FIBER:
408 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
409 hw->mac_type = e1000_82571;
410 break;
411 case E1000_DEV_ID_82572EI_COPPER:
412 case E1000_DEV_ID_82572EI_FIBER:
413 case E1000_DEV_ID_82572EI_SERDES:
414 case E1000_DEV_ID_82572EI:
415 hw->mac_type = e1000_82572;
416 break;
417 case E1000_DEV_ID_82573E:
418 case E1000_DEV_ID_82573E_IAMT:
419 case E1000_DEV_ID_82573L:
420 hw->mac_type = e1000_82573;
421 break;
422 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
423 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
424 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
425 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
426 hw->mac_type = e1000_80003es2lan;
427 break;
428 case E1000_DEV_ID_ICH8_IGP_M_AMT:
429 case E1000_DEV_ID_ICH8_IGP_AMT:
430 case E1000_DEV_ID_ICH8_IGP_C:
431 case E1000_DEV_ID_ICH8_IFE:
432 case E1000_DEV_ID_ICH8_IFE_GT:
433 case E1000_DEV_ID_ICH8_IFE_G:
434 case E1000_DEV_ID_ICH8_IGP_M:
435 hw->mac_type = e1000_ich8lan;
436 break;
437 default: 321 default:
438 /* Should never have loaded on this device */ 322 /* Should never have loaded on this device */
439 return -E1000_ERR_MAC_TYPE; 323 return -E1000_ERR_MAC_TYPE;
440 } 324 }
441 325
442 switch (hw->mac_type) { 326 switch (hw->mac_type) {
443 case e1000_ich8lan:
444 hw->swfwhw_semaphore_present = true;
445 hw->asf_firmware_present = true;
446 break;
447 case e1000_80003es2lan:
448 hw->swfw_sync_present = true;
449 /* fall through */
450 case e1000_82571:
451 case e1000_82572:
452 case e1000_82573:
453 hw->eeprom_semaphore_present = true;
454 /* fall through */
455 case e1000_82541: 327 case e1000_82541:
456 case e1000_82547: 328 case e1000_82547:
457 case e1000_82541_rev_2: 329 case e1000_82541_rev_2:
@@ -468,6058 +340,4500 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
468 if (hw->mac_type == e1000_82543) 340 if (hw->mac_type == e1000_82543)
469 hw->bad_tx_carr_stats_fd = true; 341 hw->bad_tx_carr_stats_fd = true;
470 342
471 /* capable of receiving management packets to the host */
472 if (hw->mac_type >= e1000_82571)
473 hw->has_manc2h = true;
474
475 /* In rare occasions, ESB2 systems would end up started without
476 * the RX unit being turned on.
477 */
478 if (hw->mac_type == e1000_80003es2lan)
479 hw->rx_needs_kicking = true;
480
481 if (hw->mac_type > e1000_82544) 343 if (hw->mac_type > e1000_82544)
482 hw->has_smbus = true; 344 hw->has_smbus = true;
483 345
484 return E1000_SUCCESS; 346 return E1000_SUCCESS;
485} 347}
486 348
487/***************************************************************************** 349/**
488 * Set media type and TBI compatibility. 350 * e1000_set_media_type - Set media type and TBI compatibility.
489 * 351 * @hw: Struct containing variables accessed by shared code
490 * hw - Struct containing variables accessed by shared code 352 */
491 * **************************************************************************/
492void e1000_set_media_type(struct e1000_hw *hw) 353void e1000_set_media_type(struct e1000_hw *hw)
493{ 354{
494 u32 status; 355 u32 status;
495 356
496 DEBUGFUNC("e1000_set_media_type"); 357 DEBUGFUNC("e1000_set_media_type");
497 358
498 if (hw->mac_type != e1000_82543) { 359 if (hw->mac_type != e1000_82543) {
499 /* tbi_compatibility is only valid on 82543 */ 360 /* tbi_compatibility is only valid on 82543 */
500 hw->tbi_compatibility_en = false; 361 hw->tbi_compatibility_en = false;
501 } 362 }
502 363
503 switch (hw->device_id) { 364 switch (hw->device_id) {
504 case E1000_DEV_ID_82545GM_SERDES: 365 case E1000_DEV_ID_82545GM_SERDES:
505 case E1000_DEV_ID_82546GB_SERDES: 366 case E1000_DEV_ID_82546GB_SERDES:
506 case E1000_DEV_ID_82571EB_SERDES: 367 hw->media_type = e1000_media_type_internal_serdes;
507 case E1000_DEV_ID_82571EB_SERDES_DUAL: 368 break;
508 case E1000_DEV_ID_82571EB_SERDES_QUAD: 369 default:
509 case E1000_DEV_ID_82572EI_SERDES: 370 switch (hw->mac_type) {
510 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 371 case e1000_82542_rev2_0:
511 hw->media_type = e1000_media_type_internal_serdes; 372 case e1000_82542_rev2_1:
512 break; 373 hw->media_type = e1000_media_type_fiber;
513 default: 374 break;
514 switch (hw->mac_type) { 375 default:
515 case e1000_82542_rev2_0: 376 status = er32(STATUS);
516 case e1000_82542_rev2_1: 377 if (status & E1000_STATUS_TBIMODE) {
517 hw->media_type = e1000_media_type_fiber; 378 hw->media_type = e1000_media_type_fiber;
518 break; 379 /* tbi_compatibility not valid on fiber */
519 case e1000_ich8lan: 380 hw->tbi_compatibility_en = false;
520 case e1000_82573: 381 } else {
521 /* The STATUS_TBIMODE bit is reserved or reused for the this 382 hw->media_type = e1000_media_type_copper;
522 * device. 383 }
523 */ 384 break;
524 hw->media_type = e1000_media_type_copper; 385 }
525 break; 386 }
526 default:
527 status = er32(STATUS);
528 if (status & E1000_STATUS_TBIMODE) {
529 hw->media_type = e1000_media_type_fiber;
530 /* tbi_compatibility not valid on fiber */
531 hw->tbi_compatibility_en = false;
532 } else {
533 hw->media_type = e1000_media_type_copper;
534 }
535 break;
536 }
537 }
538} 387}
539 388
540/****************************************************************************** 389/**
541 * Reset the transmit and receive units; mask and clear all interrupts. 390 * e1000_reset_hw: reset the hardware completely
391 * @hw: Struct containing variables accessed by shared code
542 * 392 *
543 * hw - Struct containing variables accessed by shared code 393 * Reset the transmit and receive units; mask and clear all interrupts.
544 *****************************************************************************/ 394 */
545s32 e1000_reset_hw(struct e1000_hw *hw) 395s32 e1000_reset_hw(struct e1000_hw *hw)
546{ 396{
547 u32 ctrl; 397 u32 ctrl;
548 u32 ctrl_ext; 398 u32 ctrl_ext;
549 u32 icr; 399 u32 icr;
550 u32 manc; 400 u32 manc;
551 u32 led_ctrl; 401 u32 led_ctrl;
552 u32 timeout; 402 s32 ret_val;
553 u32 extcnf_ctrl;
554 s32 ret_val;
555
556 DEBUGFUNC("e1000_reset_hw");
557
558 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
559 if (hw->mac_type == e1000_82542_rev2_0) {
560 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
561 e1000_pci_clear_mwi(hw);
562 }
563
564 if (hw->bus_type == e1000_bus_type_pci_express) {
565 /* Prevent the PCI-E bus from sticking if there is no TLP connection
566 * on the last TLP read/write transaction when MAC is reset.
567 */
568 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
569 DEBUGOUT("PCI-E Master disable polling has failed.\n");
570 }
571 }
572
573 /* Clear interrupt mask to stop board from generating interrupts */
574 DEBUGOUT("Masking off all interrupts\n");
575 ew32(IMC, 0xffffffff);
576
577 /* Disable the Transmit and Receive units. Then delay to allow
578 * any pending transactions to complete before we hit the MAC with
579 * the global reset.
580 */
581 ew32(RCTL, 0);
582 ew32(TCTL, E1000_TCTL_PSP);
583 E1000_WRITE_FLUSH();
584
585 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
586 hw->tbi_compatibility_on = false;
587
588 /* Delay to allow any outstanding PCI transactions to complete before
589 * resetting the device
590 */
591 msleep(10);
592
593 ctrl = er32(CTRL);
594
595 /* Must reset the PHY before resetting the MAC */
596 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
597 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
598 msleep(5);
599 }
600
601 /* Must acquire the MDIO ownership before MAC reset.
602 * Ownership defaults to firmware after a reset. */
603 if (hw->mac_type == e1000_82573) {
604 timeout = 10;
605
606 extcnf_ctrl = er32(EXTCNF_CTRL);
607 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
608
609 do {
610 ew32(EXTCNF_CTRL, extcnf_ctrl);
611 extcnf_ctrl = er32(EXTCNF_CTRL);
612
613 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
614 break;
615 else
616 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
617
618 msleep(2);
619 timeout--;
620 } while (timeout);
621 }
622
623 /* Workaround for ICH8 bit corruption issue in FIFO memory */
624 if (hw->mac_type == e1000_ich8lan) {
625 /* Set Tx and Rx buffer allocation to 8k apiece. */
626 ew32(PBA, E1000_PBA_8K);
627 /* Set Packet Buffer Size to 16k. */
628 ew32(PBS, E1000_PBS_16K);
629 }
630
631 /* Issue a global reset to the MAC. This will reset the chip's
632 * transmit, receive, DMA, and link units. It will not effect
633 * the current PCI configuration. The global reset bit is self-
634 * clearing, and should clear within a microsecond.
635 */
636 DEBUGOUT("Issuing a global reset to MAC\n");
637
638 switch (hw->mac_type) {
639 case e1000_82544:
640 case e1000_82540:
641 case e1000_82545:
642 case e1000_82546:
643 case e1000_82541:
644 case e1000_82541_rev_2:
645 /* These controllers can't ack the 64-bit write when issuing the
646 * reset, so use IO-mapping as a workaround to issue the reset */
647 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
648 break;
649 case e1000_82545_rev_3:
650 case e1000_82546_rev_3:
651 /* Reset is performed on a shadow of the control register */
652 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
653 break;
654 case e1000_ich8lan:
655 if (!hw->phy_reset_disable &&
656 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
657 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
658 * at the same time to make sure the interface between
659 * MAC and the external PHY is reset.
660 */
661 ctrl |= E1000_CTRL_PHY_RST;
662 }
663
664 e1000_get_software_flag(hw);
665 ew32(CTRL, (ctrl | E1000_CTRL_RST));
666 msleep(5);
667 break;
668 default:
669 ew32(CTRL, (ctrl | E1000_CTRL_RST));
670 break;
671 }
672
673 /* After MAC reset, force reload of EEPROM to restore power-on settings to
674 * device. Later controllers reload the EEPROM automatically, so just wait
675 * for reload to complete.
676 */
677 switch (hw->mac_type) {
678 case e1000_82542_rev2_0:
679 case e1000_82542_rev2_1:
680 case e1000_82543:
681 case e1000_82544:
682 /* Wait for reset to complete */
683 udelay(10);
684 ctrl_ext = er32(CTRL_EXT);
685 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
686 ew32(CTRL_EXT, ctrl_ext);
687 E1000_WRITE_FLUSH();
688 /* Wait for EEPROM reload */
689 msleep(2);
690 break;
691 case e1000_82541:
692 case e1000_82541_rev_2:
693 case e1000_82547:
694 case e1000_82547_rev_2:
695 /* Wait for EEPROM reload */
696 msleep(20);
697 break;
698 case e1000_82573:
699 if (!e1000_is_onboard_nvm_eeprom(hw)) {
700 udelay(10);
701 ctrl_ext = er32(CTRL_EXT);
702 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
703 ew32(CTRL_EXT, ctrl_ext);
704 E1000_WRITE_FLUSH();
705 }
706 /* fall through */
707 default:
708 /* Auto read done will delay 5ms or poll based on mac type */
709 ret_val = e1000_get_auto_rd_done(hw);
710 if (ret_val)
711 return ret_val;
712 break;
713 }
714
715 /* Disable HW ARPs on ASF enabled adapters */
716 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
717 manc = er32(MANC);
718 manc &= ~(E1000_MANC_ARP_EN);
719 ew32(MANC, manc);
720 }
721
722 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
723 e1000_phy_init_script(hw);
724
725 /* Configure activity LED after PHY reset */
726 led_ctrl = er32(LEDCTL);
727 led_ctrl &= IGP_ACTIVITY_LED_MASK;
728 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
729 ew32(LEDCTL, led_ctrl);
730 }
731
732 /* Clear interrupt mask to stop board from generating interrupts */
733 DEBUGOUT("Masking off all interrupts\n");
734 ew32(IMC, 0xffffffff);
735
736 /* Clear any pending interrupt events. */
737 icr = er32(ICR);
738
739 /* If MWI was previously enabled, reenable it. */
740 if (hw->mac_type == e1000_82542_rev2_0) {
741 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
742 e1000_pci_set_mwi(hw);
743 }
744
745 if (hw->mac_type == e1000_ich8lan) {
746 u32 kab = er32(KABGTXD);
747 kab |= E1000_KABGTXD_BGSQLBIAS;
748 ew32(KABGTXD, kab);
749 }
750
751 return E1000_SUCCESS;
752}
753 403
754/****************************************************************************** 404 DEBUGFUNC("e1000_reset_hw");
755 * 405
756 * Initialize a number of hardware-dependent bits 406 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
757 * 407 if (hw->mac_type == e1000_82542_rev2_0) {
758 * hw: Struct containing variables accessed by shared code 408 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
759 * 409 e1000_pci_clear_mwi(hw);
760 * This function contains hardware limitation workarounds for PCI-E adapters 410 }
761 * 411
762 *****************************************************************************/ 412 /* Clear interrupt mask to stop board from generating interrupts */
763static void e1000_initialize_hardware_bits(struct e1000_hw *hw) 413 DEBUGOUT("Masking off all interrupts\n");
764{ 414 ew32(IMC, 0xffffffff);
765 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { 415
766 /* Settings common to all PCI-express silicon */ 416 /* Disable the Transmit and Receive units. Then delay to allow
767 u32 reg_ctrl, reg_ctrl_ext; 417 * any pending transactions to complete before we hit the MAC with
768 u32 reg_tarc0, reg_tarc1; 418 * the global reset.
769 u32 reg_tctl; 419 */
770 u32 reg_txdctl, reg_txdctl1; 420 ew32(RCTL, 0);
771 421 ew32(TCTL, E1000_TCTL_PSP);
772 /* link autonegotiation/sync workarounds */ 422 E1000_WRITE_FLUSH();
773 reg_tarc0 = er32(TARC0); 423
774 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 424 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
775 425 hw->tbi_compatibility_on = false;
776 /* Enable not-done TX descriptor counting */ 426
777 reg_txdctl = er32(TXDCTL); 427 /* Delay to allow any outstanding PCI transactions to complete before
778 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 428 * resetting the device
779 ew32(TXDCTL, reg_txdctl); 429 */
780 reg_txdctl1 = er32(TXDCTL1); 430 msleep(10);
781 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 431
782 ew32(TXDCTL1, reg_txdctl1); 432 ctrl = er32(CTRL);
783 433
784 switch (hw->mac_type) { 434 /* Must reset the PHY before resetting the MAC */
785 case e1000_82571: 435 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
786 case e1000_82572: 436 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
787 /* Clear PHY TX compatible mode bits */ 437 msleep(5);
788 reg_tarc1 = er32(TARC1); 438 }
789 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 439
790 440 /* Issue a global reset to the MAC. This will reset the chip's
791 /* link autonegotiation/sync workarounds */ 441 * transmit, receive, DMA, and link units. It will not effect
792 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); 442 * the current PCI configuration. The global reset bit is self-
793 443 * clearing, and should clear within a microsecond.
794 /* TX ring control fixes */ 444 */
795 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 445 DEBUGOUT("Issuing a global reset to MAC\n");
796 446
797 /* Multiple read bit is reversed polarity */ 447 switch (hw->mac_type) {
798 reg_tctl = er32(TCTL); 448 case e1000_82544:
799 if (reg_tctl & E1000_TCTL_MULR) 449 case e1000_82540:
800 reg_tarc1 &= ~(1 << 28); 450 case e1000_82545:
801 else 451 case e1000_82546:
802 reg_tarc1 |= (1 << 28); 452 case e1000_82541:
803 453 case e1000_82541_rev_2:
804 ew32(TARC1, reg_tarc1); 454 /* These controllers can't ack the 64-bit write when issuing the
805 break; 455 * reset, so use IO-mapping as a workaround to issue the reset */
806 case e1000_82573: 456 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
807 reg_ctrl_ext = er32(CTRL_EXT); 457 break;
808 reg_ctrl_ext &= ~(1 << 23); 458 case e1000_82545_rev_3:
809 reg_ctrl_ext |= (1 << 22); 459 case e1000_82546_rev_3:
810 460 /* Reset is performed on a shadow of the control register */
811 /* TX byte count fix */ 461 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
812 reg_ctrl = er32(CTRL); 462 break;
813 reg_ctrl &= ~(1 << 29); 463 default:
814 464 ew32(CTRL, (ctrl | E1000_CTRL_RST));
815 ew32(CTRL_EXT, reg_ctrl_ext); 465 break;
816 ew32(CTRL, reg_ctrl); 466 }
817 break; 467
818 case e1000_80003es2lan: 468 /* After MAC reset, force reload of EEPROM to restore power-on settings to
819 /* improve small packet performace for fiber/serdes */ 469 * device. Later controllers reload the EEPROM automatically, so just wait
820 if ((hw->media_type == e1000_media_type_fiber) || 470 * for reload to complete.
821 (hw->media_type == e1000_media_type_internal_serdes)) { 471 */
822 reg_tarc0 &= ~(1 << 20); 472 switch (hw->mac_type) {
823 } 473 case e1000_82542_rev2_0:
824 474 case e1000_82542_rev2_1:
825 /* Multiple read bit is reversed polarity */ 475 case e1000_82543:
826 reg_tctl = er32(TCTL); 476 case e1000_82544:
827 reg_tarc1 = er32(TARC1); 477 /* Wait for reset to complete */
828 if (reg_tctl & E1000_TCTL_MULR) 478 udelay(10);
829 reg_tarc1 &= ~(1 << 28); 479 ctrl_ext = er32(CTRL_EXT);
830 else 480 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
831 reg_tarc1 |= (1 << 28); 481 ew32(CTRL_EXT, ctrl_ext);
832 482 E1000_WRITE_FLUSH();
833 ew32(TARC1, reg_tarc1); 483 /* Wait for EEPROM reload */
834 break; 484 msleep(2);
835 case e1000_ich8lan: 485 break;
836 /* Reduce concurrent DMA requests to 3 from 4 */ 486 case e1000_82541:
837 if ((hw->revision_id < 3) || 487 case e1000_82541_rev_2:
838 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 488 case e1000_82547:
839 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 489 case e1000_82547_rev_2:
840 reg_tarc0 |= ((1 << 29)|(1 << 28)); 490 /* Wait for EEPROM reload */
841 491 msleep(20);
842 reg_ctrl_ext = er32(CTRL_EXT); 492 break;
843 reg_ctrl_ext |= (1 << 22); 493 default:
844 ew32(CTRL_EXT, reg_ctrl_ext); 494 /* Auto read done will delay 5ms or poll based on mac type */
845 495 ret_val = e1000_get_auto_rd_done(hw);
846 /* workaround TX hang with TSO=on */ 496 if (ret_val)
847 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 497 return ret_val;
848 498 break;
849 /* Multiple read bit is reversed polarity */ 499 }
850 reg_tctl = er32(TCTL); 500
851 reg_tarc1 = er32(TARC1); 501 /* Disable HW ARPs on ASF enabled adapters */
852 if (reg_tctl & E1000_TCTL_MULR) 502 if (hw->mac_type >= e1000_82540) {
853 reg_tarc1 &= ~(1 << 28); 503 manc = er32(MANC);
854 else 504 manc &= ~(E1000_MANC_ARP_EN);
855 reg_tarc1 |= (1 << 28); 505 ew32(MANC, manc);
856 506 }
857 /* workaround TX hang with TSO=on */ 507
858 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 508 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
859 509 e1000_phy_init_script(hw);
860 ew32(TARC1, reg_tarc1); 510
861 break; 511 /* Configure activity LED after PHY reset */
862 default: 512 led_ctrl = er32(LEDCTL);
863 break; 513 led_ctrl &= IGP_ACTIVITY_LED_MASK;
864 } 514 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
865 515 ew32(LEDCTL, led_ctrl);
866 ew32(TARC0, reg_tarc0); 516 }
867 } 517
518 /* Clear interrupt mask to stop board from generating interrupts */
519 DEBUGOUT("Masking off all interrupts\n");
520 ew32(IMC, 0xffffffff);
521
522 /* Clear any pending interrupt events. */
523 icr = er32(ICR);
524
525 /* If MWI was previously enabled, reenable it. */
526 if (hw->mac_type == e1000_82542_rev2_0) {
527 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
528 e1000_pci_set_mwi(hw);
529 }
530
531 return E1000_SUCCESS;
868} 532}
869 533
870/****************************************************************************** 534/**
871 * Performs basic configuration of the adapter. 535 * e1000_init_hw: Performs basic configuration of the adapter.
872 * 536 * @hw: Struct containing variables accessed by shared code
873 * hw - Struct containing variables accessed by shared code
874 * 537 *
875 * Assumes that the controller has previously been reset and is in a 538 * Assumes that the controller has previously been reset and is in a
876 * post-reset uninitialized state. Initializes the receive address registers, 539 * post-reset uninitialized state. Initializes the receive address registers,
877 * multicast table, and VLAN filter table. Calls routines to setup link 540 * multicast table, and VLAN filter table. Calls routines to setup link
878 * configuration and flow control settings. Clears all on-chip counters. Leaves 541 * configuration and flow control settings. Clears all on-chip counters. Leaves
879 * the transmit and receive units disabled and uninitialized. 542 * the transmit and receive units disabled and uninitialized.
880 *****************************************************************************/ 543 */
881s32 e1000_init_hw(struct e1000_hw *hw) 544s32 e1000_init_hw(struct e1000_hw *hw)
882{ 545{
883 u32 ctrl; 546 u32 ctrl;
884 u32 i; 547 u32 i;
885 s32 ret_val; 548 s32 ret_val;
886 u32 mta_size; 549 u32 mta_size;
887 u32 reg_data; 550 u32 ctrl_ext;
888 u32 ctrl_ext; 551
889 552 DEBUGFUNC("e1000_init_hw");
890 DEBUGFUNC("e1000_init_hw"); 553
891 554 /* Initialize Identification LED */
892 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 555 ret_val = e1000_id_led_init(hw);
893 if ((hw->mac_type == e1000_ich8lan) && 556 if (ret_val) {
894 ((hw->revision_id < 3) || 557 DEBUGOUT("Error Initializing Identification LED\n");
895 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 558 return ret_val;
896 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 559 }
897 reg_data = er32(STATUS); 560
898 reg_data &= ~0x80000000; 561 /* Set the media type and TBI compatibility */
899 ew32(STATUS, reg_data); 562 e1000_set_media_type(hw);
900 } 563
901 564 /* Disabling VLAN filtering. */
902 /* Initialize Identification LED */ 565 DEBUGOUT("Initializing the IEEE VLAN\n");
903 ret_val = e1000_id_led_init(hw); 566 if (hw->mac_type < e1000_82545_rev_3)
904 if (ret_val) { 567 ew32(VET, 0);
905 DEBUGOUT("Error Initializing Identification LED\n"); 568 e1000_clear_vfta(hw);
906 return ret_val; 569
907 } 570 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
908 571 if (hw->mac_type == e1000_82542_rev2_0) {
909 /* Set the media type and TBI compatibility */ 572 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
910 e1000_set_media_type(hw); 573 e1000_pci_clear_mwi(hw);
911 574 ew32(RCTL, E1000_RCTL_RST);
912 /* Must be called after e1000_set_media_type because media_type is used */ 575 E1000_WRITE_FLUSH();
913 e1000_initialize_hardware_bits(hw); 576 msleep(5);
914 577 }
915 /* Disabling VLAN filtering. */ 578
916 DEBUGOUT("Initializing the IEEE VLAN\n"); 579 /* Setup the receive address. This involves initializing all of the Receive
917 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 580 * Address Registers (RARs 0 - 15).
918 if (hw->mac_type != e1000_ich8lan) { 581 */
919 if (hw->mac_type < e1000_82545_rev_3) 582 e1000_init_rx_addrs(hw);
920 ew32(VET, 0); 583
921 e1000_clear_vfta(hw); 584 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
922 } 585 if (hw->mac_type == e1000_82542_rev2_0) {
923 586 ew32(RCTL, 0);
924 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 587 E1000_WRITE_FLUSH();
925 if (hw->mac_type == e1000_82542_rev2_0) { 588 msleep(1);
926 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 589 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
927 e1000_pci_clear_mwi(hw); 590 e1000_pci_set_mwi(hw);
928 ew32(RCTL, E1000_RCTL_RST); 591 }
929 E1000_WRITE_FLUSH(); 592
930 msleep(5); 593 /* Zero out the Multicast HASH table */
931 } 594 DEBUGOUT("Zeroing the MTA\n");
932 595 mta_size = E1000_MC_TBL_SIZE;
933 /* Setup the receive address. This involves initializing all of the Receive 596 for (i = 0; i < mta_size; i++) {
934 * Address Registers (RARs 0 - 15). 597 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
935 */ 598 /* use write flush to prevent Memory Write Block (MWB) from
936 e1000_init_rx_addrs(hw); 599 * occurring when accessing our register space */
937 600 E1000_WRITE_FLUSH();
938 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 601 }
939 if (hw->mac_type == e1000_82542_rev2_0) { 602
940 ew32(RCTL, 0); 603 /* Set the PCI priority bit correctly in the CTRL register. This
941 E1000_WRITE_FLUSH(); 604 * determines if the adapter gives priority to receives, or if it
942 msleep(1); 605 * gives equal priority to transmits and receives. Valid only on
943 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 606 * 82542 and 82543 silicon.
944 e1000_pci_set_mwi(hw); 607 */
945 } 608 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
946 609 ctrl = er32(CTRL);
947 /* Zero out the Multicast HASH table */ 610 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
948 DEBUGOUT("Zeroing the MTA\n"); 611 }
949 mta_size = E1000_MC_TBL_SIZE; 612
950 if (hw->mac_type == e1000_ich8lan) 613 switch (hw->mac_type) {
951 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 614 case e1000_82545_rev_3:
952 for (i = 0; i < mta_size; i++) { 615 case e1000_82546_rev_3:
953 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 616 break;
954 /* use write flush to prevent Memory Write Block (MWB) from 617 default:
955 * occuring when accessing our register space */ 618 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
956 E1000_WRITE_FLUSH(); 619 if (hw->bus_type == e1000_bus_type_pcix
957 } 620 && e1000_pcix_get_mmrbc(hw) > 2048)
958 621 e1000_pcix_set_mmrbc(hw, 2048);
959 /* Set the PCI priority bit correctly in the CTRL register. This 622 break;
960 * determines if the adapter gives priority to receives, or if it 623 }
961 * gives equal priority to transmits and receives. Valid only on 624
962 * 82542 and 82543 silicon. 625 /* Call a subroutine to configure the link and setup flow control. */
963 */ 626 ret_val = e1000_setup_link(hw);
964 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 627
965 ctrl = er32(CTRL); 628 /* Set the transmit descriptor write-back policy */
966 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); 629 if (hw->mac_type > e1000_82544) {
967 } 630 ctrl = er32(TXDCTL);
968 631 ctrl =
969 switch (hw->mac_type) { 632 (ctrl & ~E1000_TXDCTL_WTHRESH) |
970 case e1000_82545_rev_3: 633 E1000_TXDCTL_FULL_TX_DESC_WB;
971 case e1000_82546_rev_3: 634 ew32(TXDCTL, ctrl);
972 break; 635 }
973 default: 636
974 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 637 /* Clear all of the statistics registers (clear on read). It is
975 if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048) 638 * important that we do this after we have tried to establish link
976 e1000_pcix_set_mmrbc(hw, 2048); 639 * because the symbol error count will increment wildly if there
977 break; 640 * is no link.
978 } 641 */
979 642 e1000_clear_hw_cntrs(hw);
980 /* More time needed for PHY to initialize */ 643
981 if (hw->mac_type == e1000_ich8lan) 644 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
982 msleep(15); 645 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
983 646 ctrl_ext = er32(CTRL_EXT);
984 /* Call a subroutine to configure the link and setup flow control. */ 647 /* Relaxed ordering must be disabled to avoid a parity
985 ret_val = e1000_setup_link(hw); 648 * error crash in a PCI slot. */
986 649 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
987 /* Set the transmit descriptor write-back policy */ 650 ew32(CTRL_EXT, ctrl_ext);
988 if (hw->mac_type > e1000_82544) { 651 }
989 ctrl = er32(TXDCTL); 652
990 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 653 return ret_val;
991 ew32(TXDCTL, ctrl);
992 }
993
994 if (hw->mac_type == e1000_82573) {
995 e1000_enable_tx_pkt_filtering(hw);
996 }
997
998 switch (hw->mac_type) {
999 default:
1000 break;
1001 case e1000_80003es2lan:
1002 /* Enable retransmit on late collisions */
1003 reg_data = er32(TCTL);
1004 reg_data |= E1000_TCTL_RTLC;
1005 ew32(TCTL, reg_data);
1006
1007 /* Configure Gigabit Carry Extend Padding */
1008 reg_data = er32(TCTL_EXT);
1009 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1010 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1011 ew32(TCTL_EXT, reg_data);
1012
1013 /* Configure Transmit Inter-Packet Gap */
1014 reg_data = er32(TIPG);
1015 reg_data &= ~E1000_TIPG_IPGT_MASK;
1016 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1017 ew32(TIPG, reg_data);
1018
1019 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1020 reg_data &= ~0x00100000;
1021 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1022 /* Fall through */
1023 case e1000_82571:
1024 case e1000_82572:
1025 case e1000_ich8lan:
1026 ctrl = er32(TXDCTL1);
1027 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1028 ew32(TXDCTL1, ctrl);
1029 break;
1030 }
1031
1032
1033 if (hw->mac_type == e1000_82573) {
1034 u32 gcr = er32(GCR);
1035 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1036 ew32(GCR, gcr);
1037 }
1038
1039 /* Clear all of the statistics registers (clear on read). It is
1040 * important that we do this after we have tried to establish link
1041 * because the symbol error count will increment wildly if there
1042 * is no link.
1043 */
1044 e1000_clear_hw_cntrs(hw);
1045
1046 /* ICH8 No-snoop bits are opposite polarity.
1047 * Set to snoop by default after reset. */
1048 if (hw->mac_type == e1000_ich8lan)
1049 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1050
1051 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1052 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1053 ctrl_ext = er32(CTRL_EXT);
1054 /* Relaxed ordering must be disabled to avoid a parity
1055 * error crash in a PCI slot. */
1056 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1057 ew32(CTRL_EXT, ctrl_ext);
1058 }
1059
1060 return ret_val;
1061} 654}
1062 655
1063/****************************************************************************** 656/**
1064 * Adjust SERDES output amplitude based on EEPROM setting. 657 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
1065 * 658 * @hw: Struct containing variables accessed by shared code.
1066 * hw - Struct containing variables accessed by shared code. 659 */
1067 *****************************************************************************/
1068static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 660static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1069{ 661{
1070 u16 eeprom_data; 662 u16 eeprom_data;
1071 s32 ret_val; 663 s32 ret_val;
1072 664
1073 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 665 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1074 666
1075 if (hw->media_type != e1000_media_type_internal_serdes) 667 if (hw->media_type != e1000_media_type_internal_serdes)
1076 return E1000_SUCCESS; 668 return E1000_SUCCESS;
1077 669
1078 switch (hw->mac_type) { 670 switch (hw->mac_type) {
1079 case e1000_82545_rev_3: 671 case e1000_82545_rev_3:
1080 case e1000_82546_rev_3: 672 case e1000_82546_rev_3:
1081 break; 673 break;
1082 default: 674 default:
1083 return E1000_SUCCESS; 675 return E1000_SUCCESS;
1084 } 676 }
1085 677
1086 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 678 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
1087 if (ret_val) { 679 &eeprom_data);
1088 return ret_val; 680 if (ret_val) {
1089 } 681 return ret_val;
1090 682 }
1091 if (eeprom_data != EEPROM_RESERVED_WORD) { 683
1092 /* Adjust SERDES output amplitude only. */ 684 if (eeprom_data != EEPROM_RESERVED_WORD) {
1093 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 685 /* Adjust SERDES output amplitude only. */
1094 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 686 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1095 if (ret_val) 687 ret_val =
1096 return ret_val; 688 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1097 } 689 if (ret_val)
1098 690 return ret_val;
1099 return E1000_SUCCESS; 691 }
692
693 return E1000_SUCCESS;
1100} 694}
1101 695
1102/****************************************************************************** 696/**
1103 * Configures flow control and link settings. 697 * e1000_setup_link - Configures flow control and link settings.
1104 * 698 * @hw: Struct containing variables accessed by shared code
1105 * hw - Struct containing variables accessed by shared code
1106 * 699 *
1107 * Determines which flow control settings to use. Calls the apropriate media- 700 * Determines which flow control settings to use. Calls the appropriate media-
1108 * specific link configuration function. Configures the flow control settings. 701 * specific link configuration function. Configures the flow control settings.
1109 * Assuming the adapter has a valid link partner, a valid link should be 702 * Assuming the adapter has a valid link partner, a valid link should be
1110 * established. Assumes the hardware has previously been reset and the 703 * established. Assumes the hardware has previously been reset and the
1111 * transmitter and receiver are not enabled. 704 * transmitter and receiver are not enabled.
1112 *****************************************************************************/ 705 */
1113s32 e1000_setup_link(struct e1000_hw *hw) 706s32 e1000_setup_link(struct e1000_hw *hw)
1114{ 707{
1115 u32 ctrl_ext; 708 u32 ctrl_ext;
1116 s32 ret_val; 709 s32 ret_val;
1117 u16 eeprom_data; 710 u16 eeprom_data;
1118 711
1119 DEBUGFUNC("e1000_setup_link"); 712 DEBUGFUNC("e1000_setup_link");
1120 713
1121 /* In the case of the phy reset being blocked, we already have a link. 714 /* Read and store word 0x0F of the EEPROM. This word contains bits
1122 * We do not have to set it up again. */ 715 * that determine the hardware's default PAUSE (flow control) mode,
1123 if (e1000_check_phy_reset_block(hw)) 716 * a bit that determines whether the HW defaults to enabling or
1124 return E1000_SUCCESS; 717 * disabling auto-negotiation, and the direction of the
1125 718 * SW defined pins. If there is no SW over-ride of the flow
1126 /* Read and store word 0x0F of the EEPROM. This word contains bits 719 * control setting, then the variable hw->fc will
1127 * that determine the hardware's default PAUSE (flow control) mode, 720 * be initialized based on a value in the EEPROM.
1128 * a bit that determines whether the HW defaults to enabling or 721 */
1129 * disabling auto-negotiation, and the direction of the 722 if (hw->fc == E1000_FC_DEFAULT) {
1130 * SW defined pins. If there is no SW over-ride of the flow 723 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1131 * control setting, then the variable hw->fc will 724 1, &eeprom_data);
1132 * be initialized based on a value in the EEPROM. 725 if (ret_val) {
1133 */ 726 DEBUGOUT("EEPROM Read Error\n");
1134 if (hw->fc == E1000_FC_DEFAULT) { 727 return -E1000_ERR_EEPROM;
1135 switch (hw->mac_type) { 728 }
1136 case e1000_ich8lan: 729 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1137 case e1000_82573: 730 hw->fc = E1000_FC_NONE;
1138 hw->fc = E1000_FC_FULL; 731 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1139 break; 732 EEPROM_WORD0F_ASM_DIR)
1140 default: 733 hw->fc = E1000_FC_TX_PAUSE;
1141 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 734 else
1142 1, &eeprom_data); 735 hw->fc = E1000_FC_FULL;
1143 if (ret_val) { 736 }
1144 DEBUGOUT("EEPROM Read Error\n"); 737
1145 return -E1000_ERR_EEPROM; 738 /* We want to save off the original Flow Control configuration just
1146 } 739 * in case we get disconnected and then reconnected into a different
1147 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 740 * hub or switch with different Flow Control capabilities.
1148 hw->fc = E1000_FC_NONE; 741 */
1149 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 742 if (hw->mac_type == e1000_82542_rev2_0)
1150 EEPROM_WORD0F_ASM_DIR) 743 hw->fc &= (~E1000_FC_TX_PAUSE);
1151 hw->fc = E1000_FC_TX_PAUSE; 744
1152 else 745 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1153 hw->fc = E1000_FC_FULL; 746 hw->fc &= (~E1000_FC_RX_PAUSE);
1154 break; 747
1155 } 748 hw->original_fc = hw->fc;
1156 } 749
1157 750 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1158 /* We want to save off the original Flow Control configuration just 751
1159 * in case we get disconnected and then reconnected into a different 752 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1160 * hub or switch with different Flow Control capabilities. 753 * polarity value for the SW controlled pins, and setup the
1161 */ 754 * Extended Device Control reg with that info.
1162 if (hw->mac_type == e1000_82542_rev2_0) 755 * This is needed because one of the SW controlled pins is used for
1163 hw->fc &= (~E1000_FC_TX_PAUSE); 756 * signal detection. So this should be done before e1000_setup_pcs_link()
1164 757 * or e1000_phy_setup() is called.
1165 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 758 */
1166 hw->fc &= (~E1000_FC_RX_PAUSE); 759 if (hw->mac_type == e1000_82543) {
1167 760 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1168 hw->original_fc = hw->fc; 761 1, &eeprom_data);
1169 762 if (ret_val) {
1170 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 763 DEBUGOUT("EEPROM Read Error\n");
1171 764 return -E1000_ERR_EEPROM;
1172 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 765 }
1173 * polarity value for the SW controlled pins, and setup the 766 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1174 * Extended Device Control reg with that info. 767 SWDPIO__EXT_SHIFT);
1175 * This is needed because one of the SW controlled pins is used for 768 ew32(CTRL_EXT, ctrl_ext);
1176 * signal detection. So this should be done before e1000_setup_pcs_link() 769 }
1177 * or e1000_phy_setup() is called. 770
1178 */ 771 /* Call the necessary subroutine to configure the link. */
1179 if (hw->mac_type == e1000_82543) { 772 ret_val = (hw->media_type == e1000_media_type_copper) ?
1180 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 773 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
1181 1, &eeprom_data); 774
1182 if (ret_val) { 775 /* Initialize the flow control address, type, and PAUSE timer
1183 DEBUGOUT("EEPROM Read Error\n"); 776 * registers to their default values. This is done even if flow
1184 return -E1000_ERR_EEPROM; 777 * control is disabled, because it does not hurt anything to
1185 } 778 * initialize these registers.
1186 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 779 */
1187 SWDPIO__EXT_SHIFT); 780 DEBUGOUT
1188 ew32(CTRL_EXT, ctrl_ext); 781 ("Initializing the Flow Control address, type and timer regs\n");
1189 } 782
1190 783 ew32(FCT, FLOW_CONTROL_TYPE);
1191 /* Call the necessary subroutine to configure the link. */ 784 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1192 ret_val = (hw->media_type == e1000_media_type_copper) ? 785 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
1193 e1000_setup_copper_link(hw) : 786
1194 e1000_setup_fiber_serdes_link(hw); 787 ew32(FCTTV, hw->fc_pause_time);
1195 788
1196 /* Initialize the flow control address, type, and PAUSE timer 789 /* Set the flow control receive threshold registers. Normally,
1197 * registers to their default values. This is done even if flow 790 * these registers will be set to a default threshold that may be
1198 * control is disabled, because it does not hurt anything to 791 * adjusted later by the driver's runtime code. However, if the
1199 * initialize these registers. 792 * ability to transmit pause frames in not enabled, then these
1200 */ 793 * registers will be set to 0.
1201 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 794 */
1202 795 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1203 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 796 ew32(FCRTL, 0);
1204 if (hw->mac_type != e1000_ich8lan) { 797 ew32(FCRTH, 0);
1205 ew32(FCT, FLOW_CONTROL_TYPE); 798 } else {
1206 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 799 /* We need to set up the Receive Threshold high and low water marks
1207 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 800 * as well as (optionally) enabling the transmission of XON frames.
1208 } 801 */
1209 802 if (hw->fc_send_xon) {
1210 ew32(FCTTV, hw->fc_pause_time); 803 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1211 804 ew32(FCRTH, hw->fc_high_water);
1212 /* Set the flow control receive threshold registers. Normally, 805 } else {
1213 * these registers will be set to a default threshold that may be 806 ew32(FCRTL, hw->fc_low_water);
1214 * adjusted later by the driver's runtime code. However, if the 807 ew32(FCRTH, hw->fc_high_water);
1215 * ability to transmit pause frames in not enabled, then these 808 }
1216 * registers will be set to 0. 809 }
1217 */ 810 return ret_val;
1218 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1219 ew32(FCRTL, 0);
1220 ew32(FCRTH, 0);
1221 } else {
1222 /* We need to set up the Receive Threshold high and low water marks
1223 * as well as (optionally) enabling the transmission of XON frames.
1224 */
1225 if (hw->fc_send_xon) {
1226 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1227 ew32(FCRTH, hw->fc_high_water);
1228 } else {
1229 ew32(FCRTL, hw->fc_low_water);
1230 ew32(FCRTH, hw->fc_high_water);
1231 }
1232 }
1233 return ret_val;
1234} 811}
1235 812
1236/****************************************************************************** 813/**
1237 * Sets up link for a fiber based or serdes based adapter 814 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
1238 * 815 * @hw: Struct containing variables accessed by shared code
1239 * hw - Struct containing variables accessed by shared code
1240 * 816 *
1241 * Manipulates Physical Coding Sublayer functions in order to configure 817 * Manipulates Physical Coding Sublayer functions in order to configure
1242 * link. Assumes the hardware has been previously reset and the transmitter 818 * link. Assumes the hardware has been previously reset and the transmitter
1243 * and receiver are not enabled. 819 * and receiver are not enabled.
1244 *****************************************************************************/ 820 */
1245static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 821static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1246{ 822{
1247 u32 ctrl; 823 u32 ctrl;
1248 u32 status; 824 u32 status;
1249 u32 txcw = 0; 825 u32 txcw = 0;
1250 u32 i; 826 u32 i;
1251 u32 signal = 0; 827 u32 signal = 0;
1252 s32 ret_val; 828 s32 ret_val;
1253 829
1254 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 830 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1255 831
1256 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists 832 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1257 * until explicitly turned off or a power cycle is performed. A read to 833 * set when the optics detect a signal. On older adapters, it will be
1258 * the register does not indicate its status. Therefore, we ensure 834 * cleared when there is a signal. This applies to fiber media only.
1259 * loopback mode is disabled during initialization. 835 * If we're on serdes media, adjust the output amplitude to value
1260 */ 836 * set in the EEPROM.
1261 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) 837 */
1262 ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK); 838 ctrl = er32(CTRL);
1263 839 if (hw->media_type == e1000_media_type_fiber)
1264 /* On adapters with a MAC newer than 82544, SWDP 1 will be 840 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1265 * set when the optics detect a signal. On older adapters, it will be 841
1266 * cleared when there is a signal. This applies to fiber media only. 842 ret_val = e1000_adjust_serdes_amplitude(hw);
1267 * If we're on serdes media, adjust the output amplitude to value 843 if (ret_val)
1268 * set in the EEPROM. 844 return ret_val;
1269 */ 845
1270 ctrl = er32(CTRL); 846 /* Take the link out of reset */
1271 if (hw->media_type == e1000_media_type_fiber) 847 ctrl &= ~(E1000_CTRL_LRST);
1272 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 848
1273 849 /* Adjust VCO speed to improve BER performance */
1274 ret_val = e1000_adjust_serdes_amplitude(hw); 850 ret_val = e1000_set_vco_speed(hw);
1275 if (ret_val) 851 if (ret_val)
1276 return ret_val; 852 return ret_val;
1277 853
1278 /* Take the link out of reset */ 854 e1000_config_collision_dist(hw);
1279 ctrl &= ~(E1000_CTRL_LRST); 855
1280 856 /* Check for a software override of the flow control settings, and setup
1281 /* Adjust VCO speed to improve BER performance */ 857 * the device accordingly. If auto-negotiation is enabled, then software
1282 ret_val = e1000_set_vco_speed(hw); 858 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1283 if (ret_val) 859 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1284 return ret_val; 860 * auto-negotiation is disabled, then software will have to manually
1285 861 * configure the two flow control enable bits in the CTRL register.
1286 e1000_config_collision_dist(hw); 862 *
1287 863 * The possible values of the "fc" parameter are:
1288 /* Check for a software override of the flow control settings, and setup 864 * 0: Flow control is completely disabled
1289 * the device accordingly. If auto-negotiation is enabled, then software 865 * 1: Rx flow control is enabled (we can receive pause frames, but
1290 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 866 * not send pause frames).
1291 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 867 * 2: Tx flow control is enabled (we can send pause frames but we do
1292 * auto-negotiation is disabled, then software will have to manually 868 * not support receiving pause frames).
1293 * configure the two flow control enable bits in the CTRL register. 869 * 3: Both Rx and TX flow control (symmetric) are enabled.
1294 * 870 */
1295 * The possible values of the "fc" parameter are: 871 switch (hw->fc) {
1296 * 0: Flow control is completely disabled 872 case E1000_FC_NONE:
1297 * 1: Rx flow control is enabled (we can receive pause frames, but 873 /* Flow control is completely disabled by a software over-ride. */
1298 * not send pause frames). 874 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1299 * 2: Tx flow control is enabled (we can send pause frames but we do 875 break;
1300 * not support receiving pause frames). 876 case E1000_FC_RX_PAUSE:
1301 * 3: Both Rx and TX flow control (symmetric) are enabled. 877 /* RX Flow control is enabled and TX Flow control is disabled by a
1302 */ 878 * software over-ride. Since there really isn't a way to advertise
1303 switch (hw->fc) { 879 * that we are capable of RX Pause ONLY, we will advertise that we
1304 case E1000_FC_NONE: 880 * support both symmetric and asymmetric RX PAUSE. Later, we will
1305 /* Flow control is completely disabled by a software over-ride. */ 881 * disable the adapter's ability to send PAUSE frames.
1306 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 882 */
1307 break; 883 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1308 case E1000_FC_RX_PAUSE: 884 break;
1309 /* RX Flow control is enabled and TX Flow control is disabled by a 885 case E1000_FC_TX_PAUSE:
1310 * software over-ride. Since there really isn't a way to advertise 886 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1311 * that we are capable of RX Pause ONLY, we will advertise that we 887 * software over-ride.
1312 * support both symmetric and asymmetric RX PAUSE. Later, we will 888 */
1313 * disable the adapter's ability to send PAUSE frames. 889 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1314 */ 890 break;
1315 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 891 case E1000_FC_FULL:
1316 break; 892 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1317 case E1000_FC_TX_PAUSE: 893 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1318 /* TX Flow control is enabled, and RX Flow control is disabled, by a 894 break;
1319 * software over-ride. 895 default:
1320 */ 896 DEBUGOUT("Flow control param set incorrectly\n");
1321 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 897 return -E1000_ERR_CONFIG;
1322 break; 898 break;
1323 case E1000_FC_FULL: 899 }
1324 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 900
1325 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 901 /* Since auto-negotiation is enabled, take the link out of reset (the link
1326 break; 902 * will be in reset, because we previously reset the chip). This will
1327 default: 903 * restart auto-negotiation. If auto-negotiation is successful then the
1328 DEBUGOUT("Flow control param set incorrectly\n"); 904 * link-up status bit will be set and the flow control enable bits (RFCE
1329 return -E1000_ERR_CONFIG; 905 * and TFCE) will be set according to their negotiated value.
1330 break; 906 */
1331 } 907 DEBUGOUT("Auto-negotiation enabled\n");
1332 908
1333 /* Since auto-negotiation is enabled, take the link out of reset (the link 909 ew32(TXCW, txcw);
1334 * will be in reset, because we previously reset the chip). This will 910 ew32(CTRL, ctrl);
1335 * restart auto-negotiation. If auto-neogtiation is successful then the 911 E1000_WRITE_FLUSH();
1336 * link-up status bit will be set and the flow control enable bits (RFCE 912
1337 * and TFCE) will be set according to their negotiated value. 913 hw->txcw = txcw;
1338 */ 914 msleep(1);
1339 DEBUGOUT("Auto-negotiation enabled\n"); 915
1340 916 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1341 ew32(TXCW, txcw); 917 * indication in the Device Status Register. Time-out if a link isn't
1342 ew32(CTRL, ctrl); 918 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1343 E1000_WRITE_FLUSH(); 919 * less than 500 milliseconds even if the other end is doing it in SW).
1344 920 * For internal serdes, we just assume a signal is present, then poll.
1345 hw->txcw = txcw; 921 */
1346 msleep(1); 922 if (hw->media_type == e1000_media_type_internal_serdes ||
1347 923 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1348 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 924 DEBUGOUT("Looking for Link\n");
1349 * indication in the Device Status Register. Time-out if a link isn't 925 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1350 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 926 msleep(10);
1351 * less than 500 milliseconds even if the other end is doing it in SW). 927 status = er32(STATUS);
1352 * For internal serdes, we just assume a signal is present, then poll. 928 if (status & E1000_STATUS_LU)
1353 */ 929 break;
1354 if (hw->media_type == e1000_media_type_internal_serdes || 930 }
1355 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 931 if (i == (LINK_UP_TIMEOUT / 10)) {
1356 DEBUGOUT("Looking for Link\n"); 932 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1357 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 933 hw->autoneg_failed = 1;
1358 msleep(10); 934 /* AutoNeg failed to achieve a link, so we'll call
1359 status = er32(STATUS); 935 * e1000_check_for_link. This routine will force the link up if
1360 if (status & E1000_STATUS_LU) break; 936 * we detect a signal. This will allow us to communicate with
1361 } 937 * non-autonegotiating link partners.
1362 if (i == (LINK_UP_TIMEOUT / 10)) { 938 */
1363 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 939 ret_val = e1000_check_for_link(hw);
1364 hw->autoneg_failed = 1; 940 if (ret_val) {
1365 /* AutoNeg failed to achieve a link, so we'll call 941 DEBUGOUT("Error while checking for link\n");
1366 * e1000_check_for_link. This routine will force the link up if 942 return ret_val;
1367 * we detect a signal. This will allow us to communicate with 943 }
1368 * non-autonegotiating link partners. 944 hw->autoneg_failed = 0;
1369 */ 945 } else {
1370 ret_val = e1000_check_for_link(hw); 946 hw->autoneg_failed = 0;
1371 if (ret_val) { 947 DEBUGOUT("Valid Link Found\n");
1372 DEBUGOUT("Error while checking for link\n"); 948 }
1373 return ret_val; 949 } else {
1374 } 950 DEBUGOUT("No Signal Detected\n");
1375 hw->autoneg_failed = 0; 951 }
1376 } else { 952 return E1000_SUCCESS;
1377 hw->autoneg_failed = 0;
1378 DEBUGOUT("Valid Link Found\n");
1379 }
1380 } else {
1381 DEBUGOUT("No Signal Detected\n");
1382 }
1383 return E1000_SUCCESS;
1384} 953}
1385 954
1386/****************************************************************************** 955/**
1387* Make sure we have a valid PHY and change PHY mode before link setup. 956 * e1000_copper_link_preconfig - early configuration for copper
1388* 957 * @hw: Struct containing variables accessed by shared code
1389* hw - Struct containing variables accessed by shared code 958 *
1390******************************************************************************/ 959 * Make sure we have a valid PHY and change PHY mode before link setup.
960 */
1391static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) 961static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1392{ 962{
1393 u32 ctrl; 963 u32 ctrl;
1394 s32 ret_val; 964 s32 ret_val;
1395 u16 phy_data; 965 u16 phy_data;
1396
1397 DEBUGFUNC("e1000_copper_link_preconfig");
1398
1399 ctrl = er32(CTRL);
1400 /* With 82543, we need to force speed and duplex on the MAC equal to what
1401 * the PHY speed and duplex configuration is. In addition, we need to
1402 * perform a hardware reset on the PHY to take it out of reset.
1403 */
1404 if (hw->mac_type > e1000_82543) {
1405 ctrl |= E1000_CTRL_SLU;
1406 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1407 ew32(CTRL, ctrl);
1408 } else {
1409 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1410 ew32(CTRL, ctrl);
1411 ret_val = e1000_phy_hw_reset(hw);
1412 if (ret_val)
1413 return ret_val;
1414 }
1415
1416 /* Make sure we have a valid PHY */
1417 ret_val = e1000_detect_gig_phy(hw);
1418 if (ret_val) {
1419 DEBUGOUT("Error, did not detect valid phy.\n");
1420 return ret_val;
1421 }
1422 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1423
1424 /* Set PHY to class A mode (if necessary) */
1425 ret_val = e1000_set_phy_mode(hw);
1426 if (ret_val)
1427 return ret_val;
1428
1429 if ((hw->mac_type == e1000_82545_rev_3) ||
1430 (hw->mac_type == e1000_82546_rev_3)) {
1431 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1432 phy_data |= 0x00000008;
1433 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1434 }
1435
1436 if (hw->mac_type <= e1000_82543 ||
1437 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1438 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1439 hw->phy_reset_disable = false;
1440
1441 return E1000_SUCCESS;
1442}
1443 966
967 DEBUGFUNC("e1000_copper_link_preconfig");
1444 968
1445/******************************************************************** 969 ctrl = er32(CTRL);
1446* Copper link setup for e1000_phy_igp series. 970 /* With 82543, we need to force speed and duplex on the MAC equal to what
1447* 971 * the PHY speed and duplex configuration is. In addition, we need to
1448* hw - Struct containing variables accessed by shared code 972 * perform a hardware reset on the PHY to take it out of reset.
1449*********************************************************************/ 973 */
1450static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) 974 if (hw->mac_type > e1000_82543) {
1451{ 975 ctrl |= E1000_CTRL_SLU;
1452 u32 led_ctrl; 976 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1453 s32 ret_val; 977 ew32(CTRL, ctrl);
1454 u16 phy_data; 978 } else {
1455 979 ctrl |=
1456 DEBUGFUNC("e1000_copper_link_igp_setup"); 980 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1457 981 ew32(CTRL, ctrl);
1458 if (hw->phy_reset_disable) 982 ret_val = e1000_phy_hw_reset(hw);
1459 return E1000_SUCCESS; 983 if (ret_val)
1460 984 return ret_val;
1461 ret_val = e1000_phy_reset(hw); 985 }
1462 if (ret_val) { 986
1463 DEBUGOUT("Error Resetting the PHY\n"); 987 /* Make sure we have a valid PHY */
1464 return ret_val; 988 ret_val = e1000_detect_gig_phy(hw);
1465 } 989 if (ret_val) {
1466 990 DEBUGOUT("Error, did not detect valid phy.\n");
1467 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 991 return ret_val;
1468 msleep(15); 992 }
1469 if (hw->mac_type != e1000_ich8lan) { 993 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1470 /* Configure activity LED after PHY reset */ 994
1471 led_ctrl = er32(LEDCTL); 995 /* Set PHY to class A mode (if necessary) */
1472 led_ctrl &= IGP_ACTIVITY_LED_MASK; 996 ret_val = e1000_set_phy_mode(hw);
1473 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 997 if (ret_val)
1474 ew32(LEDCTL, led_ctrl); 998 return ret_val;
1475 } 999
1476 1000 if ((hw->mac_type == e1000_82545_rev_3) ||
1477 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1001 (hw->mac_type == e1000_82546_rev_3)) {
1478 if (hw->phy_type == e1000_phy_igp) { 1002 ret_val =
1479 /* disable lplu d3 during driver init */ 1003 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1480 ret_val = e1000_set_d3_lplu_state(hw, false); 1004 phy_data |= 0x00000008;
1481 if (ret_val) { 1005 ret_val =
1482 DEBUGOUT("Error Disabling LPLU D3\n"); 1006 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1483 return ret_val; 1007 }
1484 } 1008
1485 } 1009 if (hw->mac_type <= e1000_82543 ||
1486 1010 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1487 /* disable lplu d0 during driver init */ 1011 hw->mac_type == e1000_82541_rev_2
1488 ret_val = e1000_set_d0_lplu_state(hw, false); 1012 || hw->mac_type == e1000_82547_rev_2)
1489 if (ret_val) { 1013 hw->phy_reset_disable = false;
1490 DEBUGOUT("Error Disabling LPLU D0\n"); 1014
1491 return ret_val; 1015 return E1000_SUCCESS;
1492 }
1493 /* Configure mdi-mdix settings */
1494 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1495 if (ret_val)
1496 return ret_val;
1497
1498 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1499 hw->dsp_config_state = e1000_dsp_config_disabled;
1500 /* Force MDI for earlier revs of the IGP PHY */
1501 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1502 hw->mdix = 1;
1503
1504 } else {
1505 hw->dsp_config_state = e1000_dsp_config_enabled;
1506 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1507
1508 switch (hw->mdix) {
1509 case 1:
1510 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1511 break;
1512 case 2:
1513 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1514 break;
1515 case 0:
1516 default:
1517 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1518 break;
1519 }
1520 }
1521 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1522 if (ret_val)
1523 return ret_val;
1524
1525 /* set auto-master slave resolution settings */
1526 if (hw->autoneg) {
1527 e1000_ms_type phy_ms_setting = hw->master_slave;
1528
1529 if (hw->ffe_config_state == e1000_ffe_config_active)
1530 hw->ffe_config_state = e1000_ffe_config_enabled;
1531
1532 if (hw->dsp_config_state == e1000_dsp_config_activated)
1533 hw->dsp_config_state = e1000_dsp_config_enabled;
1534
1535 /* when autonegotiation advertisment is only 1000Mbps then we
1536 * should disable SmartSpeed and enable Auto MasterSlave
1537 * resolution as hardware default. */
1538 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1539 /* Disable SmartSpeed */
1540 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1541 &phy_data);
1542 if (ret_val)
1543 return ret_val;
1544 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1545 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1546 phy_data);
1547 if (ret_val)
1548 return ret_val;
1549 /* Set auto Master/Slave resolution process */
1550 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1551 if (ret_val)
1552 return ret_val;
1553 phy_data &= ~CR_1000T_MS_ENABLE;
1554 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1555 if (ret_val)
1556 return ret_val;
1557 }
1558
1559 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1560 if (ret_val)
1561 return ret_val;
1562
1563 /* load defaults for future use */
1564 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1565 ((phy_data & CR_1000T_MS_VALUE) ?
1566 e1000_ms_force_master :
1567 e1000_ms_force_slave) :
1568 e1000_ms_auto;
1569
1570 switch (phy_ms_setting) {
1571 case e1000_ms_force_master:
1572 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1573 break;
1574 case e1000_ms_force_slave:
1575 phy_data |= CR_1000T_MS_ENABLE;
1576 phy_data &= ~(CR_1000T_MS_VALUE);
1577 break;
1578 case e1000_ms_auto:
1579 phy_data &= ~CR_1000T_MS_ENABLE;
1580 default:
1581 break;
1582 }
1583 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1584 if (ret_val)
1585 return ret_val;
1586 }
1587
1588 return E1000_SUCCESS;
1589} 1016}
1590 1017
1591/******************************************************************** 1018/**
1592* Copper link setup for e1000_phy_gg82563 series. 1019 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1593* 1020 * @hw: Struct containing variables accessed by shared code
1594* hw - Struct containing variables accessed by shared code 1021 */
1595*********************************************************************/ 1022static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1596static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1597{ 1023{
1598 s32 ret_val; 1024 u32 led_ctrl;
1599 u16 phy_data; 1025 s32 ret_val;
1600 u32 reg_data; 1026 u16 phy_data;
1601 1027
1602 DEBUGFUNC("e1000_copper_link_ggp_setup"); 1028 DEBUGFUNC("e1000_copper_link_igp_setup");
1603 1029
1604 if (!hw->phy_reset_disable) { 1030 if (hw->phy_reset_disable)
1605 1031 return E1000_SUCCESS;
1606 /* Enable CRS on TX for half-duplex operation. */ 1032
1607 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1033 ret_val = e1000_phy_reset(hw);
1608 &phy_data); 1034 if (ret_val) {
1609 if (ret_val) 1035 DEBUGOUT("Error Resetting the PHY\n");
1610 return ret_val; 1036 return ret_val;
1611 1037 }
1612 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1038
1613 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 1039 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1614 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 1040 msleep(15);
1615 1041 /* Configure activity LED after PHY reset */
1616 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1042 led_ctrl = er32(LEDCTL);
1617 phy_data); 1043 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1618 if (ret_val) 1044 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1619 return ret_val; 1045 ew32(LEDCTL, led_ctrl);
1620 1046
1621 /* Options: 1047 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1622 * MDI/MDI-X = 0 (default) 1048 if (hw->phy_type == e1000_phy_igp) {
1623 * 0 - Auto for all speeds 1049 /* disable lplu d3 during driver init */
1624 * 1 - MDI mode 1050 ret_val = e1000_set_d3_lplu_state(hw, false);
1625 * 2 - MDI-X mode 1051 if (ret_val) {
1626 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1052 DEBUGOUT("Error Disabling LPLU D3\n");
1627 */ 1053 return ret_val;
1628 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); 1054 }
1629 if (ret_val) 1055 }
1630 return ret_val; 1056
1631 1057 /* Configure mdi-mdix settings */
1632 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1058 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1633 1059 if (ret_val)
1634 switch (hw->mdix) { 1060 return ret_val;
1635 case 1: 1061
1636 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1062 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1637 break; 1063 hw->dsp_config_state = e1000_dsp_config_disabled;
1638 case 2: 1064 /* Force MDI for earlier revs of the IGP PHY */
1639 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1065 phy_data &=
1640 break; 1066 ~(IGP01E1000_PSCR_AUTO_MDIX |
1641 case 0: 1067 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1642 default: 1068 hw->mdix = 1;
1643 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1069
1644 break; 1070 } else {
1645 } 1071 hw->dsp_config_state = e1000_dsp_config_enabled;
1646 1072 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1647 /* Options: 1073
1648 * disable_polarity_correction = 0 (default) 1074 switch (hw->mdix) {
1649 * Automatic Correction for Reversed Cable Polarity 1075 case 1:
1650 * 0 - Disabled 1076 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1651 * 1 - Enabled 1077 break;
1652 */ 1078 case 2:
1653 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1079 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1654 if (hw->disable_polarity_correction == 1) 1080 break;
1655 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1081 case 0:
1656 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 1082 default:
1657 1083 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1658 if (ret_val) 1084 break;
1659 return ret_val; 1085 }
1660 1086 }
1661 /* SW Reset the PHY so all changes take effect */ 1087 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1662 ret_val = e1000_phy_reset(hw); 1088 if (ret_val)
1663 if (ret_val) { 1089 return ret_val;
1664 DEBUGOUT("Error Resetting the PHY\n"); 1090
1665 return ret_val; 1091 /* set auto-master slave resolution settings */
1666 } 1092 if (hw->autoneg) {
1667 } /* phy_reset_disable */ 1093 e1000_ms_type phy_ms_setting = hw->master_slave;
1668 1094
1669 if (hw->mac_type == e1000_80003es2lan) { 1095 if (hw->ffe_config_state == e1000_ffe_config_active)
1670 /* Bypass RX and TX FIFO's */ 1096 hw->ffe_config_state = e1000_ffe_config_enabled;
1671 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 1097
1672 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 1098 if (hw->dsp_config_state == e1000_dsp_config_activated)
1673 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 1099 hw->dsp_config_state = e1000_dsp_config_enabled;
1674 if (ret_val) 1100
1675 return ret_val; 1101 /* when autonegotiation advertisement is only 1000Mbps then we
1676 1102 * should disable SmartSpeed and enable Auto MasterSlave
1677 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); 1103 * resolution as hardware default. */
1678 if (ret_val) 1104 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1679 return ret_val; 1105 /* Disable SmartSpeed */
1680 1106 ret_val =
1681 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1107 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1682 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); 1108 &phy_data);
1683 1109 if (ret_val)
1684 if (ret_val) 1110 return ret_val;
1685 return ret_val; 1111 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1686 1112 ret_val =
1687 reg_data = er32(CTRL_EXT); 1113 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1688 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1114 phy_data);
1689 ew32(CTRL_EXT, reg_data); 1115 if (ret_val)
1690 1116 return ret_val;
1691 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1117 /* Set auto Master/Slave resolution process */
1692 &phy_data); 1118 ret_val =
1693 if (ret_val) 1119 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1694 return ret_val; 1120 if (ret_val)
1695 1121 return ret_val;
1696 /* Do not init these registers when the HW is in IAMT mode, since the 1122 phy_data &= ~CR_1000T_MS_ENABLE;
1697 * firmware will have already initialized them. We only initialize 1123 ret_val =
1698 * them if the HW is not in IAMT mode. 1124 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1699 */ 1125 if (ret_val)
1700 if (!e1000_check_mng_mode(hw)) { 1126 return ret_val;
1701 /* Enable Electrical Idle on the PHY */ 1127 }
1702 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1128
1703 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1129 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1704 phy_data); 1130 if (ret_val)
1705 if (ret_val) 1131 return ret_val;
1706 return ret_val; 1132
1707 1133 /* load defaults for future use */
1708 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1134 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1709 &phy_data); 1135 ((phy_data & CR_1000T_MS_VALUE) ?
1710 if (ret_val) 1136 e1000_ms_force_master :
1711 return ret_val; 1137 e1000_ms_force_slave) : e1000_ms_auto;
1712 1138
1713 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1139 switch (phy_ms_setting) {
1714 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1140 case e1000_ms_force_master:
1715 phy_data); 1141 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1716 1142 break;
1717 if (ret_val) 1143 case e1000_ms_force_slave:
1718 return ret_val; 1144 phy_data |= CR_1000T_MS_ENABLE;
1719 } 1145 phy_data &= ~(CR_1000T_MS_VALUE);
1720 1146 break;
1721 /* Workaround: Disable padding in Kumeran interface in the MAC 1147 case e1000_ms_auto:
1722 * and in the PHY to avoid CRC errors. 1148 phy_data &= ~CR_1000T_MS_ENABLE;
1723 */ 1149 default:
1724 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 1150 break;
1725 &phy_data); 1151 }
1726 if (ret_val) 1152 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1727 return ret_val; 1153 if (ret_val)
1728 phy_data |= GG82563_ICR_DIS_PADDING; 1154 return ret_val;
1729 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 1155 }
1730 phy_data); 1156
1731 if (ret_val) 1157 return E1000_SUCCESS;
1732 return ret_val;
1733 }
1734
1735 return E1000_SUCCESS;
1736} 1158}
1737 1159
1738/******************************************************************** 1160/**
1739* Copper link setup for e1000_phy_m88 series. 1161 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1740* 1162 * @hw: Struct containing variables accessed by shared code
1741* hw - Struct containing variables accessed by shared code 1163 */
1742*********************************************************************/
1743static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1164static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1744{ 1165{
1745 s32 ret_val; 1166 s32 ret_val;
1746 u16 phy_data; 1167 u16 phy_data;
1747 1168
1748 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1169 DEBUGFUNC("e1000_copper_link_mgp_setup");
1749 1170
1750 if (hw->phy_reset_disable) 1171 if (hw->phy_reset_disable)
1751 return E1000_SUCCESS; 1172 return E1000_SUCCESS;
1752 1173
1753 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1174 /* Enable CRS on TX. This must be set for half-duplex operation. */
1754 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1175 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1755 if (ret_val) 1176 if (ret_val)
1756 return ret_val; 1177 return ret_val;
1757 1178
1758 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1179 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1759 1180
1760 /* Options: 1181 /* Options:
1761 * MDI/MDI-X = 0 (default) 1182 * MDI/MDI-X = 0 (default)
1762 * 0 - Auto for all speeds 1183 * 0 - Auto for all speeds
1763 * 1 - MDI mode 1184 * 1 - MDI mode
1764 * 2 - MDI-X mode 1185 * 2 - MDI-X mode
1765 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1186 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1766 */ 1187 */
1767 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1188 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1768 1189
1769 switch (hw->mdix) { 1190 switch (hw->mdix) {
1770 case 1: 1191 case 1:
1771 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1192 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1772 break; 1193 break;
1773 case 2: 1194 case 2:
1774 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1195 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1775 break; 1196 break;
1776 case 3: 1197 case 3:
1777 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1198 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1778 break; 1199 break;
1779 case 0: 1200 case 0:
1780 default: 1201 default:
1781 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1202 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1782 break; 1203 break;
1783 } 1204 }
1784 1205
1785 /* Options: 1206 /* Options:
1786 * disable_polarity_correction = 0 (default) 1207 * disable_polarity_correction = 0 (default)
1787 * Automatic Correction for Reversed Cable Polarity 1208 * Automatic Correction for Reversed Cable Polarity
1788 * 0 - Disabled 1209 * 0 - Disabled
1789 * 1 - Enabled 1210 * 1 - Enabled
1790 */ 1211 */
1791 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1212 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1792 if (hw->disable_polarity_correction == 1) 1213 if (hw->disable_polarity_correction == 1)
1793 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1214 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1794 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1215 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1795 if (ret_val) 1216 if (ret_val)
1796 return ret_val; 1217 return ret_val;
1797 1218
1798 if (hw->phy_revision < M88E1011_I_REV_4) { 1219 if (hw->phy_revision < M88E1011_I_REV_4) {
1799 /* Force TX_CLK in the Extended PHY Specific Control Register 1220 /* Force TX_CLK in the Extended PHY Specific Control Register
1800 * to 25MHz clock. 1221 * to 25MHz clock.
1801 */ 1222 */
1802 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1223 ret_val =
1803 if (ret_val) 1224 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1804 return ret_val; 1225 &phy_data);
1805 1226 if (ret_val)
1806 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1227 return ret_val;
1807 1228
1808 if ((hw->phy_revision == E1000_REVISION_2) && 1229 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1809 (hw->phy_id == M88E1111_I_PHY_ID)) { 1230
1810 /* Vidalia Phy, set the downshift counter to 5x */ 1231 if ((hw->phy_revision == E1000_REVISION_2) &&
1811 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1232 (hw->phy_id == M88E1111_I_PHY_ID)) {
1812 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1233 /* Vidalia Phy, set the downshift counter to 5x */
1813 ret_val = e1000_write_phy_reg(hw, 1234 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1814 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1235 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1815 if (ret_val) 1236 ret_val = e1000_write_phy_reg(hw,
1816 return ret_val; 1237 M88E1000_EXT_PHY_SPEC_CTRL,
1817 } else { 1238 phy_data);
1818 /* Configure Master and Slave downshift values */ 1239 if (ret_val)
1819 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1240 return ret_val;
1820 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1241 } else {
1821 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1242 /* Configure Master and Slave downshift values */
1822 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1243 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1823 ret_val = e1000_write_phy_reg(hw, 1244 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1824 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1245 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1825 if (ret_val) 1246 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1826 return ret_val; 1247 ret_val = e1000_write_phy_reg(hw,
1827 } 1248 M88E1000_EXT_PHY_SPEC_CTRL,
1828 } 1249 phy_data);
1829 1250 if (ret_val)
1830 /* SW Reset the PHY so all changes take effect */ 1251 return ret_val;
1831 ret_val = e1000_phy_reset(hw); 1252 }
1832 if (ret_val) { 1253 }
1833 DEBUGOUT("Error Resetting the PHY\n"); 1254
1834 return ret_val; 1255 /* SW Reset the PHY so all changes take effect */
1835 } 1256 ret_val = e1000_phy_reset(hw);
1836 1257 if (ret_val) {
1837 return E1000_SUCCESS; 1258 DEBUGOUT("Error Resetting the PHY\n");
1259 return ret_val;
1260 }
1261
1262 return E1000_SUCCESS;
1838} 1263}
1839 1264
1840/******************************************************************** 1265/**
1841* Setup auto-negotiation and flow control advertisements, 1266 * e1000_copper_link_autoneg - setup auto-neg
1842* and then perform auto-negotiation. 1267 * @hw: Struct containing variables accessed by shared code
1843* 1268 *
1844* hw - Struct containing variables accessed by shared code 1269 * Setup auto-negotiation and flow control advertisements,
1845*********************************************************************/ 1270 * and then perform auto-negotiation.
1271 */
1846static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1272static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1847{ 1273{
1848 s32 ret_val; 1274 s32 ret_val;
1849 u16 phy_data; 1275 u16 phy_data;
1850 1276
1851 DEBUGFUNC("e1000_copper_link_autoneg"); 1277 DEBUGFUNC("e1000_copper_link_autoneg");
1852 1278
1853 /* Perform some bounds checking on the hw->autoneg_advertised 1279 /* Perform some bounds checking on the hw->autoneg_advertised
1854 * parameter. If this variable is zero, then set it to the default. 1280 * parameter. If this variable is zero, then set it to the default.
1855 */ 1281 */
1856 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1282 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1857 1283
1858 /* If autoneg_advertised is zero, we assume it was not defaulted 1284 /* If autoneg_advertised is zero, we assume it was not defaulted
1859 * by the calling code so we set to advertise full capability. 1285 * by the calling code so we set to advertise full capability.
1860 */ 1286 */
1861 if (hw->autoneg_advertised == 0) 1287 if (hw->autoneg_advertised == 0)
1862 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1288 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1863 1289
1864 /* IFE phy only supports 10/100 */ 1290 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1865 if (hw->phy_type == e1000_phy_ife) 1291 ret_val = e1000_phy_setup_autoneg(hw);
1866 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 1292 if (ret_val) {
1867 1293 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1868 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1294 return ret_val;
1869 ret_val = e1000_phy_setup_autoneg(hw); 1295 }
1870 if (ret_val) { 1296 DEBUGOUT("Restarting Auto-Neg\n");
1871 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1297
1872 return ret_val; 1298 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1873 } 1299 * the Auto Neg Restart bit in the PHY control register.
1874 DEBUGOUT("Restarting Auto-Neg\n"); 1300 */
1875 1301 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1876 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1302 if (ret_val)
1877 * the Auto Neg Restart bit in the PHY control register. 1303 return ret_val;
1878 */ 1304
1879 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1305 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1880 if (ret_val) 1306 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1881 return ret_val; 1307 if (ret_val)
1882 1308 return ret_val;
1883 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1309
1884 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1310 /* Does the user want to wait for Auto-Neg to complete here, or
1885 if (ret_val) 1311 * check at a later time (for example, callback routine).
1886 return ret_val; 1312 */
1887 1313 if (hw->wait_autoneg_complete) {
1888 /* Does the user want to wait for Auto-Neg to complete here, or 1314 ret_val = e1000_wait_autoneg(hw);
1889 * check at a later time (for example, callback routine). 1315 if (ret_val) {
1890 */ 1316 DEBUGOUT
1891 if (hw->wait_autoneg_complete) { 1317 ("Error while waiting for autoneg to complete\n");
1892 ret_val = e1000_wait_autoneg(hw); 1318 return ret_val;
1893 if (ret_val) { 1319 }
1894 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1320 }
1895 return ret_val; 1321
1896 } 1322 hw->get_link_status = true;
1897 } 1323
1898 1324 return E1000_SUCCESS;
1899 hw->get_link_status = true;
1900
1901 return E1000_SUCCESS;
1902} 1325}
1903 1326
1904/****************************************************************************** 1327/**
1905* Config the MAC and the PHY after link is up. 1328 * e1000_copper_link_postconfig - post link setup
1906* 1) Set up the MAC to the current PHY speed/duplex 1329 * @hw: Struct containing variables accessed by shared code
1907* if we are on 82543. If we 1330 *
1908* are on newer silicon, we only need to configure 1331 * Config the MAC and the PHY after link is up.
1909* collision distance in the Transmit Control Register. 1332 * 1) Set up the MAC to the current PHY speed/duplex
1910* 2) Set up flow control on the MAC to that established with 1333 * if we are on 82543. If we
1911* the link partner. 1334 * are on newer silicon, we only need to configure
1912* 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1335 * collision distance in the Transmit Control Register.
1913* 1336 * 2) Set up flow control on the MAC to that established with
1914* hw - Struct containing variables accessed by shared code 1337 * the link partner.
1915******************************************************************************/ 1338 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1339 */
1916static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1340static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1917{ 1341{
1918 s32 ret_val; 1342 s32 ret_val;
1919 DEBUGFUNC("e1000_copper_link_postconfig"); 1343 DEBUGFUNC("e1000_copper_link_postconfig");
1920 1344
1921 if (hw->mac_type >= e1000_82544) { 1345 if (hw->mac_type >= e1000_82544) {
1922 e1000_config_collision_dist(hw); 1346 e1000_config_collision_dist(hw);
1923 } else { 1347 } else {
1924 ret_val = e1000_config_mac_to_phy(hw); 1348 ret_val = e1000_config_mac_to_phy(hw);
1925 if (ret_val) { 1349 if (ret_val) {
1926 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1350 DEBUGOUT("Error configuring MAC to PHY settings\n");
1927 return ret_val; 1351 return ret_val;
1928 } 1352 }
1929 } 1353 }
1930 ret_val = e1000_config_fc_after_link_up(hw); 1354 ret_val = e1000_config_fc_after_link_up(hw);
1931 if (ret_val) { 1355 if (ret_val) {
1932 DEBUGOUT("Error Configuring Flow Control\n"); 1356 DEBUGOUT("Error Configuring Flow Control\n");
1933 return ret_val; 1357 return ret_val;
1934 } 1358 }
1935 1359
1936 /* Config DSP to improve Giga link quality */ 1360 /* Config DSP to improve Giga link quality */
1937 if (hw->phy_type == e1000_phy_igp) { 1361 if (hw->phy_type == e1000_phy_igp) {
1938 ret_val = e1000_config_dsp_after_link_change(hw, true); 1362 ret_val = e1000_config_dsp_after_link_change(hw, true);
1939 if (ret_val) { 1363 if (ret_val) {
1940 DEBUGOUT("Error Configuring DSP after link up\n"); 1364 DEBUGOUT("Error Configuring DSP after link up\n");
1941 return ret_val; 1365 return ret_val;
1942 } 1366 }
1943 } 1367 }
1944 1368
1945 return E1000_SUCCESS; 1369 return E1000_SUCCESS;
1946} 1370}
1947 1371
1948/****************************************************************************** 1372/**
1949* Detects which PHY is present and setup the speed and duplex 1373 * e1000_setup_copper_link - phy/speed/duplex setting
1950* 1374 * @hw: Struct containing variables accessed by shared code
1951* hw - Struct containing variables accessed by shared code 1375 *
1952******************************************************************************/ 1376 * Detects which PHY is present and sets up the speed and duplex
1377 */
1953static s32 e1000_setup_copper_link(struct e1000_hw *hw) 1378static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1954{ 1379{
1955 s32 ret_val; 1380 s32 ret_val;
1956 u16 i; 1381 u16 i;
1957 u16 phy_data; 1382 u16 phy_data;
1958 u16 reg_data = 0; 1383
1959 1384 DEBUGFUNC("e1000_setup_copper_link");
1960 DEBUGFUNC("e1000_setup_copper_link"); 1385
1961 1386 /* Check if it is a valid PHY and set PHY mode if necessary. */
1962 switch (hw->mac_type) { 1387 ret_val = e1000_copper_link_preconfig(hw);
1963 case e1000_80003es2lan: 1388 if (ret_val)
1964 case e1000_ich8lan: 1389 return ret_val;
1965 /* Set the mac to wait the maximum time between each 1390
1966 * iteration and increase the max iterations when 1391 if (hw->phy_type == e1000_phy_igp) {
1967 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 1392 ret_val = e1000_copper_link_igp_setup(hw);
1968 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1393 if (ret_val)
1969 if (ret_val) 1394 return ret_val;
1970 return ret_val; 1395 } else if (hw->phy_type == e1000_phy_m88) {
1971 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data); 1396 ret_val = e1000_copper_link_mgp_setup(hw);
1972 if (ret_val) 1397 if (ret_val)
1973 return ret_val; 1398 return ret_val;
1974 reg_data |= 0x3F; 1399 }
1975 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 1400
1976 if (ret_val) 1401 if (hw->autoneg) {
1977 return ret_val; 1402 /* Setup autoneg and flow control advertisement
1978 default: 1403 * and perform autonegotiation */
1979 break; 1404 ret_val = e1000_copper_link_autoneg(hw);
1980 } 1405 if (ret_val)
1981 1406 return ret_val;
1982 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1407 } else {
1983 ret_val = e1000_copper_link_preconfig(hw); 1408 /* PHY will be set to 10H, 10F, 100H,or 100F
1984 if (ret_val) 1409 * depending on value from forced_speed_duplex. */
1985 return ret_val; 1410 DEBUGOUT("Forcing speed and duplex\n");
1986 1411 ret_val = e1000_phy_force_speed_duplex(hw);
1987 switch (hw->mac_type) { 1412 if (ret_val) {
1988 case e1000_80003es2lan: 1413 DEBUGOUT("Error Forcing Speed and Duplex\n");
1989 /* Kumeran registers are written-only */ 1414 return ret_val;
1990 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 1415 }
1991 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 1416 }
1992 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1417
1993 reg_data); 1418 /* Check link status. Wait up to 100 microseconds for link to become
1994 if (ret_val) 1419 * valid.
1995 return ret_val; 1420 */
1996 break; 1421 for (i = 0; i < 10; i++) {
1997 default: 1422 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1998 break; 1423 if (ret_val)
1999 } 1424 return ret_val;
2000 1425 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2001 if (hw->phy_type == e1000_phy_igp || 1426 if (ret_val)
2002 hw->phy_type == e1000_phy_igp_3 || 1427 return ret_val;
2003 hw->phy_type == e1000_phy_igp_2) { 1428
2004 ret_val = e1000_copper_link_igp_setup(hw); 1429 if (phy_data & MII_SR_LINK_STATUS) {
2005 if (ret_val) 1430 /* Config the MAC and PHY after link is up */
2006 return ret_val; 1431 ret_val = e1000_copper_link_postconfig(hw);
2007 } else if (hw->phy_type == e1000_phy_m88) { 1432 if (ret_val)
2008 ret_val = e1000_copper_link_mgp_setup(hw); 1433 return ret_val;
2009 if (ret_val) 1434
2010 return ret_val; 1435 DEBUGOUT("Valid link established!!!\n");
2011 } else if (hw->phy_type == e1000_phy_gg82563) { 1436 return E1000_SUCCESS;
2012 ret_val = e1000_copper_link_ggp_setup(hw); 1437 }
2013 if (ret_val) 1438 udelay(10);
2014 return ret_val; 1439 }
2015 } 1440
2016 1441 DEBUGOUT("Unable to establish link!!!\n");
2017 if (hw->autoneg) { 1442 return E1000_SUCCESS;
2018 /* Setup autoneg and flow control advertisement
2019 * and perform autonegotiation */
2020 ret_val = e1000_copper_link_autoneg(hw);
2021 if (ret_val)
2022 return ret_val;
2023 } else {
2024 /* PHY will be set to 10H, 10F, 100H,or 100F
2025 * depending on value from forced_speed_duplex. */
2026 DEBUGOUT("Forcing speed and duplex\n");
2027 ret_val = e1000_phy_force_speed_duplex(hw);
2028 if (ret_val) {
2029 DEBUGOUT("Error Forcing Speed and Duplex\n");
2030 return ret_val;
2031 }
2032 }
2033
2034 /* Check link status. Wait up to 100 microseconds for link to become
2035 * valid.
2036 */
2037 for (i = 0; i < 10; i++) {
2038 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2039 if (ret_val)
2040 return ret_val;
2041 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2042 if (ret_val)
2043 return ret_val;
2044
2045 if (phy_data & MII_SR_LINK_STATUS) {
2046 /* Config the MAC and PHY after link is up */
2047 ret_val = e1000_copper_link_postconfig(hw);
2048 if (ret_val)
2049 return ret_val;
2050
2051 DEBUGOUT("Valid link established!!!\n");
2052 return E1000_SUCCESS;
2053 }
2054 udelay(10);
2055 }
2056
2057 DEBUGOUT("Unable to establish link!!!\n");
2058 return E1000_SUCCESS;
2059} 1443}
2060 1444
2061/****************************************************************************** 1445/**
2062* Configure the MAC-to-PHY interface for 10/100Mbps 1446 * e1000_phy_setup_autoneg - phy settings
2063* 1447 * @hw: Struct containing variables accessed by shared code
2064* hw - Struct containing variables accessed by shared code 1448 *
2065******************************************************************************/ 1449 * Configures PHY autoneg and flow control advertisement settings
2066static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex) 1450 */
1451s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2067{ 1452{
2068 s32 ret_val = E1000_SUCCESS; 1453 s32 ret_val;
2069 u32 tipg; 1454 u16 mii_autoneg_adv_reg;
2070 u16 reg_data; 1455 u16 mii_1000t_ctrl_reg;
2071 1456
2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1457 DEBUGFUNC("e1000_phy_setup_autoneg");
2073 1458
2074 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 1459 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2075 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 1460 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2076 reg_data); 1461 if (ret_val)
2077 if (ret_val) 1462 return ret_val;
2078 return ret_val;
2079 1463
2080 /* Configure Transmit Inter-Packet Gap */ 1464 /* Read the MII 1000Base-T Control Register (Address 9). */
2081 tipg = er32(TIPG); 1465 ret_val =
2082 tipg &= ~E1000_TIPG_IPGT_MASK; 1466 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2083 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 1467 if (ret_val)
2084 ew32(TIPG, tipg); 1468 return ret_val;
2085 1469
2086 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); 1470 /* Need to parse both autoneg_advertised and fc and set up
1471 * the appropriate PHY registers. First we will parse for
1472 * autoneg_advertised software override. Since we can advertise
1473 * a plethora of combinations, we need to check each bit
1474 * individually.
1475 */
2087 1476
2088 if (ret_val) 1477 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2089 return ret_val; 1478 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1479 * the 1000Base-T Control Register (Address 9).
1480 */
1481 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1482 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2090 1483
2091 if (duplex == HALF_DUPLEX) 1484 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2092 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2093 else
2094 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2095 1485
2096 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1486 /* Do we want to advertise 10 Mb Half Duplex? */
1487 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1488 DEBUGOUT("Advertise 10mb Half duplex\n");
1489 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1490 }
2097 1491
2098 return ret_val; 1492 /* Do we want to advertise 10 Mb Full Duplex? */
2099} 1493 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1494 DEBUGOUT("Advertise 10mb Full duplex\n");
1495 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1496 }
2100 1497
2101static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) 1498 /* Do we want to advertise 100 Mb Half Duplex? */
2102{ 1499 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2103 s32 ret_val = E1000_SUCCESS; 1500 DEBUGOUT("Advertise 100mb Half duplex\n");
2104 u16 reg_data; 1501 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2105 u32 tipg; 1502 }
2106 1503
2107 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1504 /* Do we want to advertise 100 Mb Full Duplex? */
1505 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1506 DEBUGOUT("Advertise 100mb Full duplex\n");
1507 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1508 }
2108 1509
2109 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 1510 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2110 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 1511 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2111 reg_data); 1512 DEBUGOUT
2112 if (ret_val) 1513 ("Advertise 1000mb Half duplex requested, request denied!\n");
2113 return ret_val; 1514 }
2114 1515
2115 /* Configure Transmit Inter-Packet Gap */ 1516 /* Do we want to advertise 1000 Mb Full Duplex? */
2116 tipg = er32(TIPG); 1517 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2117 tipg &= ~E1000_TIPG_IPGT_MASK; 1518 DEBUGOUT("Advertise 1000mb Full duplex\n");
2118 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1519 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2119 ew32(TIPG, tipg); 1520 }
2120 1521
2121 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); 1522 /* Check for a software override of the flow control settings, and
1523 * setup the PHY advertisement registers accordingly. If
1524 * auto-negotiation is enabled, then software will have to set the
1525 * "PAUSE" bits to the correct value in the Auto-Negotiation
1526 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1527 *
1528 * The possible values of the "fc" parameter are:
1529 * 0: Flow control is completely disabled
1530 * 1: Rx flow control is enabled (we can receive pause frames
1531 * but not send pause frames).
1532 * 2: Tx flow control is enabled (we can send pause frames
1533 * but we do not support receiving pause frames).
1534 * 3: Both Rx and TX flow control (symmetric) are enabled.
1535 * other: No software override. The flow control configuration
1536 * in the EEPROM is used.
1537 */
1538 switch (hw->fc) {
1539 case E1000_FC_NONE: /* 0 */
1540 /* Flow control (RX & TX) is completely disabled by a
1541 * software over-ride.
1542 */
1543 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1544 break;
1545 case E1000_FC_RX_PAUSE: /* 1 */
1546 /* RX Flow control is enabled, and TX Flow control is
1547 * disabled, by a software over-ride.
1548 */
1549 /* Since there really isn't a way to advertise that we are
1550 * capable of RX Pause ONLY, we will advertise that we
1551 * support both symmetric and asymmetric RX PAUSE. Later
1552 * (in e1000_config_fc_after_link_up) we will disable the
1553 *hw's ability to send PAUSE frames.
1554 */
1555 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1556 break;
1557 case E1000_FC_TX_PAUSE: /* 2 */
1558 /* TX Flow control is enabled, and RX Flow control is
1559 * disabled, by a software over-ride.
1560 */
1561 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1562 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1563 break;
1564 case E1000_FC_FULL: /* 3 */
1565 /* Flow control (both RX and TX) is enabled by a software
1566 * over-ride.
1567 */
1568 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1569 break;
1570 default:
1571 DEBUGOUT("Flow control param set incorrectly\n");
1572 return -E1000_ERR_CONFIG;
1573 }
2122 1574
2123 if (ret_val) 1575 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2124 return ret_val; 1576 if (ret_val)
1577 return ret_val;
2125 1578
2126 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1579 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2127 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2128 1580
2129 return ret_val; 1581 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2130} 1582 if (ret_val)
1583 return ret_val;
2131 1584
2132/****************************************************************************** 1585 return E1000_SUCCESS;
2133* Configures PHY autoneg and flow control advertisement settings
2134*
2135* hw - Struct containing variables accessed by shared code
2136******************************************************************************/
2137s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2138{
2139 s32 ret_val;
2140 u16 mii_autoneg_adv_reg;
2141 u16 mii_1000t_ctrl_reg;
2142
2143 DEBUGFUNC("e1000_phy_setup_autoneg");
2144
2145 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2146 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2147 if (ret_val)
2148 return ret_val;
2149
2150 if (hw->phy_type != e1000_phy_ife) {
2151 /* Read the MII 1000Base-T Control Register (Address 9). */
2152 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2153 if (ret_val)
2154 return ret_val;
2155 } else
2156 mii_1000t_ctrl_reg=0;
2157
2158 /* Need to parse both autoneg_advertised and fc and set up
2159 * the appropriate PHY registers. First we will parse for
2160 * autoneg_advertised software override. Since we can advertise
2161 * a plethora of combinations, we need to check each bit
2162 * individually.
2163 */
2164
2165 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2166 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2167 * the 1000Base-T Control Register (Address 9).
2168 */
2169 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2170 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2171
2172 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2173
2174 /* Do we want to advertise 10 Mb Half Duplex? */
2175 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2176 DEBUGOUT("Advertise 10mb Half duplex\n");
2177 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2178 }
2179
2180 /* Do we want to advertise 10 Mb Full Duplex? */
2181 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2182 DEBUGOUT("Advertise 10mb Full duplex\n");
2183 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2184 }
2185
2186 /* Do we want to advertise 100 Mb Half Duplex? */
2187 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2188 DEBUGOUT("Advertise 100mb Half duplex\n");
2189 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2190 }
2191
2192 /* Do we want to advertise 100 Mb Full Duplex? */
2193 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2194 DEBUGOUT("Advertise 100mb Full duplex\n");
2195 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2196 }
2197
2198 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2199 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2200 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2201 }
2202
2203 /* Do we want to advertise 1000 Mb Full Duplex? */
2204 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2205 DEBUGOUT("Advertise 1000mb Full duplex\n");
2206 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2207 if (hw->phy_type == e1000_phy_ife) {
2208 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2209 }
2210 }
2211
2212 /* Check for a software override of the flow control settings, and
2213 * setup the PHY advertisement registers accordingly. If
2214 * auto-negotiation is enabled, then software will have to set the
2215 * "PAUSE" bits to the correct value in the Auto-Negotiation
2216 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2217 *
2218 * The possible values of the "fc" parameter are:
2219 * 0: Flow control is completely disabled
2220 * 1: Rx flow control is enabled (we can receive pause frames
2221 * but not send pause frames).
2222 * 2: Tx flow control is enabled (we can send pause frames
2223 * but we do not support receiving pause frames).
2224 * 3: Both Rx and TX flow control (symmetric) are enabled.
2225 * other: No software override. The flow control configuration
2226 * in the EEPROM is used.
2227 */
2228 switch (hw->fc) {
2229 case E1000_FC_NONE: /* 0 */
2230 /* Flow control (RX & TX) is completely disabled by a
2231 * software over-ride.
2232 */
2233 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2234 break;
2235 case E1000_FC_RX_PAUSE: /* 1 */
2236 /* RX Flow control is enabled, and TX Flow control is
2237 * disabled, by a software over-ride.
2238 */
2239 /* Since there really isn't a way to advertise that we are
2240 * capable of RX Pause ONLY, we will advertise that we
2241 * support both symmetric and asymmetric RX PAUSE. Later
2242 * (in e1000_config_fc_after_link_up) we will disable the
2243 *hw's ability to send PAUSE frames.
2244 */
2245 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2246 break;
2247 case E1000_FC_TX_PAUSE: /* 2 */
2248 /* TX Flow control is enabled, and RX Flow control is
2249 * disabled, by a software over-ride.
2250 */
2251 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2252 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2253 break;
2254 case E1000_FC_FULL: /* 3 */
2255 /* Flow control (both RX and TX) is enabled by a software
2256 * over-ride.
2257 */
2258 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2259 break;
2260 default:
2261 DEBUGOUT("Flow control param set incorrectly\n");
2262 return -E1000_ERR_CONFIG;
2263 }
2264
2265 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2266 if (ret_val)
2267 return ret_val;
2268
2269 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2270
2271 if (hw->phy_type != e1000_phy_ife) {
2272 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2273 if (ret_val)
2274 return ret_val;
2275 }
2276
2277 return E1000_SUCCESS;
2278} 1586}
2279 1587
2280/****************************************************************************** 1588/**
2281* Force PHY speed and duplex settings to hw->forced_speed_duplex 1589 * e1000_phy_force_speed_duplex - force link settings
2282* 1590 * @hw: Struct containing variables accessed by shared code
2283* hw - Struct containing variables accessed by shared code 1591 *
2284******************************************************************************/ 1592 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1593 */
2285static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1594static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2286{ 1595{
2287 u32 ctrl; 1596 u32 ctrl;
2288 s32 ret_val; 1597 s32 ret_val;
2289 u16 mii_ctrl_reg; 1598 u16 mii_ctrl_reg;
2290 u16 mii_status_reg; 1599 u16 mii_status_reg;
2291 u16 phy_data; 1600 u16 phy_data;
2292 u16 i; 1601 u16 i;
2293 1602
2294 DEBUGFUNC("e1000_phy_force_speed_duplex"); 1603 DEBUGFUNC("e1000_phy_force_speed_duplex");
2295 1604
2296 /* Turn off Flow control if we are forcing speed and duplex. */ 1605 /* Turn off Flow control if we are forcing speed and duplex. */
2297 hw->fc = E1000_FC_NONE; 1606 hw->fc = E1000_FC_NONE;
2298 1607
2299 DEBUGOUT1("hw->fc = %d\n", hw->fc); 1608 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2300 1609
2301 /* Read the Device Control Register. */ 1610 /* Read the Device Control Register. */
2302 ctrl = er32(CTRL); 1611 ctrl = er32(CTRL);
2303 1612
2304 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1613 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2305 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1614 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2306 ctrl &= ~(DEVICE_SPEED_MASK); 1615 ctrl &= ~(DEVICE_SPEED_MASK);
2307 1616
2308 /* Clear the Auto Speed Detect Enable bit. */ 1617 /* Clear the Auto Speed Detect Enable bit. */
2309 ctrl &= ~E1000_CTRL_ASDE; 1618 ctrl &= ~E1000_CTRL_ASDE;
2310 1619
2311 /* Read the MII Control Register. */ 1620 /* Read the MII Control Register. */
2312 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1621 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2313 if (ret_val) 1622 if (ret_val)
2314 return ret_val; 1623 return ret_val;
2315 1624
2316 /* We need to disable autoneg in order to force link and duplex. */ 1625 /* We need to disable autoneg in order to force link and duplex. */
2317 1626
2318 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1627 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2319 1628
2320 /* Are we forcing Full or Half Duplex? */ 1629 /* Are we forcing Full or Half Duplex? */
2321 if (hw->forced_speed_duplex == e1000_100_full || 1630 if (hw->forced_speed_duplex == e1000_100_full ||
2322 hw->forced_speed_duplex == e1000_10_full) { 1631 hw->forced_speed_duplex == e1000_10_full) {
2323 /* We want to force full duplex so we SET the full duplex bits in the 1632 /* We want to force full duplex so we SET the full duplex bits in the
2324 * Device and MII Control Registers. 1633 * Device and MII Control Registers.
2325 */ 1634 */
2326 ctrl |= E1000_CTRL_FD; 1635 ctrl |= E1000_CTRL_FD;
2327 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1636 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2328 DEBUGOUT("Full Duplex\n"); 1637 DEBUGOUT("Full Duplex\n");
2329 } else { 1638 } else {
2330 /* We want to force half duplex so we CLEAR the full duplex bits in 1639 /* We want to force half duplex so we CLEAR the full duplex bits in
2331 * the Device and MII Control Registers. 1640 * the Device and MII Control Registers.
2332 */ 1641 */
2333 ctrl &= ~E1000_CTRL_FD; 1642 ctrl &= ~E1000_CTRL_FD;
2334 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1643 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2335 DEBUGOUT("Half Duplex\n"); 1644 DEBUGOUT("Half Duplex\n");
2336 } 1645 }
2337 1646
2338 /* Are we forcing 100Mbps??? */ 1647 /* Are we forcing 100Mbps??? */
2339 if (hw->forced_speed_duplex == e1000_100_full || 1648 if (hw->forced_speed_duplex == e1000_100_full ||
2340 hw->forced_speed_duplex == e1000_100_half) { 1649 hw->forced_speed_duplex == e1000_100_half) {
2341 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1650 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2342 ctrl |= E1000_CTRL_SPD_100; 1651 ctrl |= E1000_CTRL_SPD_100;
2343 mii_ctrl_reg |= MII_CR_SPEED_100; 1652 mii_ctrl_reg |= MII_CR_SPEED_100;
2344 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1653 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2345 DEBUGOUT("Forcing 100mb "); 1654 DEBUGOUT("Forcing 100mb ");
2346 } else { 1655 } else {
2347 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1656 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2348 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1657 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2349 mii_ctrl_reg |= MII_CR_SPEED_10; 1658 mii_ctrl_reg |= MII_CR_SPEED_10;
2350 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1659 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2351 DEBUGOUT("Forcing 10mb "); 1660 DEBUGOUT("Forcing 10mb ");
2352 } 1661 }
2353 1662
2354 e1000_config_collision_dist(hw); 1663 e1000_config_collision_dist(hw);
2355 1664
2356 /* Write the configured values back to the Device Control Reg. */ 1665 /* Write the configured values back to the Device Control Reg. */
2357 ew32(CTRL, ctrl); 1666 ew32(CTRL, ctrl);
2358 1667
2359 if ((hw->phy_type == e1000_phy_m88) || 1668 if (hw->phy_type == e1000_phy_m88) {
2360 (hw->phy_type == e1000_phy_gg82563)) { 1669 ret_val =
2361 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1670 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2362 if (ret_val) 1671 if (ret_val)
2363 return ret_val; 1672 return ret_val;
2364 1673
2365 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1674 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2366 * forced whenever speed are duplex are forced. 1675 * forced whenever speed are duplex are forced.
2367 */ 1676 */
2368 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1677 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2369 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1678 ret_val =
2370 if (ret_val) 1679 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2371 return ret_val; 1680 if (ret_val)
2372 1681 return ret_val;
2373 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 1682
2374 1683 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2375 /* Need to reset the PHY or these changes will be ignored */ 1684
2376 mii_ctrl_reg |= MII_CR_RESET; 1685 /* Need to reset the PHY or these changes will be ignored */
2377 1686 mii_ctrl_reg |= MII_CR_RESET;
2378 /* Disable MDI-X support for 10/100 */ 1687
2379 } else if (hw->phy_type == e1000_phy_ife) { 1688 /* Disable MDI-X support for 10/100 */
2380 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 1689 } else {
2381 if (ret_val) 1690 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2382 return ret_val; 1691 * forced whenever speed or duplex are forced.
2383 1692 */
2384 phy_data &= ~IFE_PMC_AUTO_MDIX; 1693 ret_val =
2385 phy_data &= ~IFE_PMC_FORCE_MDIX; 1694 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2386 1695 if (ret_val)
2387 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 1696 return ret_val;
2388 if (ret_val) 1697
2389 return ret_val; 1698 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2390 1699 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2391 } else { 1700
2392 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1701 ret_val =
2393 * forced whenever speed or duplex are forced. 1702 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2394 */ 1703 if (ret_val)
2395 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1704 return ret_val;
2396 if (ret_val) 1705 }
2397 return ret_val; 1706
2398 1707 /* Write back the modified PHY MII control register. */
2399 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1708 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2400 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1709 if (ret_val)
2401 1710 return ret_val;
2402 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1711
2403 if (ret_val) 1712 udelay(1);
2404 return ret_val; 1713
2405 } 1714 /* The wait_autoneg_complete flag may be a little misleading here.
2406 1715 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2407 /* Write back the modified PHY MII control register. */ 1716 * But we do want to delay for a period while forcing only so we
2408 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1717 * don't generate false No Link messages. So we will wait here
2409 if (ret_val) 1718 * only if the user has set wait_autoneg_complete to 1, which is
2410 return ret_val; 1719 * the default.
2411 1720 */
2412 udelay(1); 1721 if (hw->wait_autoneg_complete) {
2413 1722 /* We will wait for autoneg to complete. */
2414 /* The wait_autoneg_complete flag may be a little misleading here. 1723 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2415 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1724 mii_status_reg = 0;
2416 * But we do want to delay for a period while forcing only so we 1725
2417 * don't generate false No Link messages. So we will wait here 1726 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2418 * only if the user has set wait_autoneg_complete to 1, which is 1727 for (i = PHY_FORCE_TIME; i > 0; i--) {
2419 * the default. 1728 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2420 */ 1729 * to be set.
2421 if (hw->wait_autoneg_complete) { 1730 */
2422 /* We will wait for autoneg to complete. */ 1731 ret_val =
2423 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 1732 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2424 mii_status_reg = 0; 1733 if (ret_val)
2425 1734 return ret_val;
2426 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1735
2427 for (i = PHY_FORCE_TIME; i > 0; i--) { 1736 ret_val =
2428 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1737 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2429 * to be set. 1738 if (ret_val)
2430 */ 1739 return ret_val;
2431 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1740
2432 if (ret_val) 1741 if (mii_status_reg & MII_SR_LINK_STATUS)
2433 return ret_val; 1742 break;
2434 1743 msleep(100);
2435 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1744 }
2436 if (ret_val) 1745 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
2437 return ret_val; 1746 /* We didn't get link. Reset the DSP and wait again for link. */
2438 1747 ret_val = e1000_phy_reset_dsp(hw);
2439 if (mii_status_reg & MII_SR_LINK_STATUS) break; 1748 if (ret_val) {
2440 msleep(100); 1749 DEBUGOUT("Error Resetting PHY DSP\n");
2441 } 1750 return ret_val;
2442 if ((i == 0) && 1751 }
2443 ((hw->phy_type == e1000_phy_m88) || 1752 }
2444 (hw->phy_type == e1000_phy_gg82563))) { 1753 /* This loop will early-out if the link condition has been met. */
2445 /* We didn't get link. Reset the DSP and wait again for link. */ 1754 for (i = PHY_FORCE_TIME; i > 0; i--) {
2446 ret_val = e1000_phy_reset_dsp(hw); 1755 if (mii_status_reg & MII_SR_LINK_STATUS)
2447 if (ret_val) { 1756 break;
2448 DEBUGOUT("Error Resetting PHY DSP\n"); 1757 msleep(100);
2449 return ret_val; 1758 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2450 } 1759 * to be set.
2451 } 1760 */
2452 /* This loop will early-out if the link condition has been met. */ 1761 ret_val =
2453 for (i = PHY_FORCE_TIME; i > 0; i--) { 1762 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2454 if (mii_status_reg & MII_SR_LINK_STATUS) break; 1763 if (ret_val)
2455 msleep(100); 1764 return ret_val;
2456 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1765
2457 * to be set. 1766 ret_val =
2458 */ 1767 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2459 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1768 if (ret_val)
2460 if (ret_val) 1769 return ret_val;
2461 return ret_val; 1770 }
2462 1771 }
2463 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1772
2464 if (ret_val) 1773 if (hw->phy_type == e1000_phy_m88) {
2465 return ret_val; 1774 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2466 } 1775 * Extended PHY Specific Control Register to 25MHz clock. This value
2467 } 1776 * defaults back to a 2.5MHz clock when the PHY is reset.
2468 1777 */
2469 if (hw->phy_type == e1000_phy_m88) { 1778 ret_val =
2470 /* Because we reset the PHY above, we need to re-force TX_CLK in the 1779 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2471 * Extended PHY Specific Control Register to 25MHz clock. This value 1780 &phy_data);
2472 * defaults back to a 2.5MHz clock when the PHY is reset. 1781 if (ret_val)
2473 */ 1782 return ret_val;
2474 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1783
2475 if (ret_val) 1784 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2476 return ret_val; 1785 ret_val =
2477 1786 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2478 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1787 phy_data);
2479 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1788 if (ret_val)
2480 if (ret_val) 1789 return ret_val;
2481 return ret_val; 1790
2482 1791 /* In addition, because of the s/w reset above, we need to enable CRS on
2483 /* In addition, because of the s/w reset above, we need to enable CRS on 1792 * TX. This must be set for both full and half duplex operation.
2484 * TX. This must be set for both full and half duplex operation. 1793 */
2485 */ 1794 ret_val =
2486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1795 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2487 if (ret_val) 1796 if (ret_val)
2488 return ret_val; 1797 return ret_val;
2489 1798
2490 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1799 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2491 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1800 ret_val =
2492 if (ret_val) 1801 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2493 return ret_val; 1802 if (ret_val)
2494 1803 return ret_val;
2495 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 1804
2496 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || 1805 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
2497 hw->forced_speed_duplex == e1000_10_half)) { 1806 && (!hw->autoneg)
2498 ret_val = e1000_polarity_reversal_workaround(hw); 1807 && (hw->forced_speed_duplex == e1000_10_full
2499 if (ret_val) 1808 || hw->forced_speed_duplex == e1000_10_half)) {
2500 return ret_val; 1809 ret_val = e1000_polarity_reversal_workaround(hw);
2501 } 1810 if (ret_val)
2502 } else if (hw->phy_type == e1000_phy_gg82563) { 1811 return ret_val;
2503 /* The TX_CLK of the Extended PHY Specific Control Register defaults 1812 }
2504 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if 1813 }
2505 * we're not in a forced 10/duplex configuration. */ 1814 return E1000_SUCCESS;
2506 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2507 if (ret_val)
2508 return ret_val;
2509
2510 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2511 if ((hw->forced_speed_duplex == e1000_10_full) ||
2512 (hw->forced_speed_duplex == e1000_10_half))
2513 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2514 else
2515 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2516
2517 /* Also due to the reset, we need to enable CRS on Tx. */
2518 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2519
2520 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2521 if (ret_val)
2522 return ret_val;
2523 }
2524 return E1000_SUCCESS;
2525} 1815}
2526 1816
2527/****************************************************************************** 1817/**
2528* Sets the collision distance in the Transmit Control register 1818 * e1000_config_collision_dist - set collision distance register
2529* 1819 * @hw: Struct containing variables accessed by shared code
2530* hw - Struct containing variables accessed by shared code 1820 *
2531* 1821 * Sets the collision distance in the Transmit Control register.
2532* Link should have been established previously. Reads the speed and duplex 1822 * Link should have been established previously. Reads the speed and duplex
2533* information from the Device Status register. 1823 * information from the Device Status register.
2534******************************************************************************/ 1824 */
2535void e1000_config_collision_dist(struct e1000_hw *hw) 1825void e1000_config_collision_dist(struct e1000_hw *hw)
2536{ 1826{
2537 u32 tctl, coll_dist; 1827 u32 tctl, coll_dist;
2538 1828
2539 DEBUGFUNC("e1000_config_collision_dist"); 1829 DEBUGFUNC("e1000_config_collision_dist");
2540 1830
2541 if (hw->mac_type < e1000_82543) 1831 if (hw->mac_type < e1000_82543)
2542 coll_dist = E1000_COLLISION_DISTANCE_82542; 1832 coll_dist = E1000_COLLISION_DISTANCE_82542;
2543 else 1833 else
2544 coll_dist = E1000_COLLISION_DISTANCE; 1834 coll_dist = E1000_COLLISION_DISTANCE;
2545 1835
2546 tctl = er32(TCTL); 1836 tctl = er32(TCTL);
2547 1837
2548 tctl &= ~E1000_TCTL_COLD; 1838 tctl &= ~E1000_TCTL_COLD;
2549 tctl |= coll_dist << E1000_COLD_SHIFT; 1839 tctl |= coll_dist << E1000_COLD_SHIFT;
2550 1840
2551 ew32(TCTL, tctl); 1841 ew32(TCTL, tctl);
2552 E1000_WRITE_FLUSH(); 1842 E1000_WRITE_FLUSH();
2553} 1843}
2554 1844
2555/****************************************************************************** 1845/**
2556* Sets MAC speed and duplex settings to reflect the those in the PHY 1846 * e1000_config_mac_to_phy - sync phy and mac settings
2557* 1847 * @hw: Struct containing variables accessed by shared code
2558* hw - Struct containing variables accessed by shared code 1848 * @mii_reg: data to write to the MII control register
2559* mii_reg - data to write to the MII control register 1849 *
2560* 1850 * Sets MAC speed and duplex settings to reflect the those in the PHY
2561* The contents of the PHY register containing the needed information need to 1851 * The contents of the PHY register containing the needed information need to
2562* be passed in. 1852 * be passed in.
2563******************************************************************************/ 1853 */
2564static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) 1854static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
2565{ 1855{
2566 u32 ctrl; 1856 u32 ctrl;
2567 s32 ret_val; 1857 s32 ret_val;
2568 u16 phy_data; 1858 u16 phy_data;
2569 1859
2570 DEBUGFUNC("e1000_config_mac_to_phy"); 1860 DEBUGFUNC("e1000_config_mac_to_phy");
2571 1861
2572 /* 82544 or newer MAC, Auto Speed Detection takes care of 1862 /* 82544 or newer MAC, Auto Speed Detection takes care of
2573 * MAC speed/duplex configuration.*/ 1863 * MAC speed/duplex configuration.*/
2574 if (hw->mac_type >= e1000_82544) 1864 if (hw->mac_type >= e1000_82544)
2575 return E1000_SUCCESS; 1865 return E1000_SUCCESS;
2576 1866
2577 /* Read the Device Control Register and set the bits to Force Speed 1867 /* Read the Device Control Register and set the bits to Force Speed
2578 * and Duplex. 1868 * and Duplex.
2579 */ 1869 */
2580 ctrl = er32(CTRL); 1870 ctrl = er32(CTRL);
2581 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1871 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2582 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1872 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2583 1873
2584 /* Set up duplex in the Device Control and Transmit Control 1874 /* Set up duplex in the Device Control and Transmit Control
2585 * registers depending on negotiated values. 1875 * registers depending on negotiated values.
2586 */ 1876 */
2587 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1877 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2588 if (ret_val) 1878 if (ret_val)
2589 return ret_val; 1879 return ret_val;
2590 1880
2591 if (phy_data & M88E1000_PSSR_DPLX) 1881 if (phy_data & M88E1000_PSSR_DPLX)
2592 ctrl |= E1000_CTRL_FD; 1882 ctrl |= E1000_CTRL_FD;
2593 else 1883 else
2594 ctrl &= ~E1000_CTRL_FD; 1884 ctrl &= ~E1000_CTRL_FD;
2595 1885
2596 e1000_config_collision_dist(hw); 1886 e1000_config_collision_dist(hw);
2597 1887
2598 /* Set up speed in the Device Control register depending on 1888 /* Set up speed in the Device Control register depending on
2599 * negotiated values. 1889 * negotiated values.
2600 */ 1890 */
2601 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1891 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2602 ctrl |= E1000_CTRL_SPD_1000; 1892 ctrl |= E1000_CTRL_SPD_1000;
2603 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1893 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2604 ctrl |= E1000_CTRL_SPD_100; 1894 ctrl |= E1000_CTRL_SPD_100;
2605 1895
2606 /* Write the configured values back to the Device Control Reg. */ 1896 /* Write the configured values back to the Device Control Reg. */
2607 ew32(CTRL, ctrl); 1897 ew32(CTRL, ctrl);
2608 return E1000_SUCCESS; 1898 return E1000_SUCCESS;
2609} 1899}
2610 1900
2611/****************************************************************************** 1901/**
2612 * Forces the MAC's flow control settings. 1902 * e1000_force_mac_fc - force flow control settings
2613 * 1903 * @hw: Struct containing variables accessed by shared code
2614 * hw - Struct containing variables accessed by shared code
2615 * 1904 *
1905 * Forces the MAC's flow control settings.
2616 * Sets the TFCE and RFCE bits in the device control register to reflect 1906 * Sets the TFCE and RFCE bits in the device control register to reflect
2617 * the adapter settings. TFCE and RFCE need to be explicitly set by 1907 * the adapter settings. TFCE and RFCE need to be explicitly set by
2618 * software when a Copper PHY is used because autonegotiation is managed 1908 * software when a Copper PHY is used because autonegotiation is managed
2619 * by the PHY rather than the MAC. Software must also configure these 1909 * by the PHY rather than the MAC. Software must also configure these
2620 * bits when link is forced on a fiber connection. 1910 * bits when link is forced on a fiber connection.
2621 *****************************************************************************/ 1911 */
2622s32 e1000_force_mac_fc(struct e1000_hw *hw) 1912s32 e1000_force_mac_fc(struct e1000_hw *hw)
2623{ 1913{
2624 u32 ctrl; 1914 u32 ctrl;
2625 1915
2626 DEBUGFUNC("e1000_force_mac_fc"); 1916 DEBUGFUNC("e1000_force_mac_fc");
2627 1917
2628 /* Get the current configuration of the Device Control Register */ 1918 /* Get the current configuration of the Device Control Register */
2629 ctrl = er32(CTRL); 1919 ctrl = er32(CTRL);
2630 1920
2631 /* Because we didn't get link via the internal auto-negotiation 1921 /* Because we didn't get link via the internal auto-negotiation
2632 * mechanism (we either forced link or we got link via PHY 1922 * mechanism (we either forced link or we got link via PHY
2633 * auto-neg), we have to manually enable/disable transmit an 1923 * auto-neg), we have to manually enable/disable transmit an
2634 * receive flow control. 1924 * receive flow control.
2635 * 1925 *
2636 * The "Case" statement below enables/disable flow control 1926 * The "Case" statement below enables/disable flow control
2637 * according to the "hw->fc" parameter. 1927 * according to the "hw->fc" parameter.
2638 * 1928 *
2639 * The possible values of the "fc" parameter are: 1929 * The possible values of the "fc" parameter are:
2640 * 0: Flow control is completely disabled 1930 * 0: Flow control is completely disabled
2641 * 1: Rx flow control is enabled (we can receive pause 1931 * 1: Rx flow control is enabled (we can receive pause
2642 * frames but not send pause frames). 1932 * frames but not send pause frames).
2643 * 2: Tx flow control is enabled (we can send pause frames 1933 * 2: Tx flow control is enabled (we can send pause frames
2644 * frames but we do not receive pause frames). 1934 * frames but we do not receive pause frames).
2645 * 3: Both Rx and TX flow control (symmetric) is enabled. 1935 * 3: Both Rx and TX flow control (symmetric) is enabled.
2646 * other: No other values should be possible at this point. 1936 * other: No other values should be possible at this point.
2647 */ 1937 */
2648 1938
2649 switch (hw->fc) { 1939 switch (hw->fc) {
2650 case E1000_FC_NONE: 1940 case E1000_FC_NONE:
2651 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1941 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2652 break; 1942 break;
2653 case E1000_FC_RX_PAUSE: 1943 case E1000_FC_RX_PAUSE:
2654 ctrl &= (~E1000_CTRL_TFCE); 1944 ctrl &= (~E1000_CTRL_TFCE);
2655 ctrl |= E1000_CTRL_RFCE; 1945 ctrl |= E1000_CTRL_RFCE;
2656 break; 1946 break;
2657 case E1000_FC_TX_PAUSE: 1947 case E1000_FC_TX_PAUSE:
2658 ctrl &= (~E1000_CTRL_RFCE); 1948 ctrl &= (~E1000_CTRL_RFCE);
2659 ctrl |= E1000_CTRL_TFCE; 1949 ctrl |= E1000_CTRL_TFCE;
2660 break; 1950 break;
2661 case E1000_FC_FULL: 1951 case E1000_FC_FULL:
2662 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1952 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2663 break; 1953 break;
2664 default: 1954 default:
2665 DEBUGOUT("Flow control param set incorrectly\n"); 1955 DEBUGOUT("Flow control param set incorrectly\n");
2666 return -E1000_ERR_CONFIG; 1956 return -E1000_ERR_CONFIG;
2667 } 1957 }
2668 1958
2669 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1959 /* Disable TX Flow Control for 82542 (rev 2.0) */
2670 if (hw->mac_type == e1000_82542_rev2_0) 1960 if (hw->mac_type == e1000_82542_rev2_0)
2671 ctrl &= (~E1000_CTRL_TFCE); 1961 ctrl &= (~E1000_CTRL_TFCE);
2672 1962
2673 ew32(CTRL, ctrl); 1963 ew32(CTRL, ctrl);
2674 return E1000_SUCCESS; 1964 return E1000_SUCCESS;
2675} 1965}
2676 1966
2677/****************************************************************************** 1967/**
2678 * Configures flow control settings after link is established 1968 * e1000_config_fc_after_link_up - configure flow control after autoneg
2679 * 1969 * @hw: Struct containing variables accessed by shared code
2680 * hw - Struct containing variables accessed by shared code
2681 * 1970 *
1971 * Configures flow control settings after link is established
2682 * Should be called immediately after a valid link has been established. 1972 * Should be called immediately after a valid link has been established.
2683 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1973 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2684 * and autonegotiation is enabled, the MAC flow control settings will be set 1974 * and autonegotiation is enabled, the MAC flow control settings will be set
2685 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1975 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2686 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1976 * and RFCE bits will be automatically set to the negotiated flow control mode.
2687 *****************************************************************************/ 1977 */
2688static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1978static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2689{ 1979{
2690 s32 ret_val; 1980 s32 ret_val;
2691 u16 mii_status_reg; 1981 u16 mii_status_reg;
2692 u16 mii_nway_adv_reg; 1982 u16 mii_nway_adv_reg;
2693 u16 mii_nway_lp_ability_reg; 1983 u16 mii_nway_lp_ability_reg;
2694 u16 speed; 1984 u16 speed;
2695 u16 duplex; 1985 u16 duplex;
2696 1986
2697 DEBUGFUNC("e1000_config_fc_after_link_up"); 1987 DEBUGFUNC("e1000_config_fc_after_link_up");
2698 1988
2699 /* Check for the case where we have fiber media and auto-neg failed 1989 /* Check for the case where we have fiber media and auto-neg failed
2700 * so we had to force link. In this case, we need to force the 1990 * so we had to force link. In this case, we need to force the
2701 * configuration of the MAC to match the "fc" parameter. 1991 * configuration of the MAC to match the "fc" parameter.
2702 */ 1992 */
2703 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || 1993 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
2704 ((hw->media_type == e1000_media_type_internal_serdes) && 1994 || ((hw->media_type == e1000_media_type_internal_serdes)
2705 (hw->autoneg_failed)) || 1995 && (hw->autoneg_failed))
2706 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { 1996 || ((hw->media_type == e1000_media_type_copper)
2707 ret_val = e1000_force_mac_fc(hw); 1997 && (!hw->autoneg))) {
2708 if (ret_val) { 1998 ret_val = e1000_force_mac_fc(hw);
2709 DEBUGOUT("Error forcing flow control settings\n"); 1999 if (ret_val) {
2710 return ret_val; 2000 DEBUGOUT("Error forcing flow control settings\n");
2711 } 2001 return ret_val;
2712 } 2002 }
2713 2003 }
2714 /* Check for the case where we have copper media and auto-neg is 2004
2715 * enabled. In this case, we need to check and see if Auto-Neg 2005 /* Check for the case where we have copper media and auto-neg is
2716 * has completed, and if so, how the PHY and link partner has 2006 * enabled. In this case, we need to check and see if Auto-Neg
2717 * flow control configured. 2007 * has completed, and if so, how the PHY and link partner has
2718 */ 2008 * flow control configured.
2719 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2009 */
2720 /* Read the MII Status Register and check to see if AutoNeg 2010 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2721 * has completed. We read this twice because this reg has 2011 /* Read the MII Status Register and check to see if AutoNeg
2722 * some "sticky" (latched) bits. 2012 * has completed. We read this twice because this reg has
2723 */ 2013 * some "sticky" (latched) bits.
2724 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2014 */
2725 if (ret_val) 2015 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2726 return ret_val; 2016 if (ret_val)
2727 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2017 return ret_val;
2728 if (ret_val) 2018 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2729 return ret_val; 2019 if (ret_val)
2730 2020 return ret_val;
2731 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2021
2732 /* The AutoNeg process has completed, so we now need to 2022 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2733 * read both the Auto Negotiation Advertisement Register 2023 /* The AutoNeg process has completed, so we now need to
2734 * (Address 4) and the Auto_Negotiation Base Page Ability 2024 * read both the Auto Negotiation Advertisement Register
2735 * Register (Address 5) to determine how flow control was 2025 * (Address 4) and the Auto_Negotiation Base Page Ability
2736 * negotiated. 2026 * Register (Address 5) to determine how flow control was
2737 */ 2027 * negotiated.
2738 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2028 */
2739 &mii_nway_adv_reg); 2029 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2740 if (ret_val) 2030 &mii_nway_adv_reg);
2741 return ret_val; 2031 if (ret_val)
2742 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2032 return ret_val;
2743 &mii_nway_lp_ability_reg); 2033 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2744 if (ret_val) 2034 &mii_nway_lp_ability_reg);
2745 return ret_val; 2035 if (ret_val)
2746 2036 return ret_val;
2747 /* Two bits in the Auto Negotiation Advertisement Register 2037
2748 * (Address 4) and two bits in the Auto Negotiation Base 2038 /* Two bits in the Auto Negotiation Advertisement Register
2749 * Page Ability Register (Address 5) determine flow control 2039 * (Address 4) and two bits in the Auto Negotiation Base
2750 * for both the PHY and the link partner. The following 2040 * Page Ability Register (Address 5) determine flow control
2751 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 2041 * for both the PHY and the link partner. The following
2752 * 1999, describes these PAUSE resolution bits and how flow 2042 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2753 * control is determined based upon these settings. 2043 * 1999, describes these PAUSE resolution bits and how flow
2754 * NOTE: DC = Don't Care 2044 * control is determined based upon these settings.
2755 * 2045 * NOTE: DC = Don't Care
2756 * LOCAL DEVICE | LINK PARTNER 2046 *
2757 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2047 * LOCAL DEVICE | LINK PARTNER
2758 *-------|---------|-------|---------|-------------------- 2048 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2759 * 0 | 0 | DC | DC | E1000_FC_NONE 2049 *-------|---------|-------|---------|--------------------
2760 * 0 | 1 | 0 | DC | E1000_FC_NONE 2050 * 0 | 0 | DC | DC | E1000_FC_NONE
2761 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2051 * 0 | 1 | 0 | DC | E1000_FC_NONE
2762 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2052 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2763 * 1 | 0 | 0 | DC | E1000_FC_NONE 2053 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2764 * 1 | DC | 1 | DC | E1000_FC_FULL 2054 * 1 | 0 | 0 | DC | E1000_FC_NONE
2765 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2055 * 1 | DC | 1 | DC | E1000_FC_FULL
2766 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2056 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2767 * 2057 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2768 */ 2058 *
2769 /* Are both PAUSE bits set to 1? If so, this implies 2059 */
2770 * Symmetric Flow Control is enabled at both ends. The 2060 /* Are both PAUSE bits set to 1? If so, this implies
2771 * ASM_DIR bits are irrelevant per the spec. 2061 * Symmetric Flow Control is enabled at both ends. The
2772 * 2062 * ASM_DIR bits are irrelevant per the spec.
2773 * For Symmetric Flow Control: 2063 *
2774 * 2064 * For Symmetric Flow Control:
2775 * LOCAL DEVICE | LINK PARTNER 2065 *
2776 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2066 * LOCAL DEVICE | LINK PARTNER
2777 *-------|---------|-------|---------|-------------------- 2067 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2778 * 1 | DC | 1 | DC | E1000_FC_FULL 2068 *-------|---------|-------|---------|--------------------
2779 * 2069 * 1 | DC | 1 | DC | E1000_FC_FULL
2780 */ 2070 *
2781 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2071 */
2782 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2072 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2783 /* Now we need to check if the user selected RX ONLY 2073 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2784 * of pause frames. In this case, we had to advertise 2074 /* Now we need to check if the user selected RX ONLY
2785 * FULL flow control because we could not advertise RX 2075 * of pause frames. In this case, we had to advertise
2786 * ONLY. Hence, we must now check to see if we need to 2076 * FULL flow control because we could not advertise RX
2787 * turn OFF the TRANSMISSION of PAUSE frames. 2077 * ONLY. Hence, we must now check to see if we need to
2788 */ 2078 * turn OFF the TRANSMISSION of PAUSE frames.
2789 if (hw->original_fc == E1000_FC_FULL) { 2079 */
2790 hw->fc = E1000_FC_FULL; 2080 if (hw->original_fc == E1000_FC_FULL) {
2791 DEBUGOUT("Flow Control = FULL.\n"); 2081 hw->fc = E1000_FC_FULL;
2792 } else { 2082 DEBUGOUT("Flow Control = FULL.\n");
2793 hw->fc = E1000_FC_RX_PAUSE; 2083 } else {
2794 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2084 hw->fc = E1000_FC_RX_PAUSE;
2795 } 2085 DEBUGOUT
2796 } 2086 ("Flow Control = RX PAUSE frames only.\n");
2797 /* For receiving PAUSE frames ONLY. 2087 }
2798 * 2088 }
2799 * LOCAL DEVICE | LINK PARTNER 2089 /* For receiving PAUSE frames ONLY.
2800 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2090 *
2801 *-------|---------|-------|---------|-------------------- 2091 * LOCAL DEVICE | LINK PARTNER
2802 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2092 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2803 * 2093 *-------|---------|-------|---------|--------------------
2804 */ 2094 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2805 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2095 *
2806 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2096 */
2807 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2097 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2808 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2098 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2809 hw->fc = E1000_FC_TX_PAUSE; 2099 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2810 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2100 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2811 } 2101 {
2812 /* For transmitting PAUSE frames ONLY. 2102 hw->fc = E1000_FC_TX_PAUSE;
2813 * 2103 DEBUGOUT
2814 * LOCAL DEVICE | LINK PARTNER 2104 ("Flow Control = TX PAUSE frames only.\n");
2815 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2105 }
2816 *-------|---------|-------|---------|-------------------- 2106 /* For transmitting PAUSE frames ONLY.
2817 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2107 *
2818 * 2108 * LOCAL DEVICE | LINK PARTNER
2819 */ 2109 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2820 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2110 *-------|---------|-------|---------|--------------------
2821 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2111 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2822 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2112 *
2823 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2113 */
2824 hw->fc = E1000_FC_RX_PAUSE; 2114 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2825 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2115 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2826 } 2116 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2827 /* Per the IEEE spec, at this point flow control should be 2117 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2828 * disabled. However, we want to consider that we could 2118 {
2829 * be connected to a legacy switch that doesn't advertise 2119 hw->fc = E1000_FC_RX_PAUSE;
2830 * desired flow control, but can be forced on the link 2120 DEBUGOUT
2831 * partner. So if we advertised no flow control, that is 2121 ("Flow Control = RX PAUSE frames only.\n");
2832 * what we will resolve to. If we advertised some kind of 2122 }
2833 * receive capability (Rx Pause Only or Full Flow Control) 2123 /* Per the IEEE spec, at this point flow control should be
2834 * and the link partner advertised none, we will configure 2124 * disabled. However, we want to consider that we could
2835 * ourselves to enable Rx Flow Control only. We can do 2125 * be connected to a legacy switch that doesn't advertise
2836 * this safely for two reasons: If the link partner really 2126 * desired flow control, but can be forced on the link
2837 * didn't want flow control enabled, and we enable Rx, no 2127 * partner. So if we advertised no flow control, that is
2838 * harm done since we won't be receiving any PAUSE frames 2128 * what we will resolve to. If we advertised some kind of
2839 * anyway. If the intent on the link partner was to have 2129 * receive capability (Rx Pause Only or Full Flow Control)
2840 * flow control enabled, then by us enabling RX only, we 2130 * and the link partner advertised none, we will configure
2841 * can at least receive pause frames and process them. 2131 * ourselves to enable Rx Flow Control only. We can do
2842 * This is a good idea because in most cases, since we are 2132 * this safely for two reasons: If the link partner really
2843 * predominantly a server NIC, more times than not we will 2133 * didn't want flow control enabled, and we enable Rx, no
2844 * be asked to delay transmission of packets than asking 2134 * harm done since we won't be receiving any PAUSE frames
2845 * our link partner to pause transmission of frames. 2135 * anyway. If the intent on the link partner was to have
2846 */ 2136 * flow control enabled, then by us enabling RX only, we
2847 else if ((hw->original_fc == E1000_FC_NONE || 2137 * can at least receive pause frames and process them.
2848 hw->original_fc == E1000_FC_TX_PAUSE) || 2138 * This is a good idea because in most cases, since we are
2849 hw->fc_strict_ieee) { 2139 * predominantly a server NIC, more times than not we will
2850 hw->fc = E1000_FC_NONE; 2140 * be asked to delay transmission of packets than asking
2851 DEBUGOUT("Flow Control = NONE.\n"); 2141 * our link partner to pause transmission of frames.
2852 } else { 2142 */
2853 hw->fc = E1000_FC_RX_PAUSE; 2143 else if ((hw->original_fc == E1000_FC_NONE ||
2854 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2144 hw->original_fc == E1000_FC_TX_PAUSE) ||
2855 } 2145 hw->fc_strict_ieee) {
2856 2146 hw->fc = E1000_FC_NONE;
2857 /* Now we need to do one last check... If we auto- 2147 DEBUGOUT("Flow Control = NONE.\n");
2858 * negotiated to HALF DUPLEX, flow control should not be 2148 } else {
2859 * enabled per IEEE 802.3 spec. 2149 hw->fc = E1000_FC_RX_PAUSE;
2860 */ 2150 DEBUGOUT
2861 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2151 ("Flow Control = RX PAUSE frames only.\n");
2862 if (ret_val) { 2152 }
2863 DEBUGOUT("Error getting link speed and duplex\n"); 2153
2864 return ret_val; 2154 /* Now we need to do one last check... If we auto-
2865 } 2155 * negotiated to HALF DUPLEX, flow control should not be
2866 2156 * enabled per IEEE 802.3 spec.
2867 if (duplex == HALF_DUPLEX) 2157 */
2868 hw->fc = E1000_FC_NONE; 2158 ret_val =
2869 2159 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2870 /* Now we call a subroutine to actually force the MAC 2160 if (ret_val) {
2871 * controller to use the correct flow control settings. 2161 DEBUGOUT
2872 */ 2162 ("Error getting link speed and duplex\n");
2873 ret_val = e1000_force_mac_fc(hw); 2163 return ret_val;
2874 if (ret_val) { 2164 }
2875 DEBUGOUT("Error forcing flow control settings\n"); 2165
2876 return ret_val; 2166 if (duplex == HALF_DUPLEX)
2877 } 2167 hw->fc = E1000_FC_NONE;
2878 } else { 2168
2879 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 2169 /* Now we call a subroutine to actually force the MAC
2880 } 2170 * controller to use the correct flow control settings.
2881 } 2171 */
2882 return E1000_SUCCESS; 2172 ret_val = e1000_force_mac_fc(hw);
2173 if (ret_val) {
2174 DEBUGOUT
2175 ("Error forcing flow control settings\n");
2176 return ret_val;
2177 }
2178 } else {
2179 DEBUGOUT
2180 ("Copper PHY and Auto Neg has not completed.\n");
2181 }
2182 }
2183 return E1000_SUCCESS;
2883} 2184}
2884 2185
2885/****************************************************************************** 2186/**
2886 * Checks to see if the link status of the hardware has changed. 2187 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2188 * @hw: pointer to the HW structure
2887 * 2189 *
2888 * hw - Struct containing variables accessed by shared code 2190 * Checks for link up on the hardware. If link is not up and we have
2191 * a signal, then we need to force link up.
2192 */
2193static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2194{
2195 u32 rxcw;
2196 u32 ctrl;
2197 u32 status;
2198 s32 ret_val = E1000_SUCCESS;
2199
2200 DEBUGFUNC("e1000_check_for_serdes_link_generic");
2201
2202 ctrl = er32(CTRL);
2203 status = er32(STATUS);
2204 rxcw = er32(RXCW);
2205
2206 /*
2207 * If we don't have link (auto-negotiation failed or link partner
2208 * cannot auto-negotiate), and our link partner is not trying to
2209 * auto-negotiate with us (we are receiving idles or data),
2210 * we need to force link up. We also need to give auto-negotiation
2211 * time to complete.
2212 */
2213 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2214 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2215 if (hw->autoneg_failed == 0) {
2216 hw->autoneg_failed = 1;
2217 goto out;
2218 }
2219 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2220
2221 /* Disable auto-negotiation in the TXCW register */
2222 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2223
2224 /* Force link-up and also force full-duplex. */
2225 ctrl = er32(CTRL);
2226 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2227 ew32(CTRL, ctrl);
2228
2229 /* Configure Flow Control after forcing link up. */
2230 ret_val = e1000_config_fc_after_link_up(hw);
2231 if (ret_val) {
2232 DEBUGOUT("Error configuring flow control\n");
2233 goto out;
2234 }
2235 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2236 /*
2237 * If we are forcing link and we are receiving /C/ ordered
2238 * sets, re-enable auto-negotiation in the TXCW register
2239 * and disable forced link in the Device Control register
2240 * in an attempt to auto-negotiate with our link partner.
2241 */
2242 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2243 ew32(TXCW, hw->txcw);
2244 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2245
2246 hw->serdes_has_link = true;
2247 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2248 /*
2249 * If we force link for non-auto-negotiation switch, check
2250 * link status based on MAC synchronization for internal
2251 * serdes media type.
2252 */
2253 /* SYNCH bit and IV bit are sticky. */
2254 udelay(10);
2255 rxcw = er32(RXCW);
2256 if (rxcw & E1000_RXCW_SYNCH) {
2257 if (!(rxcw & E1000_RXCW_IV)) {
2258 hw->serdes_has_link = true;
2259 DEBUGOUT("SERDES: Link up - forced.\n");
2260 }
2261 } else {
2262 hw->serdes_has_link = false;
2263 DEBUGOUT("SERDES: Link down - force failed.\n");
2264 }
2265 }
2266
2267 if (E1000_TXCW_ANE & er32(TXCW)) {
2268 status = er32(STATUS);
2269 if (status & E1000_STATUS_LU) {
2270 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2271 udelay(10);
2272 rxcw = er32(RXCW);
2273 if (rxcw & E1000_RXCW_SYNCH) {
2274 if (!(rxcw & E1000_RXCW_IV)) {
2275 hw->serdes_has_link = true;
2276 DEBUGOUT("SERDES: Link up - autoneg "
2277 "completed successfully.\n");
2278 } else {
2279 hw->serdes_has_link = false;
2280 DEBUGOUT("SERDES: Link down - invalid"
2281 "codewords detected in autoneg.\n");
2282 }
2283 } else {
2284 hw->serdes_has_link = false;
2285 DEBUGOUT("SERDES: Link down - no sync.\n");
2286 }
2287 } else {
2288 hw->serdes_has_link = false;
2289 DEBUGOUT("SERDES: Link down - autoneg failed\n");
2290 }
2291 }
2292
2293 out:
2294 return ret_val;
2295}
2296
2297/**
2298 * e1000_check_for_link
2299 * @hw: Struct containing variables accessed by shared code
2889 * 2300 *
2301 * Checks to see if the link status of the hardware has changed.
2890 * Called by any function that needs to check the link status of the adapter. 2302 * Called by any function that needs to check the link status of the adapter.
2891 *****************************************************************************/ 2303 */
2892s32 e1000_check_for_link(struct e1000_hw *hw) 2304s32 e1000_check_for_link(struct e1000_hw *hw)
2893{ 2305{
2894 u32 rxcw = 0; 2306 u32 rxcw = 0;
2895 u32 ctrl; 2307 u32 ctrl;
2896 u32 status; 2308 u32 status;
2897 u32 rctl; 2309 u32 rctl;
2898 u32 icr; 2310 u32 icr;
2899 u32 signal = 0; 2311 u32 signal = 0;
2900 s32 ret_val; 2312 s32 ret_val;
2901 u16 phy_data; 2313 u16 phy_data;
2902 2314
2903 DEBUGFUNC("e1000_check_for_link"); 2315 DEBUGFUNC("e1000_check_for_link");
2904 2316
2905 ctrl = er32(CTRL); 2317 ctrl = er32(CTRL);
2906 status = er32(STATUS); 2318 status = er32(STATUS);
2907 2319
2908 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 2320 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2909 * set when the optics detect a signal. On older adapters, it will be 2321 * set when the optics detect a signal. On older adapters, it will be
2910 * cleared when there is a signal. This applies to fiber media only. 2322 * cleared when there is a signal. This applies to fiber media only.
2911 */ 2323 */
2912 if ((hw->media_type == e1000_media_type_fiber) || 2324 if ((hw->media_type == e1000_media_type_fiber) ||
2913 (hw->media_type == e1000_media_type_internal_serdes)) { 2325 (hw->media_type == e1000_media_type_internal_serdes)) {
2914 rxcw = er32(RXCW); 2326 rxcw = er32(RXCW);
2915 2327
2916 if (hw->media_type == e1000_media_type_fiber) { 2328 if (hw->media_type == e1000_media_type_fiber) {
2917 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2329 signal =
2918 if (status & E1000_STATUS_LU) 2330 (hw->mac_type >
2919 hw->get_link_status = false; 2331 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2920 } 2332 if (status & E1000_STATUS_LU)
2921 } 2333 hw->get_link_status = false;
2922 2334 }
2923 /* If we have a copper PHY then we only want to go out to the PHY 2335 }
2924 * registers to see if Auto-Neg has completed and/or if our link 2336
2925 * status has changed. The get_link_status flag will be set if we 2337 /* If we have a copper PHY then we only want to go out to the PHY
2926 * receive a Link Status Change interrupt or we have Rx Sequence 2338 * registers to see if Auto-Neg has completed and/or if our link
2927 * Errors. 2339 * status has changed. The get_link_status flag will be set if we
2928 */ 2340 * receive a Link Status Change interrupt or we have Rx Sequence
2929 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2341 * Errors.
2930 /* First we want to see if the MII Status Register reports 2342 */
2931 * link. If so, then we want to get the current speed/duplex 2343 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2932 * of the PHY. 2344 /* First we want to see if the MII Status Register reports
2933 * Read the register twice since the link bit is sticky. 2345 * link. If so, then we want to get the current speed/duplex
2934 */ 2346 * of the PHY.
2935 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2347 * Read the register twice since the link bit is sticky.
2936 if (ret_val) 2348 */
2937 return ret_val; 2349 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2938 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2350 if (ret_val)
2939 if (ret_val) 2351 return ret_val;
2940 return ret_val; 2352 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2941 2353 if (ret_val)
2942 if (phy_data & MII_SR_LINK_STATUS) { 2354 return ret_val;
2943 hw->get_link_status = false; 2355
2944 /* Check if there was DownShift, must be checked immediately after 2356 if (phy_data & MII_SR_LINK_STATUS) {
2945 * link-up */ 2357 hw->get_link_status = false;
2946 e1000_check_downshift(hw); 2358 /* Check if there was DownShift, must be checked immediately after
2947 2359 * link-up */
2948 /* If we are on 82544 or 82543 silicon and speed/duplex 2360 e1000_check_downshift(hw);
2949 * are forced to 10H or 10F, then we will implement the polarity 2361
2950 * reversal workaround. We disable interrupts first, and upon 2362 /* If we are on 82544 or 82543 silicon and speed/duplex
2951 * returning, place the devices interrupt state to its previous 2363 * are forced to 10H or 10F, then we will implement the polarity
2952 * value except for the link status change interrupt which will 2364 * reversal workaround. We disable interrupts first, and upon
2953 * happen due to the execution of this workaround. 2365 * returning, place the devices interrupt state to its previous
2954 */ 2366 * value except for the link status change interrupt which will
2955 2367 * happen due to the execution of this workaround.
2956 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2368 */
2957 (!hw->autoneg) && 2369
2958 (hw->forced_speed_duplex == e1000_10_full || 2370 if ((hw->mac_type == e1000_82544
2959 hw->forced_speed_duplex == e1000_10_half)) { 2371 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2960 ew32(IMC, 0xffffffff); 2372 && (hw->forced_speed_duplex == e1000_10_full
2961 ret_val = e1000_polarity_reversal_workaround(hw); 2373 || hw->forced_speed_duplex == e1000_10_half)) {
2962 icr = er32(ICR); 2374 ew32(IMC, 0xffffffff);
2963 ew32(ICS, (icr & ~E1000_ICS_LSC)); 2375 ret_val =
2964 ew32(IMS, IMS_ENABLE_MASK); 2376 e1000_polarity_reversal_workaround(hw);
2965 } 2377 icr = er32(ICR);
2966 2378 ew32(ICS, (icr & ~E1000_ICS_LSC));
2967 } else { 2379 ew32(IMS, IMS_ENABLE_MASK);
2968 /* No link detected */ 2380 }
2969 e1000_config_dsp_after_link_change(hw, false); 2381
2970 return 0; 2382 } else {
2971 } 2383 /* No link detected */
2972 2384 e1000_config_dsp_after_link_change(hw, false);
2973 /* If we are forcing speed/duplex, then we simply return since 2385 return 0;
2974 * we have already determined whether we have link or not. 2386 }
2975 */ 2387
2976 if (!hw->autoneg) return -E1000_ERR_CONFIG; 2388 /* If we are forcing speed/duplex, then we simply return since
2977 2389 * we have already determined whether we have link or not.
2978 /* optimize the dsp settings for the igp phy */ 2390 */
2979 e1000_config_dsp_after_link_change(hw, true); 2391 if (!hw->autoneg)
2980 2392 return -E1000_ERR_CONFIG;
2981 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2393
2982 * have Si on board that is 82544 or newer, Auto 2394 /* optimize the dsp settings for the igp phy */
2983 * Speed Detection takes care of MAC speed/duplex 2395 e1000_config_dsp_after_link_change(hw, true);
2984 * configuration. So we only need to configure Collision 2396
2985 * Distance in the MAC. Otherwise, we need to force 2397 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2986 * speed/duplex on the MAC to the current PHY speed/duplex 2398 * have Si on board that is 82544 or newer, Auto
2987 * settings. 2399 * Speed Detection takes care of MAC speed/duplex
2988 */ 2400 * configuration. So we only need to configure Collision
2989 if (hw->mac_type >= e1000_82544) 2401 * Distance in the MAC. Otherwise, we need to force
2990 e1000_config_collision_dist(hw); 2402 * speed/duplex on the MAC to the current PHY speed/duplex
2991 else { 2403 * settings.
2992 ret_val = e1000_config_mac_to_phy(hw); 2404 */
2993 if (ret_val) { 2405 if (hw->mac_type >= e1000_82544)
2994 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2406 e1000_config_collision_dist(hw);
2995 return ret_val; 2407 else {
2996 } 2408 ret_val = e1000_config_mac_to_phy(hw);
2997 } 2409 if (ret_val) {
2998 2410 DEBUGOUT
2999 /* Configure Flow Control now that Auto-Neg has completed. First, we 2411 ("Error configuring MAC to PHY settings\n");
3000 * need to restore the desired flow control settings because we may 2412 return ret_val;
3001 * have had to re-autoneg with a different link partner. 2413 }
3002 */ 2414 }
3003 ret_val = e1000_config_fc_after_link_up(hw); 2415
3004 if (ret_val) { 2416 /* Configure Flow Control now that Auto-Neg has completed. First, we
3005 DEBUGOUT("Error configuring flow control\n"); 2417 * need to restore the desired flow control settings because we may
3006 return ret_val; 2418 * have had to re-autoneg with a different link partner.
3007 } 2419 */
3008 2420 ret_val = e1000_config_fc_after_link_up(hw);
3009 /* At this point we know that we are on copper and we have 2421 if (ret_val) {
3010 * auto-negotiated link. These are conditions for checking the link 2422 DEBUGOUT("Error configuring flow control\n");
3011 * partner capability register. We use the link speed to determine if 2423 return ret_val;
3012 * TBI compatibility needs to be turned on or off. If the link is not 2424 }
3013 * at gigabit speed, then TBI compatibility is not needed. If we are 2425
3014 * at gigabit speed, we turn on TBI compatibility. 2426 /* At this point we know that we are on copper and we have
3015 */ 2427 * auto-negotiated link. These are conditions for checking the link
3016 if (hw->tbi_compatibility_en) { 2428 * partner capability register. We use the link speed to determine if
3017 u16 speed, duplex; 2429 * TBI compatibility needs to be turned on or off. If the link is not
3018 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2430 * at gigabit speed, then TBI compatibility is not needed. If we are
3019 if (ret_val) { 2431 * at gigabit speed, we turn on TBI compatibility.
3020 DEBUGOUT("Error getting link speed and duplex\n"); 2432 */
3021 return ret_val; 2433 if (hw->tbi_compatibility_en) {
3022 } 2434 u16 speed, duplex;
3023 if (speed != SPEED_1000) { 2435 ret_val =
3024 /* If link speed is not set to gigabit speed, we do not need 2436 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3025 * to enable TBI compatibility. 2437 if (ret_val) {
3026 */ 2438 DEBUGOUT
3027 if (hw->tbi_compatibility_on) { 2439 ("Error getting link speed and duplex\n");
3028 /* If we previously were in the mode, turn it off. */ 2440 return ret_val;
3029 rctl = er32(RCTL); 2441 }
3030 rctl &= ~E1000_RCTL_SBP; 2442 if (speed != SPEED_1000) {
3031 ew32(RCTL, rctl); 2443 /* If link speed is not set to gigabit speed, we do not need
3032 hw->tbi_compatibility_on = false; 2444 * to enable TBI compatibility.
3033 } 2445 */
3034 } else { 2446 if (hw->tbi_compatibility_on) {
3035 /* If TBI compatibility is was previously off, turn it on. For 2447 /* If we previously were in the mode, turn it off. */
3036 * compatibility with a TBI link partner, we will store bad 2448 rctl = er32(RCTL);
3037 * packets. Some frames have an additional byte on the end and 2449 rctl &= ~E1000_RCTL_SBP;
3038 * will look like CRC errors to the hardware. 2450 ew32(RCTL, rctl);
3039 */ 2451 hw->tbi_compatibility_on = false;
3040 if (!hw->tbi_compatibility_on) { 2452 }
3041 hw->tbi_compatibility_on = true; 2453 } else {
3042 rctl = er32(RCTL); 2454 /* If TBI compatibility is was previously off, turn it on. For
3043 rctl |= E1000_RCTL_SBP; 2455 * compatibility with a TBI link partner, we will store bad
3044 ew32(RCTL, rctl); 2456 * packets. Some frames have an additional byte on the end and
3045 } 2457 * will look like CRC errors to to the hardware.
3046 } 2458 */
3047 } 2459 if (!hw->tbi_compatibility_on) {
3048 } 2460 hw->tbi_compatibility_on = true;
3049 /* If we don't have link (auto-negotiation failed or link partner cannot 2461 rctl = er32(RCTL);
3050 * auto-negotiate), the cable is plugged in (we have signal), and our 2462 rctl |= E1000_RCTL_SBP;
3051 * link partner is not trying to auto-negotiate with us (we are receiving 2463 ew32(RCTL, rctl);
3052 * idles or data), we need to force link up. We also need to give 2464 }
3053 * auto-negotiation time to complete, in case the cable was just plugged 2465 }
3054 * in. The autoneg_failed flag does this. 2466 }
3055 */ 2467 }
3056 else if ((((hw->media_type == e1000_media_type_fiber) && 2468
3057 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 2469 if ((hw->media_type == e1000_media_type_fiber) ||
3058 (hw->media_type == e1000_media_type_internal_serdes)) && 2470 (hw->media_type == e1000_media_type_internal_serdes))
3059 (!(status & E1000_STATUS_LU)) && 2471 e1000_check_for_serdes_link_generic(hw);
3060 (!(rxcw & E1000_RXCW_C))) { 2472
3061 if (hw->autoneg_failed == 0) { 2473 return E1000_SUCCESS;
3062 hw->autoneg_failed = 1;
3063 return 0;
3064 }
3065 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3066
3067 /* Disable auto-negotiation in the TXCW register */
3068 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3069
3070 /* Force link-up and also force full-duplex. */
3071 ctrl = er32(CTRL);
3072 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3073 ew32(CTRL, ctrl);
3074
3075 /* Configure Flow Control after forcing link up. */
3076 ret_val = e1000_config_fc_after_link_up(hw);
3077 if (ret_val) {
3078 DEBUGOUT("Error configuring flow control\n");
3079 return ret_val;
3080 }
3081 }
3082 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3083 * auto-negotiation in the TXCW register and disable forced link in the
3084 * Device Control register in an attempt to auto-negotiate with our link
3085 * partner.
3086 */
3087 else if (((hw->media_type == e1000_media_type_fiber) ||
3088 (hw->media_type == e1000_media_type_internal_serdes)) &&
3089 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3090 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3091 ew32(TXCW, hw->txcw);
3092 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
3093
3094 hw->serdes_link_down = false;
3095 }
3096 /* If we force link for non-auto-negotiation switch, check link status
3097 * based on MAC synchronization for internal serdes media type.
3098 */
3099 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3100 !(E1000_TXCW_ANE & er32(TXCW))) {
3101 /* SYNCH bit and IV bit are sticky. */
3102 udelay(10);
3103 if (E1000_RXCW_SYNCH & er32(RXCW)) {
3104 if (!(rxcw & E1000_RXCW_IV)) {
3105 hw->serdes_link_down = false;
3106 DEBUGOUT("SERDES: Link is up.\n");
3107 }
3108 } else {
3109 hw->serdes_link_down = true;
3110 DEBUGOUT("SERDES: Link is down.\n");
3111 }
3112 }
3113 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3114 (E1000_TXCW_ANE & er32(TXCW))) {
3115 hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
3116 }
3117 return E1000_SUCCESS;
3118} 2474}
3119 2475
3120/****************************************************************************** 2476/**
2477 * e1000_get_speed_and_duplex
2478 * @hw: Struct containing variables accessed by shared code
2479 * @speed: Speed of the connection
2480 * @duplex: Duplex setting of the connection
2481
3121 * Detects the current speed and duplex settings of the hardware. 2482 * Detects the current speed and duplex settings of the hardware.
3122 * 2483 */
3123 * hw - Struct containing variables accessed by shared code
3124 * speed - Speed of the connection
3125 * duplex - Duplex setting of the connection
3126 *****************************************************************************/
3127s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2484s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
3128{ 2485{
3129 u32 status; 2486 u32 status;
3130 s32 ret_val; 2487 s32 ret_val;
3131 u16 phy_data; 2488 u16 phy_data;
3132 2489
3133 DEBUGFUNC("e1000_get_speed_and_duplex"); 2490 DEBUGFUNC("e1000_get_speed_and_duplex");
3134 2491
3135 if (hw->mac_type >= e1000_82543) { 2492 if (hw->mac_type >= e1000_82543) {
3136 status = er32(STATUS); 2493 status = er32(STATUS);
3137 if (status & E1000_STATUS_SPEED_1000) { 2494 if (status & E1000_STATUS_SPEED_1000) {
3138 *speed = SPEED_1000; 2495 *speed = SPEED_1000;
3139 DEBUGOUT("1000 Mbs, "); 2496 DEBUGOUT("1000 Mbs, ");
3140 } else if (status & E1000_STATUS_SPEED_100) { 2497 } else if (status & E1000_STATUS_SPEED_100) {
3141 *speed = SPEED_100; 2498 *speed = SPEED_100;
3142 DEBUGOUT("100 Mbs, "); 2499 DEBUGOUT("100 Mbs, ");
3143 } else { 2500 } else {
3144 *speed = SPEED_10; 2501 *speed = SPEED_10;
3145 DEBUGOUT("10 Mbs, "); 2502 DEBUGOUT("10 Mbs, ");
3146 } 2503 }
3147 2504
3148 if (status & E1000_STATUS_FD) { 2505 if (status & E1000_STATUS_FD) {
3149 *duplex = FULL_DUPLEX; 2506 *duplex = FULL_DUPLEX;
3150 DEBUGOUT("Full Duplex\n"); 2507 DEBUGOUT("Full Duplex\n");
3151 } else { 2508 } else {
3152 *duplex = HALF_DUPLEX; 2509 *duplex = HALF_DUPLEX;
3153 DEBUGOUT(" Half Duplex\n"); 2510 DEBUGOUT(" Half Duplex\n");
3154 } 2511 }
3155 } else { 2512 } else {
3156 DEBUGOUT("1000 Mbs, Full Duplex\n"); 2513 DEBUGOUT("1000 Mbs, Full Duplex\n");
3157 *speed = SPEED_1000; 2514 *speed = SPEED_1000;
3158 *duplex = FULL_DUPLEX; 2515 *duplex = FULL_DUPLEX;
3159 } 2516 }
3160 2517
3161 /* IGP01 PHY may advertise full duplex operation after speed downgrade even 2518 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3162 * if it is operating at half duplex. Here we set the duplex settings to 2519 * if it is operating at half duplex. Here we set the duplex settings to
3163 * match the duplex in the link partner's capabilities. 2520 * match the duplex in the link partner's capabilities.
3164 */ 2521 */
3165 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 2522 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3166 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 2523 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3167 if (ret_val) 2524 if (ret_val)
3168 return ret_val; 2525 return ret_val;
3169 2526
3170 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 2527 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3171 *duplex = HALF_DUPLEX; 2528 *duplex = HALF_DUPLEX;
3172 else { 2529 else {
3173 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 2530 ret_val =
3174 if (ret_val) 2531 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3175 return ret_val; 2532 if (ret_val)
3176 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 2533 return ret_val;
3177 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 2534 if ((*speed == SPEED_100
3178 *duplex = HALF_DUPLEX; 2535 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3179 } 2536 || (*speed == SPEED_10
3180 } 2537 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3181 2538 *duplex = HALF_DUPLEX;
3182 if ((hw->mac_type == e1000_80003es2lan) && 2539 }
3183 (hw->media_type == e1000_media_type_copper)) { 2540 }
3184 if (*speed == SPEED_1000) 2541
3185 ret_val = e1000_configure_kmrn_for_1000(hw); 2542 return E1000_SUCCESS;
3186 else
3187 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3188 if (ret_val)
3189 return ret_val;
3190 }
3191
3192 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3193 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3194 if (ret_val)
3195 return ret_val;
3196 }
3197
3198 return E1000_SUCCESS;
3199} 2543}
3200 2544
3201/****************************************************************************** 2545/**
3202* Blocks until autoneg completes or times out (~4.5 seconds) 2546 * e1000_wait_autoneg
3203* 2547 * @hw: Struct containing variables accessed by shared code
3204* hw - Struct containing variables accessed by shared code 2548 *
3205******************************************************************************/ 2549 * Blocks until autoneg completes or times out (~4.5 seconds)
2550 */
3206static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2551static s32 e1000_wait_autoneg(struct e1000_hw *hw)
3207{ 2552{
3208 s32 ret_val; 2553 s32 ret_val;
3209 u16 i; 2554 u16 i;
3210 u16 phy_data; 2555 u16 phy_data;
3211 2556
3212 DEBUGFUNC("e1000_wait_autoneg"); 2557 DEBUGFUNC("e1000_wait_autoneg");
3213 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2558 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3214 2559
3215 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2560 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3216 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2561 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3217 /* Read the MII Status Register and wait for Auto-Neg 2562 /* Read the MII Status Register and wait for Auto-Neg
3218 * Complete bit to be set. 2563 * Complete bit to be set.
3219 */ 2564 */
3220 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2565 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3221 if (ret_val) 2566 if (ret_val)
3222 return ret_val; 2567 return ret_val;
3223 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2568 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3224 if (ret_val) 2569 if (ret_val)
3225 return ret_val; 2570 return ret_val;
3226 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2571 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3227 return E1000_SUCCESS; 2572 return E1000_SUCCESS;
3228 } 2573 }
3229 msleep(100); 2574 msleep(100);
3230 } 2575 }
3231 return E1000_SUCCESS; 2576 return E1000_SUCCESS;
3232} 2577}
3233 2578
3234/****************************************************************************** 2579/**
3235* Raises the Management Data Clock 2580 * e1000_raise_mdi_clk - Raises the Management Data Clock
3236* 2581 * @hw: Struct containing variables accessed by shared code
3237* hw - Struct containing variables accessed by shared code 2582 * @ctrl: Device control register's current value
3238* ctrl - Device control register's current value 2583 */
3239******************************************************************************/
3240static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2584static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3241{ 2585{
3242 /* Raise the clock input to the Management Data Clock (by setting the MDC 2586 /* Raise the clock input to the Management Data Clock (by setting the MDC
3243 * bit), and then delay 10 microseconds. 2587 * bit), and then delay 10 microseconds.
3244 */ 2588 */
3245 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); 2589 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
3246 E1000_WRITE_FLUSH(); 2590 E1000_WRITE_FLUSH();
3247 udelay(10); 2591 udelay(10);
3248} 2592}
3249 2593
3250/****************************************************************************** 2594/**
3251* Lowers the Management Data Clock 2595 * e1000_lower_mdi_clk - Lowers the Management Data Clock
3252* 2596 * @hw: Struct containing variables accessed by shared code
3253* hw - Struct containing variables accessed by shared code 2597 * @ctrl: Device control register's current value
3254* ctrl - Device control register's current value 2598 */
3255******************************************************************************/
3256static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2599static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3257{ 2600{
3258 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2601 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3259 * bit), and then delay 10 microseconds. 2602 * bit), and then delay 10 microseconds.
3260 */ 2603 */
3261 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2604 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
3262 E1000_WRITE_FLUSH(); 2605 E1000_WRITE_FLUSH();
3263 udelay(10); 2606 udelay(10);
3264} 2607}
3265 2608
3266/****************************************************************************** 2609/**
3267* Shifts data bits out to the PHY 2610 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
3268* 2611 * @hw: Struct containing variables accessed by shared code
3269* hw - Struct containing variables accessed by shared code 2612 * @data: Data to send out to the PHY
3270* data - Data to send out to the PHY 2613 * @count: Number of bits to shift out
3271* count - Number of bits to shift out 2614 *
3272* 2615 * Bits are shifted out in MSB to LSB order.
3273* Bits are shifted out in MSB to LSB order. 2616 */
3274******************************************************************************/
3275static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) 2617static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
3276{ 2618{
3277 u32 ctrl; 2619 u32 ctrl;
3278 u32 mask; 2620 u32 mask;
3279
3280 /* We need to shift "count" number of bits out to the PHY. So, the value
3281 * in the "data" parameter will be shifted out to the PHY one bit at a
3282 * time. In order to do this, "data" must be broken down into bits.
3283 */
3284 mask = 0x01;
3285 mask <<= (count - 1);
3286
3287 ctrl = er32(CTRL);
3288
3289 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3290 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3291
3292 while (mask) {
3293 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3294 * then raising and lowering the Management Data Clock. A "0" is
3295 * shifted out to the PHY by setting the MDIO bit to "0" and then
3296 * raising and lowering the clock.
3297 */
3298 if (data & mask)
3299 ctrl |= E1000_CTRL_MDIO;
3300 else
3301 ctrl &= ~E1000_CTRL_MDIO;
3302
3303 ew32(CTRL, ctrl);
3304 E1000_WRITE_FLUSH();
3305
3306 udelay(10);
3307
3308 e1000_raise_mdi_clk(hw, &ctrl);
3309 e1000_lower_mdi_clk(hw, &ctrl);
3310
3311 mask = mask >> 1;
3312 }
3313}
3314
3315/******************************************************************************
3316* Shifts data bits in from the PHY
3317*
3318* hw - Struct containing variables accessed by shared code
3319*
3320* Bits are shifted in in MSB to LSB order.
3321******************************************************************************/
3322static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3323{
3324 u32 ctrl;
3325 u16 data = 0;
3326 u8 i;
3327
3328 /* In order to read a register from the PHY, we need to shift in a total
3329 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3330 * to avoid contention on the MDIO pin when a read operation is performed.
3331 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3332 * by raising the input to the Management Data Clock (setting the MDC bit),
3333 * and then reading the value of the MDIO bit.
3334 */
3335 ctrl = er32(CTRL);
3336
3337 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3338 ctrl &= ~E1000_CTRL_MDIO_DIR;
3339 ctrl &= ~E1000_CTRL_MDIO;
3340
3341 ew32(CTRL, ctrl);
3342 E1000_WRITE_FLUSH();
3343
3344 /* Raise and Lower the clock before reading in the data. This accounts for
3345 * the turnaround bits. The first clock occurred when we clocked out the
3346 * last bit of the Register Address.
3347 */
3348 e1000_raise_mdi_clk(hw, &ctrl);
3349 e1000_lower_mdi_clk(hw, &ctrl);
3350
3351 for (data = 0, i = 0; i < 16; i++) {
3352 data = data << 1;
3353 e1000_raise_mdi_clk(hw, &ctrl);
3354 ctrl = er32(CTRL);
3355 /* Check to see if we shifted in a "1". */
3356 if (ctrl & E1000_CTRL_MDIO)
3357 data |= 1;
3358 e1000_lower_mdi_clk(hw, &ctrl);
3359 }
3360
3361 e1000_raise_mdi_clk(hw, &ctrl);
3362 e1000_lower_mdi_clk(hw, &ctrl);
3363
3364 return data;
3365}
3366
3367static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3368{
3369 u32 swfw_sync = 0;
3370 u32 swmask = mask;
3371 u32 fwmask = mask << 16;
3372 s32 timeout = 200;
3373 2621
3374 DEBUGFUNC("e1000_swfw_sync_acquire"); 2622 /* We need to shift "count" number of bits out to the PHY. So, the value
3375 2623 * in the "data" parameter will be shifted out to the PHY one bit at a
3376 if (hw->swfwhw_semaphore_present) 2624 * time. In order to do this, "data" must be broken down into bits.
3377 return e1000_get_software_flag(hw); 2625 */
2626 mask = 0x01;
2627 mask <<= (count - 1);
3378 2628
3379 if (!hw->swfw_sync_present) 2629 ctrl = er32(CTRL);
3380 return e1000_get_hw_eeprom_semaphore(hw);
3381 2630
3382 while (timeout) { 2631 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3383 if (e1000_get_hw_eeprom_semaphore(hw)) 2632 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3384 return -E1000_ERR_SWFW_SYNC;
3385 2633
3386 swfw_sync = er32(SW_FW_SYNC); 2634 while (mask) {
3387 if (!(swfw_sync & (fwmask | swmask))) { 2635 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3388 break; 2636 * then raising and lowering the Management Data Clock. A "0" is
3389 } 2637 * shifted out to the PHY by setting the MDIO bit to "0" and then
2638 * raising and lowering the clock.
2639 */
2640 if (data & mask)
2641 ctrl |= E1000_CTRL_MDIO;
2642 else
2643 ctrl &= ~E1000_CTRL_MDIO;
3390 2644
3391 /* firmware currently using resource (fwmask) */ 2645 ew32(CTRL, ctrl);
3392 /* or other software thread currently using resource (swmask) */ 2646 E1000_WRITE_FLUSH();
3393 e1000_put_hw_eeprom_semaphore(hw);
3394 mdelay(5);
3395 timeout--;
3396 }
3397 2647
3398 if (!timeout) { 2648 udelay(10);
3399 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3400 return -E1000_ERR_SWFW_SYNC;
3401 }
3402 2649
3403 swfw_sync |= swmask; 2650 e1000_raise_mdi_clk(hw, &ctrl);
3404 ew32(SW_FW_SYNC, swfw_sync); 2651 e1000_lower_mdi_clk(hw, &ctrl);
3405 2652
3406 e1000_put_hw_eeprom_semaphore(hw); 2653 mask = mask >> 1;
3407 return E1000_SUCCESS; 2654 }
3408} 2655}
3409 2656
3410static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask) 2657/**
2658 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2659 * @hw: Struct containing variables accessed by shared code
2660 *
2661 * Bits are shifted in in MSB to LSB order.
2662 */
2663static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3411{ 2664{
3412 u32 swfw_sync; 2665 u32 ctrl;
3413 u32 swmask = mask; 2666 u16 data = 0;
2667 u8 i;
3414 2668
3415 DEBUGFUNC("e1000_swfw_sync_release"); 2669 /* In order to read a register from the PHY, we need to shift in a total
2670 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2671 * to avoid contention on the MDIO pin when a read operation is performed.
2672 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2673 * by raising the input to the Management Data Clock (setting the MDC bit),
2674 * and then reading the value of the MDIO bit.
2675 */
2676 ctrl = er32(CTRL);
3416 2677
3417 if (hw->swfwhw_semaphore_present) { 2678 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3418 e1000_release_software_flag(hw); 2679 ctrl &= ~E1000_CTRL_MDIO_DIR;
3419 return; 2680 ctrl &= ~E1000_CTRL_MDIO;
3420 }
3421 2681
3422 if (!hw->swfw_sync_present) { 2682 ew32(CTRL, ctrl);
3423 e1000_put_hw_eeprom_semaphore(hw); 2683 E1000_WRITE_FLUSH();
3424 return;
3425 }
3426 2684
3427 /* if (e1000_get_hw_eeprom_semaphore(hw)) 2685 /* Raise and Lower the clock before reading in the data. This accounts for
3428 * return -E1000_ERR_SWFW_SYNC; */ 2686 * the turnaround bits. The first clock occurred when we clocked out the
3429 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 2687 * last bit of the Register Address.
3430 /* empty */ 2688 */
2689 e1000_raise_mdi_clk(hw, &ctrl);
2690 e1000_lower_mdi_clk(hw, &ctrl);
2691
2692 for (data = 0, i = 0; i < 16; i++) {
2693 data = data << 1;
2694 e1000_raise_mdi_clk(hw, &ctrl);
2695 ctrl = er32(CTRL);
2696 /* Check to see if we shifted in a "1". */
2697 if (ctrl & E1000_CTRL_MDIO)
2698 data |= 1;
2699 e1000_lower_mdi_clk(hw, &ctrl);
2700 }
3431 2701
3432 swfw_sync = er32(SW_FW_SYNC); 2702 e1000_raise_mdi_clk(hw, &ctrl);
3433 swfw_sync &= ~swmask; 2703 e1000_lower_mdi_clk(hw, &ctrl);
3434 ew32(SW_FW_SYNC, swfw_sync);
3435 2704
3436 e1000_put_hw_eeprom_semaphore(hw); 2705 return data;
3437} 2706}
3438 2707
3439/***************************************************************************** 2708
3440* Reads the value from a PHY register, if the value is on a specific non zero 2709/**
3441* page, sets the page first. 2710 * e1000_read_phy_reg - read a phy register
3442* hw - Struct containing variables accessed by shared code 2711 * @hw: Struct containing variables accessed by shared code
3443* reg_addr - address of the PHY register to read 2712 * @reg_addr: address of the PHY register to read
3444******************************************************************************/ 2713 *
2714 * Reads the value from a PHY register, if the value is on a specific non zero
2715 * page, sets the page first.
2716 */
3445s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) 2717s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
3446{ 2718{
3447 u32 ret_val; 2719 u32 ret_val;
3448 u16 swfw; 2720
3449 2721 DEBUGFUNC("e1000_read_phy_reg");
3450 DEBUGFUNC("e1000_read_phy_reg"); 2722
3451 2723 if ((hw->phy_type == e1000_phy_igp) &&
3452 if ((hw->mac_type == e1000_80003es2lan) && 2724 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3453 (er32(STATUS) & E1000_STATUS_FUNC_1)) { 2725 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3454 swfw = E1000_SWFW_PHY1_SM; 2726 (u16) reg_addr);
3455 } else { 2727 if (ret_val)
3456 swfw = E1000_SWFW_PHY0_SM; 2728 return ret_val;
3457 } 2729 }
3458 if (e1000_swfw_sync_acquire(hw, swfw)) 2730
3459 return -E1000_ERR_SWFW_SYNC; 2731 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3460 2732 phy_data);
3461 if ((hw->phy_type == e1000_phy_igp || 2733
3462 hw->phy_type == e1000_phy_igp_3 || 2734 return ret_val;
3463 hw->phy_type == e1000_phy_igp_2) &&
3464 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3465 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3466 (u16)reg_addr);
3467 if (ret_val) {
3468 e1000_swfw_sync_release(hw, swfw);
3469 return ret_val;
3470 }
3471 } else if (hw->phy_type == e1000_phy_gg82563) {
3472 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3473 (hw->mac_type == e1000_80003es2lan)) {
3474 /* Select Configuration Page */
3475 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3476 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3477 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3478 } else {
3479 /* Use Alternative Page Select register to access
3480 * registers 30 and 31
3481 */
3482 ret_val = e1000_write_phy_reg_ex(hw,
3483 GG82563_PHY_PAGE_SELECT_ALT,
3484 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3485 }
3486
3487 if (ret_val) {
3488 e1000_swfw_sync_release(hw, swfw);
3489 return ret_val;
3490 }
3491 }
3492 }
3493
3494 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3495 phy_data);
3496
3497 e1000_swfw_sync_release(hw, swfw);
3498 return ret_val;
3499} 2735}
3500 2736
3501static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2737static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3502 u16 *phy_data) 2738 u16 *phy_data)
3503{ 2739{
3504 u32 i; 2740 u32 i;
3505 u32 mdic = 0; 2741 u32 mdic = 0;
3506 const u32 phy_addr = 1; 2742 const u32 phy_addr = 1;
3507 2743
3508 DEBUGFUNC("e1000_read_phy_reg_ex"); 2744 DEBUGFUNC("e1000_read_phy_reg_ex");
3509 2745
3510 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2746 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3511 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2747 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3512 return -E1000_ERR_PARAM; 2748 return -E1000_ERR_PARAM;
3513 } 2749 }
3514 2750
3515 if (hw->mac_type > e1000_82543) { 2751 if (hw->mac_type > e1000_82543) {
3516 /* Set up Op-code, Phy Address, and register address in the MDI 2752 /* Set up Op-code, Phy Address, and register address in the MDI
3517 * Control register. The MAC will take care of interfacing with the 2753 * Control register. The MAC will take care of interfacing with the
3518 * PHY to retrieve the desired data. 2754 * PHY to retrieve the desired data.
3519 */ 2755 */
3520 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2756 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3521 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2757 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3522 (E1000_MDIC_OP_READ)); 2758 (E1000_MDIC_OP_READ));
3523 2759
3524 ew32(MDIC, mdic); 2760 ew32(MDIC, mdic);
3525 2761
3526 /* Poll the ready bit to see if the MDI read completed */ 2762 /* Poll the ready bit to see if the MDI read completed */
3527 for (i = 0; i < 64; i++) { 2763 for (i = 0; i < 64; i++) {
3528 udelay(50); 2764 udelay(50);
3529 mdic = er32(MDIC); 2765 mdic = er32(MDIC);
3530 if (mdic & E1000_MDIC_READY) break; 2766 if (mdic & E1000_MDIC_READY)
3531 } 2767 break;
3532 if (!(mdic & E1000_MDIC_READY)) { 2768 }
3533 DEBUGOUT("MDI Read did not complete\n"); 2769 if (!(mdic & E1000_MDIC_READY)) {
3534 return -E1000_ERR_PHY; 2770 DEBUGOUT("MDI Read did not complete\n");
3535 } 2771 return -E1000_ERR_PHY;
3536 if (mdic & E1000_MDIC_ERROR) { 2772 }
3537 DEBUGOUT("MDI Error\n"); 2773 if (mdic & E1000_MDIC_ERROR) {
3538 return -E1000_ERR_PHY; 2774 DEBUGOUT("MDI Error\n");
3539 } 2775 return -E1000_ERR_PHY;
3540 *phy_data = (u16)mdic; 2776 }
3541 } else { 2777 *phy_data = (u16) mdic;
3542 /* We must first send a preamble through the MDIO pin to signal the 2778 } else {
3543 * beginning of an MII instruction. This is done by sending 32 2779 /* We must first send a preamble through the MDIO pin to signal the
3544 * consecutive "1" bits. 2780 * beginning of an MII instruction. This is done by sending 32
3545 */ 2781 * consecutive "1" bits.
3546 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2782 */
3547 2783 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3548 /* Now combine the next few fields that are required for a read 2784
3549 * operation. We use this method instead of calling the 2785 /* Now combine the next few fields that are required for a read
3550 * e1000_shift_out_mdi_bits routine five different times. The format of 2786 * operation. We use this method instead of calling the
3551 * a MII read instruction consists of a shift out of 14 bits and is 2787 * e1000_shift_out_mdi_bits routine five different times. The format of
3552 * defined as follows: 2788 * a MII read instruction consists of a shift out of 14 bits and is
3553 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2789 * defined as follows:
3554 * followed by a shift in of 18 bits. This first two bits shifted in 2790 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3555 * are TurnAround bits used to avoid contention on the MDIO pin when a 2791 * followed by a shift in of 18 bits. This first two bits shifted in
3556 * READ operation is performed. These two bits are thrown away 2792 * are TurnAround bits used to avoid contention on the MDIO pin when a
3557 * followed by a shift in of 16 bits which contains the desired data. 2793 * READ operation is performed. These two bits are thrown away
3558 */ 2794 * followed by a shift in of 16 bits which contains the desired data.
3559 mdic = ((reg_addr) | (phy_addr << 5) | 2795 */
3560 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2796 mdic = ((reg_addr) | (phy_addr << 5) |
3561 2797 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3562 e1000_shift_out_mdi_bits(hw, mdic, 14); 2798
3563 2799 e1000_shift_out_mdi_bits(hw, mdic, 14);
3564 /* Now that we've shifted out the read command to the MII, we need to 2800
3565 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2801 /* Now that we've shifted out the read command to the MII, we need to
3566 * register address. 2802 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3567 */ 2803 * register address.
3568 *phy_data = e1000_shift_in_mdi_bits(hw); 2804 */
3569 } 2805 *phy_data = e1000_shift_in_mdi_bits(hw);
3570 return E1000_SUCCESS; 2806 }
2807 return E1000_SUCCESS;
3571} 2808}
3572 2809
3573/****************************************************************************** 2810/**
3574* Writes a value to a PHY register 2811 * e1000_write_phy_reg - write a phy register
3575* 2812 *
3576* hw - Struct containing variables accessed by shared code 2813 * @hw: Struct containing variables accessed by shared code
3577* reg_addr - address of the PHY register to write 2814 * @reg_addr: address of the PHY register to write
3578* data - data to write to the PHY 2815 * @data: data to write to the PHY
3579******************************************************************************/ 2816
2817 * Writes a value to a PHY register
2818 */
3580s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) 2819s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
3581{ 2820{
3582 u32 ret_val; 2821 u32 ret_val;
3583 u16 swfw; 2822
3584 2823 DEBUGFUNC("e1000_write_phy_reg");
3585 DEBUGFUNC("e1000_write_phy_reg"); 2824
3586 2825 if ((hw->phy_type == e1000_phy_igp) &&
3587 if ((hw->mac_type == e1000_80003es2lan) && 2826 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3588 (er32(STATUS) & E1000_STATUS_FUNC_1)) { 2827 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3589 swfw = E1000_SWFW_PHY1_SM; 2828 (u16) reg_addr);
3590 } else { 2829 if (ret_val)
3591 swfw = E1000_SWFW_PHY0_SM; 2830 return ret_val;
3592 } 2831 }
3593 if (e1000_swfw_sync_acquire(hw, swfw)) 2832
3594 return -E1000_ERR_SWFW_SYNC; 2833 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3595 2834 phy_data);
3596 if ((hw->phy_type == e1000_phy_igp || 2835
3597 hw->phy_type == e1000_phy_igp_3 || 2836 return ret_val;
3598 hw->phy_type == e1000_phy_igp_2) &&
3599 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3600 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3601 (u16)reg_addr);
3602 if (ret_val) {
3603 e1000_swfw_sync_release(hw, swfw);
3604 return ret_val;
3605 }
3606 } else if (hw->phy_type == e1000_phy_gg82563) {
3607 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3608 (hw->mac_type == e1000_80003es2lan)) {
3609 /* Select Configuration Page */
3610 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3611 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3612 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3613 } else {
3614 /* Use Alternative Page Select register to access
3615 * registers 30 and 31
3616 */
3617 ret_val = e1000_write_phy_reg_ex(hw,
3618 GG82563_PHY_PAGE_SELECT_ALT,
3619 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3620 }
3621
3622 if (ret_val) {
3623 e1000_swfw_sync_release(hw, swfw);
3624 return ret_val;
3625 }
3626 }
3627 }
3628
3629 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3630 phy_data);
3631
3632 e1000_swfw_sync_release(hw, swfw);
3633 return ret_val;
3634} 2837}
3635 2838
3636static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2839static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3637 u16 phy_data) 2840 u16 phy_data)
3638{ 2841{
3639 u32 i; 2842 u32 i;
3640 u32 mdic = 0; 2843 u32 mdic = 0;
3641 const u32 phy_addr = 1; 2844 const u32 phy_addr = 1;
3642
3643 DEBUGFUNC("e1000_write_phy_reg_ex");
3644
3645 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3646 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3647 return -E1000_ERR_PARAM;
3648 }
3649
3650 if (hw->mac_type > e1000_82543) {
3651 /* Set up Op-code, Phy Address, register address, and data intended
3652 * for the PHY register in the MDI Control register. The MAC will take
3653 * care of interfacing with the PHY to send the desired data.
3654 */
3655 mdic = (((u32)phy_data) |
3656 (reg_addr << E1000_MDIC_REG_SHIFT) |
3657 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3658 (E1000_MDIC_OP_WRITE));
3659
3660 ew32(MDIC, mdic);
3661
3662 /* Poll the ready bit to see if the MDI read completed */
3663 for (i = 0; i < 641; i++) {
3664 udelay(5);
3665 mdic = er32(MDIC);
3666 if (mdic & E1000_MDIC_READY) break;
3667 }
3668 if (!(mdic & E1000_MDIC_READY)) {
3669 DEBUGOUT("MDI Write did not complete\n");
3670 return -E1000_ERR_PHY;
3671 }
3672 } else {
3673 /* We'll need to use the SW defined pins to shift the write command
3674 * out to the PHY. We first send a preamble to the PHY to signal the
3675 * beginning of the MII instruction. This is done by sending 32
3676 * consecutive "1" bits.
3677 */
3678 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3679
3680 /* Now combine the remaining required fields that will indicate a
3681 * write operation. We use this method instead of calling the
3682 * e1000_shift_out_mdi_bits routine for each field in the command. The
3683 * format of a MII write instruction is as follows:
3684 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3685 */
3686 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3687 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3688 mdic <<= 16;
3689 mdic |= (u32)phy_data;
3690
3691 e1000_shift_out_mdi_bits(hw, mdic, 32);
3692 }
3693
3694 return E1000_SUCCESS;
3695}
3696 2845
3697static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data) 2846 DEBUGFUNC("e1000_write_phy_reg_ex");
3698{
3699 u32 reg_val;
3700 u16 swfw;
3701 DEBUGFUNC("e1000_read_kmrn_reg");
3702
3703 if ((hw->mac_type == e1000_80003es2lan) &&
3704 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3705 swfw = E1000_SWFW_PHY1_SM;
3706 } else {
3707 swfw = E1000_SWFW_PHY0_SM;
3708 }
3709 if (e1000_swfw_sync_acquire(hw, swfw))
3710 return -E1000_ERR_SWFW_SYNC;
3711
3712 /* Write register address */
3713 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3714 E1000_KUMCTRLSTA_OFFSET) |
3715 E1000_KUMCTRLSTA_REN;
3716 ew32(KUMCTRLSTA, reg_val);
3717 udelay(2);
3718
3719 /* Read the data returned */
3720 reg_val = er32(KUMCTRLSTA);
3721 *data = (u16)reg_val;
3722
3723 e1000_swfw_sync_release(hw, swfw);
3724 return E1000_SUCCESS;
3725}
3726 2847
3727static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data) 2848 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3728{ 2849 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3729 u32 reg_val; 2850 return -E1000_ERR_PARAM;
3730 u16 swfw; 2851 }
3731 DEBUGFUNC("e1000_write_kmrn_reg"); 2852
3732 2853 if (hw->mac_type > e1000_82543) {
3733 if ((hw->mac_type == e1000_80003es2lan) && 2854 /* Set up Op-code, Phy Address, register address, and data intended
3734 (er32(STATUS) & E1000_STATUS_FUNC_1)) { 2855 * for the PHY register in the MDI Control register. The MAC will take
3735 swfw = E1000_SWFW_PHY1_SM; 2856 * care of interfacing with the PHY to send the desired data.
3736 } else { 2857 */
3737 swfw = E1000_SWFW_PHY0_SM; 2858 mdic = (((u32) phy_data) |
3738 } 2859 (reg_addr << E1000_MDIC_REG_SHIFT) |
3739 if (e1000_swfw_sync_acquire(hw, swfw)) 2860 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3740 return -E1000_ERR_SWFW_SYNC; 2861 (E1000_MDIC_OP_WRITE));
3741 2862
3742 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 2863 ew32(MDIC, mdic);
3743 E1000_KUMCTRLSTA_OFFSET) | data; 2864
3744 ew32(KUMCTRLSTA, reg_val); 2865 /* Poll the ready bit to see if the MDI read completed */
3745 udelay(2); 2866 for (i = 0; i < 641; i++) {
3746 2867 udelay(5);
3747 e1000_swfw_sync_release(hw, swfw); 2868 mdic = er32(MDIC);
3748 return E1000_SUCCESS; 2869 if (mdic & E1000_MDIC_READY)
2870 break;
2871 }
2872 if (!(mdic & E1000_MDIC_READY)) {
2873 DEBUGOUT("MDI Write did not complete\n");
2874 return -E1000_ERR_PHY;
2875 }
2876 } else {
2877 /* We'll need to use the SW defined pins to shift the write command
2878 * out to the PHY. We first send a preamble to the PHY to signal the
2879 * beginning of the MII instruction. This is done by sending 32
2880 * consecutive "1" bits.
2881 */
2882 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2883
2884 /* Now combine the remaining required fields that will indicate a
2885 * write operation. We use this method instead of calling the
2886 * e1000_shift_out_mdi_bits routine for each field in the command. The
2887 * format of a MII write instruction is as follows:
2888 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2889 */
2890 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2891 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2892 mdic <<= 16;
2893 mdic |= (u32) phy_data;
2894
2895 e1000_shift_out_mdi_bits(hw, mdic, 32);
2896 }
2897
2898 return E1000_SUCCESS;
3749} 2899}
3750 2900
3751/****************************************************************************** 2901/**
3752* Returns the PHY to the power-on reset state 2902 * e1000_phy_hw_reset - reset the phy, hardware style
3753* 2903 * @hw: Struct containing variables accessed by shared code
3754* hw - Struct containing variables accessed by shared code 2904 *
3755******************************************************************************/ 2905 * Returns the PHY to the power-on reset state
2906 */
3756s32 e1000_phy_hw_reset(struct e1000_hw *hw) 2907s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3757{ 2908{
3758 u32 ctrl, ctrl_ext; 2909 u32 ctrl, ctrl_ext;
3759 u32 led_ctrl; 2910 u32 led_ctrl;
3760 s32 ret_val; 2911 s32 ret_val;
3761 u16 swfw; 2912
3762 2913 DEBUGFUNC("e1000_phy_hw_reset");
3763 DEBUGFUNC("e1000_phy_hw_reset"); 2914
3764 2915 DEBUGOUT("Resetting Phy...\n");
3765 /* In the case of the phy reset being blocked, it's not an error, we 2916
3766 * simply return success without performing the reset. */ 2917 if (hw->mac_type > e1000_82543) {
3767 ret_val = e1000_check_phy_reset_block(hw); 2918 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3768 if (ret_val) 2919 * bit. Then, take it out of reset.
3769 return E1000_SUCCESS; 2920 * For e1000 hardware, we delay for 10ms between the assert
3770 2921 * and deassert.
3771 DEBUGOUT("Resetting Phy...\n"); 2922 */
3772 2923 ctrl = er32(CTRL);
3773 if (hw->mac_type > e1000_82543) { 2924 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3774 if ((hw->mac_type == e1000_80003es2lan) && 2925 E1000_WRITE_FLUSH();
3775 (er32(STATUS) & E1000_STATUS_FUNC_1)) { 2926
3776 swfw = E1000_SWFW_PHY1_SM; 2927 msleep(10);
3777 } else { 2928
3778 swfw = E1000_SWFW_PHY0_SM; 2929 ew32(CTRL, ctrl);
3779 } 2930 E1000_WRITE_FLUSH();
3780 if (e1000_swfw_sync_acquire(hw, swfw)) { 2931
3781 DEBUGOUT("Unable to acquire swfw sync\n"); 2932 } else {
3782 return -E1000_ERR_SWFW_SYNC; 2933 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3783 } 2934 * bit to put the PHY into reset. Then, take it out of reset.
3784 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2935 */
3785 * bit. Then, take it out of reset. 2936 ctrl_ext = er32(CTRL_EXT);
3786 * For pre-e1000_82571 hardware, we delay for 10ms between the assert 2937 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3787 * and deassert. For e1000_82571 hardware and later, we instead delay 2938 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3788 * for 50us between and 10ms after the deassertion. 2939 ew32(CTRL_EXT, ctrl_ext);
3789 */ 2940 E1000_WRITE_FLUSH();
3790 ctrl = er32(CTRL); 2941 msleep(10);
3791 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2942 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3792 E1000_WRITE_FLUSH(); 2943 ew32(CTRL_EXT, ctrl_ext);
3793 2944 E1000_WRITE_FLUSH();
3794 if (hw->mac_type < e1000_82571) 2945 }
3795 msleep(10); 2946 udelay(150);
3796 else 2947
3797 udelay(100); 2948 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3798 2949 /* Configure activity LED after PHY reset */
3799 ew32(CTRL, ctrl); 2950 led_ctrl = er32(LEDCTL);
3800 E1000_WRITE_FLUSH(); 2951 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3801 2952 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3802 if (hw->mac_type >= e1000_82571) 2953 ew32(LEDCTL, led_ctrl);
3803 mdelay(10); 2954 }
3804 2955
3805 e1000_swfw_sync_release(hw, swfw); 2956 /* Wait for FW to finish PHY configuration. */
3806 } else { 2957 ret_val = e1000_get_phy_cfg_done(hw);
3807 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2958 if (ret_val != E1000_SUCCESS)
3808 * bit to put the PHY into reset. Then, take it out of reset. 2959 return ret_val;
3809 */ 2960
3810 ctrl_ext = er32(CTRL_EXT); 2961 return ret_val;
3811 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3812 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3813 ew32(CTRL_EXT, ctrl_ext);
3814 E1000_WRITE_FLUSH();
3815 msleep(10);
3816 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3817 ew32(CTRL_EXT, ctrl_ext);
3818 E1000_WRITE_FLUSH();
3819 }
3820 udelay(150);
3821
3822 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3823 /* Configure activity LED after PHY reset */
3824 led_ctrl = er32(LEDCTL);
3825 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3826 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3827 ew32(LEDCTL, led_ctrl);
3828 }
3829
3830 /* Wait for FW to finish PHY configuration. */
3831 ret_val = e1000_get_phy_cfg_done(hw);
3832 if (ret_val != E1000_SUCCESS)
3833 return ret_val;
3834 e1000_release_software_semaphore(hw);
3835
3836 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3837 ret_val = e1000_init_lcd_from_nvm(hw);
3838
3839 return ret_val;
3840} 2962}
3841 2963
3842/****************************************************************************** 2964/**
3843* Resets the PHY 2965 * e1000_phy_reset - reset the phy to commit settings
3844* 2966 * @hw: Struct containing variables accessed by shared code
3845* hw - Struct containing variables accessed by shared code 2967 *
3846* 2968 * Resets the PHY
3847* Sets bit 15 of the MII Control register 2969 * Sets bit 15 of the MII Control register
3848******************************************************************************/ 2970 */
3849s32 e1000_phy_reset(struct e1000_hw *hw) 2971s32 e1000_phy_reset(struct e1000_hw *hw)
3850{ 2972{
3851 s32 ret_val; 2973 s32 ret_val;
3852 u16 phy_data; 2974 u16 phy_data;
3853
3854 DEBUGFUNC("e1000_phy_reset");
3855
3856 /* In the case of the phy reset being blocked, it's not an error, we
3857 * simply return success without performing the reset. */
3858 ret_val = e1000_check_phy_reset_block(hw);
3859 if (ret_val)
3860 return E1000_SUCCESS;
3861
3862 switch (hw->phy_type) {
3863 case e1000_phy_igp:
3864 case e1000_phy_igp_2:
3865 case e1000_phy_igp_3:
3866 case e1000_phy_ife:
3867 ret_val = e1000_phy_hw_reset(hw);
3868 if (ret_val)
3869 return ret_val;
3870 break;
3871 default:
3872 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3873 if (ret_val)
3874 return ret_val;
3875
3876 phy_data |= MII_CR_RESET;
3877 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3878 if (ret_val)
3879 return ret_val;
3880
3881 udelay(1);
3882 break;
3883 }
3884
3885 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3886 e1000_phy_init_script(hw);
3887
3888 return E1000_SUCCESS;
3889}
3890 2975
3891/****************************************************************************** 2976 DEBUGFUNC("e1000_phy_reset");
3892* Work-around for 82566 power-down: on D3 entry-
3893* 1) disable gigabit link
3894* 2) write VR power-down enable
3895* 3) read it back
3896* if successful continue, else issue LCD reset and repeat
3897*
3898* hw - struct containing variables accessed by shared code
3899******************************************************************************/
3900void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3901{
3902 s32 reg;
3903 u16 phy_data;
3904 s32 retry = 0;
3905 2977
3906 DEBUGFUNC("e1000_phy_powerdown_workaround"); 2978 switch (hw->phy_type) {
2979 case e1000_phy_igp:
2980 ret_val = e1000_phy_hw_reset(hw);
2981 if (ret_val)
2982 return ret_val;
2983 break;
2984 default:
2985 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2986 if (ret_val)
2987 return ret_val;
3907 2988
3908 if (hw->phy_type != e1000_phy_igp_3) 2989 phy_data |= MII_CR_RESET;
3909 return; 2990 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2991 if (ret_val)
2992 return ret_val;
3910 2993
3911 do { 2994 udelay(1);
3912 /* Disable link */ 2995 break;
3913 reg = er32(PHY_CTRL); 2996 }
3914 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3915 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3916 2997
3917 /* Write VR power-down enable - bits 9:8 should be 10b */ 2998 if (hw->phy_type == e1000_phy_igp)
3918 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 2999 e1000_phy_init_script(hw);
3919 phy_data |= (1 << 9);
3920 phy_data &= ~(1 << 8);
3921 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3922 3000
3923 /* Read it back and test */ 3001 return E1000_SUCCESS;
3924 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 3002}
3925 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3926 break;
3927 3003
3928 /* Issue PHY reset and repeat at most one more time */ 3004/**
3929 reg = er32(CTRL); 3005 * e1000_detect_gig_phy - check the phy type
3930 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 3006 * @hw: Struct containing variables accessed by shared code
3931 retry++; 3007 *
3932 } while (retry); 3008 * Probes the expected PHY address for known PHY IDs
3009 */
3010static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3011{
3012 s32 phy_init_status, ret_val;
3013 u16 phy_id_high, phy_id_low;
3014 bool match = false;
3933 3015
3934 return; 3016 DEBUGFUNC("e1000_detect_gig_phy");
3935 3017
3936} 3018 if (hw->phy_id != 0)
3019 return E1000_SUCCESS;
3937 3020
3938/****************************************************************************** 3021 /* Read the PHY ID Registers to identify which PHY is onboard. */
3939* Work-around for 82566 Kumeran PCS lock loss: 3022 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3940* On link status change (i.e. PCI reset, speed change) and link is up and 3023 if (ret_val)
3941* speed is gigabit- 3024 return ret_val;
3942* 0) if workaround is optionally disabled do nothing
3943* 1) wait 1ms for Kumeran link to come up
3944* 2) check Kumeran Diagnostic register PCS lock loss bit
3945* 3) if not set the link is locked (all is good), otherwise...
3946* 4) reset the PHY
3947* 5) repeat up to 10 times
3948* Note: this is only called for IGP3 copper when speed is 1gb.
3949*
3950* hw - struct containing variables accessed by shared code
3951******************************************************************************/
3952static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3953{
3954 s32 ret_val;
3955 s32 reg;
3956 s32 cnt;
3957 u16 phy_data;
3958
3959 if (hw->kmrn_lock_loss_workaround_disabled)
3960 return E1000_SUCCESS;
3961
3962 /* Make sure link is up before proceeding. If not just return.
3963 * Attempting this while link is negotiating fouled up link
3964 * stability */
3965 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3966 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3967
3968 if (phy_data & MII_SR_LINK_STATUS) {
3969 for (cnt = 0; cnt < 10; cnt++) {
3970 /* read once to clear */
3971 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3972 if (ret_val)
3973 return ret_val;
3974 /* and again to get new status */
3975 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3976 if (ret_val)
3977 return ret_val;
3978
3979 /* check for PCS lock */
3980 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3981 return E1000_SUCCESS;
3982
3983 /* Issue PHY reset */
3984 e1000_phy_hw_reset(hw);
3985 mdelay(5);
3986 }
3987 /* Disable GigE link negotiation */
3988 reg = er32(PHY_CTRL);
3989 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3990 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3991
3992 /* unable to acquire PCS lock */
3993 return E1000_ERR_PHY;
3994 }
3995
3996 return E1000_SUCCESS;
3997}
3998 3025
3999/****************************************************************************** 3026 hw->phy_id = (u32) (phy_id_high << 16);
4000* Probes the expected PHY address for known PHY IDs 3027 udelay(20);
4001* 3028 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4002* hw - Struct containing variables accessed by shared code 3029 if (ret_val)
4003******************************************************************************/ 3030 return ret_val;
4004static s32 e1000_detect_gig_phy(struct e1000_hw *hw) 3031
4005{ 3032 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
4006 s32 phy_init_status, ret_val; 3033 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
4007 u16 phy_id_high, phy_id_low; 3034
4008 bool match = false; 3035 switch (hw->mac_type) {
4009 3036 case e1000_82543:
4010 DEBUGFUNC("e1000_detect_gig_phy"); 3037 if (hw->phy_id == M88E1000_E_PHY_ID)
4011 3038 match = true;
4012 if (hw->phy_id != 0) 3039 break;
4013 return E1000_SUCCESS; 3040 case e1000_82544:
4014 3041 if (hw->phy_id == M88E1000_I_PHY_ID)
4015 /* The 82571 firmware may still be configuring the PHY. In this 3042 match = true;
4016 * case, we cannot access the PHY until the configuration is done. So 3043 break;
4017 * we explicitly set the PHY values. */ 3044 case e1000_82540:
4018 if (hw->mac_type == e1000_82571 || 3045 case e1000_82545:
4019 hw->mac_type == e1000_82572) { 3046 case e1000_82545_rev_3:
4020 hw->phy_id = IGP01E1000_I_PHY_ID; 3047 case e1000_82546:
4021 hw->phy_type = e1000_phy_igp_2; 3048 case e1000_82546_rev_3:
4022 return E1000_SUCCESS; 3049 if (hw->phy_id == M88E1011_I_PHY_ID)
4023 } 3050 match = true;
4024 3051 break;
4025 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- 3052 case e1000_82541:
4026 * around that forces PHY page 0 to be set or the reads fail. The rest of 3053 case e1000_82541_rev_2:
4027 * the code in this routine uses e1000_read_phy_reg to read the PHY ID. 3054 case e1000_82547:
4028 * So for ESB-2 we need to have this set so our reads won't fail. If the 3055 case e1000_82547_rev_2:
4029 * attached PHY is not a e1000_phy_gg82563, the routines below will figure 3056 if (hw->phy_id == IGP01E1000_I_PHY_ID)
4030 * this out as well. */ 3057 match = true;
4031 if (hw->mac_type == e1000_80003es2lan) 3058 break;
4032 hw->phy_type = e1000_phy_gg82563; 3059 default:
4033 3060 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4034 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3061 return -E1000_ERR_CONFIG;
4035 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3062 }
4036 if (ret_val) 3063 phy_init_status = e1000_set_phy_type(hw);
4037 return ret_val; 3064
4038 3065 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4039 hw->phy_id = (u32)(phy_id_high << 16); 3066 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4040 udelay(20); 3067 return E1000_SUCCESS;
4041 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3068 }
4042 if (ret_val) 3069 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4043 return ret_val; 3070 return -E1000_ERR_PHY;
4044
4045 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
4046 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
4047
4048 switch (hw->mac_type) {
4049 case e1000_82543:
4050 if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
4051 break;
4052 case e1000_82544:
4053 if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
4054 break;
4055 case e1000_82540:
4056 case e1000_82545:
4057 case e1000_82545_rev_3:
4058 case e1000_82546:
4059 case e1000_82546_rev_3:
4060 if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
4061 break;
4062 case e1000_82541:
4063 case e1000_82541_rev_2:
4064 case e1000_82547:
4065 case e1000_82547_rev_2:
4066 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
4067 break;
4068 case e1000_82573:
4069 if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
4070 break;
4071 case e1000_80003es2lan:
4072 if (hw->phy_id == GG82563_E_PHY_ID) match = true;
4073 break;
4074 case e1000_ich8lan:
4075 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
4076 if (hw->phy_id == IFE_E_PHY_ID) match = true;
4077 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
4078 if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
4079 break;
4080 default:
4081 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4082 return -E1000_ERR_CONFIG;
4083 }
4084 phy_init_status = e1000_set_phy_type(hw);
4085
4086 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4087 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4088 return E1000_SUCCESS;
4089 }
4090 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4091 return -E1000_ERR_PHY;
4092} 3071}
4093 3072
4094/****************************************************************************** 3073/**
4095* Resets the PHY's DSP 3074 * e1000_phy_reset_dsp - reset DSP
4096* 3075 * @hw: Struct containing variables accessed by shared code
4097* hw - Struct containing variables accessed by shared code 3076 *
4098******************************************************************************/ 3077 * Resets the PHY's DSP
3078 */
4099static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3079static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
4100{ 3080{
4101 s32 ret_val; 3081 s32 ret_val;
4102 DEBUGFUNC("e1000_phy_reset_dsp"); 3082 DEBUGFUNC("e1000_phy_reset_dsp");
4103 3083
4104 do { 3084 do {
4105 if (hw->phy_type != e1000_phy_gg82563) { 3085 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4106 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3086 if (ret_val)
4107 if (ret_val) break; 3087 break;
4108 } 3088 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4109 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3089 if (ret_val)
4110 if (ret_val) break; 3090 break;
4111 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3091 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4112 if (ret_val) break; 3092 if (ret_val)
4113 ret_val = E1000_SUCCESS; 3093 break;
4114 } while (0); 3094 ret_val = E1000_SUCCESS;
4115 3095 } while (0);
4116 return ret_val; 3096
3097 return ret_val;
4117} 3098}
4118 3099
4119/****************************************************************************** 3100/**
4120* Get PHY information from various PHY registers for igp PHY only. 3101 * e1000_phy_igp_get_info - get igp specific registers
4121* 3102 * @hw: Struct containing variables accessed by shared code
4122* hw - Struct containing variables accessed by shared code 3103 * @phy_info: PHY information structure
4123* phy_info - PHY information structure 3104 *
4124******************************************************************************/ 3105 * Get PHY information from various PHY registers for igp PHY only.
3106 */
4125static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 3107static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
4126 struct e1000_phy_info *phy_info) 3108 struct e1000_phy_info *phy_info)
4127{ 3109{
4128 s32 ret_val; 3110 s32 ret_val;
4129 u16 phy_data, min_length, max_length, average; 3111 u16 phy_data, min_length, max_length, average;
4130 e1000_rev_polarity polarity; 3112 e1000_rev_polarity polarity;
4131 3113
4132 DEBUGFUNC("e1000_phy_igp_get_info"); 3114 DEBUGFUNC("e1000_phy_igp_get_info");
4133 3115
4134 /* The downshift status is checked only once, after link is established, 3116 /* The downshift status is checked only once, after link is established,
4135 * and it stored in the hw->speed_downgraded parameter. */ 3117 * and it stored in the hw->speed_downgraded parameter. */
4136 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 3118 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
4137 3119
4138 /* IGP01E1000 does not need to support it. */ 3120 /* IGP01E1000 does not need to support it. */
4139 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3121 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4140 3122
4141 /* IGP01E1000 always correct polarity reversal */ 3123 /* IGP01E1000 always correct polarity reversal */
4142 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 3124 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4143 3125
4144 /* Check polarity status */ 3126 /* Check polarity status */
4145 ret_val = e1000_check_polarity(hw, &polarity); 3127 ret_val = e1000_check_polarity(hw, &polarity);
4146 if (ret_val) 3128 if (ret_val)
4147 return ret_val; 3129 return ret_val;
4148 3130
4149 phy_info->cable_polarity = polarity; 3131 phy_info->cable_polarity = polarity;
4150 3132
4151 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 3133 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4152 if (ret_val) 3134 if (ret_val)
4153 return ret_val; 3135 return ret_val;
4154 3136
4155 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> 3137 phy_info->mdix_mode =
4156 IGP01E1000_PSSR_MDIX_SHIFT); 3138 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
4157 3139 IGP01E1000_PSSR_MDIX_SHIFT);
4158 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3140
4159 IGP01E1000_PSSR_SPEED_1000MBPS) { 3141 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4160 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 3142 IGP01E1000_PSSR_SPEED_1000MBPS) {
4161 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3143 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4162 if (ret_val) 3144 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4163 return ret_val; 3145 if (ret_val)
4164 3146 return ret_val;
4165 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3147
4166 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3148 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4167 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3149 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4168 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3150 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4169 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3151 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4170 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3152 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4171 3153 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4172 /* Get cable length */ 3154
4173 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 3155 /* Get cable length */
4174 if (ret_val) 3156 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4175 return ret_val; 3157 if (ret_val)
4176 3158 return ret_val;
4177 /* Translate to old method */ 3159
4178 average = (max_length + min_length) / 2; 3160 /* Translate to old method */
4179 3161 average = (max_length + min_length) / 2;
4180 if (average <= e1000_igp_cable_length_50) 3162
4181 phy_info->cable_length = e1000_cable_length_50; 3163 if (average <= e1000_igp_cable_length_50)
4182 else if (average <= e1000_igp_cable_length_80) 3164 phy_info->cable_length = e1000_cable_length_50;
4183 phy_info->cable_length = e1000_cable_length_50_80; 3165 else if (average <= e1000_igp_cable_length_80)
4184 else if (average <= e1000_igp_cable_length_110) 3166 phy_info->cable_length = e1000_cable_length_50_80;
4185 phy_info->cable_length = e1000_cable_length_80_110; 3167 else if (average <= e1000_igp_cable_length_110)
4186 else if (average <= e1000_igp_cable_length_140) 3168 phy_info->cable_length = e1000_cable_length_80_110;
4187 phy_info->cable_length = e1000_cable_length_110_140; 3169 else if (average <= e1000_igp_cable_length_140)
4188 else 3170 phy_info->cable_length = e1000_cable_length_110_140;
4189 phy_info->cable_length = e1000_cable_length_140; 3171 else
4190 } 3172 phy_info->cable_length = e1000_cable_length_140;
4191 3173 }
4192 return E1000_SUCCESS;
4193}
4194 3174
4195/****************************************************************************** 3175 return E1000_SUCCESS;
4196* Get PHY information from various PHY registers for ife PHY only.
4197*
4198* hw - Struct containing variables accessed by shared code
4199* phy_info - PHY information structure
4200******************************************************************************/
4201static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
4202 struct e1000_phy_info *phy_info)
4203{
4204 s32 ret_val;
4205 u16 phy_data;
4206 e1000_rev_polarity polarity;
4207
4208 DEBUGFUNC("e1000_phy_ife_get_info");
4209
4210 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4211 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4212
4213 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4214 if (ret_val)
4215 return ret_val;
4216 phy_info->polarity_correction =
4217 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4218 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4219 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4220
4221 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4222 ret_val = e1000_check_polarity(hw, &polarity);
4223 if (ret_val)
4224 return ret_val;
4225 } else {
4226 /* Polarity is forced. */
4227 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4228 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4229 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4230 }
4231 phy_info->cable_polarity = polarity;
4232
4233 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4234 if (ret_val)
4235 return ret_val;
4236
4237 phy_info->mdix_mode = (e1000_auto_x_mode)
4238 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4239 IFE_PMC_MDIX_MODE_SHIFT);
4240
4241 return E1000_SUCCESS;
4242} 3176}
4243 3177
4244/****************************************************************************** 3178/**
4245* Get PHY information from various PHY registers fot m88 PHY only. 3179 * e1000_phy_m88_get_info - get m88 specific registers
4246* 3180 * @hw: Struct containing variables accessed by shared code
4247* hw - Struct containing variables accessed by shared code 3181 * @phy_info: PHY information structure
4248* phy_info - PHY information structure 3182 *
4249******************************************************************************/ 3183 * Get PHY information from various PHY registers for m88 PHY only.
3184 */
4250static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 3185static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
4251 struct e1000_phy_info *phy_info) 3186 struct e1000_phy_info *phy_info)
4252{ 3187{
4253 s32 ret_val; 3188 s32 ret_val;
4254 u16 phy_data; 3189 u16 phy_data;
4255 e1000_rev_polarity polarity; 3190 e1000_rev_polarity polarity;
4256 3191
4257 DEBUGFUNC("e1000_phy_m88_get_info"); 3192 DEBUGFUNC("e1000_phy_m88_get_info");
4258 3193
4259 /* The downshift status is checked only once, after link is established, 3194 /* The downshift status is checked only once, after link is established,
4260 * and it stored in the hw->speed_downgraded parameter. */ 3195 * and it stored in the hw->speed_downgraded parameter. */
4261 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 3196 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
4262 3197
4263 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3198 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4264 if (ret_val) 3199 if (ret_val)
4265 return ret_val; 3200 return ret_val;
4266 3201
4267 phy_info->extended_10bt_distance = 3202 phy_info->extended_10bt_distance =
4268 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3203 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4269 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3204 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4270 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; 3205 e1000_10bt_ext_dist_enable_lower :
4271 3206 e1000_10bt_ext_dist_enable_normal;
4272 phy_info->polarity_correction = 3207
4273 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3208 phy_info->polarity_correction =
4274 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3209 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4275 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3210 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4276 3211 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4277 /* Check polarity status */ 3212
4278 ret_val = e1000_check_polarity(hw, &polarity); 3213 /* Check polarity status */
4279 if (ret_val) 3214 ret_val = e1000_check_polarity(hw, &polarity);
4280 return ret_val; 3215 if (ret_val)
4281 phy_info->cable_polarity = polarity; 3216 return ret_val;
4282 3217 phy_info->cable_polarity = polarity;
4283 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3218
4284 if (ret_val) 3219 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4285 return ret_val; 3220 if (ret_val)
4286 3221 return ret_val;
4287 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> 3222
4288 M88E1000_PSSR_MDIX_SHIFT); 3223 phy_info->mdix_mode =
4289 3224 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
4290 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3225 M88E1000_PSSR_MDIX_SHIFT);
4291 /* Cable Length Estimation and Local/Remote Receiver Information 3226
4292 * are only valid at 1000 Mbps. 3227 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4293 */ 3228 /* Cable Length Estimation and Local/Remote Receiver Information
4294 if (hw->phy_type != e1000_phy_gg82563) { 3229 * are only valid at 1000 Mbps.
4295 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 3230 */
4296 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3231 phy_info->cable_length =
4297 } else { 3232 (e1000_cable_length) ((phy_data &
4298 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 3233 M88E1000_PSSR_CABLE_LENGTH) >>
4299 &phy_data); 3234 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4300 if (ret_val) 3235
4301 return ret_val; 3236 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4302 3237 if (ret_val)
4303 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); 3238 return ret_val;
4304 } 3239
4305 3240 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3241 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4307 if (ret_val) 3242 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4308 return ret_val; 3243 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4309 3244 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4310 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3245 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4311 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3246
4312 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3247 }
4313 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3248
4314 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3249 return E1000_SUCCESS;
4315 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4316
4317 }
4318
4319 return E1000_SUCCESS;
4320} 3250}
4321 3251
4322/****************************************************************************** 3252/**
4323* Get PHY information from various PHY registers 3253 * e1000_phy_get_info - request phy info
4324* 3254 * @hw: Struct containing variables accessed by shared code
4325* hw - Struct containing variables accessed by shared code 3255 * @phy_info: PHY information structure
4326* phy_info - PHY information structure 3256 *
4327******************************************************************************/ 3257 * Get PHY information from various PHY registers
3258 */
4328s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) 3259s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
4329{ 3260{
4330 s32 ret_val; 3261 s32 ret_val;
4331 u16 phy_data; 3262 u16 phy_data;
4332 3263
4333 DEBUGFUNC("e1000_phy_get_info"); 3264 DEBUGFUNC("e1000_phy_get_info");
4334 3265
4335 phy_info->cable_length = e1000_cable_length_undefined; 3266 phy_info->cable_length = e1000_cable_length_undefined;
4336 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3267 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4337 phy_info->cable_polarity = e1000_rev_polarity_undefined; 3268 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4338 phy_info->downshift = e1000_downshift_undefined; 3269 phy_info->downshift = e1000_downshift_undefined;
4339 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 3270 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4340 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 3271 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4341 phy_info->local_rx = e1000_1000t_rx_status_undefined; 3272 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4342 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3273 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4343 3274
4344 if (hw->media_type != e1000_media_type_copper) { 3275 if (hw->media_type != e1000_media_type_copper) {
4345 DEBUGOUT("PHY info is only valid for copper media\n"); 3276 DEBUGOUT("PHY info is only valid for copper media\n");
4346 return -E1000_ERR_CONFIG; 3277 return -E1000_ERR_CONFIG;
4347 } 3278 }
4348 3279
4349 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3280 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4350 if (ret_val) 3281 if (ret_val)
4351 return ret_val; 3282 return ret_val;
4352 3283
4353 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3284 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4354 if (ret_val) 3285 if (ret_val)
4355 return ret_val; 3286 return ret_val;
4356 3287
4357 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3288 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4358 DEBUGOUT("PHY info is only valid if link is up\n"); 3289 DEBUGOUT("PHY info is only valid if link is up\n");
4359 return -E1000_ERR_CONFIG; 3290 return -E1000_ERR_CONFIG;
4360 } 3291 }
4361 3292
4362 if (hw->phy_type == e1000_phy_igp || 3293 if (hw->phy_type == e1000_phy_igp)
4363 hw->phy_type == e1000_phy_igp_3 || 3294 return e1000_phy_igp_get_info(hw, phy_info);
4364 hw->phy_type == e1000_phy_igp_2) 3295 else
4365 return e1000_phy_igp_get_info(hw, phy_info); 3296 return e1000_phy_m88_get_info(hw, phy_info);
4366 else if (hw->phy_type == e1000_phy_ife)
4367 return e1000_phy_ife_get_info(hw, phy_info);
4368 else
4369 return e1000_phy_m88_get_info(hw, phy_info);
4370} 3297}
4371 3298
4372s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3299s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
4373{ 3300{
4374 DEBUGFUNC("e1000_validate_mdi_settings"); 3301 DEBUGFUNC("e1000_validate_mdi_settings");
4375
4376 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4377 DEBUGOUT("Invalid MDI setting detected\n");
4378 hw->mdix = 1;
4379 return -E1000_ERR_CONFIG;
4380 }
4381 return E1000_SUCCESS;
4382}
4383 3302
3303 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3304 DEBUGOUT("Invalid MDI setting detected\n");
3305 hw->mdix = 1;
3306 return -E1000_ERR_CONFIG;
3307 }
3308 return E1000_SUCCESS;
3309}
4384 3310
4385/****************************************************************************** 3311/**
4386 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3312 * e1000_init_eeprom_params - initialize sw eeprom vars
4387 * is configured. Additionally, if this is ICH8, the flash controller GbE 3313 * @hw: Struct containing variables accessed by shared code
4388 * registers must be mapped, or this will crash.
4389 * 3314 *
4390 * hw - Struct containing variables accessed by shared code 3315 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4391 *****************************************************************************/ 3316 * is configured.
3317 */
4392s32 e1000_init_eeprom_params(struct e1000_hw *hw) 3318s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4393{ 3319{
4394 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3320 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4395 u32 eecd = er32(EECD); 3321 u32 eecd = er32(EECD);
4396 s32 ret_val = E1000_SUCCESS; 3322 s32 ret_val = E1000_SUCCESS;
4397 u16 eeprom_size; 3323 u16 eeprom_size;
4398 3324
4399 DEBUGFUNC("e1000_init_eeprom_params"); 3325 DEBUGFUNC("e1000_init_eeprom_params");
4400 3326
4401 switch (hw->mac_type) { 3327 switch (hw->mac_type) {
4402 case e1000_82542_rev2_0: 3328 case e1000_82542_rev2_0:
4403 case e1000_82542_rev2_1: 3329 case e1000_82542_rev2_1:
4404 case e1000_82543: 3330 case e1000_82543:
4405 case e1000_82544: 3331 case e1000_82544:
4406 eeprom->type = e1000_eeprom_microwire; 3332 eeprom->type = e1000_eeprom_microwire;
4407 eeprom->word_size = 64; 3333 eeprom->word_size = 64;
4408 eeprom->opcode_bits = 3; 3334 eeprom->opcode_bits = 3;
4409 eeprom->address_bits = 6; 3335 eeprom->address_bits = 6;
4410 eeprom->delay_usec = 50; 3336 eeprom->delay_usec = 50;
4411 eeprom->use_eerd = false; 3337 break;
4412 eeprom->use_eewr = false; 3338 case e1000_82540:
4413 break; 3339 case e1000_82545:
4414 case e1000_82540: 3340 case e1000_82545_rev_3:
4415 case e1000_82545: 3341 case e1000_82546:
4416 case e1000_82545_rev_3: 3342 case e1000_82546_rev_3:
4417 case e1000_82546: 3343 eeprom->type = e1000_eeprom_microwire;
4418 case e1000_82546_rev_3: 3344 eeprom->opcode_bits = 3;
4419 eeprom->type = e1000_eeprom_microwire; 3345 eeprom->delay_usec = 50;
4420 eeprom->opcode_bits = 3; 3346 if (eecd & E1000_EECD_SIZE) {
4421 eeprom->delay_usec = 50; 3347 eeprom->word_size = 256;
4422 if (eecd & E1000_EECD_SIZE) { 3348 eeprom->address_bits = 8;
4423 eeprom->word_size = 256; 3349 } else {
4424 eeprom->address_bits = 8; 3350 eeprom->word_size = 64;
4425 } else { 3351 eeprom->address_bits = 6;
4426 eeprom->word_size = 64; 3352 }
4427 eeprom->address_bits = 6; 3353 break;
4428 } 3354 case e1000_82541:
4429 eeprom->use_eerd = false; 3355 case e1000_82541_rev_2:
4430 eeprom->use_eewr = false; 3356 case e1000_82547:
4431 break; 3357 case e1000_82547_rev_2:
4432 case e1000_82541: 3358 if (eecd & E1000_EECD_TYPE) {
4433 case e1000_82541_rev_2: 3359 eeprom->type = e1000_eeprom_spi;
4434 case e1000_82547: 3360 eeprom->opcode_bits = 8;
4435 case e1000_82547_rev_2: 3361 eeprom->delay_usec = 1;
4436 if (eecd & E1000_EECD_TYPE) { 3362 if (eecd & E1000_EECD_ADDR_BITS) {
4437 eeprom->type = e1000_eeprom_spi; 3363 eeprom->page_size = 32;
4438 eeprom->opcode_bits = 8; 3364 eeprom->address_bits = 16;
4439 eeprom->delay_usec = 1; 3365 } else {
4440 if (eecd & E1000_EECD_ADDR_BITS) { 3366 eeprom->page_size = 8;
4441 eeprom->page_size = 32; 3367 eeprom->address_bits = 8;
4442 eeprom->address_bits = 16; 3368 }
4443 } else { 3369 } else {
4444 eeprom->page_size = 8; 3370 eeprom->type = e1000_eeprom_microwire;
4445 eeprom->address_bits = 8; 3371 eeprom->opcode_bits = 3;
4446 } 3372 eeprom->delay_usec = 50;
4447 } else { 3373 if (eecd & E1000_EECD_ADDR_BITS) {
4448 eeprom->type = e1000_eeprom_microwire; 3374 eeprom->word_size = 256;
4449 eeprom->opcode_bits = 3; 3375 eeprom->address_bits = 8;
4450 eeprom->delay_usec = 50; 3376 } else {
4451 if (eecd & E1000_EECD_ADDR_BITS) { 3377 eeprom->word_size = 64;
4452 eeprom->word_size = 256; 3378 eeprom->address_bits = 6;
4453 eeprom->address_bits = 8; 3379 }
4454 } else { 3380 }
4455 eeprom->word_size = 64; 3381 break;
4456 eeprom->address_bits = 6; 3382 default:
4457 } 3383 break;
4458 } 3384 }
4459 eeprom->use_eerd = false; 3385
4460 eeprom->use_eewr = false; 3386 if (eeprom->type == e1000_eeprom_spi) {
4461 break; 3387 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4462 case e1000_82571: 3388 * 32KB (incremented by powers of 2).
4463 case e1000_82572: 3389 */
4464 eeprom->type = e1000_eeprom_spi; 3390 /* Set to default value for initial eeprom read. */
4465 eeprom->opcode_bits = 8; 3391 eeprom->word_size = 64;
4466 eeprom->delay_usec = 1; 3392 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4467 if (eecd & E1000_EECD_ADDR_BITS) { 3393 if (ret_val)
4468 eeprom->page_size = 32; 3394 return ret_val;
4469 eeprom->address_bits = 16; 3395 eeprom_size =
4470 } else { 3396 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4471 eeprom->page_size = 8; 3397 /* 256B eeprom size was not supported in earlier hardware, so we
4472 eeprom->address_bits = 8; 3398 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4473 } 3399 * is never the result used in the shifting logic below. */
4474 eeprom->use_eerd = false; 3400 if (eeprom_size)
4475 eeprom->use_eewr = false; 3401 eeprom_size++;
4476 break; 3402
4477 case e1000_82573: 3403 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4478 eeprom->type = e1000_eeprom_spi; 3404 }
4479 eeprom->opcode_bits = 8; 3405 return ret_val;
4480 eeprom->delay_usec = 1;
4481 if (eecd & E1000_EECD_ADDR_BITS) {
4482 eeprom->page_size = 32;
4483 eeprom->address_bits = 16;
4484 } else {
4485 eeprom->page_size = 8;
4486 eeprom->address_bits = 8;
4487 }
4488 eeprom->use_eerd = true;
4489 eeprom->use_eewr = true;
4490 if (!e1000_is_onboard_nvm_eeprom(hw)) {
4491 eeprom->type = e1000_eeprom_flash;
4492 eeprom->word_size = 2048;
4493
4494 /* Ensure that the Autonomous FLASH update bit is cleared due to
4495 * Flash update issue on parts which use a FLASH for NVM. */
4496 eecd &= ~E1000_EECD_AUPDEN;
4497 ew32(EECD, eecd);
4498 }
4499 break;
4500 case e1000_80003es2lan:
4501 eeprom->type = e1000_eeprom_spi;
4502 eeprom->opcode_bits = 8;
4503 eeprom->delay_usec = 1;
4504 if (eecd & E1000_EECD_ADDR_BITS) {
4505 eeprom->page_size = 32;
4506 eeprom->address_bits = 16;
4507 } else {
4508 eeprom->page_size = 8;
4509 eeprom->address_bits = 8;
4510 }
4511 eeprom->use_eerd = true;
4512 eeprom->use_eewr = false;
4513 break;
4514 case e1000_ich8lan:
4515 {
4516 s32 i = 0;
4517 u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4518
4519 eeprom->type = e1000_eeprom_ich8;
4520 eeprom->use_eerd = false;
4521 eeprom->use_eewr = false;
4522 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4523
4524 /* Zero the shadow RAM structure. But don't load it from NVM
4525 * so as to save time for driver init */
4526 if (hw->eeprom_shadow_ram != NULL) {
4527 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4528 hw->eeprom_shadow_ram[i].modified = false;
4529 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4530 }
4531 }
4532
4533 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4534 ICH_FLASH_SECTOR_SIZE;
4535
4536 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4537 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4538
4539 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4540
4541 hw->flash_bank_size /= 2 * sizeof(u16);
4542
4543 break;
4544 }
4545 default:
4546 break;
4547 }
4548
4549 if (eeprom->type == e1000_eeprom_spi) {
4550 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4551 * 32KB (incremented by powers of 2).
4552 */
4553 if (hw->mac_type <= e1000_82547_rev_2) {
4554 /* Set to default value for initial eeprom read. */
4555 eeprom->word_size = 64;
4556 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4557 if (ret_val)
4558 return ret_val;
4559 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4560 /* 256B eeprom size was not supported in earlier hardware, so we
4561 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4562 * is never the result used in the shifting logic below. */
4563 if (eeprom_size)
4564 eeprom_size++;
4565 } else {
4566 eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4567 E1000_EECD_SIZE_EX_SHIFT);
4568 }
4569
4570 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4571 }
4572 return ret_val;
4573} 3406}
4574 3407
4575/****************************************************************************** 3408/**
4576 * Raises the EEPROM's clock input. 3409 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
4577 * 3410 * @hw: Struct containing variables accessed by shared code
4578 * hw - Struct containing variables accessed by shared code 3411 * @eecd: EECD's current value
4579 * eecd - EECD's current value 3412 */
4580 *****************************************************************************/
4581static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) 3413static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
4582{ 3414{
4583 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 3415 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4584 * wait <delay> microseconds. 3416 * wait <delay> microseconds.
4585 */ 3417 */
4586 *eecd = *eecd | E1000_EECD_SK; 3418 *eecd = *eecd | E1000_EECD_SK;
4587 ew32(EECD, *eecd); 3419 ew32(EECD, *eecd);
4588 E1000_WRITE_FLUSH(); 3420 E1000_WRITE_FLUSH();
4589 udelay(hw->eeprom.delay_usec); 3421 udelay(hw->eeprom.delay_usec);
4590} 3422}
4591 3423
4592/****************************************************************************** 3424/**
4593 * Lowers the EEPROM's clock input. 3425 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
4594 * 3426 * @hw: Struct containing variables accessed by shared code
4595 * hw - Struct containing variables accessed by shared code 3427 * @eecd: EECD's current value
4596 * eecd - EECD's current value 3428 */
4597 *****************************************************************************/
4598static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) 3429static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
4599{ 3430{
4600 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 3431 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4601 * wait 50 microseconds. 3432 * wait 50 microseconds.
4602 */ 3433 */
4603 *eecd = *eecd & ~E1000_EECD_SK; 3434 *eecd = *eecd & ~E1000_EECD_SK;
4604 ew32(EECD, *eecd); 3435 ew32(EECD, *eecd);
4605 E1000_WRITE_FLUSH(); 3436 E1000_WRITE_FLUSH();
4606 udelay(hw->eeprom.delay_usec); 3437 udelay(hw->eeprom.delay_usec);
4607} 3438}
4608 3439
4609/****************************************************************************** 3440/**
4610 * Shift data bits out to the EEPROM. 3441 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
4611 * 3442 * @hw: Struct containing variables accessed by shared code
4612 * hw - Struct containing variables accessed by shared code 3443 * @data: data to send to the EEPROM
4613 * data - data to send to the EEPROM 3444 * @count: number of bits to shift out
4614 * count - number of bits to shift out 3445 */
4615 *****************************************************************************/
4616static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) 3446static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
4617{ 3447{
4618 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3448 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4619 u32 eecd; 3449 u32 eecd;
4620 u32 mask; 3450 u32 mask;
4621 3451
4622 /* We need to shift "count" bits out to the EEPROM. So, value in the 3452 /* We need to shift "count" bits out to the EEPROM. So, value in the
4623 * "data" parameter will be shifted out to the EEPROM one bit at a time. 3453 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4624 * In order to do this, "data" must be broken down into bits. 3454 * In order to do this, "data" must be broken down into bits.
4625 */ 3455 */
4626 mask = 0x01 << (count - 1); 3456 mask = 0x01 << (count - 1);
4627 eecd = er32(EECD); 3457 eecd = er32(EECD);
4628 if (eeprom->type == e1000_eeprom_microwire) { 3458 if (eeprom->type == e1000_eeprom_microwire) {
4629 eecd &= ~E1000_EECD_DO; 3459 eecd &= ~E1000_EECD_DO;
4630 } else if (eeprom->type == e1000_eeprom_spi) { 3460 } else if (eeprom->type == e1000_eeprom_spi) {
4631 eecd |= E1000_EECD_DO; 3461 eecd |= E1000_EECD_DO;
4632 } 3462 }
4633 do { 3463 do {
4634 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 3464 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4635 * and then raising and then lowering the clock (the SK bit controls 3465 * and then raising and then lowering the clock (the SK bit controls
4636 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 3466 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4637 * by setting "DI" to "0" and then raising and then lowering the clock. 3467 * by setting "DI" to "0" and then raising and then lowering the clock.
4638 */ 3468 */
4639 eecd &= ~E1000_EECD_DI; 3469 eecd &= ~E1000_EECD_DI;
4640 3470
4641 if (data & mask) 3471 if (data & mask)
4642 eecd |= E1000_EECD_DI; 3472 eecd |= E1000_EECD_DI;
4643 3473
4644 ew32(EECD, eecd); 3474 ew32(EECD, eecd);
4645 E1000_WRITE_FLUSH(); 3475 E1000_WRITE_FLUSH();
4646 3476
4647 udelay(eeprom->delay_usec); 3477 udelay(eeprom->delay_usec);
4648 3478
4649 e1000_raise_ee_clk(hw, &eecd); 3479 e1000_raise_ee_clk(hw, &eecd);
4650 e1000_lower_ee_clk(hw, &eecd); 3480 e1000_lower_ee_clk(hw, &eecd);
4651 3481
4652 mask = mask >> 1; 3482 mask = mask >> 1;
4653 3483
4654 } while (mask); 3484 } while (mask);
4655 3485
4656 /* We leave the "DI" bit set to "0" when we leave this routine. */ 3486 /* We leave the "DI" bit set to "0" when we leave this routine. */
4657 eecd &= ~E1000_EECD_DI; 3487 eecd &= ~E1000_EECD_DI;
4658 ew32(EECD, eecd); 3488 ew32(EECD, eecd);
4659} 3489}
4660 3490
4661/****************************************************************************** 3491/**
4662 * Shift data bits in from the EEPROM 3492 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
4663 * 3493 * @hw: Struct containing variables accessed by shared code
4664 * hw - Struct containing variables accessed by shared code 3494 * @count: number of bits to shift in
4665 *****************************************************************************/ 3495 */
4666static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) 3496static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
4667{ 3497{
4668 u32 eecd; 3498 u32 eecd;
4669 u32 i; 3499 u32 i;
4670 u16 data; 3500 u16 data;
4671 3501
4672 /* In order to read a register from the EEPROM, we need to shift 'count' 3502 /* In order to read a register from the EEPROM, we need to shift 'count'
4673 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 3503 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4674 * input to the EEPROM (setting the SK bit), and then reading the value of 3504 * input to the EEPROM (setting the SK bit), and then reading the value of
4675 * the "DO" bit. During this "shifting in" process the "DI" bit should 3505 * the "DO" bit. During this "shifting in" process the "DI" bit should
4676 * always be clear. 3506 * always be clear.
4677 */ 3507 */
4678 3508
4679 eecd = er32(EECD); 3509 eecd = er32(EECD);
4680 3510
4681 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 3511 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4682 data = 0; 3512 data = 0;
4683 3513
4684 for (i = 0; i < count; i++) { 3514 for (i = 0; i < count; i++) {
4685 data = data << 1; 3515 data = data << 1;
4686 e1000_raise_ee_clk(hw, &eecd); 3516 e1000_raise_ee_clk(hw, &eecd);
4687 3517
4688 eecd = er32(EECD); 3518 eecd = er32(EECD);
4689 3519
4690 eecd &= ~(E1000_EECD_DI); 3520 eecd &= ~(E1000_EECD_DI);
4691 if (eecd & E1000_EECD_DO) 3521 if (eecd & E1000_EECD_DO)
4692 data |= 1; 3522 data |= 1;
4693 3523
4694 e1000_lower_ee_clk(hw, &eecd); 3524 e1000_lower_ee_clk(hw, &eecd);
4695 } 3525 }
4696 3526
4697 return data; 3527 return data;
4698} 3528}
4699 3529
4700/****************************************************************************** 3530/**
4701 * Prepares EEPROM for access 3531 * e1000_acquire_eeprom - Prepares EEPROM for access
4702 * 3532 * @hw: Struct containing variables accessed by shared code
4703 * hw - Struct containing variables accessed by shared code
4704 * 3533 *
4705 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 3534 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4706 * function should be called before issuing a command to the EEPROM. 3535 * function should be called before issuing a command to the EEPROM.
4707 *****************************************************************************/ 3536 */
4708static s32 e1000_acquire_eeprom(struct e1000_hw *hw) 3537static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
4709{ 3538{
4710 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3539 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4711 u32 eecd, i=0; 3540 u32 eecd, i = 0;
4712 3541
4713 DEBUGFUNC("e1000_acquire_eeprom"); 3542 DEBUGFUNC("e1000_acquire_eeprom");
4714 3543
4715 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 3544 eecd = er32(EECD);
4716 return -E1000_ERR_SWFW_SYNC; 3545
4717 eecd = er32(EECD); 3546 /* Request EEPROM Access */
4718 3547 if (hw->mac_type > e1000_82544) {
4719 if (hw->mac_type != e1000_82573) { 3548 eecd |= E1000_EECD_REQ;
4720 /* Request EEPROM Access */ 3549 ew32(EECD, eecd);
4721 if (hw->mac_type > e1000_82544) { 3550 eecd = er32(EECD);
4722 eecd |= E1000_EECD_REQ; 3551 while ((!(eecd & E1000_EECD_GNT)) &&
4723 ew32(EECD, eecd); 3552 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4724 eecd = er32(EECD); 3553 i++;
4725 while ((!(eecd & E1000_EECD_GNT)) && 3554 udelay(5);
4726 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3555 eecd = er32(EECD);
4727 i++; 3556 }
4728 udelay(5); 3557 if (!(eecd & E1000_EECD_GNT)) {
4729 eecd = er32(EECD); 3558 eecd &= ~E1000_EECD_REQ;
4730 } 3559 ew32(EECD, eecd);
4731 if (!(eecd & E1000_EECD_GNT)) { 3560 DEBUGOUT("Could not acquire EEPROM grant\n");
4732 eecd &= ~E1000_EECD_REQ; 3561 return -E1000_ERR_EEPROM;
4733 ew32(EECD, eecd); 3562 }
4734 DEBUGOUT("Could not acquire EEPROM grant\n"); 3563 }
4735 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 3564
4736 return -E1000_ERR_EEPROM; 3565 /* Setup EEPROM for Read/Write */
4737 } 3566
4738 } 3567 if (eeprom->type == e1000_eeprom_microwire) {
4739 } 3568 /* Clear SK and DI */
4740 3569 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4741 /* Setup EEPROM for Read/Write */ 3570 ew32(EECD, eecd);
4742 3571
4743 if (eeprom->type == e1000_eeprom_microwire) { 3572 /* Set CS */
4744 /* Clear SK and DI */ 3573 eecd |= E1000_EECD_CS;
4745 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 3574 ew32(EECD, eecd);
4746 ew32(EECD, eecd); 3575 } else if (eeprom->type == e1000_eeprom_spi) {
4747 3576 /* Clear SK and CS */
4748 /* Set CS */ 3577 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4749 eecd |= E1000_EECD_CS; 3578 ew32(EECD, eecd);
4750 ew32(EECD, eecd); 3579 udelay(1);
4751 } else if (eeprom->type == e1000_eeprom_spi) { 3580 }
4752 /* Clear SK and CS */ 3581
4753 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3582 return E1000_SUCCESS;
4754 ew32(EECD, eecd);
4755 udelay(1);
4756 }
4757
4758 return E1000_SUCCESS;
4759} 3583}
4760 3584
4761/****************************************************************************** 3585/**
4762 * Returns EEPROM to a "standby" state 3586 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
4763 * 3587 * @hw: Struct containing variables accessed by shared code
4764 * hw - Struct containing variables accessed by shared code 3588 */
4765 *****************************************************************************/
4766static void e1000_standby_eeprom(struct e1000_hw *hw) 3589static void e1000_standby_eeprom(struct e1000_hw *hw)
4767{ 3590{
4768 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3591 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4769 u32 eecd; 3592 u32 eecd;
4770 3593
4771 eecd = er32(EECD); 3594 eecd = er32(EECD);
4772 3595
4773 if (eeprom->type == e1000_eeprom_microwire) { 3596 if (eeprom->type == e1000_eeprom_microwire) {
4774 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3597 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4775 ew32(EECD, eecd); 3598 ew32(EECD, eecd);
4776 E1000_WRITE_FLUSH(); 3599 E1000_WRITE_FLUSH();
4777 udelay(eeprom->delay_usec); 3600 udelay(eeprom->delay_usec);
4778 3601
4779 /* Clock high */ 3602 /* Clock high */
4780 eecd |= E1000_EECD_SK; 3603 eecd |= E1000_EECD_SK;
4781 ew32(EECD, eecd); 3604 ew32(EECD, eecd);
4782 E1000_WRITE_FLUSH(); 3605 E1000_WRITE_FLUSH();
4783 udelay(eeprom->delay_usec); 3606 udelay(eeprom->delay_usec);
4784 3607
4785 /* Select EEPROM */ 3608 /* Select EEPROM */
4786 eecd |= E1000_EECD_CS; 3609 eecd |= E1000_EECD_CS;
4787 ew32(EECD, eecd); 3610 ew32(EECD, eecd);
4788 E1000_WRITE_FLUSH(); 3611 E1000_WRITE_FLUSH();
4789 udelay(eeprom->delay_usec); 3612 udelay(eeprom->delay_usec);
4790 3613
4791 /* Clock low */ 3614 /* Clock low */
4792 eecd &= ~E1000_EECD_SK; 3615 eecd &= ~E1000_EECD_SK;
4793 ew32(EECD, eecd); 3616 ew32(EECD, eecd);
4794 E1000_WRITE_FLUSH(); 3617 E1000_WRITE_FLUSH();
4795 udelay(eeprom->delay_usec); 3618 udelay(eeprom->delay_usec);
4796 } else if (eeprom->type == e1000_eeprom_spi) { 3619 } else if (eeprom->type == e1000_eeprom_spi) {
4797 /* Toggle CS to flush commands */ 3620 /* Toggle CS to flush commands */
4798 eecd |= E1000_EECD_CS; 3621 eecd |= E1000_EECD_CS;
4799 ew32(EECD, eecd); 3622 ew32(EECD, eecd);
4800 E1000_WRITE_FLUSH(); 3623 E1000_WRITE_FLUSH();
4801 udelay(eeprom->delay_usec); 3624 udelay(eeprom->delay_usec);
4802 eecd &= ~E1000_EECD_CS; 3625 eecd &= ~E1000_EECD_CS;
4803 ew32(EECD, eecd); 3626 ew32(EECD, eecd);
4804 E1000_WRITE_FLUSH(); 3627 E1000_WRITE_FLUSH();
4805 udelay(eeprom->delay_usec); 3628 udelay(eeprom->delay_usec);
4806 } 3629 }
4807} 3630}
4808 3631
4809/****************************************************************************** 3632/**
4810 * Terminates a command by inverting the EEPROM's chip select pin 3633 * e1000_release_eeprom - drop chip select
3634 * @hw: Struct containing variables accessed by shared code
4811 * 3635 *
4812 * hw - Struct containing variables accessed by shared code 3636 * Terminates a command by inverting the EEPROM's chip select pin
4813 *****************************************************************************/ 3637 */
4814static void e1000_release_eeprom(struct e1000_hw *hw) 3638static void e1000_release_eeprom(struct e1000_hw *hw)
4815{ 3639{
4816 u32 eecd; 3640 u32 eecd;
4817
4818 DEBUGFUNC("e1000_release_eeprom");
4819 3641
4820 eecd = er32(EECD); 3642 DEBUGFUNC("e1000_release_eeprom");
4821 3643
4822 if (hw->eeprom.type == e1000_eeprom_spi) { 3644 eecd = er32(EECD);
4823 eecd |= E1000_EECD_CS; /* Pull CS high */
4824 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4825 3645
4826 ew32(EECD, eecd); 3646 if (hw->eeprom.type == e1000_eeprom_spi) {
3647 eecd |= E1000_EECD_CS; /* Pull CS high */
3648 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4827 3649
4828 udelay(hw->eeprom.delay_usec); 3650 ew32(EECD, eecd);
4829 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4830 /* cleanup eeprom */
4831 3651
4832 /* CS on Microwire is active-high */ 3652 udelay(hw->eeprom.delay_usec);
4833 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3653 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3654 /* cleanup eeprom */
4834 3655
4835 ew32(EECD, eecd); 3656 /* CS on Microwire is active-high */
3657 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4836 3658
4837 /* Rising edge of clock */ 3659 ew32(EECD, eecd);
4838 eecd |= E1000_EECD_SK;
4839 ew32(EECD, eecd);
4840 E1000_WRITE_FLUSH();
4841 udelay(hw->eeprom.delay_usec);
4842 3660
4843 /* Falling edge of clock */ 3661 /* Rising edge of clock */
4844 eecd &= ~E1000_EECD_SK; 3662 eecd |= E1000_EECD_SK;
4845 ew32(EECD, eecd); 3663 ew32(EECD, eecd);
4846 E1000_WRITE_FLUSH(); 3664 E1000_WRITE_FLUSH();
4847 udelay(hw->eeprom.delay_usec); 3665 udelay(hw->eeprom.delay_usec);
4848 }
4849 3666
4850 /* Stop requesting EEPROM access */ 3667 /* Falling edge of clock */
4851 if (hw->mac_type > e1000_82544) { 3668 eecd &= ~E1000_EECD_SK;
4852 eecd &= ~E1000_EECD_REQ; 3669 ew32(EECD, eecd);
4853 ew32(EECD, eecd); 3670 E1000_WRITE_FLUSH();
4854 } 3671 udelay(hw->eeprom.delay_usec);
3672 }
4855 3673
4856 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 3674 /* Stop requesting EEPROM access */
3675 if (hw->mac_type > e1000_82544) {
3676 eecd &= ~E1000_EECD_REQ;
3677 ew32(EECD, eecd);
3678 }
4857} 3679}
4858 3680
4859/****************************************************************************** 3681/**
4860 * Reads a 16 bit word from the EEPROM. 3682 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
4861 * 3683 * @hw: Struct containing variables accessed by shared code
4862 * hw - Struct containing variables accessed by shared code 3684 */
4863 *****************************************************************************/
4864static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) 3685static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4865{ 3686{
4866 u16 retry_count = 0; 3687 u16 retry_count = 0;
4867 u8 spi_stat_reg; 3688 u8 spi_stat_reg;
4868
4869 DEBUGFUNC("e1000_spi_eeprom_ready");
4870
4871 /* Read "Status Register" repeatedly until the LSB is cleared. The
4872 * EEPROM will signal that the command has been completed by clearing
4873 * bit 0 of the internal status register. If it's not cleared within
4874 * 5 milliseconds, then error out.
4875 */
4876 retry_count = 0;
4877 do {
4878 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4879 hw->eeprom.opcode_bits);
4880 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
4881 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4882 break;
4883
4884 udelay(5);
4885 retry_count += 5;
4886
4887 e1000_standby_eeprom(hw);
4888 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4889
4890 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4891 * only 0-5mSec on 5V devices)
4892 */
4893 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4894 DEBUGOUT("SPI EEPROM Status error\n");
4895 return -E1000_ERR_EEPROM;
4896 }
4897
4898 return E1000_SUCCESS;
4899}
4900
4901/******************************************************************************
4902 * Reads a 16 bit word from the EEPROM.
4903 *
4904 * hw - Struct containing variables accessed by shared code
4905 * offset - offset of word in the EEPROM to read
4906 * data - word read from the EEPROM
4907 * words - number of words to read
4908 *****************************************************************************/
4909s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4910{
4911 s32 ret;
4912 spin_lock(&e1000_eeprom_lock);
4913 ret = e1000_do_read_eeprom(hw, offset, words, data);
4914 spin_unlock(&e1000_eeprom_lock);
4915 return ret;
4916}
4917
4918static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4919{
4920 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4921 u32 i = 0;
4922
4923 DEBUGFUNC("e1000_read_eeprom");
4924
4925 /* If eeprom is not yet detected, do so now */
4926 if (eeprom->word_size == 0)
4927 e1000_init_eeprom_params(hw);
4928
4929 /* A check for invalid values: offset too large, too many words, and not
4930 * enough words.
4931 */
4932 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4933 (words == 0)) {
4934 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4935 return -E1000_ERR_EEPROM;
4936 }
4937
4938 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4939 * directly. In this case, we need to acquire the EEPROM so that
4940 * FW or other port software does not interrupt.
4941 */
4942 if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
4943 /* Prepare the EEPROM for bit-bang reading */
4944 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4945 return -E1000_ERR_EEPROM;
4946 }
4947
4948 /* Eerd register EEPROM access requires no eeprom aquire/release */
4949 if (eeprom->use_eerd)
4950 return e1000_read_eeprom_eerd(hw, offset, words, data);
4951
4952 /* ICH EEPROM access is done via the ICH flash controller */
4953 if (eeprom->type == e1000_eeprom_ich8)
4954 return e1000_read_eeprom_ich8(hw, offset, words, data);
4955
4956 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
4957 * acquired the EEPROM at this point, so any returns should relase it */
4958 if (eeprom->type == e1000_eeprom_spi) {
4959 u16 word_in;
4960 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
4961
4962 if (e1000_spi_eeprom_ready(hw)) {
4963 e1000_release_eeprom(hw);
4964 return -E1000_ERR_EEPROM;
4965 }
4966
4967 e1000_standby_eeprom(hw);
4968
4969 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4970 if ((eeprom->address_bits == 8) && (offset >= 128))
4971 read_opcode |= EEPROM_A8_OPCODE_SPI;
4972
4973 /* Send the READ command (opcode + addr) */
4974 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4975 e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
4976
4977 /* Read the data. The address of the eeprom internally increments with
4978 * each byte (spi) being read, saving on the overhead of eeprom setup
4979 * and tear-down. The address counter will roll over if reading beyond
4980 * the size of the eeprom, thus allowing the entire memory to be read
4981 * starting from any offset. */
4982 for (i = 0; i < words; i++) {
4983 word_in = e1000_shift_in_ee_bits(hw, 16);
4984 data[i] = (word_in >> 8) | (word_in << 8);
4985 }
4986 } else if (eeprom->type == e1000_eeprom_microwire) {
4987 for (i = 0; i < words; i++) {
4988 /* Send the READ command (opcode + addr) */
4989 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4990 eeprom->opcode_bits);
4991 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
4992 eeprom->address_bits);
4993
4994 /* Read the data. For microwire, each word requires the overhead
4995 * of eeprom setup and tear-down. */
4996 data[i] = e1000_shift_in_ee_bits(hw, 16);
4997 e1000_standby_eeprom(hw);
4998 }
4999 }
5000
5001 /* End this read operation */
5002 e1000_release_eeprom(hw);
5003
5004 return E1000_SUCCESS;
5005}
5006 3689
5007/****************************************************************************** 3690 DEBUGFUNC("e1000_spi_eeprom_ready");
5008 * Reads a 16 bit word from the EEPROM using the EERD register.
5009 *
5010 * hw - Struct containing variables accessed by shared code
5011 * offset - offset of word in the EEPROM to read
5012 * data - word read from the EEPROM
5013 * words - number of words to read
5014 *****************************************************************************/
5015static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
5016 u16 *data)
5017{
5018 u32 i, eerd = 0;
5019 s32 error = 0;
5020 3691
5021 for (i = 0; i < words; i++) { 3692 /* Read "Status Register" repeatedly until the LSB is cleared. The
5022 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 3693 * EEPROM will signal that the command has been completed by clearing
5023 E1000_EEPROM_RW_REG_START; 3694 * bit 0 of the internal status register. If it's not cleared within
3695 * 5 milliseconds, then error out.
3696 */
3697 retry_count = 0;
3698 do {
3699 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3700 hw->eeprom.opcode_bits);
3701 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3702 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3703 break;
5024 3704
5025 ew32(EERD, eerd); 3705 udelay(5);
5026 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 3706 retry_count += 5;
5027 3707
5028 if (error) { 3708 e1000_standby_eeprom(hw);
5029 break; 3709 } while (retry_count < EEPROM_MAX_RETRY_SPI);
5030 }
5031 data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
5032 3710
5033 } 3711 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3712 * only 0-5mSec on 5V devices)
3713 */
3714 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3715 DEBUGOUT("SPI EEPROM Status error\n");
3716 return -E1000_ERR_EEPROM;
3717 }
5034 3718
5035 return error; 3719 return E1000_SUCCESS;
5036} 3720}
5037 3721
5038/****************************************************************************** 3722/**
5039 * Writes a 16 bit word from the EEPROM using the EEWR register. 3723 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
5040 * 3724 * @hw: Struct containing variables accessed by shared code
5041 * hw - Struct containing variables accessed by shared code 3725 * @offset: offset of word in the EEPROM to read
5042 * offset - offset of word in the EEPROM to read 3726 * @data: word read from the EEPROM
5043 * data - word read from the EEPROM 3727 * @words: number of words to read
5044 * words - number of words to read 3728 */
5045 *****************************************************************************/ 3729s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5046static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
5047 u16 *data)
5048{ 3730{
5049 u32 register_value = 0; 3731 s32 ret;
5050 u32 i = 0; 3732 spin_lock(&e1000_eeprom_lock);
5051 s32 error = 0; 3733 ret = e1000_do_read_eeprom(hw, offset, words, data);
5052 3734 spin_unlock(&e1000_eeprom_lock);
5053 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 3735 return ret;
5054 return -E1000_ERR_SWFW_SYNC;
5055
5056 for (i = 0; i < words; i++) {
5057 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5058 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5059 E1000_EEPROM_RW_REG_START;
5060
5061 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5062 if (error) {
5063 break;
5064 }
5065
5066 ew32(EEWR, register_value);
5067
5068 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5069
5070 if (error) {
5071 break;
5072 }
5073 }
5074
5075 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5076 return error;
5077} 3736}
5078 3737
5079/****************************************************************************** 3738static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
5080 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 3739 u16 *data)
5081 *
5082 * hw - Struct containing variables accessed by shared code
5083 *****************************************************************************/
5084static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5085{ 3740{
5086 u32 attempts = 100000; 3741 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5087 u32 i, reg = 0; 3742 u32 i = 0;
5088 s32 done = E1000_ERR_EEPROM;
5089
5090 for (i = 0; i < attempts; i++) {
5091 if (eerd == E1000_EEPROM_POLL_READ)
5092 reg = er32(EERD);
5093 else
5094 reg = er32(EEWR);
5095
5096 if (reg & E1000_EEPROM_RW_REG_DONE) {
5097 done = E1000_SUCCESS;
5098 break;
5099 }
5100 udelay(5);
5101 }
5102
5103 return done;
5104}
5105 3743
5106/*************************************************************************** 3744 DEBUGFUNC("e1000_read_eeprom");
5107* Description: Determines if the onboard NVM is FLASH or EEPROM.
5108*
5109* hw - Struct containing variables accessed by shared code
5110****************************************************************************/
5111static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5112{
5113 u32 eecd = 0;
5114 3745
5115 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 3746 /* If eeprom is not yet detected, do so now */
3747 if (eeprom->word_size == 0)
3748 e1000_init_eeprom_params(hw);
3749
3750 /* A check for invalid values: offset too large, too many words, and not
3751 * enough words.
3752 */
3753 if ((offset >= eeprom->word_size)
3754 || (words > eeprom->word_size - offset) || (words == 0)) {
3755 DEBUGOUT2
3756 ("\"words\" parameter out of bounds. Words = %d, size = %d\n",
3757 offset, eeprom->word_size);
3758 return -E1000_ERR_EEPROM;
3759 }
5116 3760
5117 if (hw->mac_type == e1000_ich8lan) 3761 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
5118 return false; 3762 * directly. In this case, we need to acquire the EEPROM so that
3763 * FW or other port software does not interrupt.
3764 */
3765 /* Prepare the EEPROM for bit-bang reading */
3766 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3767 return -E1000_ERR_EEPROM;
3768
3769 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3770 * acquired the EEPROM at this point, so any returns should release it */
3771 if (eeprom->type == e1000_eeprom_spi) {
3772 u16 word_in;
3773 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3774
3775 if (e1000_spi_eeprom_ready(hw)) {
3776 e1000_release_eeprom(hw);
3777 return -E1000_ERR_EEPROM;
3778 }
5119 3779
5120 if (hw->mac_type == e1000_82573) { 3780 e1000_standby_eeprom(hw);
5121 eecd = er32(EECD); 3781
3782 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3783 if ((eeprom->address_bits == 8) && (offset >= 128))
3784 read_opcode |= EEPROM_A8_OPCODE_SPI;
3785
3786 /* Send the READ command (opcode + addr) */
3787 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3788 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3789 eeprom->address_bits);
3790
3791 /* Read the data. The address of the eeprom internally increments with
3792 * each byte (spi) being read, saving on the overhead of eeprom setup
3793 * and tear-down. The address counter will roll over if reading beyond
3794 * the size of the eeprom, thus allowing the entire memory to be read
3795 * starting from any offset. */
3796 for (i = 0; i < words; i++) {
3797 word_in = e1000_shift_in_ee_bits(hw, 16);
3798 data[i] = (word_in >> 8) | (word_in << 8);
3799 }
3800 } else if (eeprom->type == e1000_eeprom_microwire) {
3801 for (i = 0; i < words; i++) {
3802 /* Send the READ command (opcode + addr) */
3803 e1000_shift_out_ee_bits(hw,
3804 EEPROM_READ_OPCODE_MICROWIRE,
3805 eeprom->opcode_bits);
3806 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3807 eeprom->address_bits);
3808
3809 /* Read the data. For microwire, each word requires the overhead
3810 * of eeprom setup and tear-down. */
3811 data[i] = e1000_shift_in_ee_bits(hw, 16);
3812 e1000_standby_eeprom(hw);
3813 }
3814 }
5122 3815
5123 /* Isolate bits 15 & 16 */ 3816 /* End this read operation */
5124 eecd = ((eecd >> 15) & 0x03); 3817 e1000_release_eeprom(hw);
5125 3818
5126 /* If both bits are set, device is Flash type */ 3819 return E1000_SUCCESS;
5127 if (eecd == 0x03) {
5128 return false;
5129 }
5130 }
5131 return true;
5132} 3820}
5133 3821
5134/****************************************************************************** 3822/**
5135 * Verifies that the EEPROM has a valid checksum 3823 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
5136 * 3824 * @hw: Struct containing variables accessed by shared code
5137 * hw - Struct containing variables accessed by shared code
5138 * 3825 *
5139 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 3826 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5140 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 3827 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5141 * valid. 3828 * valid.
5142 *****************************************************************************/ 3829 */
5143s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) 3830s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5144{ 3831{
5145 u16 checksum = 0; 3832 u16 checksum = 0;
5146 u16 i, eeprom_data; 3833 u16 i, eeprom_data;
5147 3834
5148 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3835 DEBUGFUNC("e1000_validate_eeprom_checksum");
5149 3836
5150 if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) { 3837 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5151 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 3838 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5152 * 10h-12h. Checksum may need to be fixed. */ 3839 DEBUGOUT("EEPROM Read Error\n");
5153 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); 3840 return -E1000_ERR_EEPROM;
5154 if ((eeprom_data & 0x10) == 0) { 3841 }
5155 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum 3842 checksum += eeprom_data;
5156 * has already been fixed. If the checksum is still wrong and this 3843 }
5157 * bit is a 1, we need to return bad checksum. Otherwise, we need 3844
5158 * to set this bit to a 1 and update the checksum. */ 3845 if (checksum == (u16) EEPROM_SUM)
5159 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); 3846 return E1000_SUCCESS;
5160 if ((eeprom_data & 0x8000) == 0) { 3847 else {
5161 eeprom_data |= 0x8000; 3848 DEBUGOUT("EEPROM Checksum Invalid\n");
5162 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); 3849 return -E1000_ERR_EEPROM;
5163 e1000_update_eeprom_checksum(hw); 3850 }
5164 }
5165 }
5166 }
5167
5168 if (hw->mac_type == e1000_ich8lan) {
5169 /* Drivers must allocate the shadow ram structure for the
5170 * EEPROM checksum to be updated. Otherwise, this bit as well
5171 * as the checksum must both be set correctly for this
5172 * validation to pass.
5173 */
5174 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5175 if ((eeprom_data & 0x40) == 0) {
5176 eeprom_data |= 0x40;
5177 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5178 e1000_update_eeprom_checksum(hw);
5179 }
5180 }
5181
5182 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5183 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5184 DEBUGOUT("EEPROM Read Error\n");
5185 return -E1000_ERR_EEPROM;
5186 }
5187 checksum += eeprom_data;
5188 }
5189
5190 if (checksum == (u16)EEPROM_SUM)
5191 return E1000_SUCCESS;
5192 else {
5193 DEBUGOUT("EEPROM Checksum Invalid\n");
5194 return -E1000_ERR_EEPROM;
5195 }
5196} 3851}
5197 3852
5198/****************************************************************************** 3853/**
5199 * Calculates the EEPROM checksum and writes it to the EEPROM 3854 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
5200 * 3855 * @hw: Struct containing variables accessed by shared code
5201 * hw - Struct containing variables accessed by shared code
5202 * 3856 *
5203 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 3857 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5204 * Writes the difference to word offset 63 of the EEPROM. 3858 * Writes the difference to word offset 63 of the EEPROM.
5205 *****************************************************************************/ 3859 */
5206s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 3860s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5207{ 3861{
5208 u32 ctrl_ext; 3862 u16 checksum = 0;
5209 u16 checksum = 0; 3863 u16 i, eeprom_data;
5210 u16 i, eeprom_data; 3864
5211 3865 DEBUGFUNC("e1000_update_eeprom_checksum");
5212 DEBUGFUNC("e1000_update_eeprom_checksum"); 3866
5213 3867 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5214 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 3868 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5215 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3869 DEBUGOUT("EEPROM Read Error\n");
5216 DEBUGOUT("EEPROM Read Error\n"); 3870 return -E1000_ERR_EEPROM;
5217 return -E1000_ERR_EEPROM; 3871 }
5218 } 3872 checksum += eeprom_data;
5219 checksum += eeprom_data; 3873 }
5220 } 3874 checksum = (u16) EEPROM_SUM - checksum;
5221 checksum = (u16)EEPROM_SUM - checksum; 3875 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5222 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 3876 DEBUGOUT("EEPROM Write Error\n");
5223 DEBUGOUT("EEPROM Write Error\n"); 3877 return -E1000_ERR_EEPROM;
5224 return -E1000_ERR_EEPROM; 3878 }
5225 } else if (hw->eeprom.type == e1000_eeprom_flash) { 3879 return E1000_SUCCESS;
5226 e1000_commit_shadow_ram(hw);
5227 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5228 e1000_commit_shadow_ram(hw);
5229 /* Reload the EEPROM, or else modifications will not appear
5230 * until after next adapter reset. */
5231 ctrl_ext = er32(CTRL_EXT);
5232 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5233 ew32(CTRL_EXT, ctrl_ext);
5234 msleep(10);
5235 }
5236 return E1000_SUCCESS;
5237} 3880}
5238 3881
5239/****************************************************************************** 3882/**
5240 * Parent function for writing words to the different EEPROM types. 3883 * e1000_write_eeprom - write words to the different EEPROM types.
5241 * 3884 * @hw: Struct containing variables accessed by shared code
5242 * hw - Struct containing variables accessed by shared code 3885 * @offset: offset within the EEPROM to be written to
5243 * offset - offset within the EEPROM to be written to 3886 * @words: number of words to write
5244 * words - number of words to write 3887 * @data: 16 bit word to be written to the EEPROM
5245 * data - 16 bit word to be written to the EEPROM
5246 * 3888 *
5247 * If e1000_update_eeprom_checksum is not called after this function, the 3889 * If e1000_update_eeprom_checksum is not called after this function, the
5248 * EEPROM will most likely contain an invalid checksum. 3890 * EEPROM will most likely contain an invalid checksum.
5249 *****************************************************************************/ 3891 */
5250s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3892s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5251{ 3893{
5252 s32 ret; 3894 s32 ret;
5253 spin_lock(&e1000_eeprom_lock); 3895 spin_lock(&e1000_eeprom_lock);
5254 ret = e1000_do_write_eeprom(hw, offset, words, data); 3896 ret = e1000_do_write_eeprom(hw, offset, words, data);
5255 spin_unlock(&e1000_eeprom_lock); 3897 spin_unlock(&e1000_eeprom_lock);
5256 return ret; 3898 return ret;
5257} 3899}
5258 3900
5259 3901static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
5260static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3902 u16 *data)
5261{ 3903{
5262 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3904 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5263 s32 status = 0; 3905 s32 status = 0;
5264 3906
5265 DEBUGFUNC("e1000_write_eeprom"); 3907 DEBUGFUNC("e1000_write_eeprom");
5266 3908
5267 /* If eeprom is not yet detected, do so now */ 3909 /* If eeprom is not yet detected, do so now */
5268 if (eeprom->word_size == 0) 3910 if (eeprom->word_size == 0)
5269 e1000_init_eeprom_params(hw); 3911 e1000_init_eeprom_params(hw);
5270 3912
5271 /* A check for invalid values: offset too large, too many words, and not 3913 /* A check for invalid values: offset too large, too many words, and not
5272 * enough words. 3914 * enough words.
5273 */ 3915 */
5274 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 3916 if ((offset >= eeprom->word_size)
5275 (words == 0)) { 3917 || (words > eeprom->word_size - offset) || (words == 0)) {
5276 DEBUGOUT("\"words\" parameter out of bounds\n"); 3918 DEBUGOUT("\"words\" parameter out of bounds\n");
5277 return -E1000_ERR_EEPROM; 3919 return -E1000_ERR_EEPROM;
5278 } 3920 }
5279 3921
5280 /* 82573 writes only through eewr */ 3922 /* Prepare the EEPROM for writing */
5281 if (eeprom->use_eewr) 3923 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5282 return e1000_write_eeprom_eewr(hw, offset, words, data); 3924 return -E1000_ERR_EEPROM;
5283 3925
5284 if (eeprom->type == e1000_eeprom_ich8) 3926 if (eeprom->type == e1000_eeprom_microwire) {
5285 return e1000_write_eeprom_ich8(hw, offset, words, data); 3927 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5286 3928 } else {
5287 /* Prepare the EEPROM for writing */ 3929 status = e1000_write_eeprom_spi(hw, offset, words, data);
5288 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3930 msleep(10);
5289 return -E1000_ERR_EEPROM; 3931 }
5290 3932
5291 if (eeprom->type == e1000_eeprom_microwire) { 3933 /* Done with writing */
5292 status = e1000_write_eeprom_microwire(hw, offset, words, data); 3934 e1000_release_eeprom(hw);
5293 } else { 3935
5294 status = e1000_write_eeprom_spi(hw, offset, words, data); 3936 return status;
5295 msleep(10);
5296 }
5297
5298 /* Done with writing */
5299 e1000_release_eeprom(hw);
5300
5301 return status;
5302} 3937}
5303 3938
5304/****************************************************************************** 3939/**
5305 * Writes a 16 bit word to a given offset in an SPI EEPROM. 3940 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
5306 * 3941 * @hw: Struct containing variables accessed by shared code
5307 * hw - Struct containing variables accessed by shared code 3942 * @offset: offset within the EEPROM to be written to
5308 * offset - offset within the EEPROM to be written to 3943 * @words: number of words to write
5309 * words - number of words to write 3944 * @data: pointer to array of 8 bit words to be written to the EEPROM
5310 * data - pointer to array of 8 bit words to be written to the EEPROM 3945 */
5311 *
5312 *****************************************************************************/
5313static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, 3946static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
5314 u16 *data) 3947 u16 *data)
5315{ 3948{
5316 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3949 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5317 u16 widx = 0; 3950 u16 widx = 0;
5318 3951
5319 DEBUGFUNC("e1000_write_eeprom_spi"); 3952 DEBUGFUNC("e1000_write_eeprom_spi");
5320 3953
5321 while (widx < words) { 3954 while (widx < words) {
5322 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 3955 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
5323 3956
5324 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 3957 if (e1000_spi_eeprom_ready(hw))
3958 return -E1000_ERR_EEPROM;
5325 3959
5326 e1000_standby_eeprom(hw); 3960 e1000_standby_eeprom(hw);
5327 3961
5328 /* Send the WRITE ENABLE command (8 bit opcode ) */ 3962 /* Send the WRITE ENABLE command (8 bit opcode ) */
5329 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 3963 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5330 eeprom->opcode_bits); 3964 eeprom->opcode_bits);
5331 3965
5332 e1000_standby_eeprom(hw); 3966 e1000_standby_eeprom(hw);
5333 3967
5334 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 3968 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5335 if ((eeprom->address_bits == 8) && (offset >= 128)) 3969 if ((eeprom->address_bits == 8) && (offset >= 128))
5336 write_opcode |= EEPROM_A8_OPCODE_SPI; 3970 write_opcode |= EEPROM_A8_OPCODE_SPI;
5337 3971
5338 /* Send the Write command (8-bit opcode + addr) */ 3972 /* Send the Write command (8-bit opcode + addr) */
5339 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 3973 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5340 3974
5341 e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2), 3975 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
5342 eeprom->address_bits); 3976 eeprom->address_bits);
5343 3977
5344 /* Send the data */ 3978 /* Send the data */
5345 3979
5346 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 3980 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5347 while (widx < words) { 3981 while (widx < words) {
5348 u16 word_out = data[widx]; 3982 u16 word_out = data[widx];
5349 word_out = (word_out >> 8) | (word_out << 8); 3983 word_out = (word_out >> 8) | (word_out << 8);
5350 e1000_shift_out_ee_bits(hw, word_out, 16); 3984 e1000_shift_out_ee_bits(hw, word_out, 16);
5351 widx++; 3985 widx++;
5352 3986
5353 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE 3987 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5354 * operation, while the smaller eeproms are capable of an 8-byte 3988 * operation, while the smaller eeproms are capable of an 8-byte
5355 * PAGE WRITE operation. Break the inner loop to pass new address 3989 * PAGE WRITE operation. Break the inner loop to pass new address
5356 */ 3990 */
5357 if ((((offset + widx)*2) % eeprom->page_size) == 0) { 3991 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
5358 e1000_standby_eeprom(hw); 3992 e1000_standby_eeprom(hw);
5359 break; 3993 break;
5360 } 3994 }
5361 } 3995 }
5362 } 3996 }
5363 3997
5364 return E1000_SUCCESS; 3998 return E1000_SUCCESS;
5365} 3999}
5366 4000
5367/****************************************************************************** 4001/**
5368 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 4002 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
5369 * 4003 * @hw: Struct containing variables accessed by shared code
5370 * hw - Struct containing variables accessed by shared code 4004 * @offset: offset within the EEPROM to be written to
5371 * offset - offset within the EEPROM to be written to 4005 * @words: number of words to write
5372 * words - number of words to write 4006 * @data: pointer to array of 8 bit words to be written to the EEPROM
5373 * data - pointer to array of 16 bit words to be written to the EEPROM 4007 */
5374 *
5375 *****************************************************************************/
5376static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 4008static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
5377 u16 words, u16 *data) 4009 u16 words, u16 *data)
5378{ 4010{
5379 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4011 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5380 u32 eecd; 4012 u32 eecd;
5381 u16 words_written = 0; 4013 u16 words_written = 0;
5382 u16 i = 0; 4014 u16 i = 0;
5383
5384 DEBUGFUNC("e1000_write_eeprom_microwire");
5385
5386 /* Send the write enable command to the EEPROM (3-bit opcode plus
5387 * 6/8-bit dummy address beginning with 11). It's less work to include
5388 * the 11 of the dummy address as part of the opcode than it is to shift
5389 * it over the correct number of bits for the address. This puts the
5390 * EEPROM into write/erase mode.
5391 */
5392 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5393 (u16)(eeprom->opcode_bits + 2));
5394
5395 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5396
5397 /* Prepare the EEPROM */
5398 e1000_standby_eeprom(hw);
5399
5400 while (words_written < words) {
5401 /* Send the Write command (3-bit opcode + addr) */
5402 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5403 eeprom->opcode_bits);
5404
5405 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
5406 eeprom->address_bits);
5407
5408 /* Send the data */
5409 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5410
5411 /* Toggle the CS line. This in effect tells the EEPROM to execute
5412 * the previous command.
5413 */
5414 e1000_standby_eeprom(hw);
5415
5416 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5417 * signal that the command has been completed by raising the DO signal.
5418 * If DO does not go high in 10 milliseconds, then error out.
5419 */
5420 for (i = 0; i < 200; i++) {
5421 eecd = er32(EECD);
5422 if (eecd & E1000_EECD_DO) break;
5423 udelay(50);
5424 }
5425 if (i == 200) {
5426 DEBUGOUT("EEPROM Write did not complete\n");
5427 return -E1000_ERR_EEPROM;
5428 }
5429
5430 /* Recover from write */
5431 e1000_standby_eeprom(hw);
5432
5433 words_written++;
5434 }
5435
5436 /* Send the write disable command to the EEPROM (3-bit opcode plus
5437 * 6/8-bit dummy address beginning with 10). It's less work to include
5438 * the 10 of the dummy address as part of the opcode than it is to shift
5439 * it over the correct number of bits for the address. This takes the
5440 * EEPROM out of write/erase mode.
5441 */
5442 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5443 (u16)(eeprom->opcode_bits + 2));
5444
5445 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5446
5447 return E1000_SUCCESS;
5448}
5449 4015
5450/****************************************************************************** 4016 DEBUGFUNC("e1000_write_eeprom_microwire");
5451 * Flushes the cached eeprom to NVM. This is done by saving the modified values 4017
5452 * in the eeprom cache and the non modified values in the currently active bank 4018 /* Send the write enable command to the EEPROM (3-bit opcode plus
5453 * to the new bank. 4019 * 6/8-bit dummy address beginning with 11). It's less work to include
5454 * 4020 * the 11 of the dummy address as part of the opcode than it is to shift
5455 * hw - Struct containing variables accessed by shared code 4021 * it over the correct number of bits for the address. This puts the
5456 * offset - offset of word in the EEPROM to read 4022 * EEPROM into write/erase mode.
5457 * data - word read from the EEPROM 4023 */
5458 * words - number of words to read 4024 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5459 *****************************************************************************/ 4025 (u16) (eeprom->opcode_bits + 2));
5460static s32 e1000_commit_shadow_ram(struct e1000_hw *hw) 4026
5461{ 4027 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
5462 u32 attempts = 100000; 4028
5463 u32 eecd = 0; 4029 /* Prepare the EEPROM */
5464 u32 flop = 0; 4030 e1000_standby_eeprom(hw);
5465 u32 i = 0; 4031
5466 s32 error = E1000_SUCCESS; 4032 while (words_written < words) {
5467 u32 old_bank_offset = 0; 4033 /* Send the Write command (3-bit opcode + addr) */
5468 u32 new_bank_offset = 0; 4034 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5469 u8 low_byte = 0; 4035 eeprom->opcode_bits);
5470 u8 high_byte = 0; 4036
5471 bool sector_write_failed = false; 4037 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
5472 4038 eeprom->address_bits);
5473 if (hw->mac_type == e1000_82573) { 4039
5474 /* The flop register will be used to determine if flash type is STM */ 4040 /* Send the data */
5475 flop = er32(FLOP); 4041 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5476 for (i=0; i < attempts; i++) { 4042
5477 eecd = er32(EECD); 4043 /* Toggle the CS line. This in effect tells the EEPROM to execute
5478 if ((eecd & E1000_EECD_FLUPD) == 0) { 4044 * the previous command.
5479 break; 4045 */
5480 } 4046 e1000_standby_eeprom(hw);
5481 udelay(5); 4047
5482 } 4048 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5483 4049 * signal that the command has been completed by raising the DO signal.
5484 if (i == attempts) { 4050 * If DO does not go high in 10 milliseconds, then error out.
5485 return -E1000_ERR_EEPROM; 4051 */
5486 } 4052 for (i = 0; i < 200; i++) {
5487 4053 eecd = er32(EECD);
5488 /* If STM opcode located in bits 15:8 of flop, reset firmware */ 4054 if (eecd & E1000_EECD_DO)
5489 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 4055 break;
5490 ew32(HICR, E1000_HICR_FW_RESET); 4056 udelay(50);
5491 } 4057 }
5492 4058 if (i == 200) {
5493 /* Perform the flash update */ 4059 DEBUGOUT("EEPROM Write did not complete\n");
5494 ew32(EECD, eecd | E1000_EECD_FLUPD); 4060 return -E1000_ERR_EEPROM;
5495 4061 }
5496 for (i=0; i < attempts; i++) { 4062
5497 eecd = er32(EECD); 4063 /* Recover from write */
5498 if ((eecd & E1000_EECD_FLUPD) == 0) { 4064 e1000_standby_eeprom(hw);
5499 break; 4065
5500 } 4066 words_written++;
5501 udelay(5); 4067 }
5502 } 4068
5503 4069 /* Send the write disable command to the EEPROM (3-bit opcode plus
5504 if (i == attempts) { 4070 * 6/8-bit dummy address beginning with 10). It's less work to include
5505 return -E1000_ERR_EEPROM; 4071 * the 10 of the dummy address as part of the opcode than it is to shift
5506 } 4072 * it over the correct number of bits for the address. This takes the
5507 } 4073 * EEPROM out of write/erase mode.
5508 4074 */
5509 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { 4075 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5510 /* We're writing to the opposite bank so if we're on bank 1, 4076 (u16) (eeprom->opcode_bits + 2));
5511 * write to bank 0 etc. We also need to erase the segment that 4077
5512 * is going to be written */ 4078 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
5513 if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { 4079
5514 new_bank_offset = hw->flash_bank_size * 2; 4080 return E1000_SUCCESS;
5515 old_bank_offset = 0;
5516 e1000_erase_ich8_4k_segment(hw, 1);
5517 } else {
5518 old_bank_offset = hw->flash_bank_size * 2;
5519 new_bank_offset = 0;
5520 e1000_erase_ich8_4k_segment(hw, 0);
5521 }
5522
5523 sector_write_failed = false;
5524 /* Loop for every byte in the shadow RAM,
5525 * which is in units of words. */
5526 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5527 /* Determine whether to write the value stored
5528 * in the other NVM bank or a modified value stored
5529 * in the shadow RAM */
5530 if (hw->eeprom_shadow_ram[i].modified) {
5531 low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
5532 udelay(100);
5533 error = e1000_verify_write_ich8_byte(hw,
5534 (i << 1) + new_bank_offset, low_byte);
5535
5536 if (error != E1000_SUCCESS)
5537 sector_write_failed = true;
5538 else {
5539 high_byte =
5540 (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5541 udelay(100);
5542 }
5543 } else {
5544 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5545 &low_byte);
5546 udelay(100);
5547 error = e1000_verify_write_ich8_byte(hw,
5548 (i << 1) + new_bank_offset, low_byte);
5549
5550 if (error != E1000_SUCCESS)
5551 sector_write_failed = true;
5552 else {
5553 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5554 &high_byte);
5555 udelay(100);
5556 }
5557 }
5558
5559 /* If the write of the low byte was successful, go ahead and
5560 * write the high byte while checking to make sure that if it
5561 * is the signature byte, then it is handled properly */
5562 if (!sector_write_failed) {
5563 /* If the word is 0x13, then make sure the signature bits
5564 * (15:14) are 11b until the commit has completed.
5565 * This will allow us to write 10b which indicates the
5566 * signature is valid. We want to do this after the write
5567 * has completed so that we don't mark the segment valid
5568 * while the write is still in progress */
5569 if (i == E1000_ICH_NVM_SIG_WORD)
5570 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5571
5572 error = e1000_verify_write_ich8_byte(hw,
5573 (i << 1) + new_bank_offset + 1, high_byte);
5574 if (error != E1000_SUCCESS)
5575 sector_write_failed = true;
5576
5577 } else {
5578 /* If the write failed then break from the loop and
5579 * return an error */
5580 break;
5581 }
5582 }
5583
5584 /* Don't bother writing the segment valid bits if sector
5585 * programming failed. */
5586 if (!sector_write_failed) {
5587 /* Finally validate the new segment by setting bit 15:14
5588 * to 10b in word 0x13 , this can be done without an
5589 * erase as well since these bits are 11 to start with
5590 * and we need to change bit 14 to 0b */
5591 e1000_read_ich8_byte(hw,
5592 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5593 &high_byte);
5594 high_byte &= 0xBF;
5595 error = e1000_verify_write_ich8_byte(hw,
5596 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5597 /* And invalidate the previously valid segment by setting
5598 * its signature word (0x13) high_byte to 0b. This can be
5599 * done without an erase because flash erase sets all bits
5600 * to 1's. We can write 1's to 0's without an erase */
5601 if (error == E1000_SUCCESS) {
5602 error = e1000_verify_write_ich8_byte(hw,
5603 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5604 }
5605
5606 /* Clear the now not used entry in the cache */
5607 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5608 hw->eeprom_shadow_ram[i].modified = false;
5609 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5610 }
5611 }
5612 }
5613
5614 return error;
5615} 4081}
5616 4082
5617/****************************************************************************** 4083/**
4084 * e1000_read_mac_addr - read the adapters MAC from eeprom
4085 * @hw: Struct containing variables accessed by shared code
4086 *
5618 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4087 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5619 * second function of dual function devices 4088 * second function of dual function devices
5620 * 4089 */
5621 * hw - Struct containing variables accessed by shared code
5622 *****************************************************************************/
5623s32 e1000_read_mac_addr(struct e1000_hw *hw) 4090s32 e1000_read_mac_addr(struct e1000_hw *hw)
5624{ 4091{
5625 u16 offset; 4092 u16 offset;
5626 u16 eeprom_data, i; 4093 u16 eeprom_data, i;
5627 4094
5628 DEBUGFUNC("e1000_read_mac_addr"); 4095 DEBUGFUNC("e1000_read_mac_addr");
5629 4096
5630 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4097 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5631 offset = i >> 1; 4098 offset = i >> 1;
5632 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4099 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5633 DEBUGOUT("EEPROM Read Error\n"); 4100 DEBUGOUT("EEPROM Read Error\n");
5634 return -E1000_ERR_EEPROM; 4101 return -E1000_ERR_EEPROM;
5635 } 4102 }
5636 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF); 4103 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
5637 hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8); 4104 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
5638 } 4105 }
5639 4106
5640 switch (hw->mac_type) { 4107 switch (hw->mac_type) {
5641 default: 4108 default:
5642 break; 4109 break;
5643 case e1000_82546: 4110 case e1000_82546:
5644 case e1000_82546_rev_3: 4111 case e1000_82546_rev_3:
5645 case e1000_82571: 4112 if (er32(STATUS) & E1000_STATUS_FUNC_1)
5646 case e1000_80003es2lan: 4113 hw->perm_mac_addr[5] ^= 0x01;
5647 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4114 break;
5648 hw->perm_mac_addr[5] ^= 0x01; 4115 }
5649 break; 4116
5650 } 4117 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5651 4118 hw->mac_addr[i] = hw->perm_mac_addr[i];
5652 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 4119 return E1000_SUCCESS;
5653 hw->mac_addr[i] = hw->perm_mac_addr[i];
5654 return E1000_SUCCESS;
5655} 4120}
5656 4121
5657/****************************************************************************** 4122/**
5658 * Initializes receive address filters. 4123 * e1000_init_rx_addrs - Initializes receive address filters.
5659 * 4124 * @hw: Struct containing variables accessed by shared code
5660 * hw - Struct containing variables accessed by shared code
5661 * 4125 *
5662 * Places the MAC address in receive address register 0 and clears the rest 4126 * Places the MAC address in receive address register 0 and clears the rest
5663 * of the receive addresss registers. Clears the multicast table. Assumes 4127 * of the receive address registers. Clears the multicast table. Assumes
5664 * the receiver is in reset when the routine is called. 4128 * the receiver is in reset when the routine is called.
5665 *****************************************************************************/ 4129 */
5666static void e1000_init_rx_addrs(struct e1000_hw *hw) 4130static void e1000_init_rx_addrs(struct e1000_hw *hw)
5667{ 4131{
5668 u32 i; 4132 u32 i;
5669 u32 rar_num; 4133 u32 rar_num;
5670 4134
5671 DEBUGFUNC("e1000_init_rx_addrs"); 4135 DEBUGFUNC("e1000_init_rx_addrs");
5672 4136
5673 /* Setup the receive address. */ 4137 /* Setup the receive address. */
5674 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 4138 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5675 4139
5676 e1000_rar_set(hw, hw->mac_addr, 0); 4140 e1000_rar_set(hw, hw->mac_addr, 0);
5677 4141
5678 rar_num = E1000_RAR_ENTRIES; 4142 rar_num = E1000_RAR_ENTRIES;
5679 4143
5680 /* Reserve a spot for the Locally Administered Address to work around 4144 /* Zero out the other 15 receive addresses. */
5681 * an 82571 issue in which a reset on one port will reload the MAC on 4145 DEBUGOUT("Clearing RAR[1-15]\n");
5682 * the other port. */ 4146 for (i = 1; i < rar_num; i++) {
5683 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present)) 4147 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5684 rar_num -= 1; 4148 E1000_WRITE_FLUSH();
5685 if (hw->mac_type == e1000_ich8lan) 4149 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5686 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 4150 E1000_WRITE_FLUSH();
5687 4151 }
5688 /* Zero out the other 15 receive addresses. */
5689 DEBUGOUT("Clearing RAR[1-15]\n");
5690 for (i = 1; i < rar_num; i++) {
5691 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5692 E1000_WRITE_FLUSH();
5693 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5694 E1000_WRITE_FLUSH();
5695 }
5696} 4152}
5697 4153
5698/****************************************************************************** 4154/**
5699 * Hashes an address to determine its location in the multicast table 4155 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
5700 * 4156 * @hw: Struct containing variables accessed by shared code
5701 * hw - Struct containing variables accessed by shared code 4157 * @mc_addr: the multicast address to hash
5702 * mc_addr - the multicast address to hash 4158 */
5703 *****************************************************************************/
5704u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 4159u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
5705{ 4160{
5706 u32 hash_value = 0; 4161 u32 hash_value = 0;
5707 4162
5708 /* The portion of the address that is used for the hash table is 4163 /* The portion of the address that is used for the hash table is
5709 * determined by the mc_filter_type setting. 4164 * determined by the mc_filter_type setting.
5710 */ 4165 */
5711 switch (hw->mc_filter_type) { 4166 switch (hw->mc_filter_type) {
5712 /* [0] [1] [2] [3] [4] [5] 4167 /* [0] [1] [2] [3] [4] [5]
5713 * 01 AA 00 12 34 56 4168 * 01 AA 00 12 34 56
5714 * LSB MSB 4169 * LSB MSB
5715 */ 4170 */
5716 case 0: 4171 case 0:
5717 if (hw->mac_type == e1000_ich8lan) { 4172 /* [47:36] i.e. 0x563 for above example address */
5718 /* [47:38] i.e. 0x158 for above example address */ 4173 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
5719 hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2)); 4174 break;
5720 } else { 4175 case 1:
5721 /* [47:36] i.e. 0x563 for above example address */ 4176 /* [46:35] i.e. 0xAC6 for above example address */
5722 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 4177 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
5723 } 4178 break;
5724 break; 4179 case 2:
5725 case 1: 4180 /* [45:34] i.e. 0x5D8 for above example address */
5726 if (hw->mac_type == e1000_ich8lan) { 4181 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
5727 /* [46:37] i.e. 0x2B1 for above example address */ 4182 break;
5728 hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3)); 4183 case 3:
5729 } else { 4184 /* [43:32] i.e. 0x634 for above example address */
5730 /* [46:35] i.e. 0xAC6 for above example address */ 4185 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
5731 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 4186 break;
5732 } 4187 }
5733 break; 4188
5734 case 2: 4189 hash_value &= 0xFFF;
5735 if (hw->mac_type == e1000_ich8lan) { 4190 return hash_value;
5736 /*[45:36] i.e. 0x163 for above example address */
5737 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5738 } else {
5739 /* [45:34] i.e. 0x5D8 for above example address */
5740 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5741 }
5742 break;
5743 case 3:
5744 if (hw->mac_type == e1000_ich8lan) {
5745 /* [43:34] i.e. 0x18D for above example address */
5746 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5747 } else {
5748 /* [43:32] i.e. 0x634 for above example address */
5749 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
5750 }
5751 break;
5752 }
5753
5754 hash_value &= 0xFFF;
5755 if (hw->mac_type == e1000_ich8lan)
5756 hash_value &= 0x3FF;
5757
5758 return hash_value;
5759} 4191}
5760 4192
5761/****************************************************************************** 4193/**
5762 * Puts an ethernet address into a receive address register. 4194 * e1000_rar_set - Puts an ethernet address into a receive address register.
5763 * 4195 * @hw: Struct containing variables accessed by shared code
5764 * hw - Struct containing variables accessed by shared code 4196 * @addr: Address to put into receive address register
5765 * addr - Address to put into receive address register 4197 * @index: Receive address register to write
5766 * index - Receive address register to write 4198 */
5767 *****************************************************************************/
5768void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 4199void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
5769{ 4200{
5770 u32 rar_low, rar_high; 4201 u32 rar_low, rar_high;
5771 4202
5772 /* HW expects these in little endian so we reverse the byte order 4203 /* HW expects these in little endian so we reverse the byte order
5773 * from network order (big endian) to little endian 4204 * from network order (big endian) to little endian
5774 */ 4205 */
5775 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 4206 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5776 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 4207 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5777 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 4208 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5778 4209
5779 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 4210 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5780 * unit hang. 4211 * unit hang.
5781 * 4212 *
5782 * Description: 4213 * Description:
5783 * If there are any Rx frames queued up or otherwise present in the HW 4214 * If there are any Rx frames queued up or otherwise present in the HW
5784 * before RSS is enabled, and then we enable RSS, the HW Rx unit will 4215 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5785 * hang. To work around this issue, we have to disable receives and 4216 * hang. To work around this issue, we have to disable receives and
5786 * flush out all Rx frames before we enable RSS. To do so, we modify we 4217 * flush out all Rx frames before we enable RSS. To do so, we modify we
5787 * redirect all Rx traffic to manageability and then reset the HW. 4218 * redirect all Rx traffic to manageability and then reset the HW.
5788 * This flushes away Rx frames, and (since the redirections to 4219 * This flushes away Rx frames, and (since the redirections to
5789 * manageability persists across resets) keeps new ones from coming in 4220 * manageability persists across resets) keeps new ones from coming in
5790 * while we work. Then, we clear the Address Valid AV bit for all MAC 4221 * while we work. Then, we clear the Address Valid AV bit for all MAC
5791 * addresses and undo the re-direction to manageability. 4222 * addresses and undo the re-direction to manageability.
5792 * Now, frames are coming in again, but the MAC won't accept them, so 4223 * Now, frames are coming in again, but the MAC won't accept them, so
5793 * far so good. We now proceed to initialize RSS (if necessary) and 4224 * far so good. We now proceed to initialize RSS (if necessary) and
5794 * configure the Rx unit. Last, we re-enable the AV bits and continue 4225 * configure the Rx unit. Last, we re-enable the AV bits and continue
5795 * on our merry way. 4226 * on our merry way.
5796 */ 4227 */
5797 switch (hw->mac_type) { 4228 switch (hw->mac_type) {
5798 case e1000_82571: 4229 default:
5799 case e1000_82572: 4230 /* Indicate to hardware the Address is Valid. */
5800 case e1000_80003es2lan: 4231 rar_high |= E1000_RAH_AV;
5801 if (hw->leave_av_bit_off) 4232 break;
5802 break; 4233 }
5803 default: 4234
5804 /* Indicate to hardware the Address is Valid. */ 4235 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5805 rar_high |= E1000_RAH_AV; 4236 E1000_WRITE_FLUSH();
5806 break; 4237 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5807 } 4238 E1000_WRITE_FLUSH();
5808
5809 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5810 E1000_WRITE_FLUSH();
5811 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5812 E1000_WRITE_FLUSH();
5813} 4239}
5814 4240
5815/****************************************************************************** 4241/**
5816 * Writes a value to the specified offset in the VLAN filter table. 4242 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
5817 * 4243 * @hw: Struct containing variables accessed by shared code
5818 * hw - Struct containing variables accessed by shared code 4244 * @offset: Offset in VLAN filer table to write
5819 * offset - Offset in VLAN filer table to write 4245 * @value: Value to write into VLAN filter table
5820 * value - Value to write into VLAN filter table 4246 */
5821 *****************************************************************************/
5822void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 4247void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
5823{ 4248{
5824 u32 temp; 4249 u32 temp;
5825 4250
5826 if (hw->mac_type == e1000_ich8lan) 4251 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5827 return; 4252 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5828 4253 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5829 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4254 E1000_WRITE_FLUSH();
5830 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4255 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5831 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4256 E1000_WRITE_FLUSH();
5832 E1000_WRITE_FLUSH(); 4257 } else {
5833 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 4258 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5834 E1000_WRITE_FLUSH(); 4259 E1000_WRITE_FLUSH();
5835 } else { 4260 }
5836 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5837 E1000_WRITE_FLUSH();
5838 }
5839} 4261}
5840 4262
5841/****************************************************************************** 4263/**
5842 * Clears the VLAN filer table 4264 * e1000_clear_vfta - Clears the VLAN filer table
5843 * 4265 * @hw: Struct containing variables accessed by shared code
5844 * hw - Struct containing variables accessed by shared code 4266 */
5845 *****************************************************************************/
5846static void e1000_clear_vfta(struct e1000_hw *hw) 4267static void e1000_clear_vfta(struct e1000_hw *hw)
5847{ 4268{
5848 u32 offset; 4269 u32 offset;
5849 u32 vfta_value = 0; 4270 u32 vfta_value = 0;
5850 u32 vfta_offset = 0; 4271 u32 vfta_offset = 0;
5851 u32 vfta_bit_in_reg = 0; 4272 u32 vfta_bit_in_reg = 0;
5852 4273
5853 if (hw->mac_type == e1000_ich8lan) 4274 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5854 return; 4275 /* If the offset we want to clear is the same offset of the
5855 4276 * manageability VLAN ID, then clear all bits except that of the
5856 if (hw->mac_type == e1000_82573) { 4277 * manageability unit */
5857 if (hw->mng_cookie.vlan_id != 0) { 4278 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5858 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 4279 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5859 * ID. The following operations determine which 32b entry 4280 E1000_WRITE_FLUSH();
5860 * (i.e. offset) into the array we want to set the VLAN ID 4281 }
5861 * (i.e. bit) of the manageability unit. */
5862 vfta_offset = (hw->mng_cookie.vlan_id >>
5863 E1000_VFTA_ENTRY_SHIFT) &
5864 E1000_VFTA_ENTRY_MASK;
5865 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5866 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5867 }
5868 }
5869 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5870 /* If the offset we want to clear is the same offset of the
5871 * manageability VLAN ID, then clear all bits except that of the
5872 * manageability unit */
5873 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5874 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5875 E1000_WRITE_FLUSH();
5876 }
5877} 4282}
5878 4283
5879static s32 e1000_id_led_init(struct e1000_hw *hw) 4284static s32 e1000_id_led_init(struct e1000_hw *hw)
5880{ 4285{
5881 u32 ledctl; 4286 u32 ledctl;
5882 const u32 ledctl_mask = 0x000000FF; 4287 const u32 ledctl_mask = 0x000000FF;
5883 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 4288 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5884 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 4289 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5885 u16 eeprom_data, i, temp; 4290 u16 eeprom_data, i, temp;
5886 const u16 led_mask = 0x0F; 4291 const u16 led_mask = 0x0F;
5887 4292
5888 DEBUGFUNC("e1000_id_led_init"); 4293 DEBUGFUNC("e1000_id_led_init");
5889 4294
5890 if (hw->mac_type < e1000_82540) { 4295 if (hw->mac_type < e1000_82540) {
5891 /* Nothing to do */ 4296 /* Nothing to do */
5892 return E1000_SUCCESS; 4297 return E1000_SUCCESS;
5893 } 4298 }
5894 4299
5895 ledctl = er32(LEDCTL); 4300 ledctl = er32(LEDCTL);
5896 hw->ledctl_default = ledctl; 4301 hw->ledctl_default = ledctl;
5897 hw->ledctl_mode1 = hw->ledctl_default; 4302 hw->ledctl_mode1 = hw->ledctl_default;
5898 hw->ledctl_mode2 = hw->ledctl_default; 4303 hw->ledctl_mode2 = hw->ledctl_default;
5899 4304
5900 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4305 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5901 DEBUGOUT("EEPROM Read Error\n"); 4306 DEBUGOUT("EEPROM Read Error\n");
5902 return -E1000_ERR_EEPROM; 4307 return -E1000_ERR_EEPROM;
5903 } 4308 }
5904 4309
5905 if ((hw->mac_type == e1000_82573) && 4310 if ((eeprom_data == ID_LED_RESERVED_0000) ||
5906 (eeprom_data == ID_LED_RESERVED_82573)) 4311 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5907 eeprom_data = ID_LED_DEFAULT_82573; 4312 eeprom_data = ID_LED_DEFAULT;
5908 else if ((eeprom_data == ID_LED_RESERVED_0000) || 4313 }
5909 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4314
5910 if (hw->mac_type == e1000_ich8lan) 4315 for (i = 0; i < 4; i++) {
5911 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 4316 temp = (eeprom_data >> (i << 2)) & led_mask;
5912 else 4317 switch (temp) {
5913 eeprom_data = ID_LED_DEFAULT; 4318 case ID_LED_ON1_DEF2:
5914 } 4319 case ID_LED_ON1_ON2:
5915 4320 case ID_LED_ON1_OFF2:
5916 for (i = 0; i < 4; i++) { 4321 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5917 temp = (eeprom_data >> (i << 2)) & led_mask; 4322 hw->ledctl_mode1 |= ledctl_on << (i << 3);
5918 switch (temp) { 4323 break;
5919 case ID_LED_ON1_DEF2: 4324 case ID_LED_OFF1_DEF2:
5920 case ID_LED_ON1_ON2: 4325 case ID_LED_OFF1_ON2:
5921 case ID_LED_ON1_OFF2: 4326 case ID_LED_OFF1_OFF2:
5922 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4327 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5923 hw->ledctl_mode1 |= ledctl_on << (i << 3); 4328 hw->ledctl_mode1 |= ledctl_off << (i << 3);
5924 break; 4329 break;
5925 case ID_LED_OFF1_DEF2: 4330 default:
5926 case ID_LED_OFF1_ON2: 4331 /* Do nothing */
5927 case ID_LED_OFF1_OFF2: 4332 break;
5928 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4333 }
5929 hw->ledctl_mode1 |= ledctl_off << (i << 3); 4334 switch (temp) {
5930 break; 4335 case ID_LED_DEF1_ON2:
5931 default: 4336 case ID_LED_ON1_ON2:
5932 /* Do nothing */ 4337 case ID_LED_OFF1_ON2:
5933 break; 4338 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5934 } 4339 hw->ledctl_mode2 |= ledctl_on << (i << 3);
5935 switch (temp) { 4340 break;
5936 case ID_LED_DEF1_ON2: 4341 case ID_LED_DEF1_OFF2:
5937 case ID_LED_ON1_ON2: 4342 case ID_LED_ON1_OFF2:
5938 case ID_LED_OFF1_ON2: 4343 case ID_LED_OFF1_OFF2:
5939 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4344 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5940 hw->ledctl_mode2 |= ledctl_on << (i << 3); 4345 hw->ledctl_mode2 |= ledctl_off << (i << 3);
5941 break; 4346 break;
5942 case ID_LED_DEF1_OFF2: 4347 default:
5943 case ID_LED_ON1_OFF2: 4348 /* Do nothing */
5944 case ID_LED_OFF1_OFF2: 4349 break;
5945 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4350 }
5946 hw->ledctl_mode2 |= ledctl_off << (i << 3); 4351 }
5947 break; 4352 return E1000_SUCCESS;
5948 default:
5949 /* Do nothing */
5950 break;
5951 }
5952 }
5953 return E1000_SUCCESS;
5954} 4353}
5955 4354
5956/****************************************************************************** 4355/**
5957 * Prepares SW controlable LED for use and saves the current state of the LED. 4356 * e1000_setup_led
4357 * @hw: Struct containing variables accessed by shared code
5958 * 4358 *
5959 * hw - Struct containing variables accessed by shared code 4359 * Prepares SW controlable LED for use and saves the current state of the LED.
5960 *****************************************************************************/ 4360 */
5961s32 e1000_setup_led(struct e1000_hw *hw) 4361s32 e1000_setup_led(struct e1000_hw *hw)
5962{ 4362{
5963 u32 ledctl; 4363 u32 ledctl;
5964 s32 ret_val = E1000_SUCCESS; 4364 s32 ret_val = E1000_SUCCESS;
5965
5966 DEBUGFUNC("e1000_setup_led");
5967
5968 switch (hw->mac_type) {
5969 case e1000_82542_rev2_0:
5970 case e1000_82542_rev2_1:
5971 case e1000_82543:
5972 case e1000_82544:
5973 /* No setup necessary */
5974 break;
5975 case e1000_82541:
5976 case e1000_82547:
5977 case e1000_82541_rev_2:
5978 case e1000_82547_rev_2:
5979 /* Turn off PHY Smart Power Down (if enabled) */
5980 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
5981 &hw->phy_spd_default);
5982 if (ret_val)
5983 return ret_val;
5984 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5985 (u16)(hw->phy_spd_default &
5986 ~IGP01E1000_GMII_SPD));
5987 if (ret_val)
5988 return ret_val;
5989 /* Fall Through */
5990 default:
5991 if (hw->media_type == e1000_media_type_fiber) {
5992 ledctl = er32(LEDCTL);
5993 /* Save current LEDCTL settings */
5994 hw->ledctl_default = ledctl;
5995 /* Turn off LED0 */
5996 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
5997 E1000_LEDCTL_LED0_BLINK |
5998 E1000_LEDCTL_LED0_MODE_MASK);
5999 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6000 E1000_LEDCTL_LED0_MODE_SHIFT);
6001 ew32(LEDCTL, ledctl);
6002 } else if (hw->media_type == e1000_media_type_copper)
6003 ew32(LEDCTL, hw->ledctl_mode1);
6004 break;
6005 }
6006
6007 return E1000_SUCCESS;
6008}
6009 4365
4366 DEBUGFUNC("e1000_setup_led");
6010 4367
6011/****************************************************************************** 4368 switch (hw->mac_type) {
6012 * Used on 82571 and later Si that has LED blink bits. 4369 case e1000_82542_rev2_0:
6013 * Callers must use their own timer and should have already called 4370 case e1000_82542_rev2_1:
6014 * e1000_id_led_init() 4371 case e1000_82543:
6015 * Call e1000_cleanup led() to stop blinking 4372 case e1000_82544:
6016 * 4373 /* No setup necessary */
6017 * hw - Struct containing variables accessed by shared code 4374 break;
6018 *****************************************************************************/ 4375 case e1000_82541:
6019s32 e1000_blink_led_start(struct e1000_hw *hw) 4376 case e1000_82547:
6020{ 4377 case e1000_82541_rev_2:
6021 s16 i; 4378 case e1000_82547_rev_2:
6022 u32 ledctl_blink = 0; 4379 /* Turn off PHY Smart Power Down (if enabled) */
6023 4380 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6024 DEBUGFUNC("e1000_id_led_blink_on"); 4381 &hw->phy_spd_default);
6025 4382 if (ret_val)
6026 if (hw->mac_type < e1000_82571) { 4383 return ret_val;
6027 /* Nothing to do */ 4384 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6028 return E1000_SUCCESS; 4385 (u16) (hw->phy_spd_default &
6029 } 4386 ~IGP01E1000_GMII_SPD));
6030 if (hw->media_type == e1000_media_type_fiber) { 4387 if (ret_val)
6031 /* always blink LED0 for PCI-E fiber */ 4388 return ret_val;
6032 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 4389 /* Fall Through */
6033 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 4390 default:
6034 } else { 4391 if (hw->media_type == e1000_media_type_fiber) {
6035 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ 4392 ledctl = er32(LEDCTL);
6036 ledctl_blink = hw->ledctl_mode2; 4393 /* Save current LEDCTL settings */
6037 for (i=0; i < 4; i++) 4394 hw->ledctl_default = ledctl;
6038 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == 4395 /* Turn off LED0 */
6039 E1000_LEDCTL_MODE_LED_ON) 4396 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6040 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); 4397 E1000_LEDCTL_LED0_BLINK |
6041 } 4398 E1000_LEDCTL_LED0_MODE_MASK);
6042 4399 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6043 ew32(LEDCTL, ledctl_blink); 4400 E1000_LEDCTL_LED0_MODE_SHIFT);
6044 4401 ew32(LEDCTL, ledctl);
6045 return E1000_SUCCESS; 4402 } else if (hw->media_type == e1000_media_type_copper)
4403 ew32(LEDCTL, hw->ledctl_mode1);
4404 break;
4405 }
4406
4407 return E1000_SUCCESS;
6046} 4408}
6047 4409
6048/****************************************************************************** 4410/**
6049 * Restores the saved state of the SW controlable LED. 4411 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
6050 * 4412 * @hw: Struct containing variables accessed by shared code
6051 * hw - Struct containing variables accessed by shared code 4413 */
6052 *****************************************************************************/
6053s32 e1000_cleanup_led(struct e1000_hw *hw) 4414s32 e1000_cleanup_led(struct e1000_hw *hw)
6054{ 4415{
6055 s32 ret_val = E1000_SUCCESS; 4416 s32 ret_val = E1000_SUCCESS;
6056 4417
6057 DEBUGFUNC("e1000_cleanup_led"); 4418 DEBUGFUNC("e1000_cleanup_led");
6058 4419
6059 switch (hw->mac_type) { 4420 switch (hw->mac_type) {
6060 case e1000_82542_rev2_0: 4421 case e1000_82542_rev2_0:
6061 case e1000_82542_rev2_1: 4422 case e1000_82542_rev2_1:
6062 case e1000_82543: 4423 case e1000_82543:
6063 case e1000_82544: 4424 case e1000_82544:
6064 /* No cleanup necessary */ 4425 /* No cleanup necessary */
6065 break; 4426 break;
6066 case e1000_82541: 4427 case e1000_82541:
6067 case e1000_82547: 4428 case e1000_82547:
6068 case e1000_82541_rev_2: 4429 case e1000_82541_rev_2:
6069 case e1000_82547_rev_2: 4430 case e1000_82547_rev_2:
6070 /* Turn on PHY Smart Power Down (if previously enabled) */ 4431 /* Turn on PHY Smart Power Down (if previously enabled) */
6071 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4432 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6072 hw->phy_spd_default); 4433 hw->phy_spd_default);
6073 if (ret_val) 4434 if (ret_val)
6074 return ret_val; 4435 return ret_val;
6075 /* Fall Through */ 4436 /* Fall Through */
6076 default: 4437 default:
6077 if (hw->phy_type == e1000_phy_ife) { 4438 /* Restore LEDCTL settings */
6078 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 4439 ew32(LEDCTL, hw->ledctl_default);
6079 break; 4440 break;
6080 } 4441 }
6081 /* Restore LEDCTL settings */ 4442
6082 ew32(LEDCTL, hw->ledctl_default); 4443 return E1000_SUCCESS;
6083 break;
6084 }
6085
6086 return E1000_SUCCESS;
6087} 4444}
6088 4445
6089/****************************************************************************** 4446/**
6090 * Turns on the software controllable LED 4447 * e1000_led_on - Turns on the software controllable LED
6091 * 4448 * @hw: Struct containing variables accessed by shared code
6092 * hw - Struct containing variables accessed by shared code 4449 */
6093 *****************************************************************************/
6094s32 e1000_led_on(struct e1000_hw *hw) 4450s32 e1000_led_on(struct e1000_hw *hw)
6095{ 4451{
6096 u32 ctrl = er32(CTRL); 4452 u32 ctrl = er32(CTRL);
6097 4453
6098 DEBUGFUNC("e1000_led_on"); 4454 DEBUGFUNC("e1000_led_on");
6099 4455
6100 switch (hw->mac_type) { 4456 switch (hw->mac_type) {
6101 case e1000_82542_rev2_0: 4457 case e1000_82542_rev2_0:
6102 case e1000_82542_rev2_1: 4458 case e1000_82542_rev2_1:
6103 case e1000_82543: 4459 case e1000_82543:
6104 /* Set SW Defineable Pin 0 to turn on the LED */ 4460 /* Set SW Defineable Pin 0 to turn on the LED */
6105 ctrl |= E1000_CTRL_SWDPIN0; 4461 ctrl |= E1000_CTRL_SWDPIN0;
6106 ctrl |= E1000_CTRL_SWDPIO0; 4462 ctrl |= E1000_CTRL_SWDPIO0;
6107 break; 4463 break;
6108 case e1000_82544: 4464 case e1000_82544:
6109 if (hw->media_type == e1000_media_type_fiber) { 4465 if (hw->media_type == e1000_media_type_fiber) {
6110 /* Set SW Defineable Pin 0 to turn on the LED */ 4466 /* Set SW Defineable Pin 0 to turn on the LED */
6111 ctrl |= E1000_CTRL_SWDPIN0; 4467 ctrl |= E1000_CTRL_SWDPIN0;
6112 ctrl |= E1000_CTRL_SWDPIO0; 4468 ctrl |= E1000_CTRL_SWDPIO0;
6113 } else { 4469 } else {
6114 /* Clear SW Defineable Pin 0 to turn on the LED */ 4470 /* Clear SW Defineable Pin 0 to turn on the LED */
6115 ctrl &= ~E1000_CTRL_SWDPIN0; 4471 ctrl &= ~E1000_CTRL_SWDPIN0;
6116 ctrl |= E1000_CTRL_SWDPIO0; 4472 ctrl |= E1000_CTRL_SWDPIO0;
6117 } 4473 }
6118 break; 4474 break;
6119 default: 4475 default:
6120 if (hw->media_type == e1000_media_type_fiber) { 4476 if (hw->media_type == e1000_media_type_fiber) {
6121 /* Clear SW Defineable Pin 0 to turn on the LED */ 4477 /* Clear SW Defineable Pin 0 to turn on the LED */
6122 ctrl &= ~E1000_CTRL_SWDPIN0; 4478 ctrl &= ~E1000_CTRL_SWDPIN0;
6123 ctrl |= E1000_CTRL_SWDPIO0; 4479 ctrl |= E1000_CTRL_SWDPIO0;
6124 } else if (hw->phy_type == e1000_phy_ife) { 4480 } else if (hw->media_type == e1000_media_type_copper) {
6125 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4481 ew32(LEDCTL, hw->ledctl_mode2);
6126 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 4482 return E1000_SUCCESS;
6127 } else if (hw->media_type == e1000_media_type_copper) { 4483 }
6128 ew32(LEDCTL, hw->ledctl_mode2); 4484 break;
6129 return E1000_SUCCESS; 4485 }
6130 } 4486
6131 break; 4487 ew32(CTRL, ctrl);
6132 } 4488
6133 4489 return E1000_SUCCESS;
6134 ew32(CTRL, ctrl);
6135
6136 return E1000_SUCCESS;
6137} 4490}
6138 4491
6139/****************************************************************************** 4492/**
6140 * Turns off the software controllable LED 4493 * e1000_led_off - Turns off the software controllable LED
6141 * 4494 * @hw: Struct containing variables accessed by shared code
6142 * hw - Struct containing variables accessed by shared code 4495 */
6143 *****************************************************************************/
6144s32 e1000_led_off(struct e1000_hw *hw) 4496s32 e1000_led_off(struct e1000_hw *hw)
6145{ 4497{
6146 u32 ctrl = er32(CTRL); 4498 u32 ctrl = er32(CTRL);
6147 4499
6148 DEBUGFUNC("e1000_led_off"); 4500 DEBUGFUNC("e1000_led_off");
6149 4501
6150 switch (hw->mac_type) { 4502 switch (hw->mac_type) {
6151 case e1000_82542_rev2_0: 4503 case e1000_82542_rev2_0:
6152 case e1000_82542_rev2_1: 4504 case e1000_82542_rev2_1:
6153 case e1000_82543: 4505 case e1000_82543:
6154 /* Clear SW Defineable Pin 0 to turn off the LED */ 4506 /* Clear SW Defineable Pin 0 to turn off the LED */
6155 ctrl &= ~E1000_CTRL_SWDPIN0; 4507 ctrl &= ~E1000_CTRL_SWDPIN0;
6156 ctrl |= E1000_CTRL_SWDPIO0; 4508 ctrl |= E1000_CTRL_SWDPIO0;
6157 break; 4509 break;
6158 case e1000_82544: 4510 case e1000_82544:
6159 if (hw->media_type == e1000_media_type_fiber) { 4511 if (hw->media_type == e1000_media_type_fiber) {
6160 /* Clear SW Defineable Pin 0 to turn off the LED */ 4512 /* Clear SW Defineable Pin 0 to turn off the LED */
6161 ctrl &= ~E1000_CTRL_SWDPIN0; 4513 ctrl &= ~E1000_CTRL_SWDPIN0;
6162 ctrl |= E1000_CTRL_SWDPIO0; 4514 ctrl |= E1000_CTRL_SWDPIO0;
6163 } else { 4515 } else {
6164 /* Set SW Defineable Pin 0 to turn off the LED */ 4516 /* Set SW Defineable Pin 0 to turn off the LED */
6165 ctrl |= E1000_CTRL_SWDPIN0; 4517 ctrl |= E1000_CTRL_SWDPIN0;
6166 ctrl |= E1000_CTRL_SWDPIO0; 4518 ctrl |= E1000_CTRL_SWDPIO0;
6167 } 4519 }
6168 break; 4520 break;
6169 default: 4521 default:
6170 if (hw->media_type == e1000_media_type_fiber) { 4522 if (hw->media_type == e1000_media_type_fiber) {
6171 /* Set SW Defineable Pin 0 to turn off the LED */ 4523 /* Set SW Defineable Pin 0 to turn off the LED */
6172 ctrl |= E1000_CTRL_SWDPIN0; 4524 ctrl |= E1000_CTRL_SWDPIN0;
6173 ctrl |= E1000_CTRL_SWDPIO0; 4525 ctrl |= E1000_CTRL_SWDPIO0;
6174 } else if (hw->phy_type == e1000_phy_ife) { 4526 } else if (hw->media_type == e1000_media_type_copper) {
6175 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 4527 ew32(LEDCTL, hw->ledctl_mode1);
6176 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 4528 return E1000_SUCCESS;
6177 } else if (hw->media_type == e1000_media_type_copper) { 4529 }
6178 ew32(LEDCTL, hw->ledctl_mode1); 4530 break;
6179 return E1000_SUCCESS; 4531 }
6180 } 4532
6181 break; 4533 ew32(CTRL, ctrl);
6182 } 4534
6183 4535 return E1000_SUCCESS;
6184 ew32(CTRL, ctrl);
6185
6186 return E1000_SUCCESS;
6187} 4536}
6188 4537
6189/****************************************************************************** 4538/**
6190 * Clears all hardware statistics counters. 4539 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
6191 * 4540 * @hw: Struct containing variables accessed by shared code
6192 * hw - Struct containing variables accessed by shared code 4541 */
6193 *****************************************************************************/
6194static void e1000_clear_hw_cntrs(struct e1000_hw *hw) 4542static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6195{ 4543{
6196 volatile u32 temp; 4544 volatile u32 temp;
6197 4545
6198 temp = er32(CRCERRS); 4546 temp = er32(CRCERRS);
6199 temp = er32(SYMERRS); 4547 temp = er32(SYMERRS);
6200 temp = er32(MPC); 4548 temp = er32(MPC);
6201 temp = er32(SCC); 4549 temp = er32(SCC);
6202 temp = er32(ECOL); 4550 temp = er32(ECOL);
6203 temp = er32(MCC); 4551 temp = er32(MCC);
6204 temp = er32(LATECOL); 4552 temp = er32(LATECOL);
6205 temp = er32(COLC); 4553 temp = er32(COLC);
6206 temp = er32(DC); 4554 temp = er32(DC);
6207 temp = er32(SEC); 4555 temp = er32(SEC);
6208 temp = er32(RLEC); 4556 temp = er32(RLEC);
6209 temp = er32(XONRXC); 4557 temp = er32(XONRXC);
6210 temp = er32(XONTXC); 4558 temp = er32(XONTXC);
6211 temp = er32(XOFFRXC); 4559 temp = er32(XOFFRXC);
6212 temp = er32(XOFFTXC); 4560 temp = er32(XOFFTXC);
6213 temp = er32(FCRUC); 4561 temp = er32(FCRUC);
6214 4562
6215 if (hw->mac_type != e1000_ich8lan) { 4563 temp = er32(PRC64);
6216 temp = er32(PRC64); 4564 temp = er32(PRC127);
6217 temp = er32(PRC127); 4565 temp = er32(PRC255);
6218 temp = er32(PRC255); 4566 temp = er32(PRC511);
6219 temp = er32(PRC511); 4567 temp = er32(PRC1023);
6220 temp = er32(PRC1023); 4568 temp = er32(PRC1522);
6221 temp = er32(PRC1522); 4569
6222 } 4570 temp = er32(GPRC);
6223 4571 temp = er32(BPRC);
6224 temp = er32(GPRC); 4572 temp = er32(MPRC);
6225 temp = er32(BPRC); 4573 temp = er32(GPTC);
6226 temp = er32(MPRC); 4574 temp = er32(GORCL);
6227 temp = er32(GPTC); 4575 temp = er32(GORCH);
6228 temp = er32(GORCL); 4576 temp = er32(GOTCL);
6229 temp = er32(GORCH); 4577 temp = er32(GOTCH);
6230 temp = er32(GOTCL); 4578 temp = er32(RNBC);
6231 temp = er32(GOTCH); 4579 temp = er32(RUC);
6232 temp = er32(RNBC); 4580 temp = er32(RFC);
6233 temp = er32(RUC); 4581 temp = er32(ROC);
6234 temp = er32(RFC); 4582 temp = er32(RJC);
6235 temp = er32(ROC); 4583 temp = er32(TORL);
6236 temp = er32(RJC); 4584 temp = er32(TORH);
6237 temp = er32(TORL); 4585 temp = er32(TOTL);
6238 temp = er32(TORH); 4586 temp = er32(TOTH);
6239 temp = er32(TOTL); 4587 temp = er32(TPR);
6240 temp = er32(TOTH); 4588 temp = er32(TPT);
6241 temp = er32(TPR); 4589
6242 temp = er32(TPT); 4590 temp = er32(PTC64);
6243 4591 temp = er32(PTC127);
6244 if (hw->mac_type != e1000_ich8lan) { 4592 temp = er32(PTC255);
6245 temp = er32(PTC64); 4593 temp = er32(PTC511);
6246 temp = er32(PTC127); 4594 temp = er32(PTC1023);
6247 temp = er32(PTC255); 4595 temp = er32(PTC1522);
6248 temp = er32(PTC511); 4596
6249 temp = er32(PTC1023); 4597 temp = er32(MPTC);
6250 temp = er32(PTC1522); 4598 temp = er32(BPTC);
6251 } 4599
6252 4600 if (hw->mac_type < e1000_82543)
6253 temp = er32(MPTC); 4601 return;
6254 temp = er32(BPTC); 4602
6255 4603 temp = er32(ALGNERRC);
6256 if (hw->mac_type < e1000_82543) return; 4604 temp = er32(RXERRC);
6257 4605 temp = er32(TNCRS);
6258 temp = er32(ALGNERRC); 4606 temp = er32(CEXTERR);
6259 temp = er32(RXERRC); 4607 temp = er32(TSCTC);
6260 temp = er32(TNCRS); 4608 temp = er32(TSCTFC);
6261 temp = er32(CEXTERR); 4609
6262 temp = er32(TSCTC); 4610 if (hw->mac_type <= e1000_82544)
6263 temp = er32(TSCTFC); 4611 return;
6264 4612
6265 if (hw->mac_type <= e1000_82544) return; 4613 temp = er32(MGTPRC);
6266 4614 temp = er32(MGTPDC);
6267 temp = er32(MGTPRC); 4615 temp = er32(MGTPTC);
6268 temp = er32(MGTPDC); 4616}
6269 temp = er32(MGTPTC); 4617
6270 4618/**
6271 if (hw->mac_type <= e1000_82547_rev_2) return; 4619 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
6272 4620 * @hw: Struct containing variables accessed by shared code
6273 temp = er32(IAC);
6274 temp = er32(ICRXOC);
6275
6276 if (hw->mac_type == e1000_ich8lan) return;
6277
6278 temp = er32(ICRXPTC);
6279 temp = er32(ICRXATC);
6280 temp = er32(ICTXPTC);
6281 temp = er32(ICTXATC);
6282 temp = er32(ICTXQEC);
6283 temp = er32(ICTXQMTC);
6284 temp = er32(ICRXDMTC);
6285}
6286
6287/******************************************************************************
6288 * Resets Adaptive IFS to its default state.
6289 *
6290 * hw - Struct containing variables accessed by shared code
6291 * 4621 *
6292 * Call this after e1000_init_hw. You may override the IFS defaults by setting 4622 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6293 * hw->ifs_params_forced to true. However, you must initialize hw-> 4623 * hw->ifs_params_forced to true. However, you must initialize hw->
6294 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4624 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6295 * before calling this function. 4625 * before calling this function.
6296 *****************************************************************************/ 4626 */
6297void e1000_reset_adaptive(struct e1000_hw *hw) 4627void e1000_reset_adaptive(struct e1000_hw *hw)
6298{ 4628{
6299 DEBUGFUNC("e1000_reset_adaptive"); 4629 DEBUGFUNC("e1000_reset_adaptive");
6300 4630
6301 if (hw->adaptive_ifs) { 4631 if (hw->adaptive_ifs) {
6302 if (!hw->ifs_params_forced) { 4632 if (!hw->ifs_params_forced) {
6303 hw->current_ifs_val = 0; 4633 hw->current_ifs_val = 0;
6304 hw->ifs_min_val = IFS_MIN; 4634 hw->ifs_min_val = IFS_MIN;
6305 hw->ifs_max_val = IFS_MAX; 4635 hw->ifs_max_val = IFS_MAX;
6306 hw->ifs_step_size = IFS_STEP; 4636 hw->ifs_step_size = IFS_STEP;
6307 hw->ifs_ratio = IFS_RATIO; 4637 hw->ifs_ratio = IFS_RATIO;
6308 } 4638 }
6309 hw->in_ifs_mode = false; 4639 hw->in_ifs_mode = false;
6310 ew32(AIT, 0); 4640 ew32(AIT, 0);
6311 } else { 4641 } else {
6312 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4642 DEBUGOUT("Not in Adaptive IFS mode!\n");
6313 } 4643 }
6314} 4644}
6315 4645
6316/****************************************************************************** 4646/**
4647 * e1000_update_adaptive - update adaptive IFS
4648 * @hw: Struct containing variables accessed by shared code
4649 * @tx_packets: Number of transmits since last callback
4650 * @total_collisions: Number of collisions since last callback
4651 *
6317 * Called during the callback/watchdog routine to update IFS value based on 4652 * Called during the callback/watchdog routine to update IFS value based on
6318 * the ratio of transmits to collisions. 4653 * the ratio of transmits to collisions.
6319 * 4654 */
6320 * hw - Struct containing variables accessed by shared code
6321 * tx_packets - Number of transmits since last callback
6322 * total_collisions - Number of collisions since last callback
6323 *****************************************************************************/
6324void e1000_update_adaptive(struct e1000_hw *hw) 4655void e1000_update_adaptive(struct e1000_hw *hw)
6325{ 4656{
6326 DEBUGFUNC("e1000_update_adaptive"); 4657 DEBUGFUNC("e1000_update_adaptive");
6327 4658
6328 if (hw->adaptive_ifs) { 4659 if (hw->adaptive_ifs) {
6329 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { 4660 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
6330 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 4661 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6331 hw->in_ifs_mode = true; 4662 hw->in_ifs_mode = true;
6332 if (hw->current_ifs_val < hw->ifs_max_val) { 4663 if (hw->current_ifs_val < hw->ifs_max_val) {
6333 if (hw->current_ifs_val == 0) 4664 if (hw->current_ifs_val == 0)
6334 hw->current_ifs_val = hw->ifs_min_val; 4665 hw->current_ifs_val =
6335 else 4666 hw->ifs_min_val;
6336 hw->current_ifs_val += hw->ifs_step_size; 4667 else
6337 ew32(AIT, hw->current_ifs_val); 4668 hw->current_ifs_val +=
6338 } 4669 hw->ifs_step_size;
6339 } 4670 ew32(AIT, hw->current_ifs_val);
6340 } else { 4671 }
6341 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4672 }
6342 hw->current_ifs_val = 0; 4673 } else {
6343 hw->in_ifs_mode = false; 4674 if (hw->in_ifs_mode
6344 ew32(AIT, 0); 4675 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6345 } 4676 hw->current_ifs_val = 0;
6346 } 4677 hw->in_ifs_mode = false;
6347 } else { 4678 ew32(AIT, 0);
6348 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4679 }
6349 } 4680 }
4681 } else {
4682 DEBUGOUT("Not in Adaptive IFS mode!\n");
4683 }
6350} 4684}
6351 4685
6352/****************************************************************************** 4686/**
6353 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 4687 * e1000_tbi_adjust_stats
4688 * @hw: Struct containing variables accessed by shared code
4689 * @frame_len: The length of the frame in question
4690 * @mac_addr: The Ethernet destination address of the frame in question
6354 * 4691 *
6355 * hw - Struct containing variables accessed by shared code 4692 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6356 * frame_len - The length of the frame in question 4693 */
6357 * mac_addr - The Ethernet destination address of the frame in question
6358 *****************************************************************************/
6359void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, 4694void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
6360 u32 frame_len, u8 *mac_addr) 4695 u32 frame_len, u8 *mac_addr)
6361{ 4696{
6362 u64 carry_bit; 4697 u64 carry_bit;
6363 4698
6364 /* First adjust the frame length. */ 4699 /* First adjust the frame length. */
6365 frame_len--; 4700 frame_len--;
6366 /* We need to adjust the statistics counters, since the hardware 4701 /* We need to adjust the statistics counters, since the hardware
6367 * counters overcount this packet as a CRC error and undercount 4702 * counters overcount this packet as a CRC error and undercount
6368 * the packet as a good packet 4703 * the packet as a good packet
6369 */ 4704 */
6370 /* This packet should not be counted as a CRC error. */ 4705 /* This packet should not be counted as a CRC error. */
6371 stats->crcerrs--; 4706 stats->crcerrs--;
6372 /* This packet does count as a Good Packet Received. */ 4707 /* This packet does count as a Good Packet Received. */
6373 stats->gprc++; 4708 stats->gprc++;
6374 4709
6375 /* Adjust the Good Octets received counters */ 4710 /* Adjust the Good Octets received counters */
6376 carry_bit = 0x80000000 & stats->gorcl; 4711 carry_bit = 0x80000000 & stats->gorcl;
6377 stats->gorcl += frame_len; 4712 stats->gorcl += frame_len;
6378 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 4713 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6379 * Received Count) was one before the addition, 4714 * Received Count) was one before the addition,
6380 * AND it is zero after, then we lost the carry out, 4715 * AND it is zero after, then we lost the carry out,
6381 * need to add one to Gorch (Good Octets Received Count High). 4716 * need to add one to Gorch (Good Octets Received Count High).
6382 * This could be simplified if all environments supported 4717 * This could be simplified if all environments supported
6383 * 64-bit integers. 4718 * 64-bit integers.
6384 */ 4719 */
6385 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 4720 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6386 stats->gorch++; 4721 stats->gorch++;
6387 /* Is this a broadcast or multicast? Check broadcast first, 4722 /* Is this a broadcast or multicast? Check broadcast first,
6388 * since the test for a multicast frame will test positive on 4723 * since the test for a multicast frame will test positive on
6389 * a broadcast frame. 4724 * a broadcast frame.
6390 */ 4725 */
6391 if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff)) 4726 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
6392 /* Broadcast packet */ 4727 /* Broadcast packet */
6393 stats->bprc++; 4728 stats->bprc++;
6394 else if (*mac_addr & 0x01) 4729 else if (*mac_addr & 0x01)
6395 /* Multicast packet */ 4730 /* Multicast packet */
6396 stats->mprc++; 4731 stats->mprc++;
6397 4732
6398 if (frame_len == hw->max_frame_size) { 4733 if (frame_len == hw->max_frame_size) {
6399 /* In this case, the hardware has overcounted the number of 4734 /* In this case, the hardware has overcounted the number of
6400 * oversize frames. 4735 * oversize frames.
6401 */ 4736 */
6402 if (stats->roc > 0) 4737 if (stats->roc > 0)
6403 stats->roc--; 4738 stats->roc--;
6404 } 4739 }
6405 4740
6406 /* Adjust the bin counters when the extra byte put the frame in the 4741 /* Adjust the bin counters when the extra byte put the frame in the
6407 * wrong bin. Remember that the frame_len was adjusted above. 4742 * wrong bin. Remember that the frame_len was adjusted above.
6408 */ 4743 */
6409 if (frame_len == 64) { 4744 if (frame_len == 64) {
6410 stats->prc64++; 4745 stats->prc64++;
6411 stats->prc127--; 4746 stats->prc127--;
6412 } else if (frame_len == 127) { 4747 } else if (frame_len == 127) {
6413 stats->prc127++; 4748 stats->prc127++;
6414 stats->prc255--; 4749 stats->prc255--;
6415 } else if (frame_len == 255) { 4750 } else if (frame_len == 255) {
6416 stats->prc255++; 4751 stats->prc255++;
6417 stats->prc511--; 4752 stats->prc511--;
6418 } else if (frame_len == 511) { 4753 } else if (frame_len == 511) {
6419 stats->prc511++; 4754 stats->prc511++;
6420 stats->prc1023--; 4755 stats->prc1023--;
6421 } else if (frame_len == 1023) { 4756 } else if (frame_len == 1023) {
6422 stats->prc1023++; 4757 stats->prc1023++;
6423 stats->prc1522--; 4758 stats->prc1522--;
6424 } else if (frame_len == 1522) { 4759 } else if (frame_len == 1522) {
6425 stats->prc1522++; 4760 stats->prc1522++;
6426 } 4761 }
6427} 4762}
6428 4763
6429/****************************************************************************** 4764/**
6430 * Gets the current PCI bus type, speed, and width of the hardware 4765 * e1000_get_bus_info
4766 * @hw: Struct containing variables accessed by shared code
6431 * 4767 *
6432 * hw - Struct containing variables accessed by shared code 4768 * Gets the current PCI bus type, speed, and width of the hardware
6433 *****************************************************************************/ 4769 */
6434void e1000_get_bus_info(struct e1000_hw *hw) 4770void e1000_get_bus_info(struct e1000_hw *hw)
6435{ 4771{
6436 s32 ret_val; 4772 u32 status;
6437 u16 pci_ex_link_status; 4773
6438 u32 status; 4774 switch (hw->mac_type) {
6439 4775 case e1000_82542_rev2_0:
6440 switch (hw->mac_type) { 4776 case e1000_82542_rev2_1:
6441 case e1000_82542_rev2_0: 4777 hw->bus_type = e1000_bus_type_pci;
6442 case e1000_82542_rev2_1: 4778 hw->bus_speed = e1000_bus_speed_unknown;
6443 hw->bus_type = e1000_bus_type_pci; 4779 hw->bus_width = e1000_bus_width_unknown;
6444 hw->bus_speed = e1000_bus_speed_unknown; 4780 break;
6445 hw->bus_width = e1000_bus_width_unknown; 4781 default:
6446 break; 4782 status = er32(STATUS);
6447 case e1000_82571: 4783 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6448 case e1000_82572: 4784 e1000_bus_type_pcix : e1000_bus_type_pci;
6449 case e1000_82573: 4785
6450 case e1000_80003es2lan: 4786 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6451 hw->bus_type = e1000_bus_type_pci_express; 4787 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6452 hw->bus_speed = e1000_bus_speed_2500; 4788 e1000_bus_speed_66 : e1000_bus_speed_120;
6453 ret_val = e1000_read_pcie_cap_reg(hw, 4789 } else if (hw->bus_type == e1000_bus_type_pci) {
6454 PCI_EX_LINK_STATUS, 4790 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6455 &pci_ex_link_status); 4791 e1000_bus_speed_66 : e1000_bus_speed_33;
6456 if (ret_val) 4792 } else {
6457 hw->bus_width = e1000_bus_width_unknown; 4793 switch (status & E1000_STATUS_PCIX_SPEED) {
6458 else 4794 case E1000_STATUS_PCIX_SPEED_66:
6459 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> 4795 hw->bus_speed = e1000_bus_speed_66;
6460 PCI_EX_LINK_WIDTH_SHIFT; 4796 break;
6461 break; 4797 case E1000_STATUS_PCIX_SPEED_100:
6462 case e1000_ich8lan: 4798 hw->bus_speed = e1000_bus_speed_100;
6463 hw->bus_type = e1000_bus_type_pci_express; 4799 break;
6464 hw->bus_speed = e1000_bus_speed_2500; 4800 case E1000_STATUS_PCIX_SPEED_133:
6465 hw->bus_width = e1000_bus_width_pciex_1; 4801 hw->bus_speed = e1000_bus_speed_133;
6466 break; 4802 break;
6467 default: 4803 default:
6468 status = er32(STATUS); 4804 hw->bus_speed = e1000_bus_speed_reserved;
6469 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4805 break;
6470 e1000_bus_type_pcix : e1000_bus_type_pci; 4806 }
6471 4807 }
6472 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4808 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6473 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 4809 e1000_bus_width_64 : e1000_bus_width_32;
6474 e1000_bus_speed_66 : e1000_bus_speed_120; 4810 break;
6475 } else if (hw->bus_type == e1000_bus_type_pci) { 4811 }
6476 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6477 e1000_bus_speed_66 : e1000_bus_speed_33;
6478 } else {
6479 switch (status & E1000_STATUS_PCIX_SPEED) {
6480 case E1000_STATUS_PCIX_SPEED_66:
6481 hw->bus_speed = e1000_bus_speed_66;
6482 break;
6483 case E1000_STATUS_PCIX_SPEED_100:
6484 hw->bus_speed = e1000_bus_speed_100;
6485 break;
6486 case E1000_STATUS_PCIX_SPEED_133:
6487 hw->bus_speed = e1000_bus_speed_133;
6488 break;
6489 default:
6490 hw->bus_speed = e1000_bus_speed_reserved;
6491 break;
6492 }
6493 }
6494 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6495 e1000_bus_width_64 : e1000_bus_width_32;
6496 break;
6497 }
6498} 4812}
6499 4813
6500/****************************************************************************** 4814/**
4815 * e1000_write_reg_io
4816 * @hw: Struct containing variables accessed by shared code
4817 * @offset: offset to write to
4818 * @value: value to write
4819 *
6501 * Writes a value to one of the devices registers using port I/O (as opposed to 4820 * Writes a value to one of the devices registers using port I/O (as opposed to
6502 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4821 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6503 * 4822 */
6504 * hw - Struct containing variables accessed by shared code
6505 * offset - offset to write to
6506 * value - value to write
6507 *****************************************************************************/
6508static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) 4823static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
6509{ 4824{
6510 unsigned long io_addr = hw->io_base; 4825 unsigned long io_addr = hw->io_base;
6511 unsigned long io_data = hw->io_base + 4; 4826 unsigned long io_data = hw->io_base + 4;
6512 4827
6513 e1000_io_write(hw, io_addr, offset); 4828 e1000_io_write(hw, io_addr, offset);
6514 e1000_io_write(hw, io_data, value); 4829 e1000_io_write(hw, io_data, value);
6515} 4830}
6516 4831
6517/****************************************************************************** 4832/**
6518 * Estimates the cable length. 4833 * e1000_get_cable_length - Estimates the cable length.
6519 * 4834 * @hw: Struct containing variables accessed by shared code
6520 * hw - Struct containing variables accessed by shared code 4835 * @min_length: The estimated minimum length
6521 * min_length - The estimated minimum length 4836 * @max_length: The estimated maximum length
6522 * max_length - The estimated maximum length
6523 * 4837 *
6524 * returns: - E1000_ERR_XXX 4838 * returns: - E1000_ERR_XXX
6525 * E1000_SUCCESS 4839 * E1000_SUCCESS
@@ -6528,185 +4842,115 @@ static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
6528 * So for M88 phy's, this function interprets the one value returned from the 4842 * So for M88 phy's, this function interprets the one value returned from the
6529 * register to the minimum and maximum range. 4843 * register to the minimum and maximum range.
6530 * For IGP phy's, the function calculates the range by the AGC registers. 4844 * For IGP phy's, the function calculates the range by the AGC registers.
6531 *****************************************************************************/ 4845 */
6532static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 4846static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
6533 u16 *max_length) 4847 u16 *max_length)
6534{ 4848{
6535 s32 ret_val; 4849 s32 ret_val;
6536 u16 agc_value = 0; 4850 u16 agc_value = 0;
6537 u16 i, phy_data; 4851 u16 i, phy_data;
6538 u16 cable_length; 4852 u16 cable_length;
6539 4853
6540 DEBUGFUNC("e1000_get_cable_length"); 4854 DEBUGFUNC("e1000_get_cable_length");
6541 4855
6542 *min_length = *max_length = 0; 4856 *min_length = *max_length = 0;
6543 4857
6544 /* Use old method for Phy older than IGP */ 4858 /* Use old method for Phy older than IGP */
6545 if (hw->phy_type == e1000_phy_m88) { 4859 if (hw->phy_type == e1000_phy_m88) {
6546 4860
6547 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 4861 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6548 &phy_data); 4862 &phy_data);
6549 if (ret_val) 4863 if (ret_val)
6550 return ret_val; 4864 return ret_val;
6551 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4865 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6552 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 4866 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6553 4867
6554 /* Convert the enum value to ranged values */ 4868 /* Convert the enum value to ranged values */
6555 switch (cable_length) { 4869 switch (cable_length) {
6556 case e1000_cable_length_50: 4870 case e1000_cable_length_50:
6557 *min_length = 0; 4871 *min_length = 0;
6558 *max_length = e1000_igp_cable_length_50; 4872 *max_length = e1000_igp_cable_length_50;
6559 break; 4873 break;
6560 case e1000_cable_length_50_80: 4874 case e1000_cable_length_50_80:
6561 *min_length = e1000_igp_cable_length_50; 4875 *min_length = e1000_igp_cable_length_50;
6562 *max_length = e1000_igp_cable_length_80; 4876 *max_length = e1000_igp_cable_length_80;
6563 break; 4877 break;
6564 case e1000_cable_length_80_110: 4878 case e1000_cable_length_80_110:
6565 *min_length = e1000_igp_cable_length_80; 4879 *min_length = e1000_igp_cable_length_80;
6566 *max_length = e1000_igp_cable_length_110; 4880 *max_length = e1000_igp_cable_length_110;
6567 break; 4881 break;
6568 case e1000_cable_length_110_140: 4882 case e1000_cable_length_110_140:
6569 *min_length = e1000_igp_cable_length_110; 4883 *min_length = e1000_igp_cable_length_110;
6570 *max_length = e1000_igp_cable_length_140; 4884 *max_length = e1000_igp_cable_length_140;
6571 break; 4885 break;
6572 case e1000_cable_length_140: 4886 case e1000_cable_length_140:
6573 *min_length = e1000_igp_cable_length_140; 4887 *min_length = e1000_igp_cable_length_140;
6574 *max_length = e1000_igp_cable_length_170; 4888 *max_length = e1000_igp_cable_length_170;
6575 break; 4889 break;
6576 default: 4890 default:
6577 return -E1000_ERR_PHY; 4891 return -E1000_ERR_PHY;
6578 break; 4892 break;
6579 } 4893 }
6580 } else if (hw->phy_type == e1000_phy_gg82563) { 4894 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6581 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 4895 u16 cur_agc_value;
6582 &phy_data); 4896 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6583 if (ret_val) 4897 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6584 return ret_val; 4898 { IGP01E1000_PHY_AGC_A,
6585 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 4899 IGP01E1000_PHY_AGC_B,
6586 4900 IGP01E1000_PHY_AGC_C,
6587 switch (cable_length) { 4901 IGP01E1000_PHY_AGC_D
6588 case e1000_gg_cable_length_60: 4902 };
6589 *min_length = 0; 4903 /* Read the AGC registers for all channels */
6590 *max_length = e1000_igp_cable_length_60; 4904 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6591 break; 4905
6592 case e1000_gg_cable_length_60_115: 4906 ret_val =
6593 *min_length = e1000_igp_cable_length_60; 4907 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6594 *max_length = e1000_igp_cable_length_115; 4908 if (ret_val)
6595 break; 4909 return ret_val;
6596 case e1000_gg_cable_length_115_150: 4910
6597 *min_length = e1000_igp_cable_length_115; 4911 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6598 *max_length = e1000_igp_cable_length_150; 4912
6599 break; 4913 /* Value bound check. */
6600 case e1000_gg_cable_length_150: 4914 if ((cur_agc_value >=
6601 *min_length = e1000_igp_cable_length_150; 4915 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
6602 *max_length = e1000_igp_cable_length_180; 4916 || (cur_agc_value == 0))
6603 break; 4917 return -E1000_ERR_PHY;
6604 default: 4918
6605 return -E1000_ERR_PHY; 4919 agc_value += cur_agc_value;
6606 break; 4920
6607 } 4921 /* Update minimal AGC value. */
6608 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 4922 if (min_agc_value > cur_agc_value)
6609 u16 cur_agc_value; 4923 min_agc_value = cur_agc_value;
6610 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 4924 }
6611 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 4925
6612 {IGP01E1000_PHY_AGC_A, 4926 /* Remove the minimal AGC result for length < 50m */
6613 IGP01E1000_PHY_AGC_B, 4927 if (agc_value <
6614 IGP01E1000_PHY_AGC_C, 4928 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6615 IGP01E1000_PHY_AGC_D}; 4929 agc_value -= min_agc_value;
6616 /* Read the AGC registers for all channels */ 4930
6617 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 4931 /* Get the average length of the remaining 3 channels */
6618 4932 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6619 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 4933 } else {
6620 if (ret_val) 4934 /* Get the average length of all the 4 channels. */
6621 return ret_val; 4935 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6622 4936 }
6623 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 4937
6624 4938 /* Set the range of the calculated length. */
6625 /* Value bound check. */ 4939 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6626 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 4940 IGP01E1000_AGC_RANGE) > 0) ?
6627 (cur_agc_value == 0)) 4941 (e1000_igp_cable_length_table[agc_value] -
6628 return -E1000_ERR_PHY; 4942 IGP01E1000_AGC_RANGE) : 0;
6629 4943 *max_length = e1000_igp_cable_length_table[agc_value] +
6630 agc_value += cur_agc_value; 4944 IGP01E1000_AGC_RANGE;
6631 4945 }
6632 /* Update minimal AGC value. */ 4946
6633 if (min_agc_value > cur_agc_value) 4947 return E1000_SUCCESS;
6634 min_agc_value = cur_agc_value;
6635 }
6636
6637 /* Remove the minimal AGC result for length < 50m */
6638 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6639 agc_value -= min_agc_value;
6640
6641 /* Get the average length of the remaining 3 channels */
6642 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6643 } else {
6644 /* Get the average length of all the 4 channels. */
6645 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6646 }
6647
6648 /* Set the range of the calculated length. */
6649 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6650 IGP01E1000_AGC_RANGE) > 0) ?
6651 (e1000_igp_cable_length_table[agc_value] -
6652 IGP01E1000_AGC_RANGE) : 0;
6653 *max_length = e1000_igp_cable_length_table[agc_value] +
6654 IGP01E1000_AGC_RANGE;
6655 } else if (hw->phy_type == e1000_phy_igp_2 ||
6656 hw->phy_type == e1000_phy_igp_3) {
6657 u16 cur_agc_index, max_agc_index = 0;
6658 u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6659 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6660 {IGP02E1000_PHY_AGC_A,
6661 IGP02E1000_PHY_AGC_B,
6662 IGP02E1000_PHY_AGC_C,
6663 IGP02E1000_PHY_AGC_D};
6664 /* Read the AGC registers for all channels */
6665 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6666 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6667 if (ret_val)
6668 return ret_val;
6669
6670 /* Getting bits 15:9, which represent the combination of course and
6671 * fine gain values. The result is a number that can be put into
6672 * the lookup table to obtain the approximate cable length. */
6673 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6674 IGP02E1000_AGC_LENGTH_MASK;
6675
6676 /* Array index bound check. */
6677 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6678 (cur_agc_index == 0))
6679 return -E1000_ERR_PHY;
6680
6681 /* Remove min & max AGC values from calculation. */
6682 if (e1000_igp_2_cable_length_table[min_agc_index] >
6683 e1000_igp_2_cable_length_table[cur_agc_index])
6684 min_agc_index = cur_agc_index;
6685 if (e1000_igp_2_cable_length_table[max_agc_index] <
6686 e1000_igp_2_cable_length_table[cur_agc_index])
6687 max_agc_index = cur_agc_index;
6688
6689 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6690 }
6691
6692 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6693 e1000_igp_2_cable_length_table[max_agc_index]);
6694 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6695
6696 /* Calculate cable length with the error range of +/- 10 meters. */
6697 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6698 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6699 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6700 }
6701
6702 return E1000_SUCCESS;
6703} 4948}
6704 4949
6705/****************************************************************************** 4950/**
6706 * Check the cable polarity 4951 * e1000_check_polarity - Check the cable polarity
6707 * 4952 * @hw: Struct containing variables accessed by shared code
6708 * hw - Struct containing variables accessed by shared code 4953 * @polarity: output parameter : 0 - Polarity is not reversed
6709 * polarity - output parameter : 0 - Polarity is not reversed
6710 * 1 - Polarity is reversed. 4954 * 1 - Polarity is reversed.
6711 * 4955 *
6712 * returns: - E1000_ERR_XXX 4956 * returns: - E1000_ERR_XXX
@@ -6717,73 +4961,65 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
6717 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 4961 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6718 * return 0. If the link speed is 1000 Mbps the polarity status is in the 4962 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6719 * IGP01E1000_PHY_PCS_INIT_REG. 4963 * IGP01E1000_PHY_PCS_INIT_REG.
6720 *****************************************************************************/ 4964 */
6721static s32 e1000_check_polarity(struct e1000_hw *hw, 4965static s32 e1000_check_polarity(struct e1000_hw *hw,
6722 e1000_rev_polarity *polarity) 4966 e1000_rev_polarity *polarity)
6723{ 4967{
6724 s32 ret_val; 4968 s32 ret_val;
6725 u16 phy_data; 4969 u16 phy_data;
6726 4970
6727 DEBUGFUNC("e1000_check_polarity"); 4971 DEBUGFUNC("e1000_check_polarity");
6728 4972
6729 if ((hw->phy_type == e1000_phy_m88) || 4973 if (hw->phy_type == e1000_phy_m88) {
6730 (hw->phy_type == e1000_phy_gg82563)) { 4974 /* return the Polarity bit in the Status register. */
6731 /* return the Polarity bit in the Status register. */ 4975 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6732 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 4976 &phy_data);
6733 &phy_data); 4977 if (ret_val)
6734 if (ret_val) 4978 return ret_val;
6735 return ret_val; 4979 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6736 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 4980 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6737 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 4981 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6738 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 4982
6739 4983 } else if (hw->phy_type == e1000_phy_igp) {
6740 } else if (hw->phy_type == e1000_phy_igp || 4984 /* Read the Status register to check the speed */
6741 hw->phy_type == e1000_phy_igp_3 || 4985 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6742 hw->phy_type == e1000_phy_igp_2) { 4986 &phy_data);
6743 /* Read the Status register to check the speed */ 4987 if (ret_val)
6744 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 4988 return ret_val;
6745 &phy_data); 4989
6746 if (ret_val) 4990 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6747 return ret_val; 4991 * find the polarity status */
6748 4992 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6749 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 4993 IGP01E1000_PSSR_SPEED_1000MBPS) {
6750 * find the polarity status */ 4994
6751 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4995 /* Read the GIG initialization PCS register (0x00B4) */
6752 IGP01E1000_PSSR_SPEED_1000MBPS) { 4996 ret_val =
6753 4997 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6754 /* Read the GIG initialization PCS register (0x00B4) */ 4998 &phy_data);
6755 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 4999 if (ret_val)
6756 &phy_data); 5000 return ret_val;
6757 if (ret_val) 5001
6758 return ret_val; 5002 /* Check the polarity bits */
6759 5003 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6760 /* Check the polarity bits */ 5004 e1000_rev_polarity_reversed :
6761 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 5005 e1000_rev_polarity_normal;
6762 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5006 } else {
6763 } else { 5007 /* For 10 Mbps, read the polarity bit in the status register. (for
6764 /* For 10 Mbps, read the polarity bit in the status register. (for 5008 * 100 Mbps this bit is always 0) */
6765 * 100 Mbps this bit is always 0) */ 5009 *polarity =
6766 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 5010 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6767 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5011 e1000_rev_polarity_reversed :
6768 } 5012 e1000_rev_polarity_normal;
6769 } else if (hw->phy_type == e1000_phy_ife) { 5013 }
6770 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, 5014 }
6771 &phy_data); 5015 return E1000_SUCCESS;
6772 if (ret_val)
6773 return ret_val;
6774 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6775 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6776 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6777 }
6778 return E1000_SUCCESS;
6779} 5016}
6780 5017
6781/****************************************************************************** 5018/**
6782 * Check if Downshift occured 5019 * e1000_check_downshift - Check if Downshift occurred
6783 * 5020 * @hw: Struct containing variables accessed by shared code
6784 * hw - Struct containing variables accessed by shared code 5021 * @downshift: output parameter : 0 - No Downshift occurred.
6785 * downshift - output parameter : 0 - No Downshift ocured. 5022 * 1 - Downshift occurred.
6786 * 1 - Downshift ocured.
6787 * 5023 *
6788 * returns: - E1000_ERR_XXX 5024 * returns: - E1000_ERR_XXX
6789 * E1000_SUCCESS 5025 * E1000_SUCCESS
@@ -6792,2041 +5028,607 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
6792 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 5028 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6793 * Link Health register. In IGP this bit is latched high, so the driver must 5029 * Link Health register. In IGP this bit is latched high, so the driver must
6794 * read it immediately after link is established. 5030 * read it immediately after link is established.
6795 *****************************************************************************/ 5031 */
6796static s32 e1000_check_downshift(struct e1000_hw *hw) 5032static s32 e1000_check_downshift(struct e1000_hw *hw)
6797{ 5033{
6798 s32 ret_val; 5034 s32 ret_val;
6799 u16 phy_data; 5035 u16 phy_data;
6800
6801 DEBUGFUNC("e1000_check_downshift");
6802
6803 if (hw->phy_type == e1000_phy_igp ||
6804 hw->phy_type == e1000_phy_igp_3 ||
6805 hw->phy_type == e1000_phy_igp_2) {
6806 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6807 &phy_data);
6808 if (ret_val)
6809 return ret_val;
6810
6811 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6812 } else if ((hw->phy_type == e1000_phy_m88) ||
6813 (hw->phy_type == e1000_phy_gg82563)) {
6814 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6815 &phy_data);
6816 if (ret_val)
6817 return ret_val;
6818
6819 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6820 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6821 } else if (hw->phy_type == e1000_phy_ife) {
6822 /* e1000_phy_ife supports 10/100 speed only */
6823 hw->speed_downgraded = false;
6824 }
6825
6826 return E1000_SUCCESS;
6827}
6828 5036
6829/***************************************************************************** 5037 DEBUGFUNC("e1000_check_downshift");
6830 *
6831 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6832 * gigabit link is achieved to improve link quality.
6833 *
6834 * hw: Struct containing variables accessed by shared code
6835 *
6836 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6837 * E1000_SUCCESS at any other case.
6838 *
6839 ****************************************************************************/
6840 5038
6841static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 5039 if (hw->phy_type == e1000_phy_igp) {
6842{ 5040 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6843 s32 ret_val; 5041 &phy_data);
6844 u16 phy_data, phy_saved_data, speed, duplex, i; 5042 if (ret_val)
6845 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 5043 return ret_val;
6846 {IGP01E1000_PHY_AGC_PARAM_A,
6847 IGP01E1000_PHY_AGC_PARAM_B,
6848 IGP01E1000_PHY_AGC_PARAM_C,
6849 IGP01E1000_PHY_AGC_PARAM_D};
6850 u16 min_length, max_length;
6851
6852 DEBUGFUNC("e1000_config_dsp_after_link_change");
6853
6854 if (hw->phy_type != e1000_phy_igp)
6855 return E1000_SUCCESS;
6856
6857 if (link_up) {
6858 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6859 if (ret_val) {
6860 DEBUGOUT("Error getting link speed and duplex\n");
6861 return ret_val;
6862 }
6863
6864 if (speed == SPEED_1000) {
6865
6866 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6867 if (ret_val)
6868 return ret_val;
6869
6870 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6871 min_length >= e1000_igp_cable_length_50) {
6872
6873 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6874 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6875 &phy_data);
6876 if (ret_val)
6877 return ret_val;
6878
6879 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6880
6881 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6882 phy_data);
6883 if (ret_val)
6884 return ret_val;
6885 }
6886 hw->dsp_config_state = e1000_dsp_config_activated;
6887 }
6888
6889 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6890 (min_length < e1000_igp_cable_length_50)) {
6891
6892 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
6893 u32 idle_errs = 0;
6894
6895 /* clear previous idle error counts */
6896 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6897 &phy_data);
6898 if (ret_val)
6899 return ret_val;
6900
6901 for (i = 0; i < ffe_idle_err_timeout; i++) {
6902 udelay(1000);
6903 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6904 &phy_data);
6905 if (ret_val)
6906 return ret_val;
6907
6908 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
6909 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
6910 hw->ffe_config_state = e1000_ffe_config_active;
6911
6912 ret_val = e1000_write_phy_reg(hw,
6913 IGP01E1000_PHY_DSP_FFE,
6914 IGP01E1000_PHY_DSP_FFE_CM_CP);
6915 if (ret_val)
6916 return ret_val;
6917 break;
6918 }
6919
6920 if (idle_errs)
6921 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
6922 }
6923 }
6924 }
6925 } else {
6926 if (hw->dsp_config_state == e1000_dsp_config_activated) {
6927 /* Save off the current value of register 0x2F5B to be restored at
6928 * the end of the routines. */
6929 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6930
6931 if (ret_val)
6932 return ret_val;
6933
6934 /* Disable the PHY transmitter */
6935 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6936
6937 if (ret_val)
6938 return ret_val;
6939
6940 mdelay(20);
6941
6942 ret_val = e1000_write_phy_reg(hw, 0x0000,
6943 IGP01E1000_IEEE_FORCE_GIGA);
6944 if (ret_val)
6945 return ret_val;
6946 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6947 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
6948 if (ret_val)
6949 return ret_val;
6950
6951 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6952 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
6953
6954 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
6955 if (ret_val)
6956 return ret_val;
6957 }
6958
6959 ret_val = e1000_write_phy_reg(hw, 0x0000,
6960 IGP01E1000_IEEE_RESTART_AUTONEG);
6961 if (ret_val)
6962 return ret_val;
6963
6964 mdelay(20);
6965
6966 /* Now enable the transmitter */
6967 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
6968
6969 if (ret_val)
6970 return ret_val;
6971
6972 hw->dsp_config_state = e1000_dsp_config_enabled;
6973 }
6974
6975 if (hw->ffe_config_state == e1000_ffe_config_active) {
6976 /* Save off the current value of register 0x2F5B to be restored at
6977 * the end of the routines. */
6978 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6979
6980 if (ret_val)
6981 return ret_val;
6982
6983 /* Disable the PHY transmitter */
6984 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6985
6986 if (ret_val)
6987 return ret_val;
6988
6989 mdelay(20);
6990
6991 ret_val = e1000_write_phy_reg(hw, 0x0000,
6992 IGP01E1000_IEEE_FORCE_GIGA);
6993 if (ret_val)
6994 return ret_val;
6995 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
6996 IGP01E1000_PHY_DSP_FFE_DEFAULT);
6997 if (ret_val)
6998 return ret_val;
6999
7000 ret_val = e1000_write_phy_reg(hw, 0x0000,
7001 IGP01E1000_IEEE_RESTART_AUTONEG);
7002 if (ret_val)
7003 return ret_val;
7004
7005 mdelay(20);
7006
7007 /* Now enable the transmitter */
7008 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7009
7010 if (ret_val)
7011 return ret_val;
7012
7013 hw->ffe_config_state = e1000_ffe_config_enabled;
7014 }
7015 }
7016 return E1000_SUCCESS;
7017}
7018 5044
7019/***************************************************************************** 5045 hw->speed_downgraded =
7020 * Set PHY to class A mode 5046 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
7021 * Assumes the following operations will follow to enable the new class mode. 5047 } else if (hw->phy_type == e1000_phy_m88) {
7022 * 1. Do a PHY soft reset 5048 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7023 * 2. Restart auto-negotiation or force link. 5049 &phy_data);
7024 * 5050 if (ret_val)
7025 * hw - Struct containing variables accessed by shared code 5051 return ret_val;
7026 ****************************************************************************/
7027static s32 e1000_set_phy_mode(struct e1000_hw *hw)
7028{
7029 s32 ret_val;
7030 u16 eeprom_data;
7031
7032 DEBUGFUNC("e1000_set_phy_mode");
7033
7034 if ((hw->mac_type == e1000_82545_rev_3) &&
7035 (hw->media_type == e1000_media_type_copper)) {
7036 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7037 if (ret_val) {
7038 return ret_val;
7039 }
7040
7041 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7042 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7043 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7044 if (ret_val)
7045 return ret_val;
7046 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7047 if (ret_val)
7048 return ret_val;
7049
7050 hw->phy_reset_disable = false;
7051 }
7052 }
7053
7054 return E1000_SUCCESS;
7055}
7056 5052
7057/***************************************************************************** 5053 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
7058 * 5054 M88E1000_PSSR_DOWNSHIFT_SHIFT;
7059 * This function sets the lplu state according to the active flag. When 5055 }
7060 * activating lplu this function also disables smart speed and vise versa.
7061 * lplu will not be activated unless the device autonegotiation advertisment
7062 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7063 * hw: Struct containing variables accessed by shared code
7064 * active - true to enable lplu false to disable lplu.
7065 *
7066 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7067 * E1000_SUCCESS at any other case.
7068 *
7069 ****************************************************************************/
7070 5056
7071static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5057 return E1000_SUCCESS;
7072{
7073 u32 phy_ctrl = 0;
7074 s32 ret_val;
7075 u16 phy_data;
7076 DEBUGFUNC("e1000_set_d3_lplu_state");
7077
7078 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7079 && hw->phy_type != e1000_phy_igp_3)
7080 return E1000_SUCCESS;
7081
7082 /* During driver activity LPLU should not be used or it will attain link
7083 * from the lowest speeds starting from 10Mbps. The capability is used for
7084 * Dx transitions and states */
7085 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7086 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7087 if (ret_val)
7088 return ret_val;
7089 } else if (hw->mac_type == e1000_ich8lan) {
7090 /* MAC writes into PHY register based on the state transition
7091 * and start auto-negotiation. SW driver can overwrite the settings
7092 * in CSR PHY power control E1000_PHY_CTRL register. */
7093 phy_ctrl = er32(PHY_CTRL);
7094 } else {
7095 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7096 if (ret_val)
7097 return ret_val;
7098 }
7099
7100 if (!active) {
7101 if (hw->mac_type == e1000_82541_rev_2 ||
7102 hw->mac_type == e1000_82547_rev_2) {
7103 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7104 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7105 if (ret_val)
7106 return ret_val;
7107 } else {
7108 if (hw->mac_type == e1000_ich8lan) {
7109 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7110 ew32(PHY_CTRL, phy_ctrl);
7111 } else {
7112 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7113 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7114 phy_data);
7115 if (ret_val)
7116 return ret_val;
7117 }
7118 }
7119
7120 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7121 * Dx states where the power conservation is most important. During
7122 * driver activity we should enable SmartSpeed, so performance is
7123 * maintained. */
7124 if (hw->smart_speed == e1000_smart_speed_on) {
7125 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7126 &phy_data);
7127 if (ret_val)
7128 return ret_val;
7129
7130 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7131 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7132 phy_data);
7133 if (ret_val)
7134 return ret_val;
7135 } else if (hw->smart_speed == e1000_smart_speed_off) {
7136 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7137 &phy_data);
7138 if (ret_val)
7139 return ret_val;
7140
7141 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7142 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7143 phy_data);
7144 if (ret_val)
7145 return ret_val;
7146 }
7147
7148 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7149 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7150 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7151
7152 if (hw->mac_type == e1000_82541_rev_2 ||
7153 hw->mac_type == e1000_82547_rev_2) {
7154 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7155 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7156 if (ret_val)
7157 return ret_val;
7158 } else {
7159 if (hw->mac_type == e1000_ich8lan) {
7160 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7161 ew32(PHY_CTRL, phy_ctrl);
7162 } else {
7163 phy_data |= IGP02E1000_PM_D3_LPLU;
7164 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7165 phy_data);
7166 if (ret_val)
7167 return ret_val;
7168 }
7169 }
7170
7171 /* When LPLU is enabled we should disable SmartSpeed */
7172 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7173 if (ret_val)
7174 return ret_val;
7175
7176 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7177 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7178 if (ret_val)
7179 return ret_val;
7180
7181 }
7182 return E1000_SUCCESS;
7183} 5058}
7184 5059
7185/***************************************************************************** 5060/**
7186 * 5061 * e1000_config_dsp_after_link_change
7187 * This function sets the lplu d0 state according to the active flag. When 5062 * @hw: Struct containing variables accessed by shared code
7188 * activating lplu this function also disables smart speed and vise versa. 5063 * @link_up: was link up at the time this was called
7189 * lplu will not be activated unless the device autonegotiation advertisment
7190 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7191 * hw: Struct containing variables accessed by shared code
7192 * active - true to enable lplu false to disable lplu.
7193 * 5064 *
7194 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5065 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7195 * E1000_SUCCESS at any other case. 5066 * E1000_SUCCESS at any other case.
7196 * 5067 *
7197 ****************************************************************************/ 5068 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
7198 5069 * gigabit link is achieved to improve link quality.
7199static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) 5070 */
7200{
7201 u32 phy_ctrl = 0;
7202 s32 ret_val;
7203 u16 phy_data;
7204 DEBUGFUNC("e1000_set_d0_lplu_state");
7205
7206 if (hw->mac_type <= e1000_82547_rev_2)
7207 return E1000_SUCCESS;
7208
7209 if (hw->mac_type == e1000_ich8lan) {
7210 phy_ctrl = er32(PHY_CTRL);
7211 } else {
7212 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7213 if (ret_val)
7214 return ret_val;
7215 }
7216
7217 if (!active) {
7218 if (hw->mac_type == e1000_ich8lan) {
7219 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7220 ew32(PHY_CTRL, phy_ctrl);
7221 } else {
7222 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7223 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7224 if (ret_val)
7225 return ret_val;
7226 }
7227
7228 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7229 * Dx states where the power conservation is most important. During
7230 * driver activity we should enable SmartSpeed, so performance is
7231 * maintained. */
7232 if (hw->smart_speed == e1000_smart_speed_on) {
7233 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7234 &phy_data);
7235 if (ret_val)
7236 return ret_val;
7237
7238 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7239 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7240 phy_data);
7241 if (ret_val)
7242 return ret_val;
7243 } else if (hw->smart_speed == e1000_smart_speed_off) {
7244 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7245 &phy_data);
7246 if (ret_val)
7247 return ret_val;
7248
7249 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7250 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7251 phy_data);
7252 if (ret_val)
7253 return ret_val;
7254 }
7255
7256
7257 } else {
7258
7259 if (hw->mac_type == e1000_ich8lan) {
7260 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7261 ew32(PHY_CTRL, phy_ctrl);
7262 } else {
7263 phy_data |= IGP02E1000_PM_D0_LPLU;
7264 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7265 if (ret_val)
7266 return ret_val;
7267 }
7268
7269 /* When LPLU is enabled we should disable SmartSpeed */
7270 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7271 if (ret_val)
7272 return ret_val;
7273
7274 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7275 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7276 if (ret_val)
7277 return ret_val;
7278
7279 }
7280 return E1000_SUCCESS;
7281}
7282 5071
7283/****************************************************************************** 5072static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
7284 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7285 *
7286 * hw - Struct containing variables accessed by shared code
7287 *****************************************************************************/
7288static s32 e1000_set_vco_speed(struct e1000_hw *hw)
7289{ 5073{
7290 s32 ret_val; 5074 s32 ret_val;
7291 u16 default_page = 0; 5075 u16 phy_data, phy_saved_data, speed, duplex, i;
7292 u16 phy_data; 5076 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7293 5077 { IGP01E1000_PHY_AGC_PARAM_A,
7294 DEBUGFUNC("e1000_set_vco_speed"); 5078 IGP01E1000_PHY_AGC_PARAM_B,
5079 IGP01E1000_PHY_AGC_PARAM_C,
5080 IGP01E1000_PHY_AGC_PARAM_D
5081 };
5082 u16 min_length, max_length;
5083
5084 DEBUGFUNC("e1000_config_dsp_after_link_change");
5085
5086 if (hw->phy_type != e1000_phy_igp)
5087 return E1000_SUCCESS;
5088
5089 if (link_up) {
5090 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5091 if (ret_val) {
5092 DEBUGOUT("Error getting link speed and duplex\n");
5093 return ret_val;
5094 }
7295 5095
7296 switch (hw->mac_type) { 5096 if (speed == SPEED_1000) {
7297 case e1000_82545_rev_3: 5097
7298 case e1000_82546_rev_3: 5098 ret_val =
7299 break; 5099 e1000_get_cable_length(hw, &min_length,
7300 default: 5100 &max_length);
7301 return E1000_SUCCESS; 5101 if (ret_val)
7302 } 5102 return ret_val;
5103
5104 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5105 && min_length >= e1000_igp_cable_length_50) {
5106
5107 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5108 ret_val =
5109 e1000_read_phy_reg(hw,
5110 dsp_reg_array[i],
5111 &phy_data);
5112 if (ret_val)
5113 return ret_val;
5114
5115 phy_data &=
5116 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5117
5118 ret_val =
5119 e1000_write_phy_reg(hw,
5120 dsp_reg_array
5121 [i], phy_data);
5122 if (ret_val)
5123 return ret_val;
5124 }
5125 hw->dsp_config_state =
5126 e1000_dsp_config_activated;
5127 }
5128
5129 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5130 && (min_length < e1000_igp_cable_length_50)) {
5131
5132 u16 ffe_idle_err_timeout =
5133 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5134 u32 idle_errs = 0;
5135
5136 /* clear previous idle error counts */
5137 ret_val =
5138 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5139 &phy_data);
5140 if (ret_val)
5141 return ret_val;
5142
5143 for (i = 0; i < ffe_idle_err_timeout; i++) {
5144 udelay(1000);
5145 ret_val =
5146 e1000_read_phy_reg(hw,
5147 PHY_1000T_STATUS,
5148 &phy_data);
5149 if (ret_val)
5150 return ret_val;
5151
5152 idle_errs +=
5153 (phy_data &
5154 SR_1000T_IDLE_ERROR_CNT);
5155 if (idle_errs >
5156 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5157 {
5158 hw->ffe_config_state =
5159 e1000_ffe_config_active;
5160
5161 ret_val =
5162 e1000_write_phy_reg(hw,
5163 IGP01E1000_PHY_DSP_FFE,
5164 IGP01E1000_PHY_DSP_FFE_CM_CP);
5165 if (ret_val)
5166 return ret_val;
5167 break;
5168 }
5169
5170 if (idle_errs)
5171 ffe_idle_err_timeout =
5172 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5173 }
5174 }
5175 }
5176 } else {
5177 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5178 /* Save off the current value of register 0x2F5B to be restored at
5179 * the end of the routines. */
5180 ret_val =
5181 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5182
5183 if (ret_val)
5184 return ret_val;
5185
5186 /* Disable the PHY transmitter */
5187 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5188
5189 if (ret_val)
5190 return ret_val;
5191
5192 mdelay(20);
5193
5194 ret_val = e1000_write_phy_reg(hw, 0x0000,
5195 IGP01E1000_IEEE_FORCE_GIGA);
5196 if (ret_val)
5197 return ret_val;
5198 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5199 ret_val =
5200 e1000_read_phy_reg(hw, dsp_reg_array[i],
5201 &phy_data);
5202 if (ret_val)
5203 return ret_val;
5204
5205 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5206 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5207
5208 ret_val =
5209 e1000_write_phy_reg(hw, dsp_reg_array[i],
5210 phy_data);
5211 if (ret_val)
5212 return ret_val;
5213 }
5214
5215 ret_val = e1000_write_phy_reg(hw, 0x0000,
5216 IGP01E1000_IEEE_RESTART_AUTONEG);
5217 if (ret_val)
5218 return ret_val;
5219
5220 mdelay(20);
5221
5222 /* Now enable the transmitter */
5223 ret_val =
5224 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5225
5226 if (ret_val)
5227 return ret_val;
5228
5229 hw->dsp_config_state = e1000_dsp_config_enabled;
5230 }
7303 5231
7304 /* Set PHY register 30, page 5, bit 8 to 0 */ 5232 if (hw->ffe_config_state == e1000_ffe_config_active) {
5233 /* Save off the current value of register 0x2F5B to be restored at
5234 * the end of the routines. */
5235 ret_val =
5236 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7305 5237
7306 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 5238 if (ret_val)
7307 if (ret_val) 5239 return ret_val;
7308 return ret_val;
7309 5240
7310 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 5241 /* Disable the PHY transmitter */
7311 if (ret_val) 5242 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7312 return ret_val;
7313 5243
7314 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5244 if (ret_val)
7315 if (ret_val) 5245 return ret_val;
7316 return ret_val;
7317 5246
7318 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 5247 mdelay(20);
7319 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7320 if (ret_val)
7321 return ret_val;
7322 5248
7323 /* Set PHY register 30, page 4, bit 11 to 1 */ 5249 ret_val = e1000_write_phy_reg(hw, 0x0000,
5250 IGP01E1000_IEEE_FORCE_GIGA);
5251 if (ret_val)
5252 return ret_val;
5253 ret_val =
5254 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5255 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5256 if (ret_val)
5257 return ret_val;
7324 5258
7325 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 5259 ret_val = e1000_write_phy_reg(hw, 0x0000,
7326 if (ret_val) 5260 IGP01E1000_IEEE_RESTART_AUTONEG);
7327 return ret_val; 5261 if (ret_val)
5262 return ret_val;
7328 5263
7329 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5264 mdelay(20);
7330 if (ret_val)
7331 return ret_val;
7332 5265
7333 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 5266 /* Now enable the transmitter */
7334 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5267 ret_val =
7335 if (ret_val) 5268 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7336 return ret_val;
7337 5269
7338 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 5270 if (ret_val)
7339 if (ret_val) 5271 return ret_val;
7340 return ret_val;
7341 5272
7342 return E1000_SUCCESS; 5273 hw->ffe_config_state = e1000_ffe_config_enabled;
5274 }
5275 }
5276 return E1000_SUCCESS;
7343} 5277}
7344 5278
7345 5279/**
7346/***************************************************************************** 5280 * e1000_set_phy_mode - Set PHY to class A mode
7347 * This function reads the cookie from ARC ram. 5281 * @hw: Struct containing variables accessed by shared code
7348 * 5282 *
7349 * returns: - E1000_SUCCESS . 5283 * Assumes the following operations will follow to enable the new class mode.
7350 ****************************************************************************/ 5284 * 1. Do a PHY soft reset
7351static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer) 5285 * 2. Restart auto-negotiation or force link.
5286 */
5287static s32 e1000_set_phy_mode(struct e1000_hw *hw)
7352{ 5288{
7353 u8 i; 5289 s32 ret_val;
7354 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET; 5290 u16 eeprom_data;
7355 u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
7356
7357 length = (length >> 2);
7358 offset = (offset >> 2);
7359
7360 for (i = 0; i < length; i++) {
7361 *((u32 *)buffer + i) =
7362 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7363 }
7364 return E1000_SUCCESS;
7365}
7366 5291
5292 DEBUGFUNC("e1000_set_phy_mode");
7367 5293
7368/***************************************************************************** 5294 if ((hw->mac_type == e1000_82545_rev_3) &&
7369 * This function checks whether the HOST IF is enabled for command operaton 5295 (hw->media_type == e1000_media_type_copper)) {
7370 * and also checks whether the previous command is completed. 5296 ret_val =
7371 * It busy waits in case of previous command is not completed. 5297 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
7372 * 5298 &eeprom_data);
7373 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 5299 if (ret_val) {
7374 * timeout 5300 return ret_val;
7375 * - E1000_SUCCESS for success. 5301 }
7376 ****************************************************************************/
7377static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
7378{
7379 u32 hicr;
7380 u8 i;
7381
7382 /* Check that the host interface is enabled. */
7383 hicr = er32(HICR);
7384 if ((hicr & E1000_HICR_EN) == 0) {
7385 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7386 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7387 }
7388 /* check the previous command is completed */
7389 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7390 hicr = er32(HICR);
7391 if (!(hicr & E1000_HICR_C))
7392 break;
7393 mdelay(1);
7394 }
7395
7396 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7397 DEBUGOUT("Previous command timeout failed .\n");
7398 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7399 }
7400 return E1000_SUCCESS;
7401}
7402 5302
7403/***************************************************************************** 5303 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7404 * This function writes the buffer content at the offset given on the host if. 5304 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7405 * It also does alignment considerations to do the writes in most efficient way. 5305 ret_val =
7406 * Also fills up the sum of the buffer in *buffer parameter. 5306 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
7407 * 5307 0x000B);
7408 * returns - E1000_SUCCESS for success. 5308 if (ret_val)
7409 ****************************************************************************/ 5309 return ret_val;
7410static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, 5310 ret_val =
7411 u16 offset, u8 *sum) 5311 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
7412{ 5312 0x8104);
7413 u8 *tmp; 5313 if (ret_val)
7414 u8 *bufptr = buffer; 5314 return ret_val;
7415 u32 data = 0; 5315
7416 u16 remaining, i, j, prev_bytes; 5316 hw->phy_reset_disable = false;
7417 5317 }
7418 /* sum = only sum of the data and it is not checksum */ 5318 }
7419
7420 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7421 return -E1000_ERR_PARAM;
7422 }
7423
7424 tmp = (u8 *)&data;
7425 prev_bytes = offset & 0x3;
7426 offset &= 0xFFFC;
7427 offset >>= 2;
7428
7429 if (prev_bytes) {
7430 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7431 for (j = prev_bytes; j < sizeof(u32); j++) {
7432 *(tmp + j) = *bufptr++;
7433 *sum += *(tmp + j);
7434 }
7435 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7436 length -= j - prev_bytes;
7437 offset++;
7438 }
7439
7440 remaining = length & 0x3;
7441 length -= remaining;
7442
7443 /* Calculate length in DWORDs */
7444 length >>= 2;
7445
7446 /* The device driver writes the relevant command block into the
7447 * ram area. */
7448 for (i = 0; i < length; i++) {
7449 for (j = 0; j < sizeof(u32); j++) {
7450 *(tmp + j) = *bufptr++;
7451 *sum += *(tmp + j);
7452 }
7453
7454 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7455 }
7456 if (remaining) {
7457 for (j = 0; j < sizeof(u32); j++) {
7458 if (j < remaining)
7459 *(tmp + j) = *bufptr++;
7460 else
7461 *(tmp + j) = 0;
7462
7463 *sum += *(tmp + j);
7464 }
7465 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7466 }
7467
7468 return E1000_SUCCESS;
7469}
7470 5319
5320 return E1000_SUCCESS;
5321}
7471 5322
7472/***************************************************************************** 5323/**
7473 * This function writes the command header after does the checksum calculation. 5324 * e1000_set_d3_lplu_state - set d3 link power state
5325 * @hw: Struct containing variables accessed by shared code
5326 * @active: true to enable lplu false to disable lplu.
5327 *
5328 * This function sets the lplu state according to the active flag. When
5329 * activating lplu this function also disables smart speed and vise versa.
5330 * lplu will not be activated unless the device autonegotiation advertisement
5331 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7474 * 5332 *
7475 * returns - E1000_SUCCESS for success. 5333 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7476 ****************************************************************************/ 5334 * E1000_SUCCESS at any other case.
7477static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, 5335 */
7478 struct e1000_host_mng_command_header *hdr) 5336static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7479{ 5337{
7480 u16 i; 5338 s32 ret_val;
7481 u8 sum; 5339 u16 phy_data;
7482 u8 *buffer; 5340 DEBUGFUNC("e1000_set_d3_lplu_state");
7483 5341
7484 /* Write the whole command header structure which includes sum of 5342 if (hw->phy_type != e1000_phy_igp)
7485 * the buffer */ 5343 return E1000_SUCCESS;
7486 5344
7487 u16 length = sizeof(struct e1000_host_mng_command_header); 5345 /* During driver activity LPLU should not be used or it will attain link
5346 * from the lowest speeds starting from 10Mbps. The capability is used for
5347 * Dx transitions and states */
5348 if (hw->mac_type == e1000_82541_rev_2
5349 || hw->mac_type == e1000_82547_rev_2) {
5350 ret_val =
5351 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5352 if (ret_val)
5353 return ret_val;
5354 }
7488 5355
7489 sum = hdr->checksum; 5356 if (!active) {
7490 hdr->checksum = 0; 5357 if (hw->mac_type == e1000_82541_rev_2 ||
5358 hw->mac_type == e1000_82547_rev_2) {
5359 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5360 ret_val =
5361 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5362 phy_data);
5363 if (ret_val)
5364 return ret_val;
5365 }
7491 5366
7492 buffer = (u8 *)hdr; 5367 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7493 i = length; 5368 * Dx states where the power conservation is most important. During
7494 while (i--) 5369 * driver activity we should enable SmartSpeed, so performance is
7495 sum += buffer[i]; 5370 * maintained. */
5371 if (hw->smart_speed == e1000_smart_speed_on) {
5372 ret_val =
5373 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5374 &phy_data);
5375 if (ret_val)
5376 return ret_val;
5377
5378 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5379 ret_val =
5380 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5381 phy_data);
5382 if (ret_val)
5383 return ret_val;
5384 } else if (hw->smart_speed == e1000_smart_speed_off) {
5385 ret_val =
5386 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5387 &phy_data);
5388 if (ret_val)
5389 return ret_val;
5390
5391 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5392 ret_val =
5393 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5394 phy_data);
5395 if (ret_val)
5396 return ret_val;
5397 }
5398 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5399 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5400 || (hw->autoneg_advertised ==
5401 AUTONEG_ADVERTISE_10_100_ALL)) {
5402
5403 if (hw->mac_type == e1000_82541_rev_2 ||
5404 hw->mac_type == e1000_82547_rev_2) {
5405 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5406 ret_val =
5407 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5408 phy_data);
5409 if (ret_val)
5410 return ret_val;
5411 }
7496 5412
7497 hdr->checksum = 0 - sum; 5413 /* When LPLU is enabled we should disable SmartSpeed */
5414 ret_val =
5415 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5416 &phy_data);
5417 if (ret_val)
5418 return ret_val;
7498 5419
7499 length >>= 2; 5420 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7500 /* The device driver writes the relevant command block into the ram area. */ 5421 ret_val =
7501 for (i = 0; i < length; i++) { 5422 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7502 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i)); 5423 phy_data);
7503 E1000_WRITE_FLUSH(); 5424 if (ret_val)
7504 } 5425 return ret_val;
7505 5426
7506 return E1000_SUCCESS; 5427 }
5428 return E1000_SUCCESS;
7507} 5429}
7508 5430
7509 5431/**
7510/***************************************************************************** 5432 * e1000_set_vco_speed
7511 * This function indicates to ARC that a new command is pending which completes 5433 * @hw: Struct containing variables accessed by shared code
7512 * one write operation by the driver.
7513 * 5434 *
7514 * returns - E1000_SUCCESS for success. 5435 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7515 ****************************************************************************/ 5436 */
7516static s32 e1000_mng_write_commit(struct e1000_hw *hw) 5437static s32 e1000_set_vco_speed(struct e1000_hw *hw)
7517{ 5438{
7518 u32 hicr; 5439 s32 ret_val;
5440 u16 default_page = 0;
5441 u16 phy_data;
7519 5442
7520 hicr = er32(HICR); 5443 DEBUGFUNC("e1000_set_vco_speed");
7521 /* Setting this bit tells the ARC that a new command is pending. */
7522 ew32(HICR, hicr | E1000_HICR_C);
7523 5444
7524 return E1000_SUCCESS; 5445 switch (hw->mac_type) {
7525} 5446 case e1000_82545_rev_3:
5447 case e1000_82546_rev_3:
5448 break;
5449 default:
5450 return E1000_SUCCESS;
5451 }
7526 5452
5453 /* Set PHY register 30, page 5, bit 8 to 0 */
7527 5454
7528/***************************************************************************** 5455 ret_val =
7529 * This function checks the mode of the firmware. 5456 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7530 * 5457 if (ret_val)
7531 * returns - true when the mode is IAMT or false. 5458 return ret_val;
7532 ****************************************************************************/
7533bool e1000_check_mng_mode(struct e1000_hw *hw)
7534{
7535 u32 fwsm;
7536
7537 fwsm = er32(FWSM);
7538 5459
7539 if (hw->mac_type == e1000_ich8lan) { 5460 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7540 if ((fwsm & E1000_FWSM_MODE_MASK) == 5461 if (ret_val)
7541 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 5462 return ret_val;
7542 return true;
7543 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7544 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7545 return true;
7546 5463
7547 return false; 5464 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7548} 5465 if (ret_val)
5466 return ret_val;
7549 5467
5468 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5469 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5470 if (ret_val)
5471 return ret_val;
7550 5472
7551/***************************************************************************** 5473 /* Set PHY register 30, page 4, bit 11 to 1 */
7552 * This function writes the dhcp info .
7553 ****************************************************************************/
7554s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
7555{
7556 s32 ret_val;
7557 struct e1000_host_mng_command_header hdr;
7558
7559 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7560 hdr.command_length = length;
7561 hdr.reserved1 = 0;
7562 hdr.reserved2 = 0;
7563 hdr.checksum = 0;
7564
7565 ret_val = e1000_mng_enable_host_if(hw);
7566 if (ret_val == E1000_SUCCESS) {
7567 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7568 &(hdr.checksum));
7569 if (ret_val == E1000_SUCCESS) {
7570 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7571 if (ret_val == E1000_SUCCESS)
7572 ret_val = e1000_mng_write_commit(hw);
7573 }
7574 }
7575 return ret_val;
7576}
7577 5474
5475 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5476 if (ret_val)
5477 return ret_val;
7578 5478
7579/***************************************************************************** 5479 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7580 * This function calculates the checksum. 5480 if (ret_val)
7581 * 5481 return ret_val;
7582 * returns - checksum of buffer contents.
7583 ****************************************************************************/
7584static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
7585{
7586 u8 sum = 0;
7587 u32 i;
7588 5482
7589 if (!buffer) 5483 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7590 return 0; 5484 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5485 if (ret_val)
5486 return ret_val;
7591 5487
7592 for (i=0; i < length; i++) 5488 ret_val =
7593 sum += buffer[i]; 5489 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5490 if (ret_val)
5491 return ret_val;
7594 5492
7595 return (u8)(0 - sum); 5493 return E1000_SUCCESS;
7596} 5494}
7597 5495
7598/*****************************************************************************
7599 * This function checks whether tx pkt filtering needs to be enabled or not.
7600 *
7601 * returns - true for packet filtering or false.
7602 ****************************************************************************/
7603bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7604{
7605 /* called in init as well as watchdog timer functions */
7606
7607 s32 ret_val, checksum;
7608 bool tx_filter = false;
7609 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7610 u8 *buffer = (u8 *) &(hw->mng_cookie);
7611
7612 if (e1000_check_mng_mode(hw)) {
7613 ret_val = e1000_mng_enable_host_if(hw);
7614 if (ret_val == E1000_SUCCESS) {
7615 ret_val = e1000_host_if_read_cookie(hw, buffer);
7616 if (ret_val == E1000_SUCCESS) {
7617 checksum = hdr->checksum;
7618 hdr->checksum = 0;
7619 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7620 checksum == e1000_calculate_mng_checksum((char *)buffer,
7621 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7622 if (hdr->status &
7623 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7624 tx_filter = true;
7625 } else
7626 tx_filter = true;
7627 } else
7628 tx_filter = true;
7629 }
7630 }
7631
7632 hw->tx_pkt_filtering = tx_filter;
7633 return tx_filter;
7634}
7635 5496
7636/****************************************************************************** 5497/**
7637 * Verifies the hardware needs to allow ARPs to be processed by the host 5498 * e1000_enable_mng_pass_thru - check for bmc pass through
7638 * 5499 * @hw: Struct containing variables accessed by shared code
7639 * hw - Struct containing variables accessed by shared code
7640 * 5500 *
5501 * Verifies the hardware needs to allow ARPs to be processed by the host
7641 * returns: - true/false 5502 * returns: - true/false
7642 * 5503 */
7643 *****************************************************************************/
7644u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5504u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7645{ 5505{
7646 u32 manc; 5506 u32 manc;
7647 u32 fwsm, factps;
7648
7649 if (hw->asf_firmware_present) {
7650 manc = er32(MANC);
7651
7652 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7653 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7654 return false;
7655 if (e1000_arc_subsystem_valid(hw)) {
7656 fwsm = er32(FWSM);
7657 factps = er32(FACTPS);
7658
7659 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7660 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7661 return true;
7662 } else
7663 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7664 return true;
7665 }
7666 return false;
7667}
7668 5507
7669static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) 5508 if (hw->asf_firmware_present) {
7670{ 5509 manc = er32(MANC);
7671 s32 ret_val; 5510
7672 u16 mii_status_reg; 5511 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7673 u16 i; 5512 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7674 5513 return false;
7675 /* Polarity reversal workaround for forced 10F/10H links. */ 5514 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7676 5515 return true;
7677 /* Disable the transmitter on the PHY */ 5516 }
7678 5517 return false;
7679 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7680 if (ret_val)
7681 return ret_val;
7682 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7683 if (ret_val)
7684 return ret_val;
7685
7686 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7687 if (ret_val)
7688 return ret_val;
7689
7690 /* This loop will early-out if the NO link condition has been met. */
7691 for (i = PHY_FORCE_TIME; i > 0; i--) {
7692 /* Read the MII Status Register and wait for Link Status bit
7693 * to be clear.
7694 */
7695
7696 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7697 if (ret_val)
7698 return ret_val;
7699
7700 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7701 if (ret_val)
7702 return ret_val;
7703
7704 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7705 mdelay(100);
7706 }
7707
7708 /* Recommended delay time after link has been lost */
7709 mdelay(1000);
7710
7711 /* Now we will re-enable th transmitter on the PHY */
7712
7713 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7714 if (ret_val)
7715 return ret_val;
7716 mdelay(50);
7717 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7718 if (ret_val)
7719 return ret_val;
7720 mdelay(50);
7721 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7722 if (ret_val)
7723 return ret_val;
7724 mdelay(50);
7725 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7726 if (ret_val)
7727 return ret_val;
7728
7729 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7730 if (ret_val)
7731 return ret_val;
7732
7733 /* This loop will early-out if the link condition has been met. */
7734 for (i = PHY_FORCE_TIME; i > 0; i--) {
7735 /* Read the MII Status Register and wait for Link Status bit
7736 * to be set.
7737 */
7738
7739 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7740 if (ret_val)
7741 return ret_val;
7742
7743 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7744 if (ret_val)
7745 return ret_val;
7746
7747 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7748 mdelay(100);
7749 }
7750 return E1000_SUCCESS;
7751} 5518}
7752 5519
7753/*************************************************************************** 5520static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7754 *
7755 * Disables PCI-Express master access.
7756 *
7757 * hw: Struct containing variables accessed by shared code
7758 *
7759 * returns: - none.
7760 *
7761 ***************************************************************************/
7762static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7763{ 5521{
7764 u32 ctrl; 5522 s32 ret_val;
5523 u16 mii_status_reg;
5524 u16 i;
7765 5525
7766 DEBUGFUNC("e1000_set_pci_express_master_disable"); 5526 /* Polarity reversal workaround for forced 10F/10H links. */
7767 5527
7768 if (hw->bus_type != e1000_bus_type_pci_express) 5528 /* Disable the transmitter on the PHY */
7769 return;
7770 5529
7771 ctrl = er32(CTRL); 5530 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7772 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 5531 if (ret_val)
7773 ew32(CTRL, ctrl); 5532 return ret_val;
7774} 5533 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5534 if (ret_val)
5535 return ret_val;
7775 5536
7776/******************************************************************************* 5537 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7777 * 5538 if (ret_val)
7778 * Disables PCI-Express master access and verifies there are no pending requests 5539 return ret_val;
7779 *
7780 * hw: Struct containing variables accessed by shared code
7781 *
7782 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7783 * caused the master requests to be disabled.
7784 * E1000_SUCCESS master requests disabled.
7785 *
7786 ******************************************************************************/
7787s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7788{
7789 s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7790 5540
7791 DEBUGFUNC("e1000_disable_pciex_master"); 5541 /* This loop will early-out if the NO link condition has been met. */
5542 for (i = PHY_FORCE_TIME; i > 0; i--) {
5543 /* Read the MII Status Register and wait for Link Status bit
5544 * to be clear.
5545 */
7792 5546
7793 if (hw->bus_type != e1000_bus_type_pci_express) 5547 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7794 return E1000_SUCCESS; 5548 if (ret_val)
5549 return ret_val;
7795 5550
7796 e1000_set_pci_express_master_disable(hw); 5551 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5552 if (ret_val)
5553 return ret_val;
7797 5554
7798 while (timeout) { 5555 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
7799 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 5556 break;
7800 break; 5557 mdelay(100);
7801 else 5558 }
7802 udelay(100);
7803 timeout--;
7804 }
7805
7806 if (!timeout) {
7807 DEBUGOUT("Master requests are pending.\n");
7808 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7809 }
7810 5559
7811 return E1000_SUCCESS; 5560 /* Recommended delay time after link has been lost */
5561 mdelay(1000);
5562
5563 /* Now we will re-enable th transmitter on the PHY */
5564
5565 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5566 if (ret_val)
5567 return ret_val;
5568 mdelay(50);
5569 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5570 if (ret_val)
5571 return ret_val;
5572 mdelay(50);
5573 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5574 if (ret_val)
5575 return ret_val;
5576 mdelay(50);
5577 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5578 if (ret_val)
5579 return ret_val;
5580
5581 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5582 if (ret_val)
5583 return ret_val;
5584
5585 /* This loop will early-out if the link condition has been met. */
5586 for (i = PHY_FORCE_TIME; i > 0; i--) {
5587 /* Read the MII Status Register and wait for Link Status bit
5588 * to be set.
5589 */
5590
5591 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5592 if (ret_val)
5593 return ret_val;
5594
5595 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5596 if (ret_val)
5597 return ret_val;
5598
5599 if (mii_status_reg & MII_SR_LINK_STATUS)
5600 break;
5601 mdelay(100);
5602 }
5603 return E1000_SUCCESS;
7812} 5604}
7813 5605
7814/******************************************************************************* 5606/**
5607 * e1000_get_auto_rd_done
5608 * @hw: Struct containing variables accessed by shared code
7815 * 5609 *
7816 * Check for EEPROM Auto Read bit done. 5610 * Check for EEPROM Auto Read bit done.
7817 *
7818 * hw: Struct containing variables accessed by shared code
7819 *
7820 * returns: - E1000_ERR_RESET if fail to reset MAC 5611 * returns: - E1000_ERR_RESET if fail to reset MAC
7821 * E1000_SUCCESS at any other case. 5612 * E1000_SUCCESS at any other case.
7822 * 5613 */
7823 ******************************************************************************/
7824static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5614static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7825{ 5615{
7826 s32 timeout = AUTO_READ_DONE_TIMEOUT; 5616 DEBUGFUNC("e1000_get_auto_rd_done");
7827 5617 msleep(5);
7828 DEBUGFUNC("e1000_get_auto_rd_done"); 5618 return E1000_SUCCESS;
7829
7830 switch (hw->mac_type) {
7831 default:
7832 msleep(5);
7833 break;
7834 case e1000_82571:
7835 case e1000_82572:
7836 case e1000_82573:
7837 case e1000_80003es2lan:
7838 case e1000_ich8lan:
7839 while (timeout) {
7840 if (er32(EECD) & E1000_EECD_AUTO_RD)
7841 break;
7842 else msleep(1);
7843 timeout--;
7844 }
7845
7846 if (!timeout) {
7847 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7848 return -E1000_ERR_RESET;
7849 }
7850 break;
7851 }
7852
7853 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
7854 * Need to wait for PHY configuration completion before accessing NVM
7855 * and PHY. */
7856 if (hw->mac_type == e1000_82573)
7857 msleep(25);
7858
7859 return E1000_SUCCESS;
7860} 5619}
7861 5620
7862/*************************************************************************** 5621/**
7863 * Checks if the PHY configuration is done 5622 * e1000_get_phy_cfg_done
7864 * 5623 * @hw: Struct containing variables accessed by shared code
7865 * hw: Struct containing variables accessed by shared code
7866 * 5624 *
5625 * Checks if the PHY configuration is done
7867 * returns: - E1000_ERR_RESET if fail to reset MAC 5626 * returns: - E1000_ERR_RESET if fail to reset MAC
7868 * E1000_SUCCESS at any other case. 5627 * E1000_SUCCESS at any other case.
7869 * 5628 */
7870 ***************************************************************************/
7871static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5629static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7872{ 5630{
7873 s32 timeout = PHY_CFG_TIMEOUT; 5631 DEBUGFUNC("e1000_get_phy_cfg_done");
7874 u32 cfg_mask = E1000_EEPROM_CFG_DONE; 5632 mdelay(10);
7875 5633 return E1000_SUCCESS;
7876 DEBUGFUNC("e1000_get_phy_cfg_done");
7877
7878 switch (hw->mac_type) {
7879 default:
7880 mdelay(10);
7881 break;
7882 case e1000_80003es2lan:
7883 /* Separate *_CFG_DONE_* bit for each port */
7884 if (er32(STATUS) & E1000_STATUS_FUNC_1)
7885 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7886 /* Fall Through */
7887 case e1000_82571:
7888 case e1000_82572:
7889 while (timeout) {
7890 if (er32(EEMNGCTL) & cfg_mask)
7891 break;
7892 else
7893 msleep(1);
7894 timeout--;
7895 }
7896 if (!timeout) {
7897 DEBUGOUT("MNG configuration cycle has not completed.\n");
7898 return -E1000_ERR_RESET;
7899 }
7900 break;
7901 }
7902
7903 return E1000_SUCCESS;
7904}
7905
7906/***************************************************************************
7907 *
7908 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
7909 * adapter or Eeprom access.
7910 *
7911 * hw: Struct containing variables accessed by shared code
7912 *
7913 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
7914 * E1000_SUCCESS at any other case.
7915 *
7916 ***************************************************************************/
7917static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7918{
7919 s32 timeout;
7920 u32 swsm;
7921
7922 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
7923
7924 if (!hw->eeprom_semaphore_present)
7925 return E1000_SUCCESS;
7926
7927 if (hw->mac_type == e1000_80003es2lan) {
7928 /* Get the SW semaphore. */
7929 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
7930 return -E1000_ERR_EEPROM;
7931 }
7932
7933 /* Get the FW semaphore. */
7934 timeout = hw->eeprom.word_size + 1;
7935 while (timeout) {
7936 swsm = er32(SWSM);
7937 swsm |= E1000_SWSM_SWESMBI;
7938 ew32(SWSM, swsm);
7939 /* if we managed to set the bit we got the semaphore. */
7940 swsm = er32(SWSM);
7941 if (swsm & E1000_SWSM_SWESMBI)
7942 break;
7943
7944 udelay(50);
7945 timeout--;
7946 }
7947
7948 if (!timeout) {
7949 /* Release semaphores */
7950 e1000_put_hw_eeprom_semaphore(hw);
7951 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
7952 return -E1000_ERR_EEPROM;
7953 }
7954
7955 return E1000_SUCCESS;
7956}
7957
7958/***************************************************************************
7959 * This function clears HW semaphore bits.
7960 *
7961 * hw: Struct containing variables accessed by shared code
7962 *
7963 * returns: - None.
7964 *
7965 ***************************************************************************/
7966static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7967{
7968 u32 swsm;
7969
7970 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
7971
7972 if (!hw->eeprom_semaphore_present)
7973 return;
7974
7975 swsm = er32(SWSM);
7976 if (hw->mac_type == e1000_80003es2lan) {
7977 /* Release both semaphores. */
7978 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
7979 } else
7980 swsm &= ~(E1000_SWSM_SWESMBI);
7981 ew32(SWSM, swsm);
7982}
7983
7984/***************************************************************************
7985 *
7986 * Obtaining software semaphore bit (SMBI) before resetting PHY.
7987 *
7988 * hw: Struct containing variables accessed by shared code
7989 *
7990 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
7991 * E1000_SUCCESS at any other case.
7992 *
7993 ***************************************************************************/
7994static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
7995{
7996 s32 timeout = hw->eeprom.word_size + 1;
7997 u32 swsm;
7998
7999 DEBUGFUNC("e1000_get_software_semaphore");
8000
8001 if (hw->mac_type != e1000_80003es2lan) {
8002 return E1000_SUCCESS;
8003 }
8004
8005 while (timeout) {
8006 swsm = er32(SWSM);
8007 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8008 if (!(swsm & E1000_SWSM_SMBI))
8009 break;
8010 mdelay(1);
8011 timeout--;
8012 }
8013
8014 if (!timeout) {
8015 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8016 return -E1000_ERR_RESET;
8017 }
8018
8019 return E1000_SUCCESS;
8020}
8021
8022/***************************************************************************
8023 *
8024 * Release semaphore bit (SMBI).
8025 *
8026 * hw: Struct containing variables accessed by shared code
8027 *
8028 ***************************************************************************/
8029static void e1000_release_software_semaphore(struct e1000_hw *hw)
8030{
8031 u32 swsm;
8032
8033 DEBUGFUNC("e1000_release_software_semaphore");
8034
8035 if (hw->mac_type != e1000_80003es2lan) {
8036 return;
8037 }
8038
8039 swsm = er32(SWSM);
8040 /* Release the SW semaphores.*/
8041 swsm &= ~E1000_SWSM_SMBI;
8042 ew32(SWSM, swsm);
8043}
8044
8045/******************************************************************************
8046 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8047 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8048 * the caller to figure out how to deal with it.
8049 *
8050 * hw - Struct containing variables accessed by shared code
8051 *
8052 * returns: - E1000_BLK_PHY_RESET
8053 * E1000_SUCCESS
8054 *
8055 *****************************************************************************/
8056s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
8057{
8058 u32 manc = 0;
8059 u32 fwsm = 0;
8060
8061 if (hw->mac_type == e1000_ich8lan) {
8062 fwsm = er32(FWSM);
8063 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8064 : E1000_BLK_PHY_RESET;
8065 }
8066
8067 if (hw->mac_type > e1000_82547_rev_2)
8068 manc = er32(MANC);
8069 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8070 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8071}
8072
8073static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8074{
8075 u32 fwsm;
8076
8077 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8078 * may not be provided a DMA clock when no manageability features are
8079 * enabled. We do not want to perform any reads/writes to these registers
8080 * if this is the case. We read FWSM to determine the manageability mode.
8081 */
8082 switch (hw->mac_type) {
8083 case e1000_82571:
8084 case e1000_82572:
8085 case e1000_82573:
8086 case e1000_80003es2lan:
8087 fwsm = er32(FWSM);
8088 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8089 return true;
8090 break;
8091 case e1000_ich8lan:
8092 return true;
8093 default:
8094 break;
8095 }
8096 return false;
8097}
8098
8099
8100/******************************************************************************
8101 * Configure PCI-Ex no-snoop
8102 *
8103 * hw - Struct containing variables accessed by shared code.
8104 * no_snoop - Bitmap of no-snoop events.
8105 *
8106 * returns: E1000_SUCCESS
8107 *
8108 *****************************************************************************/
8109static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8110{
8111 u32 gcr_reg = 0;
8112
8113 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8114
8115 if (hw->bus_type == e1000_bus_type_unknown)
8116 e1000_get_bus_info(hw);
8117
8118 if (hw->bus_type != e1000_bus_type_pci_express)
8119 return E1000_SUCCESS;
8120
8121 if (no_snoop) {
8122 gcr_reg = er32(GCR);
8123 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8124 gcr_reg |= no_snoop;
8125 ew32(GCR, gcr_reg);
8126 }
8127 if (hw->mac_type == e1000_ich8lan) {
8128 u32 ctrl_ext;
8129
8130 ew32(GCR, PCI_EX_82566_SNOOP_ALL);
8131
8132 ctrl_ext = er32(CTRL_EXT);
8133 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8134 ew32(CTRL_EXT, ctrl_ext);
8135 }
8136
8137 return E1000_SUCCESS;
8138}
8139
8140/***************************************************************************
8141 *
8142 * Get software semaphore FLAG bit (SWFLAG).
8143 * SWFLAG is used to synchronize the access to all shared resource between
8144 * SW, FW and HW.
8145 *
8146 * hw: Struct containing variables accessed by shared code
8147 *
8148 ***************************************************************************/
8149static s32 e1000_get_software_flag(struct e1000_hw *hw)
8150{
8151 s32 timeout = PHY_CFG_TIMEOUT;
8152 u32 extcnf_ctrl;
8153
8154 DEBUGFUNC("e1000_get_software_flag");
8155
8156 if (hw->mac_type == e1000_ich8lan) {
8157 while (timeout) {
8158 extcnf_ctrl = er32(EXTCNF_CTRL);
8159 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8160 ew32(EXTCNF_CTRL, extcnf_ctrl);
8161
8162 extcnf_ctrl = er32(EXTCNF_CTRL);
8163 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8164 break;
8165 mdelay(1);
8166 timeout--;
8167 }
8168
8169 if (!timeout) {
8170 DEBUGOUT("FW or HW locks the resource too long.\n");
8171 return -E1000_ERR_CONFIG;
8172 }
8173 }
8174
8175 return E1000_SUCCESS;
8176}
8177
8178/***************************************************************************
8179 *
8180 * Release software semaphore FLAG bit (SWFLAG).
8181 * SWFLAG is used to synchronize the access to all shared resource between
8182 * SW, FW and HW.
8183 *
8184 * hw: Struct containing variables accessed by shared code
8185 *
8186 ***************************************************************************/
8187static void e1000_release_software_flag(struct e1000_hw *hw)
8188{
8189 u32 extcnf_ctrl;
8190
8191 DEBUGFUNC("e1000_release_software_flag");
8192
8193 if (hw->mac_type == e1000_ich8lan) {
8194 extcnf_ctrl= er32(EXTCNF_CTRL);
8195 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8196 ew32(EXTCNF_CTRL, extcnf_ctrl);
8197 }
8198
8199 return;
8200}
8201
8202/******************************************************************************
8203 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8204 * register.
8205 *
8206 * hw - Struct containing variables accessed by shared code
8207 * offset - offset of word in the EEPROM to read
8208 * data - word read from the EEPROM
8209 * words - number of words to read
8210 *****************************************************************************/
8211static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8212 u16 *data)
8213{
8214 s32 error = E1000_SUCCESS;
8215 u32 flash_bank = 0;
8216 u32 act_offset = 0;
8217 u32 bank_offset = 0;
8218 u16 word = 0;
8219 u16 i = 0;
8220
8221 /* We need to know which is the valid flash bank. In the event
8222 * that we didn't allocate eeprom_shadow_ram, we may not be
8223 * managing flash_bank. So it cannot be trusted and needs
8224 * to be updated with each read.
8225 */
8226 /* Value of bit 22 corresponds to the flash bank we're on. */
8227 flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8228
8229 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8230 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8231
8232 error = e1000_get_software_flag(hw);
8233 if (error != E1000_SUCCESS)
8234 return error;
8235
8236 for (i = 0; i < words; i++) {
8237 if (hw->eeprom_shadow_ram != NULL &&
8238 hw->eeprom_shadow_ram[offset+i].modified) {
8239 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8240 } else {
8241 /* The NVM part needs a byte offset, hence * 2 */
8242 act_offset = bank_offset + ((offset + i) * 2);
8243 error = e1000_read_ich8_word(hw, act_offset, &word);
8244 if (error != E1000_SUCCESS)
8245 break;
8246 data[i] = word;
8247 }
8248 }
8249
8250 e1000_release_software_flag(hw);
8251
8252 return error;
8253}
8254
8255/******************************************************************************
8256 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8257 * register. Actually, writes are written to the shadow ram cache in the hw
8258 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8259 * the NVM, which occurs when the NVM checksum is updated.
8260 *
8261 * hw - Struct containing variables accessed by shared code
8262 * offset - offset of word in the EEPROM to write
8263 * words - number of words to write
8264 * data - words to write to the EEPROM
8265 *****************************************************************************/
8266static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8267 u16 *data)
8268{
8269 u32 i = 0;
8270 s32 error = E1000_SUCCESS;
8271
8272 error = e1000_get_software_flag(hw);
8273 if (error != E1000_SUCCESS)
8274 return error;
8275
8276 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8277 * allocated. Subsequent reads to the modified words are read from
8278 * this cached structure as well. Writes will only go into this
8279 * cached structure unless it's followed by a call to
8280 * e1000_update_eeprom_checksum() where it will commit the changes
8281 * and clear the "modified" field.
8282 */
8283 if (hw->eeprom_shadow_ram != NULL) {
8284 for (i = 0; i < words; i++) {
8285 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8286 hw->eeprom_shadow_ram[offset+i].modified = true;
8287 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8288 } else {
8289 error = -E1000_ERR_EEPROM;
8290 break;
8291 }
8292 }
8293 } else {
8294 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8295 * as they don't perform any NVM writes. An attempt in doing so
8296 * will result in this error.
8297 */
8298 error = -E1000_ERR_EEPROM;
8299 }
8300
8301 e1000_release_software_flag(hw);
8302
8303 return error;
8304}
8305
8306/******************************************************************************
8307 * This function does initial flash setup so that a new read/write/erase cycle
8308 * can be started.
8309 *
8310 * hw - The pointer to the hw structure
8311 ****************************************************************************/
8312static s32 e1000_ich8_cycle_init(struct e1000_hw *hw)
8313{
8314 union ich8_hws_flash_status hsfsts;
8315 s32 error = E1000_ERR_EEPROM;
8316 s32 i = 0;
8317
8318 DEBUGFUNC("e1000_ich8_cycle_init");
8319
8320 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8321
8322 /* May be check the Flash Des Valid bit in Hw status */
8323 if (hsfsts.hsf_status.fldesvalid == 0) {
8324 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8325 return error;
8326 }
8327
8328 /* Clear FCERR in Hw status by writing 1 */
8329 /* Clear DAEL in Hw status by writing a 1 */
8330 hsfsts.hsf_status.flcerr = 1;
8331 hsfsts.hsf_status.dael = 1;
8332
8333 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8334
8335 /* Either we should have a hardware SPI cycle in progress bit to check
8336 * against, in order to start a new cycle or FDONE bit should be changed
8337 * in the hardware so that it is 1 after harware reset, which can then be
8338 * used as an indication whether a cycle is in progress or has been
8339 * completed .. we should also have some software semaphore mechanism to
8340 * guard FDONE or the cycle in progress bit so that two threads access to
8341 * those bits can be sequentiallized or a way so that 2 threads dont
8342 * start the cycle at the same time */
8343
8344 if (hsfsts.hsf_status.flcinprog == 0) {
8345 /* There is no cycle running at present, so we can start a cycle */
8346 /* Begin by setting Flash Cycle Done. */
8347 hsfsts.hsf_status.flcdone = 1;
8348 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8349 error = E1000_SUCCESS;
8350 } else {
8351 /* otherwise poll for sometime so the current cycle has a chance
8352 * to end before giving up. */
8353 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8354 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8355 if (hsfsts.hsf_status.flcinprog == 0) {
8356 error = E1000_SUCCESS;
8357 break;
8358 }
8359 udelay(1);
8360 }
8361 if (error == E1000_SUCCESS) {
8362 /* Successful in waiting for previous cycle to timeout,
8363 * now set the Flash Cycle Done. */
8364 hsfsts.hsf_status.flcdone = 1;
8365 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8366 } else {
8367 DEBUGOUT("Flash controller busy, cannot get access");
8368 }
8369 }
8370 return error;
8371}
8372
8373/******************************************************************************
8374 * This function starts a flash cycle and waits for its completion
8375 *
8376 * hw - The pointer to the hw structure
8377 ****************************************************************************/
8378static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8379{
8380 union ich8_hws_flash_ctrl hsflctl;
8381 union ich8_hws_flash_status hsfsts;
8382 s32 error = E1000_ERR_EEPROM;
8383 u32 i = 0;
8384
8385 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8386 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8387 hsflctl.hsf_ctrl.flcgo = 1;
8388 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8389
8390 /* wait till FDONE bit is set to 1 */
8391 do {
8392 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8393 if (hsfsts.hsf_status.flcdone == 1)
8394 break;
8395 udelay(1);
8396 i++;
8397 } while (i < timeout);
8398 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8399 error = E1000_SUCCESS;
8400 }
8401 return error;
8402}
8403
8404/******************************************************************************
8405 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8406 *
8407 * hw - The pointer to the hw structure
8408 * index - The index of the byte or word to read.
8409 * size - Size of data to read, 1=byte 2=word
8410 * data - Pointer to the word to store the value read.
8411 *****************************************************************************/
8412static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8413 u16 *data)
8414{
8415 union ich8_hws_flash_status hsfsts;
8416 union ich8_hws_flash_ctrl hsflctl;
8417 u32 flash_linear_address;
8418 u32 flash_data = 0;
8419 s32 error = -E1000_ERR_EEPROM;
8420 s32 count = 0;
8421
8422 DEBUGFUNC("e1000_read_ich8_data");
8423
8424 if (size < 1 || size > 2 || data == NULL ||
8425 index > ICH_FLASH_LINEAR_ADDR_MASK)
8426 return error;
8427
8428 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8429 hw->flash_base_addr;
8430
8431 do {
8432 udelay(1);
8433 /* Steps */
8434 error = e1000_ich8_cycle_init(hw);
8435 if (error != E1000_SUCCESS)
8436 break;
8437
8438 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8439 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8440 hsflctl.hsf_ctrl.fldbcount = size - 1;
8441 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8442 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8443
8444 /* Write the last 24 bits of index into Flash Linear address field in
8445 * Flash Address */
8446 /* TODO: TBD maybe check the index against the size of flash */
8447
8448 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8449
8450 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8451
8452 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8453 * sequence a few more times, else read in (shift in) the Flash Data0,
8454 * the order is least significant byte first msb to lsb */
8455 if (error == E1000_SUCCESS) {
8456 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8457 if (size == 1) {
8458 *data = (u8)(flash_data & 0x000000FF);
8459 } else if (size == 2) {
8460 *data = (u16)(flash_data & 0x0000FFFF);
8461 }
8462 break;
8463 } else {
8464 /* If we've gotten here, then things are probably completely hosed,
8465 * but if the error condition is detected, it won't hurt to give
8466 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8467 */
8468 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8469 if (hsfsts.hsf_status.flcerr == 1) {
8470 /* Repeat for some time before giving up. */
8471 continue;
8472 } else if (hsfsts.hsf_status.flcdone == 0) {
8473 DEBUGOUT("Timeout error - flash cycle did not complete.");
8474 break;
8475 }
8476 }
8477 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8478
8479 return error;
8480}
8481
8482/******************************************************************************
8483 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8484 *
8485 * hw - The pointer to the hw structure
8486 * index - The index of the byte/word to read.
8487 * size - Size of data to read, 1=byte 2=word
8488 * data - The byte(s) to write to the NVM.
8489 *****************************************************************************/
8490static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8491 u16 data)
8492{
8493 union ich8_hws_flash_status hsfsts;
8494 union ich8_hws_flash_ctrl hsflctl;
8495 u32 flash_linear_address;
8496 u32 flash_data = 0;
8497 s32 error = -E1000_ERR_EEPROM;
8498 s32 count = 0;
8499
8500 DEBUGFUNC("e1000_write_ich8_data");
8501
8502 if (size < 1 || size > 2 || data > size * 0xff ||
8503 index > ICH_FLASH_LINEAR_ADDR_MASK)
8504 return error;
8505
8506 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8507 hw->flash_base_addr;
8508
8509 do {
8510 udelay(1);
8511 /* Steps */
8512 error = e1000_ich8_cycle_init(hw);
8513 if (error != E1000_SUCCESS)
8514 break;
8515
8516 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8517 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8518 hsflctl.hsf_ctrl.fldbcount = size -1;
8519 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8520 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8521
8522 /* Write the last 24 bits of index into Flash Linear address field in
8523 * Flash Address */
8524 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8525
8526 if (size == 1)
8527 flash_data = (u32)data & 0x00FF;
8528 else
8529 flash_data = (u32)data;
8530
8531 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8532
8533 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8534 * sequence a few more times else done */
8535 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8536 if (error == E1000_SUCCESS) {
8537 break;
8538 } else {
8539 /* If we're here, then things are most likely completely hosed,
8540 * but if the error condition is detected, it won't hurt to give
8541 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8542 */
8543 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8544 if (hsfsts.hsf_status.flcerr == 1) {
8545 /* Repeat for some time before giving up. */
8546 continue;
8547 } else if (hsfsts.hsf_status.flcdone == 0) {
8548 DEBUGOUT("Timeout error - flash cycle did not complete.");
8549 break;
8550 }
8551 }
8552 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8553
8554 return error;
8555}
8556
8557/******************************************************************************
8558 * Reads a single byte from the NVM using the ICH8 flash access registers.
8559 *
8560 * hw - pointer to e1000_hw structure
8561 * index - The index of the byte to read.
8562 * data - Pointer to a byte to store the value read.
8563 *****************************************************************************/
8564static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data)
8565{
8566 s32 status = E1000_SUCCESS;
8567 u16 word = 0;
8568
8569 status = e1000_read_ich8_data(hw, index, 1, &word);
8570 if (status == E1000_SUCCESS) {
8571 *data = (u8)word;
8572 }
8573
8574 return status;
8575}
8576
8577/******************************************************************************
8578 * Writes a single byte to the NVM using the ICH8 flash access registers.
8579 * Performs verification by reading back the value and then going through
8580 * a retry algorithm before giving up.
8581 *
8582 * hw - pointer to e1000_hw structure
8583 * index - The index of the byte to write.
8584 * byte - The byte to write to the NVM.
8585 *****************************************************************************/
8586static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8587{
8588 s32 error = E1000_SUCCESS;
8589 s32 program_retries = 0;
8590
8591 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8592
8593 error = e1000_write_ich8_byte(hw, index, byte);
8594
8595 if (error != E1000_SUCCESS) {
8596 for (program_retries = 0; program_retries < 100; program_retries++) {
8597 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8598 error = e1000_write_ich8_byte(hw, index, byte);
8599 udelay(100);
8600 if (error == E1000_SUCCESS)
8601 break;
8602 }
8603 }
8604
8605 if (program_retries == 100)
8606 error = E1000_ERR_EEPROM;
8607
8608 return error;
8609}
8610
8611/******************************************************************************
8612 * Writes a single byte to the NVM using the ICH8 flash access registers.
8613 *
8614 * hw - pointer to e1000_hw structure
8615 * index - The index of the byte to read.
8616 * data - The byte to write to the NVM.
8617 *****************************************************************************/
8618static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8619{
8620 s32 status = E1000_SUCCESS;
8621 u16 word = (u16)data;
8622
8623 status = e1000_write_ich8_data(hw, index, 1, word);
8624
8625 return status;
8626}
8627
8628/******************************************************************************
8629 * Reads a word from the NVM using the ICH8 flash access registers.
8630 *
8631 * hw - pointer to e1000_hw structure
8632 * index - The starting byte index of the word to read.
8633 * data - Pointer to a word to store the value read.
8634 *****************************************************************************/
8635static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8636{
8637 s32 status = E1000_SUCCESS;
8638 status = e1000_read_ich8_data(hw, index, 2, data);
8639 return status;
8640}
8641
8642/******************************************************************************
8643 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8644 * based.
8645 *
8646 * hw - pointer to e1000_hw structure
8647 * bank - 0 for first bank, 1 for second bank
8648 *
8649 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8650 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8651 * bank size may be 4, 8 or 64 KBytes
8652 *****************************************************************************/
8653static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8654{
8655 union ich8_hws_flash_status hsfsts;
8656 union ich8_hws_flash_ctrl hsflctl;
8657 u32 flash_linear_address;
8658 s32 count = 0;
8659 s32 error = E1000_ERR_EEPROM;
8660 s32 iteration;
8661 s32 sub_sector_size = 0;
8662 s32 bank_size;
8663 s32 j = 0;
8664 s32 error_flag = 0;
8665
8666 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8667
8668 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8669 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8670 * consecutive sectors. The start index for the nth Hw sector can be
8671 * calculated as bank * 4096 + n * 256
8672 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8673 * The start index for the nth Hw sector can be calculated
8674 * as bank * 4096
8675 * 10: The HW sector is 8K bytes
8676 * 11: The Hw sector size is 64K bytes */
8677 if (hsfsts.hsf_status.berasesz == 0x0) {
8678 /* Hw sector size 256 */
8679 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8680 bank_size = ICH_FLASH_SECTOR_SIZE;
8681 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8682 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8683 bank_size = ICH_FLASH_SEG_SIZE_4K;
8684 iteration = 1;
8685 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8686 bank_size = ICH_FLASH_SEG_SIZE_64K;
8687 iteration = 1;
8688 } else {
8689 return error;
8690 }
8691
8692 for (j = 0; j < iteration ; j++) {
8693 do {
8694 count++;
8695 /* Steps */
8696 error = e1000_ich8_cycle_init(hw);
8697 if (error != E1000_SUCCESS) {
8698 error_flag = 1;
8699 break;
8700 }
8701
8702 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8703 * Control */
8704 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8705 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8706 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8707
8708 /* Write the last 24 bits of an index within the block into Flash
8709 * Linear address field in Flash Address. This probably needs to
8710 * be calculated here based off the on-chip erase sector size and
8711 * the software bank size (4, 8 or 64 KBytes) */
8712 flash_linear_address = bank * bank_size + j * sub_sector_size;
8713 flash_linear_address += hw->flash_base_addr;
8714 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8715
8716 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8717
8718 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8719 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8720 * sequence a few more times else Done */
8721 if (error == E1000_SUCCESS) {
8722 break;
8723 } else {
8724 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8725 if (hsfsts.hsf_status.flcerr == 1) {
8726 /* repeat for some time before giving up */
8727 continue;
8728 } else if (hsfsts.hsf_status.flcdone == 0) {
8729 error_flag = 1;
8730 break;
8731 }
8732 }
8733 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8734 if (error_flag == 1)
8735 break;
8736 }
8737 if (error_flag != 1)
8738 error = E1000_SUCCESS;
8739 return error;
8740}
8741
8742static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8743 u32 cnf_base_addr,
8744 u32 cnf_size)
8745{
8746 u32 ret_val = E1000_SUCCESS;
8747 u16 word_addr, reg_data, reg_addr;
8748 u16 i;
8749
8750 /* cnf_base_addr is in DWORD */
8751 word_addr = (u16)(cnf_base_addr << 1);
8752
8753 /* cnf_size is returned in size of dwords */
8754 for (i = 0; i < cnf_size; i++) {
8755 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8756 if (ret_val)
8757 return ret_val;
8758
8759 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8760 if (ret_val)
8761 return ret_val;
8762
8763 ret_val = e1000_get_software_flag(hw);
8764 if (ret_val != E1000_SUCCESS)
8765 return ret_val;
8766
8767 ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
8768
8769 e1000_release_software_flag(hw);
8770 }
8771
8772 return ret_val;
8773}
8774
8775
8776/******************************************************************************
8777 * This function initializes the PHY from the NVM on ICH8 platforms. This
8778 * is needed due to an issue where the NVM configuration is not properly
8779 * autoloaded after power transitions. Therefore, after each PHY reset, we
8780 * will load the configuration data out of the NVM manually.
8781 *
8782 * hw: Struct containing variables accessed by shared code
8783 *****************************************************************************/
8784static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8785{
8786 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8787
8788 if (hw->phy_type != e1000_phy_igp_3)
8789 return E1000_SUCCESS;
8790
8791 /* Check if SW needs configure the PHY */
8792 reg_data = er32(FEXTNVM);
8793 if (!(reg_data & FEXTNVM_SW_CONFIG))
8794 return E1000_SUCCESS;
8795
8796 /* Wait for basic configuration completes before proceeding*/
8797 loop = 0;
8798 do {
8799 reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
8800 udelay(100);
8801 loop++;
8802 } while ((!reg_data) && (loop < 50));
8803
8804 /* Clear the Init Done bit for the next init event */
8805 reg_data = er32(STATUS);
8806 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8807 ew32(STATUS, reg_data);
8808
8809 /* Make sure HW does not configure LCD from PHY extended configuration
8810 before SW configuration */
8811 reg_data = er32(EXTCNF_CTRL);
8812 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8813 reg_data = er32(EXTCNF_SIZE);
8814 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8815 cnf_size >>= 16;
8816 if (cnf_size) {
8817 reg_data = er32(EXTCNF_CTRL);
8818 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
8819 /* cnf_base_addr is in DWORD */
8820 cnf_base_addr >>= 16;
8821
8822 /* Configure LCD from extended configuration region. */
8823 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
8824 cnf_size);
8825 if (ret_val)
8826 return ret_val;
8827 }
8828 }
8829
8830 return E1000_SUCCESS;
8831} 5634}
8832
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 15:43:17 -0500