diff options
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r-- | drivers/net/e1000/e1000_hw.c | 1000 |
1 files changed, 999 insertions, 1 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 784f9505864a..a3f5ccdfafc6 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -3617,11 +3617,120 @@ e1000_phy_reset(struct e1000_hw *hw) | |||
3617 | } | 3617 | } |
3618 | 3618 | ||
3619 | /****************************************************************************** | 3619 | /****************************************************************************** |
3620 | * Work-around for 82566 power-down: on D3 entry- | ||
3621 | * 1) disable gigabit link | ||
3622 | * 2) write VR power-down enable | ||
3623 | * 3) read it back | ||
3624 | * if successful continue, else issue LCD reset and repeat | ||
3625 | * | ||
3626 | * hw - struct containing variables accessed by shared code | ||
3627 | ******************************************************************************/ | ||
3628 | void | ||
3629 | e1000_phy_powerdown_workaround(struct e1000_hw *hw) | ||
3630 | { | ||
3631 | int32_t reg; | ||
3632 | uint16_t phy_data; | ||
3633 | int32_t retry = 0; | ||
3634 | |||
3635 | DEBUGFUNC("e1000_phy_powerdown_workaround"); | ||
3636 | |||
3637 | if (hw->phy_type != e1000_phy_igp_3) | ||
3638 | return; | ||
3639 | |||
3640 | do { | ||
3641 | /* Disable link */ | ||
3642 | reg = E1000_READ_REG(hw, PHY_CTRL); | ||
3643 | E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | ||
3644 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | ||
3645 | |||
3646 | /* Write VR power-down enable */ | ||
3647 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); | ||
3648 | e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data | | ||
3649 | IGP3_VR_CTRL_MODE_SHUT); | ||
3650 | |||
3651 | /* Read it back and test */ | ||
3652 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); | ||
3653 | if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry) | ||
3654 | break; | ||
3655 | |||
3656 | /* Issue PHY reset and repeat at most one more time */ | ||
3657 | reg = E1000_READ_REG(hw, CTRL); | ||
3658 | E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); | ||
3659 | retry++; | ||
3660 | } while (retry); | ||
3661 | |||
3662 | return; | ||
3663 | |||
3664 | } | ||
3665 | |||
3666 | /****************************************************************************** | ||
3667 | * Work-around for 82566 Kumeran PCS lock loss: | ||
3668 | * On link status change (i.e. PCI reset, speed change) and link is up and | ||
3669 | * speed is gigabit- | ||
3670 | * 0) if workaround is optionally disabled do nothing | ||
3671 | * 1) wait 1ms for Kumeran link to come up | ||
3672 | * 2) check Kumeran Diagnostic register PCS lock loss bit | ||
3673 | * 3) if not set the link is locked (all is good), otherwise... | ||
3674 | * 4) reset the PHY | ||
3675 | * 5) repeat up to 10 times | ||
3676 | * Note: this is only called for IGP3 copper when speed is 1gb. | ||
3677 | * | ||
3678 | * hw - struct containing variables accessed by shared code | ||
3679 | ******************************************************************************/ | ||
3680 | int32_t | ||
3681 | e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) | ||
3682 | { | ||
3683 | int32_t ret_val; | ||
3684 | int32_t reg; | ||
3685 | int32_t cnt; | ||
3686 | uint16_t phy_data; | ||
3687 | |||
3688 | if (hw->kmrn_lock_loss_workaround_disabled) | ||
3689 | return E1000_SUCCESS; | ||
3690 | |||
3691 | /* Make sure link is up before proceeding. If not just return. | ||
3692 | * Attempting this while link is negotiating fouls up link | ||
3693 | * stability */ | ||
3694 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | ||
3695 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | ||
3696 | |||
3697 | if (phy_data & MII_SR_LINK_STATUS) { | ||
3698 | for (cnt = 0; cnt < 10; cnt++) { | ||
3699 | /* read once to clear */ | ||
3700 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | ||
3701 | if (ret_val) | ||
3702 | return ret_val; | ||
3703 | /* and again to get new status */ | ||
3704 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | ||
3705 | if (ret_val) | ||
3706 | return ret_val; | ||
3707 | |||
3708 | /* check for PCS lock */ | ||
3709 | if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | ||
3710 | return E1000_SUCCESS; | ||
3711 | |||
3712 | /* Issue PHY reset */ | ||
3713 | e1000_phy_hw_reset(hw); | ||
3714 | msec_delay_irq(5); | ||
3715 | } | ||
3716 | /* Disable GigE link negotiation */ | ||
3717 | reg = E1000_READ_REG(hw, PHY_CTRL); | ||
3718 | E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | ||
3719 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | ||
3720 | |||
3721 | /* unable to acquire PCS lock */ | ||
3722 | return E1000_ERR_PHY; | ||
3723 | } | ||
3724 | |||
3725 | return E1000_SUCCESS; | ||
3726 | } | ||
3727 | |||
3728 | /****************************************************************************** | ||
3620 | * Probes the expected PHY address for known PHY IDs | 3729 | * Probes the expected PHY address for known PHY IDs |
3621 | * | 3730 | * |
3622 | * hw - Struct containing variables accessed by shared code | 3731 | * hw - Struct containing variables accessed by shared code |
3623 | ******************************************************************************/ | 3732 | ******************************************************************************/ |
3624 | static int32_t | 3733 | int32_t |
3625 | e1000_detect_gig_phy(struct e1000_hw *hw) | 3734 | e1000_detect_gig_phy(struct e1000_hw *hw) |
3626 | { | 3735 | { |
3627 | int32_t phy_init_status, ret_val; | 3736 | int32_t phy_init_status, ret_val; |
@@ -3804,6 +3913,53 @@ e1000_phy_igp_get_info(struct e1000_hw *hw, | |||
3804 | } | 3913 | } |
3805 | 3914 | ||
3806 | /****************************************************************************** | 3915 | /****************************************************************************** |
3916 | * Get PHY information from various PHY registers for ife PHY only. | ||
3917 | * | ||
3918 | * hw - Struct containing variables accessed by shared code | ||
3919 | * phy_info - PHY information structure | ||
3920 | ******************************************************************************/ | ||
3921 | int32_t | ||
3922 | e1000_phy_ife_get_info(struct e1000_hw *hw, | ||
3923 | struct e1000_phy_info *phy_info) | ||
3924 | { | ||
3925 | int32_t ret_val; | ||
3926 | uint16_t phy_data, polarity; | ||
3927 | |||
3928 | DEBUGFUNC("e1000_phy_ife_get_info"); | ||
3929 | |||
3930 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; | ||
3931 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | ||
3932 | |||
3933 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | ||
3934 | if (ret_val) | ||
3935 | return ret_val; | ||
3936 | phy_info->polarity_correction = | ||
3937 | (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> | ||
3938 | IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT; | ||
3939 | |||
3940 | if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { | ||
3941 | ret_val = e1000_check_polarity(hw, &polarity); | ||
3942 | if (ret_val) | ||
3943 | return ret_val; | ||
3944 | } else { | ||
3945 | /* Polarity is forced. */ | ||
3946 | polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >> | ||
3947 | IFE_PSC_FORCE_POLARITY_SHIFT; | ||
3948 | } | ||
3949 | phy_info->cable_polarity = polarity; | ||
3950 | |||
3951 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); | ||
3952 | if (ret_val) | ||
3953 | return ret_val; | ||
3954 | |||
3955 | phy_info->mdix_mode = | ||
3956 | (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> | ||
3957 | IFE_PMC_MDIX_MODE_SHIFT; | ||
3958 | |||
3959 | return E1000_SUCCESS; | ||
3960 | } | ||
3961 | |||
3962 | /****************************************************************************** | ||
3807 | * Get PHY information from various PHY registers fot m88 PHY only. | 3963 | * Get PHY information from various PHY registers fot m88 PHY only. |
3808 | * | 3964 | * |
3809 | * hw - Struct containing variables accessed by shared code | 3965 | * hw - Struct containing variables accessed by shared code |
@@ -7630,4 +7786,846 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw) | |||
7630 | } | 7786 | } |
7631 | 7787 | ||
7632 | 7788 | ||
7789 | /****************************************************************************** | ||
7790 | * Configure PCI-Ex no-snoop | ||
7791 | * | ||
7792 | * hw - Struct containing variables accessed by shared code. | ||
7793 | * no_snoop - Bitmap of no-snoop events. | ||
7794 | * | ||
7795 | * returns: E1000_SUCCESS | ||
7796 | * | ||
7797 | *****************************************************************************/ | ||
7798 | int32_t | ||
7799 | e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) | ||
7800 | { | ||
7801 | uint32_t gcr_reg = 0; | ||
7802 | |||
7803 | DEBUGFUNC("e1000_set_pci_ex_no_snoop"); | ||
7804 | |||
7805 | if (hw->bus_type == e1000_bus_type_unknown) | ||
7806 | e1000_get_bus_info(hw); | ||
7807 | |||
7808 | if (hw->bus_type != e1000_bus_type_pci_express) | ||
7809 | return E1000_SUCCESS; | ||
7810 | |||
7811 | if (no_snoop) { | ||
7812 | gcr_reg = E1000_READ_REG(hw, GCR); | ||
7813 | gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); | ||
7814 | gcr_reg |= no_snoop; | ||
7815 | E1000_WRITE_REG(hw, GCR, gcr_reg); | ||
7816 | } | ||
7817 | if (hw->mac_type == e1000_ich8lan) { | ||
7818 | uint32_t ctrl_ext; | ||
7819 | |||
7820 | E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); | ||
7821 | |||
7822 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | ||
7823 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | ||
7824 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | ||
7825 | } | ||
7826 | |||
7827 | return E1000_SUCCESS; | ||
7828 | } | ||
7829 | |||
7830 | /*************************************************************************** | ||
7831 | * | ||
7832 | * Get software semaphore FLAG bit (SWFLAG). | ||
7833 | * SWFLAG is used to synchronize the access to all shared resource between | ||
7834 | * SW, FW and HW. | ||
7835 | * | ||
7836 | * hw: Struct containing variables accessed by shared code | ||
7837 | * | ||
7838 | ***************************************************************************/ | ||
7839 | int32_t | ||
7840 | e1000_get_software_flag(struct e1000_hw *hw) | ||
7841 | { | ||
7842 | int32_t timeout = PHY_CFG_TIMEOUT; | ||
7843 | uint32_t extcnf_ctrl; | ||
7844 | |||
7845 | DEBUGFUNC("e1000_get_software_flag"); | ||
7846 | |||
7847 | if (hw->mac_type == e1000_ich8lan) { | ||
7848 | while (timeout) { | ||
7849 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | ||
7850 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | ||
7851 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | ||
7852 | |||
7853 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | ||
7854 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | ||
7855 | break; | ||
7856 | msec_delay_irq(1); | ||
7857 | timeout--; | ||
7858 | } | ||
7859 | |||
7860 | if (!timeout) { | ||
7861 | DEBUGOUT("FW or HW locks the resource too long.\n"); | ||
7862 | return -E1000_ERR_CONFIG; | ||
7863 | } | ||
7864 | } | ||
7865 | |||
7866 | return E1000_SUCCESS; | ||
7867 | } | ||
7868 | |||
7869 | /*************************************************************************** | ||
7870 | * | ||
7871 | * Release software semaphore FLAG bit (SWFLAG). | ||
7872 | * SWFLAG is used to synchronize the access to all shared resource between | ||
7873 | * SW, FW and HW. | ||
7874 | * | ||
7875 | * hw: Struct containing variables accessed by shared code | ||
7876 | * | ||
7877 | ***************************************************************************/ | ||
7878 | void | ||
7879 | e1000_release_software_flag(struct e1000_hw *hw) | ||
7880 | { | ||
7881 | uint32_t extcnf_ctrl; | ||
7882 | |||
7883 | DEBUGFUNC("e1000_release_software_flag"); | ||
7884 | |||
7885 | if (hw->mac_type == e1000_ich8lan) { | ||
7886 | extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); | ||
7887 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | ||
7888 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | ||
7889 | } | ||
7890 | |||
7891 | return; | ||
7892 | } | ||
7893 | |||
7894 | /*************************************************************************** | ||
7895 | * | ||
7896 | * Disable dynamic power down mode in ife PHY. | ||
7897 | * It can be used to workaround band-gap problem. | ||
7898 | * | ||
7899 | * hw: Struct containing variables accessed by shared code | ||
7900 | * | ||
7901 | ***************************************************************************/ | ||
7902 | int32_t | ||
7903 | e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw) | ||
7904 | { | ||
7905 | uint16_t phy_data; | ||
7906 | int32_t ret_val = E1000_SUCCESS; | ||
7907 | |||
7908 | DEBUGFUNC("e1000_ife_disable_dynamic_power_down"); | ||
7909 | |||
7910 | if (hw->phy_type == e1000_phy_ife) { | ||
7911 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | ||
7912 | if (ret_val) | ||
7913 | return ret_val; | ||
7914 | |||
7915 | phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; | ||
7916 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); | ||
7917 | } | ||
7918 | |||
7919 | return ret_val; | ||
7920 | } | ||
7921 | |||
7922 | /*************************************************************************** | ||
7923 | * | ||
7924 | * Enable dynamic power down mode in ife PHY. | ||
7925 | * It can be used to workaround band-gap problem. | ||
7926 | * | ||
7927 | * hw: Struct containing variables accessed by shared code | ||
7928 | * | ||
7929 | ***************************************************************************/ | ||
7930 | int32_t | ||
7931 | e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw) | ||
7932 | { | ||
7933 | uint16_t phy_data; | ||
7934 | int32_t ret_val = E1000_SUCCESS; | ||
7935 | |||
7936 | DEBUGFUNC("e1000_ife_enable_dynamic_power_down"); | ||
7937 | |||
7938 | if (hw->phy_type == e1000_phy_ife) { | ||
7939 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | ||
7940 | if (ret_val) | ||
7941 | return ret_val; | ||
7942 | |||
7943 | phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; | ||
7944 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); | ||
7945 | } | ||
7946 | |||
7947 | return ret_val; | ||
7948 | } | ||
7949 | |||
7950 | /****************************************************************************** | ||
7951 | * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access | ||
7952 | * register. | ||
7953 | * | ||
7954 | * hw - Struct containing variables accessed by shared code | ||
7955 | * offset - offset of word in the EEPROM to read | ||
7956 | * data - word read from the EEPROM | ||
7957 | * words - number of words to read | ||
7958 | *****************************************************************************/ | ||
7959 | int32_t | ||
7960 | e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, | ||
7961 | uint16_t *data) | ||
7962 | { | ||
7963 | int32_t error = E1000_SUCCESS; | ||
7964 | uint32_t flash_bank = 0; | ||
7965 | uint32_t act_offset = 0; | ||
7966 | uint32_t bank_offset = 0; | ||
7967 | uint16_t word = 0; | ||
7968 | uint16_t i = 0; | ||
7969 | |||
7970 | /* We need to know which is the valid flash bank. In the event | ||
7971 | * that we didn't allocate eeprom_shadow_ram, we may not be | ||
7972 | * managing flash_bank. So it cannot be trusted and needs | ||
7973 | * to be updated with each read. | ||
7974 | */ | ||
7975 | /* Value of bit 22 corresponds to the flash bank we're on. */ | ||
7976 | flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; | ||
7977 | |||
7978 | /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ | ||
7979 | bank_offset = flash_bank * (hw->flash_bank_size * 2); | ||
7980 | |||
7981 | error = e1000_get_software_flag(hw); | ||
7982 | if (error != E1000_SUCCESS) | ||
7983 | return error; | ||
7984 | |||
7985 | for (i = 0; i < words; i++) { | ||
7986 | if (hw->eeprom_shadow_ram != NULL && | ||
7987 | hw->eeprom_shadow_ram[offset+i].modified == TRUE) { | ||
7988 | data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; | ||
7989 | } else { | ||
7990 | /* The NVM part needs a byte offset, hence * 2 */ | ||
7991 | act_offset = bank_offset + ((offset + i) * 2); | ||
7992 | error = e1000_read_ich8_word(hw, act_offset, &word); | ||
7993 | if (error != E1000_SUCCESS) | ||
7994 | break; | ||
7995 | data[i] = word; | ||
7996 | } | ||
7997 | } | ||
7998 | |||
7999 | e1000_release_software_flag(hw); | ||
8000 | |||
8001 | return error; | ||
8002 | } | ||
8003 | |||
8004 | /****************************************************************************** | ||
8005 | * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access | ||
8006 | * register. Actually, writes are written to the shadow ram cache in the hw | ||
8007 | * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to | ||
8008 | * the NVM, which occurs when the NVM checksum is updated. | ||
8009 | * | ||
8010 | * hw - Struct containing variables accessed by shared code | ||
8011 | * offset - offset of word in the EEPROM to write | ||
8012 | * words - number of words to write | ||
8013 | * data - words to write to the EEPROM | ||
8014 | *****************************************************************************/ | ||
8015 | int32_t | ||
8016 | e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, | ||
8017 | uint16_t *data) | ||
8018 | { | ||
8019 | uint32_t i = 0; | ||
8020 | int32_t error = E1000_SUCCESS; | ||
8021 | |||
8022 | error = e1000_get_software_flag(hw); | ||
8023 | if (error != E1000_SUCCESS) | ||
8024 | return error; | ||
8025 | |||
8026 | /* A driver can write to the NVM only if it has eeprom_shadow_ram | ||
8027 | * allocated. Subsequent reads to the modified words are read from | ||
8028 | * this cached structure as well. Writes will only go into this | ||
8029 | * cached structure unless it's followed by a call to | ||
8030 | * e1000_update_eeprom_checksum() where it will commit the changes | ||
8031 | * and clear the "modified" field. | ||
8032 | */ | ||
8033 | if (hw->eeprom_shadow_ram != NULL) { | ||
8034 | for (i = 0; i < words; i++) { | ||
8035 | if ((offset + i) < E1000_SHADOW_RAM_WORDS) { | ||
8036 | hw->eeprom_shadow_ram[offset+i].modified = TRUE; | ||
8037 | hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; | ||
8038 | } else { | ||
8039 | error = -E1000_ERR_EEPROM; | ||
8040 | break; | ||
8041 | } | ||
8042 | } | ||
8043 | } else { | ||
8044 | /* Drivers have the option to not allocate eeprom_shadow_ram as long | ||
8045 | * as they don't perform any NVM writes. An attempt in doing so | ||
8046 | * will result in this error. | ||
8047 | */ | ||
8048 | error = -E1000_ERR_EEPROM; | ||
8049 | } | ||
8050 | |||
8051 | e1000_release_software_flag(hw); | ||
8052 | |||
8053 | return error; | ||
8054 | } | ||
8055 | |||
8056 | /****************************************************************************** | ||
8057 | * This function does initial flash setup so that a new read/write/erase cycle | ||
8058 | * can be started. | ||
8059 | * | ||
8060 | * hw - The pointer to the hw structure | ||
8061 | ****************************************************************************/ | ||
8062 | int32_t | ||
8063 | e1000_ich8_cycle_init(struct e1000_hw *hw) | ||
8064 | { | ||
8065 | union ich8_hws_flash_status hsfsts; | ||
8066 | int32_t error = E1000_ERR_EEPROM; | ||
8067 | int32_t i = 0; | ||
8068 | |||
8069 | DEBUGFUNC("e1000_ich8_cycle_init"); | ||
8070 | |||
8071 | hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); | ||
8072 | |||
8073 | /* May be check the Flash Des Valid bit in Hw status */ | ||
8074 | if (hsfsts.hsf_status.fldesvalid == 0) { | ||
8075 | DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); | ||
8076 | return error; | ||
8077 | } | ||
8078 | |||
8079 | /* Clear FCERR in Hw status by writing 1 */ | ||
8080 | /* Clear DAEL in Hw status by writing a 1 */ | ||
8081 | hsfsts.hsf_status.flcerr = 1; | ||
8082 | hsfsts.hsf_status.dael = 1; | ||
8083 | |||
8084 | E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); | ||
8085 | |||
8086 | /* Either we should have a hardware SPI cycle in progress bit to check | ||
8087 | * against, in order to start a new cycle or FDONE bit should be changed | ||
8088 | * in the hardware so that it is 1 after harware reset, which can then be | ||
8089 | * used as an indication whether a cycle is in progress or has been | ||
8090 | * completed .. we should also have some software semaphore mechanism to | ||
8091 | * guard FDONE or the cycle in progress bit so that two threads access to | ||
8092 | * those bits can be sequentiallized or a way so that 2 threads dont | ||
8093 | * start the cycle at the same time */ | ||
8094 | |||
8095 | if (hsfsts.hsf_status.flcinprog == 0) { | ||
8096 | /* There is no cycle running at present, so we can start a cycle */ | ||
8097 | /* Begin by setting Flash Cycle Done. */ | ||
8098 | hsfsts.hsf_status.flcdone = 1; | ||
8099 | E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); | ||
8100 | error = E1000_SUCCESS; | ||
8101 | } else { | ||
8102 | /* otherwise poll for sometime so the current cycle has a chance | ||
8103 | * to end before giving up. */ | ||
8104 | for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) { | ||
8105 | hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); | ||
8106 | if (hsfsts.hsf_status.flcinprog == 0) { | ||
8107 | error = E1000_SUCCESS; | ||
8108 | break; | ||
8109 | } | ||
8110 | udelay(1); | ||
8111 | } | ||
8112 | if (error == E1000_SUCCESS) { | ||
8113 | /* Successful in waiting for previous cycle to timeout, | ||
8114 | * now set the Flash Cycle Done. */ | ||
8115 | hsfsts.hsf_status.flcdone = 1; | ||
8116 | E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); | ||
8117 | } else { | ||
8118 | DEBUGOUT("Flash controller busy, cannot get access"); | ||
8119 | } | ||
8120 | } | ||
8121 | return error; | ||
8122 | } | ||
8123 | |||
8124 | /****************************************************************************** | ||
8125 | * This function starts a flash cycle and waits for its completion | ||
8126 | * | ||
8127 | * hw - The pointer to the hw structure | ||
8128 | ****************************************************************************/ | ||
8129 | int32_t | ||
8130 | e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) | ||
8131 | { | ||
8132 | union ich8_hws_flash_ctrl hsflctl; | ||
8133 | union ich8_hws_flash_status hsfsts; | ||
8134 | int32_t error = E1000_ERR_EEPROM; | ||
8135 | uint32_t i = 0; | ||
8136 | |||
8137 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | ||
8138 | hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); | ||
8139 | hsflctl.hsf_ctrl.flcgo = 1; | ||
8140 | E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); | ||
8141 | |||
8142 | /* wait till FDONE bit is set to 1 */ | ||
8143 | do { | ||
8144 | hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); | ||
8145 | if (hsfsts.hsf_status.flcdone == 1) | ||
8146 | break; | ||
8147 | udelay(1); | ||
8148 | i++; | ||
8149 | } while (i < timeout); | ||
8150 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { | ||
8151 | error = E1000_SUCCESS; | ||
8152 | } | ||
8153 | return error; | ||
8154 | } | ||
8155 | |||
8156 | /****************************************************************************** | ||
8157 | * Reads a byte or word from the NVM using the ICH8 flash access registers. | ||
8158 | * | ||
8159 | * hw - The pointer to the hw structure | ||
8160 | * index - The index of the byte or word to read. | ||
8161 | * size - Size of data to read, 1=byte 2=word | ||
8162 | * data - Pointer to the word to store the value read. | ||
8163 | *****************************************************************************/ | ||
8164 | int32_t | ||
8165 | e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, | ||
8166 | uint32_t size, uint16_t* data) | ||
8167 | { | ||
8168 | union ich8_hws_flash_status hsfsts; | ||
8169 | union ich8_hws_flash_ctrl hsflctl; | ||
8170 | uint32_t flash_linear_address; | ||
8171 | uint32_t flash_data = 0; | ||
8172 | int32_t error = -E1000_ERR_EEPROM; | ||
8173 | int32_t count = 0; | ||
8174 | |||
8175 | DEBUGFUNC("e1000_read_ich8_data"); | ||
8176 | |||
8177 | if (size < 1 || size > 2 || data == 0x0 || | ||
8178 | index > ICH8_FLASH_LINEAR_ADDR_MASK) | ||
8179 | return error; | ||
8180 | |||
8181 | flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + | ||
8182 | hw->flash_base_addr; | ||
8183 | |||
8184 | do { | ||
8185 | udelay(1); | ||
8186 | /* Steps */ | ||
8187 | error = e1000_ich8_cycle_init(hw); | ||
8188 | if (error != E1000_SUCCESS) | ||
8189 | break; | ||
8190 | |||
8191 | hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); | ||
8192 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | ||
8193 | hsflctl.hsf_ctrl.fldbcount = size - 1; | ||
8194 | hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ; | ||
8195 | E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); | ||
8196 | |||
8197 | /* Write the last 24 bits of index into Flash Linear address field in | ||
8198 | * Flash Address */ | ||
8199 | /* TODO: TBD maybe check the index against the size of flash */ | ||
8200 | |||
8201 | E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); | ||
8202 | |||
8203 | error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); | ||
8204 | |||
8205 | /* Check if FCERR is set to 1, if set to 1, clear it and try the whole | ||
8206 | * sequence a few more times, else read in (shift in) the Flash Data0, | ||
8207 | * the order is least significant byte first msb to lsb */ | ||
8208 | if (error == E1000_SUCCESS) { | ||
8209 | flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0); | ||
8210 | if (size == 1) { | ||
8211 | *data = (uint8_t)(flash_data & 0x000000FF); | ||
8212 | } else if (size == 2) { | ||
8213 | *data = (uint16_t)(flash_data & 0x0000FFFF); | ||
8214 | } | ||
8215 | break; | ||
8216 | } else { | ||
8217 | /* If we've gotten here, then things are probably completely hosed, | ||
8218 | * but if the error condition is detected, it won't hurt to give | ||
8219 | * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. | ||
8220 | */ | ||
8221 | hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); | ||
8222 | if (hsfsts.hsf_status.flcerr == 1) { | ||
8223 | /* Repeat for some time before giving up. */ | ||
8224 | continue; | ||
8225 | } else if (hsfsts.hsf_status.flcdone == 0) { | ||
8226 | DEBUGOUT("Timeout error - flash cycle did not complete."); | ||
8227 | break; | ||
8228 | } | ||
8229 | } | ||
8230 | } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); | ||
8231 | |||
8232 | return error; | ||
8233 | } | ||
8234 | |||
8235 | /****************************************************************************** | ||
8236 | * Writes One /two bytes to the NVM using the ICH8 flash access registers. | ||
8237 | * | ||
8238 | * hw - The pointer to the hw structure | ||
8239 | * index - The index of the byte/word to read. | ||
8240 | * size - Size of data to read, 1=byte 2=word | ||
8241 | * data - The byte(s) to write to the NVM. | ||
8242 | *****************************************************************************/ | ||
8243 | int32_t | ||
8244 | e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, | ||
8245 | uint16_t data) | ||
8246 | { | ||
8247 | union ich8_hws_flash_status hsfsts; | ||
8248 | union ich8_hws_flash_ctrl hsflctl; | ||
8249 | uint32_t flash_linear_address; | ||
8250 | uint32_t flash_data = 0; | ||
8251 | int32_t error = -E1000_ERR_EEPROM; | ||
8252 | int32_t count = 0; | ||
8253 | |||
8254 | DEBUGFUNC("e1000_write_ich8_data"); | ||
8255 | |||
8256 | if (size < 1 || size > 2 || data > size * 0xff || | ||
8257 | index > ICH8_FLASH_LINEAR_ADDR_MASK) | ||
8258 | return error; | ||
8259 | |||
8260 | flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + | ||
8261 | hw->flash_base_addr; | ||
8262 | |||
8263 | do { | ||
8264 | udelay(1); | ||
8265 | /* Steps */ | ||
8266 | error = e1000_ich8_cycle_init(hw); | ||
8267 | if (error != E1000_SUCCESS) | ||
8268 | break; | ||
8269 | |||
8270 | hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); | ||
8271 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | ||
8272 | hsflctl.hsf_ctrl.fldbcount = size -1; | ||
8273 | hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE; | ||
8274 | E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); | ||
8275 | |||
8276 | /* Write the last 24 bits of index into Flash Linear address field in | ||
8277 | * Flash Address */ | ||
8278 | E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); | ||
8279 | |||
8280 | if (size == 1) | ||
8281 | flash_data = (uint32_t)data & 0x00FF; | ||
8282 | else | ||
8283 | flash_data = (uint32_t)data; | ||
8284 | |||
8285 | E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data); | ||
8286 | |||
8287 | /* check if FCERR is set to 1 , if set to 1, clear it and try the whole | ||
8288 | * sequence a few more times else done */ | ||
8289 | error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); | ||
8290 | if (error == E1000_SUCCESS) { | ||
8291 | break; | ||
8292 | } else { | ||
8293 | /* If we're here, then things are most likely completely hosed, | ||
8294 | * but if the error condition is detected, it won't hurt to give | ||
8295 | * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. | ||
8296 | */ | ||
8297 | hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); | ||
8298 | if (hsfsts.hsf_status.flcerr == 1) { | ||
8299 | /* Repeat for some time before giving up. */ | ||
8300 | continue; | ||
8301 | } else if (hsfsts.hsf_status.flcdone == 0) { | ||
8302 | DEBUGOUT("Timeout error - flash cycle did not complete."); | ||
8303 | break; | ||
8304 | } | ||
8305 | } | ||
8306 | } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); | ||
8307 | |||
8308 | return error; | ||
8309 | } | ||
8310 | |||
8311 | /****************************************************************************** | ||
8312 | * Reads a single byte from the NVM using the ICH8 flash access registers. | ||
8313 | * | ||
8314 | * hw - pointer to e1000_hw structure | ||
8315 | * index - The index of the byte to read. | ||
8316 | * data - Pointer to a byte to store the value read. | ||
8317 | *****************************************************************************/ | ||
8318 | int32_t | ||
8319 | e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) | ||
8320 | { | ||
8321 | int32_t status = E1000_SUCCESS; | ||
8322 | uint16_t word = 0; | ||
8323 | |||
8324 | status = e1000_read_ich8_data(hw, index, 1, &word); | ||
8325 | if (status == E1000_SUCCESS) { | ||
8326 | *data = (uint8_t)word; | ||
8327 | } | ||
8328 | |||
8329 | return status; | ||
8330 | } | ||
8331 | |||
8332 | /****************************************************************************** | ||
8333 | * Writes a single byte to the NVM using the ICH8 flash access registers. | ||
8334 | * Performs verification by reading back the value and then going through | ||
8335 | * a retry algorithm before giving up. | ||
8336 | * | ||
8337 | * hw - pointer to e1000_hw structure | ||
8338 | * index - The index of the byte to write. | ||
8339 | * byte - The byte to write to the NVM. | ||
8340 | *****************************************************************************/ | ||
8341 | int32_t | ||
8342 | e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) | ||
8343 | { | ||
8344 | int32_t error = E1000_SUCCESS; | ||
8345 | int32_t program_retries; | ||
8346 | uint8_t temp_byte; | ||
8347 | |||
8348 | e1000_write_ich8_byte(hw, index, byte); | ||
8349 | udelay(100); | ||
8350 | |||
8351 | for (program_retries = 0; program_retries < 100; program_retries++) { | ||
8352 | e1000_read_ich8_byte(hw, index, &temp_byte); | ||
8353 | if (temp_byte == byte) | ||
8354 | break; | ||
8355 | udelay(10); | ||
8356 | e1000_write_ich8_byte(hw, index, byte); | ||
8357 | udelay(100); | ||
8358 | } | ||
8359 | if (program_retries == 100) | ||
8360 | error = E1000_ERR_EEPROM; | ||
8361 | |||
8362 | return error; | ||
8363 | } | ||
8364 | |||
8365 | /****************************************************************************** | ||
8366 | * Writes a single byte to the NVM using the ICH8 flash access registers. | ||
8367 | * | ||
8368 | * hw - pointer to e1000_hw structure | ||
8369 | * index - The index of the byte to read. | ||
8370 | * data - The byte to write to the NVM. | ||
8371 | *****************************************************************************/ | ||
8372 | int32_t | ||
8373 | e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) | ||
8374 | { | ||
8375 | int32_t status = E1000_SUCCESS; | ||
8376 | uint16_t word = (uint16_t)data; | ||
8377 | |||
8378 | status = e1000_write_ich8_data(hw, index, 1, word); | ||
8379 | |||
8380 | return status; | ||
8381 | } | ||
8382 | |||
8383 | /****************************************************************************** | ||
8384 | * Reads a word from the NVM using the ICH8 flash access registers. | ||
8385 | * | ||
8386 | * hw - pointer to e1000_hw structure | ||
8387 | * index - The starting byte index of the word to read. | ||
8388 | * data - Pointer to a word to store the value read. | ||
8389 | *****************************************************************************/ | ||
8390 | int32_t | ||
8391 | e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) | ||
8392 | { | ||
8393 | int32_t status = E1000_SUCCESS; | ||
8394 | status = e1000_read_ich8_data(hw, index, 2, data); | ||
8395 | return status; | ||
8396 | } | ||
8397 | |||
8398 | /****************************************************************************** | ||
8399 | * Writes a word to the NVM using the ICH8 flash access registers. | ||
8400 | * | ||
8401 | * hw - pointer to e1000_hw structure | ||
8402 | * index - The starting byte index of the word to read. | ||
8403 | * data - The word to write to the NVM. | ||
8404 | *****************************************************************************/ | ||
8405 | int32_t | ||
8406 | e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data) | ||
8407 | { | ||
8408 | int32_t status = E1000_SUCCESS; | ||
8409 | status = e1000_write_ich8_data(hw, index, 2, data); | ||
8410 | return status; | ||
8411 | } | ||
8412 | |||
8413 | /****************************************************************************** | ||
8414 | * Erases the bank specified. Each bank is a 4k block. Segments are 0 based. | ||
8415 | * segment N is 4096 * N + flash_reg_addr. | ||
8416 | * | ||
8417 | * hw - pointer to e1000_hw structure | ||
8418 | * segment - 0 for first segment, 1 for second segment, etc. | ||
8419 | *****************************************************************************/ | ||
8420 | int32_t | ||
8421 | e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment) | ||
8422 | { | ||
8423 | union ich8_hws_flash_status hsfsts; | ||
8424 | union ich8_hws_flash_ctrl hsflctl; | ||
8425 | uint32_t flash_linear_address; | ||
8426 | int32_t count = 0; | ||
8427 | int32_t error = E1000_ERR_EEPROM; | ||
8428 | int32_t iteration, seg_size; | ||
8429 | int32_t sector_size; | ||
8430 | int32_t j = 0; | ||
8431 | int32_t error_flag = 0; | ||
8432 | |||
8433 | hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); | ||
8434 | |||
8435 | /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ | ||
8436 | /* 00: The Hw sector is 256 bytes, hence we need to erase 16 | ||
8437 | * consecutive sectors. The start index for the nth Hw sector can be | ||
8438 | * calculated as = segment * 4096 + n * 256 | ||
8439 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | ||
8440 | * The start index for the nth Hw sector can be calculated | ||
8441 | * as = segment * 4096 | ||
8442 | * 10: Error condition | ||
8443 | * 11: The Hw sector size is much bigger than the size asked to | ||
8444 | * erase...error condition */ | ||
8445 | if (hsfsts.hsf_status.berasesz == 0x0) { | ||
8446 | /* Hw sector size 256 */ | ||
8447 | sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256; | ||
8448 | iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256; | ||
8449 | } else if (hsfsts.hsf_status.berasesz == 0x1) { | ||
8450 | sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K; | ||
8451 | iteration = 1; | ||
8452 | } else if (hsfsts.hsf_status.berasesz == 0x3) { | ||
8453 | sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K; | ||
8454 | iteration = 1; | ||
8455 | } else { | ||
8456 | return error; | ||
8457 | } | ||
8458 | |||
8459 | for (j = 0; j < iteration ; j++) { | ||
8460 | do { | ||
8461 | count++; | ||
8462 | /* Steps */ | ||
8463 | error = e1000_ich8_cycle_init(hw); | ||
8464 | if (error != E1000_SUCCESS) { | ||
8465 | error_flag = 1; | ||
8466 | break; | ||
8467 | } | ||
8468 | |||
8469 | /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash | ||
8470 | * Control */ | ||
8471 | hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); | ||
8472 | hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE; | ||
8473 | E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); | ||
8474 | |||
8475 | /* Write the last 24 bits of an index within the block into Flash | ||
8476 | * Linear address field in Flash Address. This probably needs to | ||
8477 | * be calculated here based off the on-chip segment size and the | ||
8478 | * software segment size assumed (4K) */ | ||
8479 | /* TBD */ | ||
8480 | flash_linear_address = segment * sector_size + j * seg_size; | ||
8481 | flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK; | ||
8482 | flash_linear_address += hw->flash_base_addr; | ||
8483 | |||
8484 | E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); | ||
8485 | |||
8486 | error = e1000_ich8_flash_cycle(hw, 1000000); | ||
8487 | /* Check if FCERR is set to 1. If 1, clear it and try the whole | ||
8488 | * sequence a few more times else Done */ | ||
8489 | if (error == E1000_SUCCESS) { | ||
8490 | break; | ||
8491 | } else { | ||
8492 | hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); | ||
8493 | if (hsfsts.hsf_status.flcerr == 1) { | ||
8494 | /* repeat for some time before giving up */ | ||
8495 | continue; | ||
8496 | } else if (hsfsts.hsf_status.flcdone == 0) { | ||
8497 | error_flag = 1; | ||
8498 | break; | ||
8499 | } | ||
8500 | } | ||
8501 | } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); | ||
8502 | if (error_flag == 1) | ||
8503 | break; | ||
8504 | } | ||
8505 | if (error_flag != 1) | ||
8506 | error = E1000_SUCCESS; | ||
8507 | return error; | ||
8508 | } | ||
8509 | |||
8510 | /****************************************************************************** | ||
8511 | * | ||
8512 | * Reverse duplex setting without breaking the link. | ||
8513 | * | ||
8514 | * hw: Struct containing variables accessed by shared code | ||
8515 | * | ||
8516 | *****************************************************************************/ | ||
8517 | int32_t | ||
8518 | e1000_duplex_reversal(struct e1000_hw *hw) | ||
8519 | { | ||
8520 | int32_t ret_val; | ||
8521 | uint16_t phy_data; | ||
8522 | |||
8523 | if (hw->phy_type != e1000_phy_igp_3) | ||
8524 | return E1000_SUCCESS; | ||
8525 | |||
8526 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | ||
8527 | if (ret_val) | ||
8528 | return ret_val; | ||
8529 | |||
8530 | phy_data ^= MII_CR_FULL_DUPLEX; | ||
8531 | |||
8532 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | ||
8533 | if (ret_val) | ||
8534 | return ret_val; | ||
8535 | |||
8536 | ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data); | ||
8537 | if (ret_val) | ||
8538 | return ret_val; | ||
8539 | |||
8540 | phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET; | ||
8541 | ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data); | ||
8542 | |||
8543 | return ret_val; | ||
8544 | } | ||
8545 | |||
8546 | int32_t | ||
8547 | e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, | ||
8548 | uint32_t cnf_base_addr, uint32_t cnf_size) | ||
8549 | { | ||
8550 | uint32_t ret_val = E1000_SUCCESS; | ||
8551 | uint16_t word_addr, reg_data, reg_addr; | ||
8552 | uint16_t i; | ||
8553 | |||
8554 | /* cnf_base_addr is in DWORD */ | ||
8555 | word_addr = (uint16_t)(cnf_base_addr << 1); | ||
8556 | |||
8557 | /* cnf_size is returned in size of dwords */ | ||
8558 | for (i = 0; i < cnf_size; i++) { | ||
8559 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); | ||
8560 | if (ret_val) | ||
8561 | return ret_val; | ||
8562 | |||
8563 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); | ||
8564 | if (ret_val) | ||
8565 | return ret_val; | ||
8566 | |||
8567 | ret_val = e1000_get_software_flag(hw); | ||
8568 | if (ret_val != E1000_SUCCESS) | ||
8569 | return ret_val; | ||
8570 | |||
8571 | ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); | ||
8572 | |||
8573 | e1000_release_software_flag(hw); | ||
8574 | } | ||
8575 | |||
8576 | return ret_val; | ||
8577 | } | ||
8578 | |||
8579 | |||
8580 | int32_t | ||
8581 | e1000_init_lcd_from_nvm(struct e1000_hw *hw) | ||
8582 | { | ||
8583 | uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; | ||
8584 | |||
8585 | if (hw->phy_type != e1000_phy_igp_3) | ||
8586 | return E1000_SUCCESS; | ||
8587 | |||
8588 | /* Check if SW needs configure the PHY */ | ||
8589 | reg_data = E1000_READ_REG(hw, FEXTNVM); | ||
8590 | if (!(reg_data & FEXTNVM_SW_CONFIG)) | ||
8591 | return E1000_SUCCESS; | ||
8592 | |||
8593 | /* Wait for basic configuration completes before proceeding*/ | ||
8594 | loop = 0; | ||
8595 | do { | ||
8596 | reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; | ||
8597 | udelay(100); | ||
8598 | loop++; | ||
8599 | } while ((!reg_data) && (loop < 50)); | ||
8600 | |||
8601 | /* Clear the Init Done bit for the next init event */ | ||
8602 | reg_data = E1000_READ_REG(hw, STATUS); | ||
8603 | reg_data &= ~E1000_STATUS_LAN_INIT_DONE; | ||
8604 | E1000_WRITE_REG(hw, STATUS, reg_data); | ||
8605 | |||
8606 | /* Make sure HW does not configure LCD from PHY extended configuration | ||
8607 | before SW configuration */ | ||
8608 | reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); | ||
8609 | if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { | ||
8610 | reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); | ||
8611 | cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; | ||
8612 | cnf_size >>= 16; | ||
8613 | if (cnf_size) { | ||
8614 | reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); | ||
8615 | cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; | ||
8616 | /* cnf_base_addr is in DWORD */ | ||
8617 | cnf_base_addr >>= 16; | ||
8618 | |||
8619 | /* Configure LCD from extended configuration region. */ | ||
8620 | ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, | ||
8621 | cnf_size); | ||
8622 | if (ret_val) | ||
8623 | return ret_val; | ||
8624 | } | ||
8625 | } | ||
8626 | |||
8627 | return E1000_SUCCESS; | ||
8628 | } | ||
8629 | |||
8630 | |||
7633 | 8631 | ||