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path: root/drivers/net/e1000/e1000_hw.c
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c1984
1 files changed, 1596 insertions, 388 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 786a9b935659..b7a7ceb67f47 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -63,10 +63,11 @@ static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64static void e1000_release_eeprom(struct e1000_hw *hw); 64static void e1000_release_eeprom(struct e1000_hw *hw);
65static void e1000_standby_eeprom(struct e1000_hw *hw); 65static void e1000_standby_eeprom(struct e1000_hw *hw);
66static int32_t e1000_id_led_init(struct e1000_hw * hw);
67static int32_t e1000_set_vco_speed(struct e1000_hw *hw); 66static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); 67static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 68static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
69static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
70static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
70 71
71/* IGP cable length table */ 72/* IGP cable length table */
72static const 73static const
@@ -80,6 +81,17 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
80 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 81 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 82 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82 83
84static const
85uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
86 { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,
87 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,
88 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,
89 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,
90 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,
91 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,
92 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,
93 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};
94
83 95
84/****************************************************************************** 96/******************************************************************************
85 * Set the phy type member in the hw struct. 97 * Set the phy type member in the hw struct.
@@ -91,10 +103,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
91{ 103{
92 DEBUGFUNC("e1000_set_phy_type"); 104 DEBUGFUNC("e1000_set_phy_type");
93 105
106 if(hw->mac_type == e1000_undefined)
107 return -E1000_ERR_PHY_TYPE;
108
94 switch(hw->phy_id) { 109 switch(hw->phy_id) {
95 case M88E1000_E_PHY_ID: 110 case M88E1000_E_PHY_ID:
96 case M88E1000_I_PHY_ID: 111 case M88E1000_I_PHY_ID:
97 case M88E1011_I_PHY_ID: 112 case M88E1011_I_PHY_ID:
113 case M88E1111_I_PHY_ID:
98 hw->phy_type = e1000_phy_m88; 114 hw->phy_type = e1000_phy_m88;
99 break; 115 break;
100 case IGP01E1000_I_PHY_ID: 116 case IGP01E1000_I_PHY_ID:
@@ -271,6 +287,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
271 case E1000_DEV_ID_82546GB_FIBER: 287 case E1000_DEV_ID_82546GB_FIBER:
272 case E1000_DEV_ID_82546GB_SERDES: 288 case E1000_DEV_ID_82546GB_SERDES:
273 case E1000_DEV_ID_82546GB_PCIE: 289 case E1000_DEV_ID_82546GB_PCIE:
290 case E1000_DEV_ID_82546GB_QUAD_COPPER:
274 hw->mac_type = e1000_82546_rev_3; 291 hw->mac_type = e1000_82546_rev_3;
275 break; 292 break;
276 case E1000_DEV_ID_82541EI: 293 case E1000_DEV_ID_82541EI:
@@ -289,12 +306,19 @@ e1000_set_mac_type(struct e1000_hw *hw)
289 case E1000_DEV_ID_82547GI: 306 case E1000_DEV_ID_82547GI:
290 hw->mac_type = e1000_82547_rev_2; 307 hw->mac_type = e1000_82547_rev_2;
291 break; 308 break;
309 case E1000_DEV_ID_82573E:
310 case E1000_DEV_ID_82573E_IAMT:
311 hw->mac_type = e1000_82573;
312 break;
292 default: 313 default:
293 /* Should never have loaded on this device */ 314 /* Should never have loaded on this device */
294 return -E1000_ERR_MAC_TYPE; 315 return -E1000_ERR_MAC_TYPE;
295 } 316 }
296 317
297 switch(hw->mac_type) { 318 switch(hw->mac_type) {
319 case e1000_82573:
320 hw->eeprom_semaphore_present = TRUE;
321 /* fall through */
298 case e1000_82541: 322 case e1000_82541:
299 case e1000_82547: 323 case e1000_82547:
300 case e1000_82541_rev_2: 324 case e1000_82541_rev_2:
@@ -360,6 +384,9 @@ e1000_reset_hw(struct e1000_hw *hw)
360 uint32_t icr; 384 uint32_t icr;
361 uint32_t manc; 385 uint32_t manc;
362 uint32_t led_ctrl; 386 uint32_t led_ctrl;
387 uint32_t timeout;
388 uint32_t extcnf_ctrl;
389 int32_t ret_val;
363 390
364 DEBUGFUNC("e1000_reset_hw"); 391 DEBUGFUNC("e1000_reset_hw");
365 392
@@ -369,6 +396,15 @@ e1000_reset_hw(struct e1000_hw *hw)
369 e1000_pci_clear_mwi(hw); 396 e1000_pci_clear_mwi(hw);
370 } 397 }
371 398
399 if(hw->bus_type == e1000_bus_type_pci_express) {
400 /* Prevent the PCI-E bus from sticking if there is no TLP connection
401 * on the last TLP read/write transaction when MAC is reset.
402 */
403 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
404 DEBUGOUT("PCI-E Master disable polling has failed.\n");
405 }
406 }
407
372 /* Clear interrupt mask to stop board from generating interrupts */ 408 /* Clear interrupt mask to stop board from generating interrupts */
373 DEBUGOUT("Masking off all interrupts\n"); 409 DEBUGOUT("Masking off all interrupts\n");
374 E1000_WRITE_REG(hw, IMC, 0xffffffff); 410 E1000_WRITE_REG(hw, IMC, 0xffffffff);
@@ -393,10 +429,32 @@ e1000_reset_hw(struct e1000_hw *hw)
393 429
394 /* Must reset the PHY before resetting the MAC */ 430 /* Must reset the PHY before resetting the MAC */
395 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 431 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
396 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 432 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
397 msec_delay(5); 433 msec_delay(5);
398 } 434 }
399 435
436 /* Must acquire the MDIO ownership before MAC reset.
437 * Ownership defaults to firmware after a reset. */
438 if(hw->mac_type == e1000_82573) {
439 timeout = 10;
440
441 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
442 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
443
444 do {
445 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
446 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
447
448 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
449 break;
450 else
451 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
452
453 msec_delay(2);
454 timeout--;
455 } while(timeout);
456 }
457
400 /* Issue a global reset to the MAC. This will reset the chip's 458 /* Issue a global reset to the MAC. This will reset the chip's
401 * transmit, receive, DMA, and link units. It will not effect 459 * transmit, receive, DMA, and link units. It will not effect
402 * the current PCI configuration. The global reset bit is self- 460 * the current PCI configuration. The global reset bit is self-
@@ -450,6 +508,18 @@ e1000_reset_hw(struct e1000_hw *hw)
450 /* Wait for EEPROM reload */ 508 /* Wait for EEPROM reload */
451 msec_delay(20); 509 msec_delay(20);
452 break; 510 break;
511 case e1000_82573:
512 udelay(10);
513 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
514 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
515 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
516 E1000_WRITE_FLUSH(hw);
517 /* fall through */
518 ret_val = e1000_get_auto_rd_done(hw);
519 if(ret_val)
520 /* We don't want to continue accessing MAC registers. */
521 return ret_val;
522 break;
453 default: 523 default:
454 /* Wait for EEPROM reload (it happens automatically) */ 524 /* Wait for EEPROM reload (it happens automatically) */
455 msec_delay(5); 525 msec_delay(5);
@@ -457,7 +527,7 @@ e1000_reset_hw(struct e1000_hw *hw)
457 } 527 }
458 528
459 /* Disable HW ARPs on ASF enabled adapters */ 529 /* Disable HW ARPs on ASF enabled adapters */
460 if(hw->mac_type >= e1000_82540) { 530 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
461 manc = E1000_READ_REG(hw, MANC); 531 manc = E1000_READ_REG(hw, MANC);
462 manc &= ~(E1000_MANC_ARP_EN); 532 manc &= ~(E1000_MANC_ARP_EN);
463 E1000_WRITE_REG(hw, MANC, manc); 533 E1000_WRITE_REG(hw, MANC, manc);
@@ -510,6 +580,8 @@ e1000_init_hw(struct e1000_hw *hw)
510 uint16_t pcix_stat_hi_word; 580 uint16_t pcix_stat_hi_word;
511 uint16_t cmd_mmrbc; 581 uint16_t cmd_mmrbc;
512 uint16_t stat_mmrbc; 582 uint16_t stat_mmrbc;
583 uint32_t mta_size;
584
513 DEBUGFUNC("e1000_init_hw"); 585 DEBUGFUNC("e1000_init_hw");
514 586
515 /* Initialize Identification LED */ 587 /* Initialize Identification LED */
@@ -524,8 +596,8 @@ e1000_init_hw(struct e1000_hw *hw)
524 596
525 /* Disabling VLAN filtering. */ 597 /* Disabling VLAN filtering. */
526 DEBUGOUT("Initializing the IEEE VLAN\n"); 598 DEBUGOUT("Initializing the IEEE VLAN\n");
527 E1000_WRITE_REG(hw, VET, 0); 599 if (hw->mac_type < e1000_82545_rev_3)
528 600 E1000_WRITE_REG(hw, VET, 0);
529 e1000_clear_vfta(hw); 601 e1000_clear_vfta(hw);
530 602
531 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 603 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
@@ -553,14 +625,16 @@ e1000_init_hw(struct e1000_hw *hw)
553 625
554 /* Zero out the Multicast HASH table */ 626 /* Zero out the Multicast HASH table */
555 DEBUGOUT("Zeroing the MTA\n"); 627 DEBUGOUT("Zeroing the MTA\n");
556 for(i = 0; i < E1000_MC_TBL_SIZE; i++) 628 mta_size = E1000_MC_TBL_SIZE;
629 for(i = 0; i < mta_size; i++)
557 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 630 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
558 631
559 /* Set the PCI priority bit correctly in the CTRL register. This 632 /* Set the PCI priority bit correctly in the CTRL register. This
560 * determines if the adapter gives priority to receives, or if it 633 * determines if the adapter gives priority to receives, or if it
561 * gives equal priority to transmits and receives. 634 * gives equal priority to transmits and receives. Valid only on
635 * 82542 and 82543 silicon.
562 */ 636 */
563 if(hw->dma_fairness) { 637 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
564 ctrl = E1000_READ_REG(hw, CTRL); 638 ctrl = E1000_READ_REG(hw, CTRL);
565 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 639 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
566 } 640 }
@@ -598,9 +672,21 @@ e1000_init_hw(struct e1000_hw *hw)
598 if(hw->mac_type > e1000_82544) { 672 if(hw->mac_type > e1000_82544) {
599 ctrl = E1000_READ_REG(hw, TXDCTL); 673 ctrl = E1000_READ_REG(hw, TXDCTL);
600 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 674 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
675 switch (hw->mac_type) {
676 default:
677 break;
678 case e1000_82573:
679 ctrl |= E1000_TXDCTL_COUNT_DESC;
680 break;
681 }
601 E1000_WRITE_REG(hw, TXDCTL, ctrl); 682 E1000_WRITE_REG(hw, TXDCTL, ctrl);
602 } 683 }
603 684
685 if (hw->mac_type == e1000_82573) {
686 e1000_enable_tx_pkt_filtering(hw);
687 }
688
689
604 /* Clear all of the statistics registers (clear on read). It is 690 /* Clear all of the statistics registers (clear on read). It is
605 * important that we do this after we have tried to establish link 691 * important that we do this after we have tried to establish link
606 * because the symbol error count will increment wildly if there 692 * because the symbol error count will increment wildly if there
@@ -679,7 +765,7 @@ e1000_setup_link(struct e1000_hw *hw)
679 * control setting, then the variable hw->fc will 765 * control setting, then the variable hw->fc will
680 * be initialized based on a value in the EEPROM. 766 * be initialized based on a value in the EEPROM.
681 */ 767 */
682 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) { 768 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) {
683 DEBUGOUT("EEPROM Read Error\n"); 769 DEBUGOUT("EEPROM Read Error\n");
684 return -E1000_ERR_EEPROM; 770 return -E1000_ERR_EEPROM;
685 } 771 }
@@ -736,6 +822,7 @@ e1000_setup_link(struct e1000_hw *hw)
736 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 822 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 823 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 824 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
825
739 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 826 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
740 827
741 /* Set the flow control receive threshold registers. Normally, 828 /* Set the flow control receive threshold registers. Normally,
@@ -906,20 +993,18 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
906} 993}
907 994
908/****************************************************************************** 995/******************************************************************************
909* Detects which PHY is present and the speed and duplex 996* Make sure we have a valid PHY and change PHY mode before link setup.
910* 997*
911* hw - Struct containing variables accessed by shared code 998* hw - Struct containing variables accessed by shared code
912******************************************************************************/ 999******************************************************************************/
913static int32_t 1000static int32_t
914e1000_setup_copper_link(struct e1000_hw *hw) 1001e1000_copper_link_preconfig(struct e1000_hw *hw)
915{ 1002{
916 uint32_t ctrl; 1003 uint32_t ctrl;
917 uint32_t led_ctrl;
918 int32_t ret_val; 1004 int32_t ret_val;
919 uint16_t i;
920 uint16_t phy_data; 1005 uint16_t phy_data;
921 1006
922 DEBUGFUNC("e1000_setup_copper_link"); 1007 DEBUGFUNC("e1000_copper_link_preconfig");
923 1008
924 ctrl = E1000_READ_REG(hw, CTRL); 1009 ctrl = E1000_READ_REG(hw, CTRL);
925 /* With 82543, we need to force speed and duplex on the MAC equal to what 1010 /* With 82543, we need to force speed and duplex on the MAC equal to what
@@ -933,7 +1018,9 @@ e1000_setup_copper_link(struct e1000_hw *hw)
933 } else { 1018 } else {
934 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1019 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
935 E1000_WRITE_REG(hw, CTRL, ctrl); 1020 E1000_WRITE_REG(hw, CTRL, ctrl);
936 e1000_phy_hw_reset(hw); 1021 ret_val = e1000_phy_hw_reset(hw);
1022 if(ret_val)
1023 return ret_val;
937 } 1024 }
938 1025
939 /* Make sure we have a valid PHY */ 1026 /* Make sure we have a valid PHY */
@@ -961,274 +1048,398 @@ e1000_setup_copper_link(struct e1000_hw *hw)
961 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1048 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
962 hw->phy_reset_disable = FALSE; 1049 hw->phy_reset_disable = FALSE;
963 1050
964 if(!hw->phy_reset_disable) { 1051 return E1000_SUCCESS;
965 if (hw->phy_type == e1000_phy_igp) { 1052}
966 1053
967 ret_val = e1000_phy_reset(hw);
968 if(ret_val) {
969 DEBUGOUT("Error Resetting the PHY\n");
970 return ret_val;
971 }
972 1054
973 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1055/********************************************************************
974 msec_delay(15); 1056* Copper link setup for e1000_phy_igp series.
1057*
1058* hw - Struct containing variables accessed by shared code
1059*********************************************************************/
1060static int32_t
1061e1000_copper_link_igp_setup(struct e1000_hw *hw)
1062{
1063 uint32_t led_ctrl;
1064 int32_t ret_val;
1065 uint16_t phy_data;
975 1066
976 /* Configure activity LED after PHY reset */ 1067 DEBUGFUNC("e1000_copper_link_igp_setup");
977 led_ctrl = E1000_READ_REG(hw, LEDCTL);
978 led_ctrl &= IGP_ACTIVITY_LED_MASK;
979 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
980 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
981 1068
982 /* disable lplu d3 during driver init */ 1069 if (hw->phy_reset_disable)
983 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1070 return E1000_SUCCESS;
984 if(ret_val) { 1071
985 DEBUGOUT("Error Disabling LPLU D3\n"); 1072 ret_val = e1000_phy_reset(hw);
986 return ret_val; 1073 if (ret_val) {
987 } 1074 DEBUGOUT("Error Resetting the PHY\n");
1075 return ret_val;
1076 }
988 1077
989 /* Configure mdi-mdix settings */ 1078 /* Wait 10ms for MAC to configure PHY from eeprom settings */
990 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 1079 msec_delay(15);
991 &phy_data);
992 if(ret_val)
993 return ret_val;
994 1080
995 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1081 /* Configure activity LED after PHY reset */
996 hw->dsp_config_state = e1000_dsp_config_disabled; 1082 led_ctrl = E1000_READ_REG(hw, LEDCTL);
997 /* Force MDI for earlier revs of the IGP PHY */ 1083 led_ctrl &= IGP_ACTIVITY_LED_MASK;
998 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 1084 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
999 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1085 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1000 hw->mdix = 1;
1001 1086
1002 } else { 1087 /* disable lplu d3 during driver init */
1003 hw->dsp_config_state = e1000_dsp_config_enabled; 1088 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1004 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1089 if (ret_val) {
1005 1090 DEBUGOUT("Error Disabling LPLU D3\n");
1006 switch (hw->mdix) { 1091 return ret_val;
1007 case 1: 1092 }
1008 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009 break;
1010 case 2:
1011 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012 break;
1013 case 0:
1014 default:
1015 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1016 break;
1017 }
1018 }
1019 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020 phy_data);
1021 if(ret_val)
1022 return ret_val;
1023 1093
1024 /* set auto-master slave resolution settings */ 1094 /* disable lplu d0 during driver init */
1025 if(hw->autoneg) { 1095 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1026 e1000_ms_type phy_ms_setting = hw->master_slave; 1096 if (ret_val) {
1097 DEBUGOUT("Error Disabling LPLU D0\n");
1098 return ret_val;
1099 }
1100 /* Configure mdi-mdix settings */
1101 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1102 if (ret_val)
1103 return ret_val;
1027 1104
1028 if(hw->ffe_config_state == e1000_ffe_config_active) 1105 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1029 hw->ffe_config_state = e1000_ffe_config_enabled; 1106 hw->dsp_config_state = e1000_dsp_config_disabled;
1107 /* Force MDI for earlier revs of the IGP PHY */
1108 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1109 hw->mdix = 1;
1030 1110
1031 if(hw->dsp_config_state == e1000_dsp_config_activated) 1111 } else {
1032 hw->dsp_config_state = e1000_dsp_config_enabled; 1112 hw->dsp_config_state = e1000_dsp_config_enabled;
1113 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1033 1114
1034 /* when autonegotiation advertisment is only 1000Mbps then we 1115 switch (hw->mdix) {
1035 * should disable SmartSpeed and enable Auto MasterSlave 1116 case 1:
1036 * resolution as hardware default. */ 1117 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1037 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1118 break;
1038 /* Disable SmartSpeed */ 1119 case 2:
1039 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1120 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1040 &phy_data); 1121 break;
1041 if(ret_val) 1122 case 0:
1042 return ret_val; 1123 default:
1043 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1124 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1044 ret_val = e1000_write_phy_reg(hw, 1125 break;
1045 IGP01E1000_PHY_PORT_CONFIG, 1126 }
1046 phy_data); 1127 }
1047 if(ret_val) 1128 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1048 return ret_val; 1129 if(ret_val)
1049 /* Set auto Master/Slave resolution process */ 1130 return ret_val;
1050 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051 if(ret_val)
1052 return ret_val;
1053 phy_data &= ~CR_1000T_MS_ENABLE;
1054 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055 if(ret_val)
1056 return ret_val;
1057 }
1058 1131
1059 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1132 /* set auto-master slave resolution settings */
1060 if(ret_val) 1133 if(hw->autoneg) {
1061 return ret_val; 1134 e1000_ms_type phy_ms_setting = hw->master_slave;
1062 1135
1063 /* load defaults for future use */ 1136 if(hw->ffe_config_state == e1000_ffe_config_active)
1064 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1137 hw->ffe_config_state = e1000_ffe_config_enabled;
1065 ((phy_data & CR_1000T_MS_VALUE) ? 1138
1066 e1000_ms_force_master : 1139 if(hw->dsp_config_state == e1000_dsp_config_activated)
1067 e1000_ms_force_slave) : 1140 hw->dsp_config_state = e1000_dsp_config_enabled;
1068 e1000_ms_auto; 1141
1069 1142 /* when autonegotiation advertisment is only 1000Mbps then we
1070 switch (phy_ms_setting) { 1143 * should disable SmartSpeed and enable Auto MasterSlave
1071 case e1000_ms_force_master: 1144 * resolution as hardware default. */
1072 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1145 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1073 break; 1146 /* Disable SmartSpeed */
1074 case e1000_ms_force_slave: 1147 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1075 phy_data |= CR_1000T_MS_ENABLE;
1076 phy_data &= ~(CR_1000T_MS_VALUE);
1077 break;
1078 case e1000_ms_auto:
1079 phy_data &= ~CR_1000T_MS_ENABLE;
1080 default:
1081 break;
1082 }
1083 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1084 if(ret_val)
1085 return ret_val;
1086 }
1087 } else {
1088 /* Enable CRS on TX. This must be set for half-duplex operation. */
1089 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1090 &phy_data);
1091 if(ret_val) 1148 if(ret_val)
1092 return ret_val; 1149 return ret_val;
1150 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1151 ret_val = e1000_write_phy_reg(hw,
1152 IGP01E1000_PHY_PORT_CONFIG,
1153 phy_data);
1154 if(ret_val)
1155 return ret_val;
1156 /* Set auto Master/Slave resolution process */
1157 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1158 if(ret_val)
1159 return ret_val;
1160 phy_data &= ~CR_1000T_MS_ENABLE;
1161 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1162 if(ret_val)
1163 return ret_val;
1164 }
1093 1165
1094 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1166 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1167 if(ret_val)
1168 return ret_val;
1095 1169
1096 /* Options: 1170 /* load defaults for future use */
1097 * MDI/MDI-X = 0 (default) 1171 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1098 * 0 - Auto for all speeds 1172 ((phy_data & CR_1000T_MS_VALUE) ?
1099 * 1 - MDI mode 1173 e1000_ms_force_master :
1100 * 2 - MDI-X mode 1174 e1000_ms_force_slave) :
1101 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1175 e1000_ms_auto;
1102 */
1103 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104 1176
1105 switch (hw->mdix) { 1177 switch (phy_ms_setting) {
1106 case 1: 1178 case e1000_ms_force_master:
1107 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1179 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1108 break; 1180 break;
1109 case 2: 1181 case e1000_ms_force_slave:
1110 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1182 phy_data |= CR_1000T_MS_ENABLE;
1111 break; 1183 phy_data &= ~(CR_1000T_MS_VALUE);
1112 case 3: 1184 break;
1113 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1185 case e1000_ms_auto:
1114 break; 1186 phy_data &= ~CR_1000T_MS_ENABLE;
1115 case 0:
1116 default: 1187 default:
1117 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1188 break;
1118 break; 1189 }
1119 } 1190 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1191 if(ret_val)
1192 return ret_val;
1193 }
1120 1194
1121 /* Options: 1195 return E1000_SUCCESS;
1122 * disable_polarity_correction = 0 (default) 1196}
1123 * Automatic Correction for Reversed Cable Polarity
1124 * 0 - Disabled
1125 * 1 - Enabled
1126 */
1127 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128 if(hw->disable_polarity_correction == 1)
1129 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1131 phy_data);
1132 if(ret_val)
1133 return ret_val;
1134 1197
1135 /* Force TX_CLK in the Extended PHY Specific Control Register
1136 * to 25MHz clock.
1137 */
1138 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139 &phy_data);
1140 if(ret_val)
1141 return ret_val;
1142 1198
1143 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1199/********************************************************************
1200* Copper link setup for e1000_phy_m88 series.
1201*
1202* hw - Struct containing variables accessed by shared code
1203*********************************************************************/
1204static int32_t
1205e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1206{
1207 int32_t ret_val;
1208 uint16_t phy_data;
1209
1210 DEBUGFUNC("e1000_copper_link_mgp_setup");
1211
1212 if(hw->phy_reset_disable)
1213 return E1000_SUCCESS;
1214
1215 /* Enable CRS on TX. This must be set for half-duplex operation. */
1216 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1217 if(ret_val)
1218 return ret_val;
1219
1220 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1221
1222 /* Options:
1223 * MDI/MDI-X = 0 (default)
1224 * 0 - Auto for all speeds
1225 * 1 - MDI mode
1226 * 2 - MDI-X mode
1227 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1228 */
1229 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1230
1231 switch (hw->mdix) {
1232 case 1:
1233 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1234 break;
1235 case 2:
1236 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1237 break;
1238 case 3:
1239 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1240 break;
1241 case 0:
1242 default:
1243 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1244 break;
1245 }
1144 1246
1145 if (hw->phy_revision < M88E1011_I_REV_4) { 1247 /* Options:
1146 /* Configure Master and Slave downshift values */ 1248 * disable_polarity_correction = 0 (default)
1147 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1249 * Automatic Correction for Reversed Cable Polarity
1250 * 0 - Disabled
1251 * 1 - Enabled
1252 */
1253 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1254 if(hw->disable_polarity_correction == 1)
1255 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1256 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1257 if(ret_val)
1258 return ret_val;
1259
1260 /* Force TX_CLK in the Extended PHY Specific Control Register
1261 * to 25MHz clock.
1262 */
1263 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1264 if(ret_val)
1265 return ret_val;
1266
1267 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1268
1269 if (hw->phy_revision < M88E1011_I_REV_4) {
1270 /* Configure Master and Slave downshift values */
1271 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1148 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1272 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1273 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1150 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1274 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1275 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1152 phy_data); 1276 if(ret_val)
1153 if(ret_val) 1277 return ret_val;
1154 return ret_val; 1278 }
1155 }
1156 1279
1157 /* SW Reset the PHY so all changes take effect */ 1280 /* SW Reset the PHY so all changes take effect */
1158 ret_val = e1000_phy_reset(hw); 1281 ret_val = e1000_phy_reset(hw);
1159 if(ret_val) { 1282 if(ret_val) {
1160 DEBUGOUT("Error Resetting the PHY\n"); 1283 DEBUGOUT("Error Resetting the PHY\n");
1161 return ret_val; 1284 return ret_val;
1162 } 1285 }
1286
1287 return E1000_SUCCESS;
1288}
1289
1290/********************************************************************
1291* Setup auto-negotiation and flow control advertisements,
1292* and then perform auto-negotiation.
1293*
1294* hw - Struct containing variables accessed by shared code
1295*********************************************************************/
1296static int32_t
1297e1000_copper_link_autoneg(struct e1000_hw *hw)
1298{
1299 int32_t ret_val;
1300 uint16_t phy_data;
1301
1302 DEBUGFUNC("e1000_copper_link_autoneg");
1303
1304 /* Perform some bounds checking on the hw->autoneg_advertised
1305 * parameter. If this variable is zero, then set it to the default.
1306 */
1307 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1308
1309 /* If autoneg_advertised is zero, we assume it was not defaulted
1310 * by the calling code so we set to advertise full capability.
1311 */
1312 if(hw->autoneg_advertised == 0)
1313 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1314
1315 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1316 ret_val = e1000_phy_setup_autoneg(hw);
1317 if(ret_val) {
1318 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1319 return ret_val;
1320 }
1321 DEBUGOUT("Restarting Auto-Neg\n");
1322
1323 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1324 * the Auto Neg Restart bit in the PHY control register.
1325 */
1326 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1327 if(ret_val)
1328 return ret_val;
1329
1330 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1331 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1332 if(ret_val)
1333 return ret_val;
1334
1335 /* Does the user want to wait for Auto-Neg to complete here, or
1336 * check at a later time (for example, callback routine).
1337 */
1338 if(hw->wait_autoneg_complete) {
1339 ret_val = e1000_wait_autoneg(hw);
1340 if(ret_val) {
1341 DEBUGOUT("Error while waiting for autoneg to complete\n");
1342 return ret_val;
1163 } 1343 }
1344 }
1164 1345
1165 /* Options: 1346 hw->get_link_status = TRUE;
1166 * autoneg = 1 (default)
1167 * PHY will advertise value(s) parsed from
1168 * autoneg_advertised and fc
1169 * autoneg = 0
1170 * PHY will be set to 10H, 10F, 100H, or 100F
1171 * depending on value parsed from forced_speed_duplex.
1172 */
1173 1347
1174 /* Is autoneg enabled? This is enabled by default or by software 1348 return E1000_SUCCESS;
1175 * override. If so, call e1000_phy_setup_autoneg routine to parse the 1349}
1176 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177 * the user should have provided a speed/duplex override. If so, then
1178 * call e1000_phy_force_speed_duplex to parse and set this up.
1179 */
1180 if(hw->autoneg) {
1181 /* Perform some bounds checking on the hw->autoneg_advertised
1182 * parameter. If this variable is zero, then set it to the default.
1183 */
1184 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1185 1350
1186 /* If autoneg_advertised is zero, we assume it was not defaulted
1187 * by the calling code so we set to advertise full capability.
1188 */
1189 if(hw->autoneg_advertised == 0)
1190 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1191 1351
1192 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1352/******************************************************************************
1193 ret_val = e1000_phy_setup_autoneg(hw); 1353* Config the MAC and the PHY after link is up.
1194 if(ret_val) { 1354* 1) Set up the MAC to the current PHY speed/duplex
1195 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1355* if we are on 82543. If we
1196 return ret_val; 1356* are on newer silicon, we only need to configure
1197 } 1357* collision distance in the Transmit Control Register.
1198 DEBUGOUT("Restarting Auto-Neg\n"); 1358* 2) Set up flow control on the MAC to that established with
1359* the link partner.
1360* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1361*
1362* hw - Struct containing variables accessed by shared code
1363******************************************************************************/
1364static int32_t
1365e1000_copper_link_postconfig(struct e1000_hw *hw)
1366{
1367 int32_t ret_val;
1368 DEBUGFUNC("e1000_copper_link_postconfig");
1369
1370 if(hw->mac_type >= e1000_82544) {
1371 e1000_config_collision_dist(hw);
1372 } else {
1373 ret_val = e1000_config_mac_to_phy(hw);
1374 if(ret_val) {
1375 DEBUGOUT("Error configuring MAC to PHY settings\n");
1376 return ret_val;
1377 }
1378 }
1379 ret_val = e1000_config_fc_after_link_up(hw);
1380 if(ret_val) {
1381 DEBUGOUT("Error Configuring Flow Control\n");
1382 return ret_val;
1383 }
1199 1384
1200 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1385 /* Config DSP to improve Giga link quality */
1201 * the Auto Neg Restart bit in the PHY control register. 1386 if(hw->phy_type == e1000_phy_igp) {
1202 */ 1387 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1203 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1388 if(ret_val) {
1204 if(ret_val) 1389 DEBUGOUT("Error Configuring DSP after link up\n");
1205 return ret_val; 1390 return ret_val;
1391 }
1392 }
1393
1394 return E1000_SUCCESS;
1395}
1206 1396
1207 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1397/******************************************************************************
1208 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1398* Detects which PHY is present and setup the speed and duplex
1209 if(ret_val) 1399*
1210 return ret_val; 1400* hw - Struct containing variables accessed by shared code
1401******************************************************************************/
1402static int32_t
1403e1000_setup_copper_link(struct e1000_hw *hw)
1404{
1405 int32_t ret_val;
1406 uint16_t i;
1407 uint16_t phy_data;
1211 1408
1212 /* Does the user want to wait for Auto-Neg to complete here, or 1409 DEBUGFUNC("e1000_setup_copper_link");
1213 * check at a later time (for example, callback routine). 1410
1214 */ 1411 /* Check if it is a valid PHY and set PHY mode if necessary. */
1215 if(hw->wait_autoneg_complete) { 1412 ret_val = e1000_copper_link_preconfig(hw);
1216 ret_val = e1000_wait_autoneg(hw); 1413 if(ret_val)
1217 if(ret_val) { 1414 return ret_val;
1218 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1415
1219 return ret_val; 1416 if (hw->phy_type == e1000_phy_igp ||
1220 } 1417 hw->phy_type == e1000_phy_igp_2) {
1221 } 1418 ret_val = e1000_copper_link_igp_setup(hw);
1222 hw->get_link_status = TRUE; 1419 if(ret_val)
1223 } else { 1420 return ret_val;
1224 DEBUGOUT("Forcing speed and duplex\n"); 1421 } else if (hw->phy_type == e1000_phy_m88) {
1225 ret_val = e1000_phy_force_speed_duplex(hw); 1422 ret_val = e1000_copper_link_mgp_setup(hw);
1226 if(ret_val) { 1423 if(ret_val)
1227 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1424 return ret_val;
1228 return ret_val; 1425 }
1229 } 1426
1427 if(hw->autoneg) {
1428 /* Setup autoneg and flow control advertisement
1429 * and perform autonegotiation */
1430 ret_val = e1000_copper_link_autoneg(hw);
1431 if(ret_val)
1432 return ret_val;
1433 } else {
1434 /* PHY will be set to 10H, 10F, 100H,or 100F
1435 * depending on value from forced_speed_duplex. */
1436 DEBUGOUT("Forcing speed and duplex\n");
1437 ret_val = e1000_phy_force_speed_duplex(hw);
1438 if(ret_val) {
1439 DEBUGOUT("Error Forcing Speed and Duplex\n");
1440 return ret_val;
1230 } 1441 }
1231 } /* !hw->phy_reset_disable */ 1442 }
1232 1443
1233 /* Check link status. Wait up to 100 microseconds for link to become 1444 /* Check link status. Wait up to 100 microseconds for link to become
1234 * valid. 1445 * valid.
@@ -1242,37 +1453,11 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1242 return ret_val; 1453 return ret_val;
1243 1454
1244 if(phy_data & MII_SR_LINK_STATUS) { 1455 if(phy_data & MII_SR_LINK_STATUS) {
1245 /* We have link, so we need to finish the config process: 1456 /* Config the MAC and PHY after link is up */
1246 * 1) Set up the MAC to the current PHY speed/duplex 1457 ret_val = e1000_copper_link_postconfig(hw);
1247 * if we are on 82543. If we 1458 if(ret_val)
1248 * are on newer silicon, we only need to configure
1249 * collision distance in the Transmit Control Register.
1250 * 2) Set up flow control on the MAC to that established with
1251 * the link partner.
1252 */
1253 if(hw->mac_type >= e1000_82544) {
1254 e1000_config_collision_dist(hw);
1255 } else {
1256 ret_val = e1000_config_mac_to_phy(hw);
1257 if(ret_val) {
1258 DEBUGOUT("Error configuring MAC to PHY settings\n");
1259 return ret_val;
1260 }
1261 }
1262 ret_val = e1000_config_fc_after_link_up(hw);
1263 if(ret_val) {
1264 DEBUGOUT("Error Configuring Flow Control\n");
1265 return ret_val; 1459 return ret_val;
1266 } 1460
1267 DEBUGOUT("Valid link established!!!\n");
1268
1269 if(hw->phy_type == e1000_phy_igp) {
1270 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271 if(ret_val) {
1272 DEBUGOUT("Error Configuring DSP after link up\n");
1273 return ret_val;
1274 }
1275 }
1276 DEBUGOUT("Valid link established!!!\n"); 1461 DEBUGOUT("Valid link established!!!\n");
1277 return E1000_SUCCESS; 1462 return E1000_SUCCESS;
1278 } 1463 }
@@ -1302,10 +1487,10 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1302 if(ret_val) 1487 if(ret_val)
1303 return ret_val; 1488 return ret_val;
1304 1489
1305 /* Read the MII 1000Base-T Control Register (Address 9). */ 1490 /* Read the MII 1000Base-T Control Register (Address 9). */
1306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1491 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307 if(ret_val) 1492 if(ret_val)
1308 return ret_val; 1493 return ret_val;
1309 1494
1310 /* Need to parse both autoneg_advertised and fc and set up 1495 /* Need to parse both autoneg_advertised and fc and set up
1311 * the appropriate PHY registers. First we will parse for 1496 * the appropriate PHY registers. First we will parse for
@@ -1417,7 +1602,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1417 1602
1418 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1603 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1419 1604
1420 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1605 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421 if(ret_val) 1606 if(ret_val)
1422 return ret_val; 1607 return ret_val;
1423 1608
@@ -1678,6 +1863,11 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1678 1863
1679 DEBUGFUNC("e1000_config_mac_to_phy"); 1864 DEBUGFUNC("e1000_config_mac_to_phy");
1680 1865
1866 /* 82544 or newer MAC, Auto Speed Detection takes care of
1867 * MAC speed/duplex configuration.*/
1868 if (hw->mac_type >= e1000_82544)
1869 return E1000_SUCCESS;
1870
1681 /* Read the Device Control Register and set the bits to Force Speed 1871 /* Read the Device Control Register and set the bits to Force Speed
1682 * and Duplex. 1872 * and Duplex.
1683 */ 1873 */
@@ -1688,45 +1878,25 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1688 /* Set up duplex in the Device Control and Transmit Control 1878 /* Set up duplex in the Device Control and Transmit Control
1689 * registers depending on negotiated values. 1879 * registers depending on negotiated values.
1690 */ 1880 */
1691 if (hw->phy_type == e1000_phy_igp) { 1881 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1692 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 1882 if(ret_val)
1693 &phy_data); 1883 return ret_val;
1694 if(ret_val)
1695 return ret_val;
1696
1697 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1698 else ctrl &= ~E1000_CTRL_FD;
1699
1700 e1000_config_collision_dist(hw);
1701 1884
1702 /* Set up speed in the Device Control register depending on 1885 if(phy_data & M88E1000_PSSR_DPLX)
1703 * negotiated values. 1886 ctrl |= E1000_CTRL_FD;
1704 */ 1887 else
1705 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 1888 ctrl &= ~E1000_CTRL_FD;
1706 IGP01E1000_PSSR_SPEED_1000MBPS)
1707 ctrl |= E1000_CTRL_SPD_1000;
1708 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1709 IGP01E1000_PSSR_SPEED_100MBPS)
1710 ctrl |= E1000_CTRL_SPD_100;
1711 } else {
1712 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1713 &phy_data);
1714 if(ret_val)
1715 return ret_val;
1716 1889
1717 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; 1890 e1000_config_collision_dist(hw);
1718 else ctrl &= ~E1000_CTRL_FD;
1719 1891
1720 e1000_config_collision_dist(hw); 1892 /* Set up speed in the Device Control register depending on
1893 * negotiated values.
1894 */
1895 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1896 ctrl |= E1000_CTRL_SPD_1000;
1897 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1898 ctrl |= E1000_CTRL_SPD_100;
1721 1899
1722 /* Set up speed in the Device Control register depending on
1723 * negotiated values.
1724 */
1725 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1726 ctrl |= E1000_CTRL_SPD_1000;
1727 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1728 ctrl |= E1000_CTRL_SPD_100;
1729 }
1730 /* Write the configured values back to the Device Control Reg. */ 1900 /* Write the configured values back to the Device Control Reg. */
1731 E1000_WRITE_REG(hw, CTRL, ctrl); 1901 E1000_WRITE_REG(hw, CTRL, ctrl);
1732 return E1000_SUCCESS; 1902 return E1000_SUCCESS;
@@ -2494,8 +2664,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
2494 2664
2495 DEBUGFUNC("e1000_read_phy_reg"); 2665 DEBUGFUNC("e1000_read_phy_reg");
2496 2666
2497 2667 if((hw->phy_type == e1000_phy_igp ||
2498 if(hw->phy_type == e1000_phy_igp && 2668 hw->phy_type == e1000_phy_igp_2) &&
2499 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2669 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2500 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2670 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2501 (uint16_t)reg_addr); 2671 (uint16_t)reg_addr);
@@ -2600,8 +2770,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
2600 2770
2601 DEBUGFUNC("e1000_write_phy_reg"); 2771 DEBUGFUNC("e1000_write_phy_reg");
2602 2772
2603 2773 if((hw->phy_type == e1000_phy_igp ||
2604 if(hw->phy_type == e1000_phy_igp && 2774 hw->phy_type == e1000_phy_igp_2) &&
2605 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2775 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2606 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2776 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2607 (uint16_t)reg_addr); 2777 (uint16_t)reg_addr);
@@ -2679,19 +2849,27 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
2679 return E1000_SUCCESS; 2849 return E1000_SUCCESS;
2680} 2850}
2681 2851
2852
2682/****************************************************************************** 2853/******************************************************************************
2683* Returns the PHY to the power-on reset state 2854* Returns the PHY to the power-on reset state
2684* 2855*
2685* hw - Struct containing variables accessed by shared code 2856* hw - Struct containing variables accessed by shared code
2686******************************************************************************/ 2857******************************************************************************/
2687void 2858int32_t
2688e1000_phy_hw_reset(struct e1000_hw *hw) 2859e1000_phy_hw_reset(struct e1000_hw *hw)
2689{ 2860{
2690 uint32_t ctrl, ctrl_ext; 2861 uint32_t ctrl, ctrl_ext;
2691 uint32_t led_ctrl; 2862 uint32_t led_ctrl;
2863 int32_t ret_val;
2692 2864
2693 DEBUGFUNC("e1000_phy_hw_reset"); 2865 DEBUGFUNC("e1000_phy_hw_reset");
2694 2866
2867 /* In the case of the phy reset being blocked, it's not an error, we
2868 * simply return success without performing the reset. */
2869 ret_val = e1000_check_phy_reset_block(hw);
2870 if (ret_val)
2871 return E1000_SUCCESS;
2872
2695 DEBUGOUT("Resetting Phy...\n"); 2873 DEBUGOUT("Resetting Phy...\n");
2696 2874
2697 if(hw->mac_type > e1000_82543) { 2875 if(hw->mac_type > e1000_82543) {
@@ -2727,6 +2905,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
2727 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2905 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2728 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2906 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2729 } 2907 }
2908
2909 /* Wait for FW to finish PHY configuration. */
2910 ret_val = e1000_get_phy_cfg_done(hw);
2911
2912 return ret_val;
2730} 2913}
2731 2914
2732/****************************************************************************** 2915/******************************************************************************
@@ -2744,7 +2927,19 @@ e1000_phy_reset(struct e1000_hw *hw)
2744 2927
2745 DEBUGFUNC("e1000_phy_reset"); 2928 DEBUGFUNC("e1000_phy_reset");
2746 2929
2747 if(hw->mac_type != e1000_82541_rev_2) { 2930 /* In the case of the phy reset being blocked, it's not an error, we
2931 * simply return success without performing the reset. */
2932 ret_val = e1000_check_phy_reset_block(hw);
2933 if (ret_val)
2934 return E1000_SUCCESS;
2935
2936 switch (hw->mac_type) {
2937 case e1000_82541_rev_2:
2938 ret_val = e1000_phy_hw_reset(hw);
2939 if(ret_val)
2940 return ret_val;
2941 break;
2942 default:
2748 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2943 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2749 if(ret_val) 2944 if(ret_val)
2750 return ret_val; 2945 return ret_val;
@@ -2755,9 +2950,10 @@ e1000_phy_reset(struct e1000_hw *hw)
2755 return ret_val; 2950 return ret_val;
2756 2951
2757 udelay(1); 2952 udelay(1);
2758 } else e1000_phy_hw_reset(hw); 2953 break;
2954 }
2759 2955
2760 if(hw->phy_type == e1000_phy_igp) 2956 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
2761 e1000_phy_init_script(hw); 2957 e1000_phy_init_script(hw);
2762 2958
2763 return E1000_SUCCESS; 2959 return E1000_SUCCESS;
@@ -2811,6 +3007,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
2811 case e1000_82547_rev_2: 3007 case e1000_82547_rev_2:
2812 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3008 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2813 break; 3009 break;
3010 case e1000_82573:
3011 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3012 break;
2814 default: 3013 default:
2815 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3014 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2816 return -E1000_ERR_CONFIG; 3015 return -E1000_ERR_CONFIG;
@@ -2866,7 +3065,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2866 3065
2867 /* The downshift status is checked only once, after link is established, 3066 /* The downshift status is checked only once, after link is established,
2868 * and it stored in the hw->speed_downgraded parameter. */ 3067 * and it stored in the hw->speed_downgraded parameter. */
2869 phy_info->downshift = hw->speed_downgraded; 3068 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2870 3069
2871 /* IGP01E1000 does not need to support it. */ 3070 /* IGP01E1000 does not need to support it. */
2872 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3071 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
@@ -2905,7 +3104,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2905 if(ret_val) 3104 if(ret_val)
2906 return ret_val; 3105 return ret_val;
2907 3106
2908 /* transalte to old method */ 3107 /* Translate to old method */
2909 average = (max_length + min_length) / 2; 3108 average = (max_length + min_length) / 2;
2910 3109
2911 if(average <= e1000_igp_cable_length_50) 3110 if(average <= e1000_igp_cable_length_50)
@@ -2940,7 +3139,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
2940 3139
2941 /* The downshift status is checked only once, after link is established, 3140 /* The downshift status is checked only once, after link is established,
2942 * and it stored in the hw->speed_downgraded parameter. */ 3141 * and it stored in the hw->speed_downgraded parameter. */
2943 phy_info->downshift = hw->speed_downgraded; 3142 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2944 3143
2945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3144 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2946 if(ret_val) 3145 if(ret_val)
@@ -3029,7 +3228,8 @@ e1000_phy_get_info(struct e1000_hw *hw,
3029 return -E1000_ERR_CONFIG; 3228 return -E1000_ERR_CONFIG;
3030 } 3229 }
3031 3230
3032 if(hw->phy_type == e1000_phy_igp) 3231 if(hw->phy_type == e1000_phy_igp ||
3232 hw->phy_type == e1000_phy_igp_2)
3033 return e1000_phy_igp_get_info(hw, phy_info); 3233 return e1000_phy_igp_get_info(hw, phy_info);
3034 else 3234 else
3035 return e1000_phy_m88_get_info(hw, phy_info); 3235 return e1000_phy_m88_get_info(hw, phy_info);
@@ -3055,11 +3255,12 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
3055 * 3255 *
3056 * hw - Struct containing variables accessed by shared code 3256 * hw - Struct containing variables accessed by shared code
3057 *****************************************************************************/ 3257 *****************************************************************************/
3058void 3258int32_t
3059e1000_init_eeprom_params(struct e1000_hw *hw) 3259e1000_init_eeprom_params(struct e1000_hw *hw)
3060{ 3260{
3061 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3261 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3062 uint32_t eecd = E1000_READ_REG(hw, EECD); 3262 uint32_t eecd = E1000_READ_REG(hw, EECD);
3263 int32_t ret_val = E1000_SUCCESS;
3063 uint16_t eeprom_size; 3264 uint16_t eeprom_size;
3064 3265
3065 DEBUGFUNC("e1000_init_eeprom_params"); 3266 DEBUGFUNC("e1000_init_eeprom_params");
@@ -3074,6 +3275,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3074 eeprom->opcode_bits = 3; 3275 eeprom->opcode_bits = 3;
3075 eeprom->address_bits = 6; 3276 eeprom->address_bits = 6;
3076 eeprom->delay_usec = 50; 3277 eeprom->delay_usec = 50;
3278 eeprom->use_eerd = FALSE;
3279 eeprom->use_eewr = FALSE;
3077 break; 3280 break;
3078 case e1000_82540: 3281 case e1000_82540:
3079 case e1000_82545: 3282 case e1000_82545:
@@ -3090,6 +3293,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3090 eeprom->word_size = 64; 3293 eeprom->word_size = 64;
3091 eeprom->address_bits = 6; 3294 eeprom->address_bits = 6;
3092 } 3295 }
3296 eeprom->use_eerd = FALSE;
3297 eeprom->use_eewr = FALSE;
3093 break; 3298 break;
3094 case e1000_82541: 3299 case e1000_82541:
3095 case e1000_82541_rev_2: 3300 case e1000_82541_rev_2:
@@ -3118,42 +3323,60 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3118 eeprom->address_bits = 6; 3323 eeprom->address_bits = 6;
3119 } 3324 }
3120 } 3325 }
3326 eeprom->use_eerd = FALSE;
3327 eeprom->use_eewr = FALSE;
3328 break;
3329 case e1000_82573:
3330 eeprom->type = e1000_eeprom_spi;
3331 eeprom->opcode_bits = 8;
3332 eeprom->delay_usec = 1;
3333 if (eecd & E1000_EECD_ADDR_BITS) {
3334 eeprom->page_size = 32;
3335 eeprom->address_bits = 16;
3336 } else {
3337 eeprom->page_size = 8;
3338 eeprom->address_bits = 8;
3339 }
3340 eeprom->use_eerd = TRUE;
3341 eeprom->use_eewr = TRUE;
3342 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
3343 eeprom->type = e1000_eeprom_flash;
3344 eeprom->word_size = 2048;
3345
3346 /* Ensure that the Autonomous FLASH update bit is cleared due to
3347 * Flash update issue on parts which use a FLASH for NVM. */
3348 eecd &= ~E1000_EECD_AUPDEN;
3349 E1000_WRITE_REG(hw, EECD, eecd);
3350 }
3121 break; 3351 break;
3122 default: 3352 default:
3123 break; 3353 break;
3124 } 3354 }
3125 3355
3126 if (eeprom->type == e1000_eeprom_spi) { 3356 if (eeprom->type == e1000_eeprom_spi) {
3127 eeprom->word_size = 64; 3357 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3128 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) { 3358 * 32KB (incremented by powers of 2).
3129 eeprom_size &= EEPROM_SIZE_MASK; 3359 */
3130 3360 if(hw->mac_type <= e1000_82547_rev_2) {
3131 switch (eeprom_size) { 3361 /* Set to default value for initial eeprom read. */
3132 case EEPROM_SIZE_16KB: 3362 eeprom->word_size = 64;
3133 eeprom->word_size = 8192; 3363 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3134 break; 3364 if(ret_val)
3135 case EEPROM_SIZE_8KB: 3365 return ret_val;
3136 eeprom->word_size = 4096; 3366 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3137 break; 3367 /* 256B eeprom size was not supported in earlier hardware, so we
3138 case EEPROM_SIZE_4KB: 3368 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3139 eeprom->word_size = 2048; 3369 * is never the result used in the shifting logic below. */
3140 break; 3370 if(eeprom_size)
3141 case EEPROM_SIZE_2KB: 3371 eeprom_size++;
3142 eeprom->word_size = 1024; 3372 } else {
3143 break; 3373 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
3144 case EEPROM_SIZE_1KB: 3374 E1000_EECD_SIZE_EX_SHIFT);
3145 eeprom->word_size = 512;
3146 break;
3147 case EEPROM_SIZE_512B:
3148 eeprom->word_size = 256;
3149 break;
3150 case EEPROM_SIZE_128B:
3151 default:
3152 eeprom->word_size = 64;
3153 break;
3154 }
3155 } 3375 }
3376
3377 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3156 } 3378 }
3379 return ret_val;
3157} 3380}
3158 3381
3159/****************************************************************************** 3382/******************************************************************************
@@ -3306,8 +3529,12 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3306 3529
3307 DEBUGFUNC("e1000_acquire_eeprom"); 3530 DEBUGFUNC("e1000_acquire_eeprom");
3308 3531
3532 if(e1000_get_hw_eeprom_semaphore(hw))
3533 return -E1000_ERR_EEPROM;
3534
3309 eecd = E1000_READ_REG(hw, EECD); 3535 eecd = E1000_READ_REG(hw, EECD);
3310 3536
3537 if (hw->mac_type != e1000_82573) {
3311 /* Request EEPROM Access */ 3538 /* Request EEPROM Access */
3312 if(hw->mac_type > e1000_82544) { 3539 if(hw->mac_type > e1000_82544) {
3313 eecd |= E1000_EECD_REQ; 3540 eecd |= E1000_EECD_REQ;
@@ -3326,6 +3553,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3326 return -E1000_ERR_EEPROM; 3553 return -E1000_ERR_EEPROM;
3327 } 3554 }
3328 } 3555 }
3556 }
3329 3557
3330 /* Setup EEPROM for Read/Write */ 3558 /* Setup EEPROM for Read/Write */
3331 3559
@@ -3443,6 +3671,8 @@ e1000_release_eeprom(struct e1000_hw *hw)
3443 eecd &= ~E1000_EECD_REQ; 3671 eecd &= ~E1000_EECD_REQ;
3444 E1000_WRITE_REG(hw, EECD, eecd); 3672 E1000_WRITE_REG(hw, EECD, eecd);
3445 } 3673 }
3674
3675 e1000_put_hw_eeprom_semaphore(hw);
3446} 3676}
3447 3677
3448/****************************************************************************** 3678/******************************************************************************
@@ -3504,8 +3734,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
3504{ 3734{
3505 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3735 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3506 uint32_t i = 0; 3736 uint32_t i = 0;
3737 int32_t ret_val;
3507 3738
3508 DEBUGFUNC("e1000_read_eeprom"); 3739 DEBUGFUNC("e1000_read_eeprom");
3740
3509 /* A check for invalid values: offset too large, too many words, and not 3741 /* A check for invalid values: offset too large, too many words, and not
3510 * enough words. 3742 * enough words.
3511 */ 3743 */
@@ -3515,9 +3747,23 @@ e1000_read_eeprom(struct e1000_hw *hw,
3515 return -E1000_ERR_EEPROM; 3747 return -E1000_ERR_EEPROM;
3516 } 3748 }
3517 3749
3518 /* Prepare the EEPROM for reading */ 3750 /* FLASH reads without acquiring the semaphore are safe in 82573-based
3519 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3751 * controllers.
3520 return -E1000_ERR_EEPROM; 3752 */
3753 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3754 (hw->mac_type != e1000_82573)) {
3755 /* Prepare the EEPROM for reading */
3756 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3757 return -E1000_ERR_EEPROM;
3758 }
3759
3760 if(eeprom->use_eerd == TRUE) {
3761 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
3762 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3763 (hw->mac_type != e1000_82573))
3764 e1000_release_eeprom(hw);
3765 return ret_val;
3766 }
3521 3767
3522 if(eeprom->type == e1000_eeprom_spi) { 3768 if(eeprom->type == e1000_eeprom_spi) {
3523 uint16_t word_in; 3769 uint16_t word_in;
@@ -3569,6 +3815,132 @@ e1000_read_eeprom(struct e1000_hw *hw,
3569} 3815}
3570 3816
3571/****************************************************************************** 3817/******************************************************************************
3818 * Reads a 16 bit word from the EEPROM using the EERD register.
3819 *
3820 * hw - Struct containing variables accessed by shared code
3821 * offset - offset of word in the EEPROM to read
3822 * data - word read from the EEPROM
3823 * words - number of words to read
3824 *****************************************************************************/
3825int32_t
3826e1000_read_eeprom_eerd(struct e1000_hw *hw,
3827 uint16_t offset,
3828 uint16_t words,
3829 uint16_t *data)
3830{
3831 uint32_t i, eerd = 0;
3832 int32_t error = 0;
3833
3834 for (i = 0; i < words; i++) {
3835 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
3836 E1000_EEPROM_RW_REG_START;
3837
3838 E1000_WRITE_REG(hw, EERD, eerd);
3839 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
3840
3841 if(error) {
3842 break;
3843 }
3844 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
3845
3846 }
3847
3848 return error;
3849}
3850
3851/******************************************************************************
3852 * Writes a 16 bit word from the EEPROM using the EEWR register.
3853 *
3854 * hw - Struct containing variables accessed by shared code
3855 * offset - offset of word in the EEPROM to read
3856 * data - word read from the EEPROM
3857 * words - number of words to read
3858 *****************************************************************************/
3859int32_t
3860e1000_write_eeprom_eewr(struct e1000_hw *hw,
3861 uint16_t offset,
3862 uint16_t words,
3863 uint16_t *data)
3864{
3865 uint32_t register_value = 0;
3866 uint32_t i = 0;
3867 int32_t error = 0;
3868
3869 for (i = 0; i < words; i++) {
3870 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
3871 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
3872 E1000_EEPROM_RW_REG_START;
3873
3874 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3875 if(error) {
3876 break;
3877 }
3878
3879 E1000_WRITE_REG(hw, EEWR, register_value);
3880
3881 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3882
3883 if(error) {
3884 break;
3885 }
3886 }
3887
3888 return error;
3889}
3890
3891/******************************************************************************
3892 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
3893 *
3894 * hw - Struct containing variables accessed by shared code
3895 *****************************************************************************/
3896int32_t
3897e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
3898{
3899 uint32_t attempts = 100000;
3900 uint32_t i, reg = 0;
3901 int32_t done = E1000_ERR_EEPROM;
3902
3903 for(i = 0; i < attempts; i++) {
3904 if(eerd == E1000_EEPROM_POLL_READ)
3905 reg = E1000_READ_REG(hw, EERD);
3906 else
3907 reg = E1000_READ_REG(hw, EEWR);
3908
3909 if(reg & E1000_EEPROM_RW_REG_DONE) {
3910 done = E1000_SUCCESS;
3911 break;
3912 }
3913 udelay(5);
3914 }
3915
3916 return done;
3917}
3918
3919/***************************************************************************
3920* Description: Determines if the onboard NVM is FLASH or EEPROM.
3921*
3922* hw - Struct containing variables accessed by shared code
3923****************************************************************************/
3924boolean_t
3925e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
3926{
3927 uint32_t eecd = 0;
3928
3929 if(hw->mac_type == e1000_82573) {
3930 eecd = E1000_READ_REG(hw, EECD);
3931
3932 /* Isolate bits 15 & 16 */
3933 eecd = ((eecd >> 15) & 0x03);
3934
3935 /* If both bits are set, device is Flash type */
3936 if(eecd == 0x03) {
3937 return FALSE;
3938 }
3939 }
3940 return TRUE;
3941}
3942
3943/******************************************************************************
3572 * Verifies that the EEPROM has a valid checksum 3944 * Verifies that the EEPROM has a valid checksum
3573 * 3945 *
3574 * hw - Struct containing variables accessed by shared code 3946 * hw - Struct containing variables accessed by shared code
@@ -3585,6 +3957,25 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3585 3957
3586 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3958 DEBUGFUNC("e1000_validate_eeprom_checksum");
3587 3959
3960 if ((hw->mac_type == e1000_82573) &&
3961 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
3962 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
3963 * 10h-12h. Checksum may need to be fixed. */
3964 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
3965 if ((eeprom_data & 0x10) == 0) {
3966 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
3967 * has already been fixed. If the checksum is still wrong and this
3968 * bit is a 1, we need to return bad checksum. Otherwise, we need
3969 * to set this bit to a 1 and update the checksum. */
3970 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
3971 if ((eeprom_data & 0x8000) == 0) {
3972 eeprom_data |= 0x8000;
3973 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
3974 e1000_update_eeprom_checksum(hw);
3975 }
3976 }
3977 }
3978
3588 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3979 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3589 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3980 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3590 DEBUGOUT("EEPROM Read Error\n"); 3981 DEBUGOUT("EEPROM Read Error\n");
@@ -3628,6 +4019,8 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
3628 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4019 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3629 DEBUGOUT("EEPROM Write Error\n"); 4020 DEBUGOUT("EEPROM Write Error\n");
3630 return -E1000_ERR_EEPROM; 4021 return -E1000_ERR_EEPROM;
4022 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4023 e1000_commit_shadow_ram(hw);
3631 } 4024 }
3632 return E1000_SUCCESS; 4025 return E1000_SUCCESS;
3633} 4026}
@@ -3663,6 +4056,10 @@ e1000_write_eeprom(struct e1000_hw *hw,
3663 return -E1000_ERR_EEPROM; 4056 return -E1000_ERR_EEPROM;
3664 } 4057 }
3665 4058
4059 /* 82573 reads only through eerd */
4060 if(eeprom->use_eewr == TRUE)
4061 return e1000_write_eeprom_eewr(hw, offset, words, data);
4062
3666 /* Prepare the EEPROM for writing */ 4063 /* Prepare the EEPROM for writing */
3667 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4064 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3668 return -E1000_ERR_EEPROM; 4065 return -E1000_ERR_EEPROM;
@@ -3833,6 +4230,65 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
3833} 4230}
3834 4231
3835/****************************************************************************** 4232/******************************************************************************
4233 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4234 * in the eeprom cache and the non modified values in the currently active bank
4235 * to the new bank.
4236 *
4237 * hw - Struct containing variables accessed by shared code
4238 * offset - offset of word in the EEPROM to read
4239 * data - word read from the EEPROM
4240 * words - number of words to read
4241 *****************************************************************************/
4242int32_t
4243e1000_commit_shadow_ram(struct e1000_hw *hw)
4244{
4245 uint32_t attempts = 100000;
4246 uint32_t eecd = 0;
4247 uint32_t flop = 0;
4248 uint32_t i = 0;
4249 int32_t error = E1000_SUCCESS;
4250
4251 /* The flop register will be used to determine if flash type is STM */
4252 flop = E1000_READ_REG(hw, FLOP);
4253
4254 if (hw->mac_type == e1000_82573) {
4255 for (i=0; i < attempts; i++) {
4256 eecd = E1000_READ_REG(hw, EECD);
4257 if ((eecd & E1000_EECD_FLUPD) == 0) {
4258 break;
4259 }
4260 udelay(5);
4261 }
4262
4263 if (i == attempts) {
4264 return -E1000_ERR_EEPROM;
4265 }
4266
4267 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4268 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4269 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4270 }
4271
4272 /* Perform the flash update */
4273 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4274
4275 for (i=0; i < attempts; i++) {
4276 eecd = E1000_READ_REG(hw, EECD);
4277 if ((eecd & E1000_EECD_FLUPD) == 0) {
4278 break;
4279 }
4280 udelay(5);
4281 }
4282
4283 if (i == attempts) {
4284 return -E1000_ERR_EEPROM;
4285 }
4286 }
4287
4288 return error;
4289}
4290
4291/******************************************************************************
3836 * Reads the adapter's part number from the EEPROM 4292 * Reads the adapter's part number from the EEPROM
3837 * 4293 *
3838 * hw - Struct containing variables accessed by shared code 4294 * hw - Struct containing variables accessed by shared code
@@ -3911,6 +4367,7 @@ void
3911e1000_init_rx_addrs(struct e1000_hw *hw) 4367e1000_init_rx_addrs(struct e1000_hw *hw)
3912{ 4368{
3913 uint32_t i; 4369 uint32_t i;
4370 uint32_t rar_num;
3914 4371
3915 DEBUGFUNC("e1000_init_rx_addrs"); 4372 DEBUGFUNC("e1000_init_rx_addrs");
3916 4373
@@ -3919,9 +4376,10 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
3919 4376
3920 e1000_rar_set(hw, hw->mac_addr, 0); 4377 e1000_rar_set(hw, hw->mac_addr, 0);
3921 4378
4379 rar_num = E1000_RAR_ENTRIES;
3922 /* Zero out the other 15 receive addresses. */ 4380 /* Zero out the other 15 receive addresses. */
3923 DEBUGOUT("Clearing RAR[1-15]\n"); 4381 DEBUGOUT("Clearing RAR[1-15]\n");
3924 for(i = 1; i < E1000_RAR_ENTRIES; i++) { 4382 for(i = 1; i < rar_num; i++) {
3925 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4383 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3926 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4384 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3927 } 4385 }
@@ -3950,7 +4408,9 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3950{ 4408{
3951 uint32_t hash_value; 4409 uint32_t hash_value;
3952 uint32_t i; 4410 uint32_t i;
3953 4411 uint32_t num_rar_entry;
4412 uint32_t num_mta_entry;
4413
3954 DEBUGFUNC("e1000_mc_addr_list_update"); 4414 DEBUGFUNC("e1000_mc_addr_list_update");
3955 4415
3956 /* Set the new number of MC addresses that we are being requested to use. */ 4416 /* Set the new number of MC addresses that we are being requested to use. */
@@ -3958,14 +4418,16 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3958 4418
3959 /* Clear RAR[1-15] */ 4419 /* Clear RAR[1-15] */
3960 DEBUGOUT(" Clearing RAR[1-15]\n"); 4420 DEBUGOUT(" Clearing RAR[1-15]\n");
3961 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) { 4421 num_rar_entry = E1000_RAR_ENTRIES;
4422 for(i = rar_used_count; i < num_rar_entry; i++) {
3962 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4423 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3963 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4424 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3964 } 4425 }
3965 4426
3966 /* Clear the MTA */ 4427 /* Clear the MTA */
3967 DEBUGOUT(" Clearing MTA\n"); 4428 DEBUGOUT(" Clearing MTA\n");
3968 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) { 4429 num_mta_entry = E1000_NUM_MTA_REGISTERS;
4430 for(i = 0; i < num_mta_entry; i++) {
3969 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 4431 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3970 } 4432 }
3971 4433
@@ -3989,7 +4451,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3989 /* Place this multicast address in the RAR if there is room, * 4451 /* Place this multicast address in the RAR if there is room, *
3990 * else put it in the MTA 4452 * else put it in the MTA
3991 */ 4453 */
3992 if(rar_used_count < E1000_RAR_ENTRIES) { 4454 if (rar_used_count < num_rar_entry) {
3993 e1000_rar_set(hw, 4455 e1000_rar_set(hw,
3994 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), 4456 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3995 rar_used_count); 4457 rar_used_count);
@@ -4040,6 +4502,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
4040 } 4502 }
4041 4503
4042 hash_value &= 0xFFF; 4504 hash_value &= 0xFFF;
4505
4043 return hash_value; 4506 return hash_value;
4044} 4507}
4045 4508
@@ -4144,12 +4607,33 @@ void
4144e1000_clear_vfta(struct e1000_hw *hw) 4607e1000_clear_vfta(struct e1000_hw *hw)
4145{ 4608{
4146 uint32_t offset; 4609 uint32_t offset;
4147 4610 uint32_t vfta_value = 0;
4148 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 4611 uint32_t vfta_offset = 0;
4149 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 4612 uint32_t vfta_bit_in_reg = 0;
4613
4614 if (hw->mac_type == e1000_82573) {
4615 if (hw->mng_cookie.vlan_id != 0) {
4616 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4617 * ID. The following operations determine which 32b entry
4618 * (i.e. offset) into the array we want to set the VLAN ID
4619 * (i.e. bit) of the manageability unit. */
4620 vfta_offset = (hw->mng_cookie.vlan_id >>
4621 E1000_VFTA_ENTRY_SHIFT) &
4622 E1000_VFTA_ENTRY_MASK;
4623 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
4624 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
4625 }
4626 }
4627 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4628 /* If the offset we want to clear is the same offset of the
4629 * manageability VLAN ID, then clear all bits except that of the
4630 * manageability unit */
4631 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4632 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4633 }
4150} 4634}
4151 4635
4152static int32_t 4636int32_t
4153e1000_id_led_init(struct e1000_hw * hw) 4637e1000_id_led_init(struct e1000_hw * hw)
4154{ 4638{
4155 uint32_t ledctl; 4639 uint32_t ledctl;
@@ -4480,6 +4964,19 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
4480 temp = E1000_READ_REG(hw, MGTPRC); 4964 temp = E1000_READ_REG(hw, MGTPRC);
4481 temp = E1000_READ_REG(hw, MGTPDC); 4965 temp = E1000_READ_REG(hw, MGTPDC);
4482 temp = E1000_READ_REG(hw, MGTPTC); 4966 temp = E1000_READ_REG(hw, MGTPTC);
4967
4968 if(hw->mac_type <= e1000_82547_rev_2) return;
4969
4970 temp = E1000_READ_REG(hw, IAC);
4971 temp = E1000_READ_REG(hw, ICRXOC);
4972 temp = E1000_READ_REG(hw, ICRXPTC);
4973 temp = E1000_READ_REG(hw, ICRXATC);
4974 temp = E1000_READ_REG(hw, ICTXPTC);
4975 temp = E1000_READ_REG(hw, ICTXATC);
4976 temp = E1000_READ_REG(hw, ICTXQEC);
4977 temp = E1000_READ_REG(hw, ICTXQMTC);
4978 temp = E1000_READ_REG(hw, ICRXDMTC);
4979
4483} 4980}
4484 4981
4485/****************************************************************************** 4982/******************************************************************************
@@ -4646,6 +5143,11 @@ e1000_get_bus_info(struct e1000_hw *hw)
4646 hw->bus_speed = e1000_bus_speed_unknown; 5143 hw->bus_speed = e1000_bus_speed_unknown;
4647 hw->bus_width = e1000_bus_width_unknown; 5144 hw->bus_width = e1000_bus_width_unknown;
4648 break; 5145 break;
5146 case e1000_82573:
5147 hw->bus_type = e1000_bus_type_pci_express;
5148 hw->bus_speed = e1000_bus_speed_2500;
5149 hw->bus_width = e1000_bus_width_pciex_4;
5150 break;
4649 default: 5151 default:
4650 status = E1000_READ_REG(hw, STATUS); 5152 status = E1000_READ_REG(hw, STATUS);
4651 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5153 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
@@ -4749,6 +5251,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
4749 5251
4750 /* Use old method for Phy older than IGP */ 5252 /* Use old method for Phy older than IGP */
4751 if(hw->phy_type == e1000_phy_m88) { 5253 if(hw->phy_type == e1000_phy_m88) {
5254
4752 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5255 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4753 &phy_data); 5256 &phy_data);
4754 if(ret_val) 5257 if(ret_val)
@@ -4865,7 +5368,8 @@ e1000_check_polarity(struct e1000_hw *hw,
4865 return ret_val; 5368 return ret_val;
4866 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 5369 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4867 M88E1000_PSSR_REV_POLARITY_SHIFT; 5370 M88E1000_PSSR_REV_POLARITY_SHIFT;
4868 } else if(hw->phy_type == e1000_phy_igp) { 5371 } else if(hw->phy_type == e1000_phy_igp ||
5372 hw->phy_type == e1000_phy_igp_2) {
4869 /* Read the Status register to check the speed */ 5373 /* Read the Status register to check the speed */
4870 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5374 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4871 &phy_data); 5375 &phy_data);
@@ -4917,7 +5421,8 @@ e1000_check_downshift(struct e1000_hw *hw)
4917 5421
4918 DEBUGFUNC("e1000_check_downshift"); 5422 DEBUGFUNC("e1000_check_downshift");
4919 5423
4920 if(hw->phy_type == e1000_phy_igp) { 5424 if(hw->phy_type == e1000_phy_igp ||
5425 hw->phy_type == e1000_phy_igp_2) {
4921 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5426 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4922 &phy_data); 5427 &phy_data);
4923 if(ret_val) 5428 if(ret_val)
@@ -4933,6 +5438,7 @@ e1000_check_downshift(struct e1000_hw *hw)
4933 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5438 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4934 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5439 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4935 } 5440 }
5441
4936 return E1000_SUCCESS; 5442 return E1000_SUCCESS;
4937} 5443}
4938 5444
@@ -5047,7 +5553,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5047 if(ret_val) 5553 if(ret_val)
5048 return ret_val; 5554 return ret_val;
5049 5555
5050 msec_delay(20); 5556 msec_delay_irq(20);
5051 5557
5052 ret_val = e1000_write_phy_reg(hw, 0x0000, 5558 ret_val = e1000_write_phy_reg(hw, 0x0000,
5053 IGP01E1000_IEEE_FORCE_GIGA); 5559 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5071,7 +5577,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5071 if(ret_val) 5577 if(ret_val)
5072 return ret_val; 5578 return ret_val;
5073 5579
5074 msec_delay(20); 5580 msec_delay_irq(20);
5075 5581
5076 /* Now enable the transmitter */ 5582 /* Now enable the transmitter */
5077 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5583 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5096,7 +5602,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5096 if(ret_val) 5602 if(ret_val)
5097 return ret_val; 5603 return ret_val;
5098 5604
5099 msec_delay(20); 5605 msec_delay_irq(20);
5100 5606
5101 ret_val = e1000_write_phy_reg(hw, 0x0000, 5607 ret_val = e1000_write_phy_reg(hw, 0x0000,
5102 IGP01E1000_IEEE_FORCE_GIGA); 5608 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5112,7 +5618,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5112 if(ret_val) 5618 if(ret_val)
5113 return ret_val; 5619 return ret_val;
5114 5620
5115 msec_delay(20); 5621 msec_delay_irq(20);
5116 5622
5117 /* Now enable the transmitter */ 5623 /* Now enable the transmitter */
5118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5624 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5187,22 +5693,36 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5187 uint16_t phy_data; 5693 uint16_t phy_data;
5188 DEBUGFUNC("e1000_set_d3_lplu_state"); 5694 DEBUGFUNC("e1000_set_d3_lplu_state");
5189 5695
5190 if(!((hw->mac_type == e1000_82541_rev_2) || 5696 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
5191 (hw->mac_type == e1000_82547_rev_2)))
5192 return E1000_SUCCESS; 5697 return E1000_SUCCESS;
5193 5698
5194 /* During driver activity LPLU should not be used or it will attain link 5699 /* During driver activity LPLU should not be used or it will attain link
5195 * from the lowest speeds starting from 10Mbps. The capability is used for 5700 * from the lowest speeds starting from 10Mbps. The capability is used for
5196 * Dx transitions and states */ 5701 * Dx transitions and states */
5197 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5702 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
5198 if(ret_val) 5703 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5199 return ret_val;
5200
5201 if(!active) {
5202 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5204 if(ret_val) 5704 if(ret_val)
5205 return ret_val; 5705 return ret_val;
5706 } else {
5707 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5708 if(ret_val)
5709 return ret_val;
5710 }
5711
5712 if(!active) {
5713 if(hw->mac_type == e1000_82541_rev_2 ||
5714 hw->mac_type == e1000_82547_rev_2) {
5715 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5716 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5717 if(ret_val)
5718 return ret_val;
5719 } else {
5720 phy_data &= ~IGP02E1000_PM_D3_LPLU;
5721 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5722 phy_data);
5723 if (ret_val)
5724 return ret_val;
5725 }
5206 5726
5207 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5727 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5208 * Dx states where the power conservation is most important. During 5728 * Dx states where the power conservation is most important. During
@@ -5236,11 +5756,105 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5236 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 5756 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5237 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 5757 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5238 5758
5239 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5759 if(hw->mac_type == e1000_82541_rev_2 ||
5240 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 5760 hw->mac_type == e1000_82547_rev_2) {
5761 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5762 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5763 if(ret_val)
5764 return ret_val;
5765 } else {
5766 phy_data |= IGP02E1000_PM_D3_LPLU;
5767 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5768 phy_data);
5769 if (ret_val)
5770 return ret_val;
5771 }
5772
5773 /* When LPLU is enabled we should disable SmartSpeed */
5774 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5775 if(ret_val)
5776 return ret_val;
5777
5778 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5779 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5241 if(ret_val) 5780 if(ret_val)
5242 return ret_val; 5781 return ret_val;
5243 5782
5783 }
5784 return E1000_SUCCESS;
5785}
5786
5787/*****************************************************************************
5788 *
5789 * This function sets the lplu d0 state according to the active flag. When
5790 * activating lplu this function also disables smart speed and vise versa.
5791 * lplu will not be activated unless the device autonegotiation advertisment
5792 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5793 * hw: Struct containing variables accessed by shared code
5794 * active - true to enable lplu false to disable lplu.
5795 *
5796 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5797 * E1000_SUCCESS at any other case.
5798 *
5799 ****************************************************************************/
5800
5801int32_t
5802e1000_set_d0_lplu_state(struct e1000_hw *hw,
5803 boolean_t active)
5804{
5805 int32_t ret_val;
5806 uint16_t phy_data;
5807 DEBUGFUNC("e1000_set_d0_lplu_state");
5808
5809 if(hw->mac_type <= e1000_82547_rev_2)
5810 return E1000_SUCCESS;
5811
5812 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5813 if(ret_val)
5814 return ret_val;
5815
5816 if (!active) {
5817 phy_data &= ~IGP02E1000_PM_D0_LPLU;
5818 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5819 if (ret_val)
5820 return ret_val;
5821
5822 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5823 * Dx states where the power conservation is most important. During
5824 * driver activity we should enable SmartSpeed, so performance is
5825 * maintained. */
5826 if (hw->smart_speed == e1000_smart_speed_on) {
5827 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5828 &phy_data);
5829 if(ret_val)
5830 return ret_val;
5831
5832 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5833 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5834 phy_data);
5835 if(ret_val)
5836 return ret_val;
5837 } else if (hw->smart_speed == e1000_smart_speed_off) {
5838 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5839 &phy_data);
5840 if (ret_val)
5841 return ret_val;
5842
5843 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5844 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5845 phy_data);
5846 if(ret_val)
5847 return ret_val;
5848 }
5849
5850
5851 } else {
5852
5853 phy_data |= IGP02E1000_PM_D0_LPLU;
5854 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5855 if (ret_val)
5856 return ret_val;
5857
5244 /* When LPLU is enabled we should disable SmartSpeed */ 5858 /* When LPLU is enabled we should disable SmartSpeed */
5245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 5859 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5246 if(ret_val) 5860 if(ret_val)
@@ -5318,6 +5932,338 @@ e1000_set_vco_speed(struct e1000_hw *hw)
5318 return E1000_SUCCESS; 5932 return E1000_SUCCESS;
5319} 5933}
5320 5934
5935
5936/*****************************************************************************
5937 * This function reads the cookie from ARC ram.
5938 *
5939 * returns: - E1000_SUCCESS .
5940 ****************************************************************************/
5941int32_t
5942e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
5943{
5944 uint8_t i;
5945 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
5946 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
5947
5948 length = (length >> 2);
5949 offset = (offset >> 2);
5950
5951 for (i = 0; i < length; i++) {
5952 *((uint32_t *) buffer + i) =
5953 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
5954 }
5955 return E1000_SUCCESS;
5956}
5957
5958
5959/*****************************************************************************
5960 * This function checks whether the HOST IF is enabled for command operaton
5961 * and also checks whether the previous command is completed.
5962 * It busy waits in case of previous command is not completed.
5963 *
5964 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
5965 * timeout
5966 * - E1000_SUCCESS for success.
5967 ****************************************************************************/
5968int32_t
5969e1000_mng_enable_host_if(struct e1000_hw * hw)
5970{
5971 uint32_t hicr;
5972 uint8_t i;
5973
5974 /* Check that the host interface is enabled. */
5975 hicr = E1000_READ_REG(hw, HICR);
5976 if ((hicr & E1000_HICR_EN) == 0) {
5977 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
5978 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5979 }
5980 /* check the previous command is completed */
5981 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
5982 hicr = E1000_READ_REG(hw, HICR);
5983 if (!(hicr & E1000_HICR_C))
5984 break;
5985 msec_delay_irq(1);
5986 }
5987
5988 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
5989 DEBUGOUT("Previous command timeout failed .\n");
5990 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5991 }
5992 return E1000_SUCCESS;
5993}
5994
5995/*****************************************************************************
5996 * This function writes the buffer content at the offset given on the host if.
5997 * It also does alignment considerations to do the writes in most efficient way.
5998 * Also fills up the sum of the buffer in *buffer parameter.
5999 *
6000 * returns - E1000_SUCCESS for success.
6001 ****************************************************************************/
6002int32_t
6003e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6004 uint16_t length, uint16_t offset, uint8_t *sum)
6005{
6006 uint8_t *tmp;
6007 uint8_t *bufptr = buffer;
6008 uint32_t data;
6009 uint16_t remaining, i, j, prev_bytes;
6010
6011 /* sum = only sum of the data and it is not checksum */
6012
6013 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6014 return -E1000_ERR_PARAM;
6015 }
6016
6017 tmp = (uint8_t *)&data;
6018 prev_bytes = offset & 0x3;
6019 offset &= 0xFFFC;
6020 offset >>= 2;
6021
6022 if (prev_bytes) {
6023 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6024 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6025 *(tmp + j) = *bufptr++;
6026 *sum += *(tmp + j);
6027 }
6028 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6029 length -= j - prev_bytes;
6030 offset++;
6031 }
6032
6033 remaining = length & 0x3;
6034 length -= remaining;
6035
6036 /* Calculate length in DWORDs */
6037 length >>= 2;
6038
6039 /* The device driver writes the relevant command block into the
6040 * ram area. */
6041 for (i = 0; i < length; i++) {
6042 for (j = 0; j < sizeof(uint32_t); j++) {
6043 *(tmp + j) = *bufptr++;
6044 *sum += *(tmp + j);
6045 }
6046
6047 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6048 }
6049 if (remaining) {
6050 for (j = 0; j < sizeof(uint32_t); j++) {
6051 if (j < remaining)
6052 *(tmp + j) = *bufptr++;
6053 else
6054 *(tmp + j) = 0;
6055
6056 *sum += *(tmp + j);
6057 }
6058 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6059 }
6060
6061 return E1000_SUCCESS;
6062}
6063
6064
6065/*****************************************************************************
6066 * This function writes the command header after does the checksum calculation.
6067 *
6068 * returns - E1000_SUCCESS for success.
6069 ****************************************************************************/
6070int32_t
6071e1000_mng_write_cmd_header(struct e1000_hw * hw,
6072 struct e1000_host_mng_command_header * hdr)
6073{
6074 uint16_t i;
6075 uint8_t sum;
6076 uint8_t *buffer;
6077
6078 /* Write the whole command header structure which includes sum of
6079 * the buffer */
6080
6081 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6082
6083 sum = hdr->checksum;
6084 hdr->checksum = 0;
6085
6086 buffer = (uint8_t *) hdr;
6087 i = length;
6088 while(i--)
6089 sum += buffer[i];
6090
6091 hdr->checksum = 0 - sum;
6092
6093 length >>= 2;
6094 /* The device driver writes the relevant command block into the ram area. */
6095 for (i = 0; i < length; i++)
6096 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6097
6098 return E1000_SUCCESS;
6099}
6100
6101
6102/*****************************************************************************
6103 * This function indicates to ARC that a new command is pending which completes
6104 * one write operation by the driver.
6105 *
6106 * returns - E1000_SUCCESS for success.
6107 ****************************************************************************/
6108int32_t
6109e1000_mng_write_commit(
6110 struct e1000_hw * hw)
6111{
6112 uint32_t hicr;
6113
6114 hicr = E1000_READ_REG(hw, HICR);
6115 /* Setting this bit tells the ARC that a new command is pending. */
6116 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6117
6118 return E1000_SUCCESS;
6119}
6120
6121
6122/*****************************************************************************
6123 * This function checks the mode of the firmware.
6124 *
6125 * returns - TRUE when the mode is IAMT or FALSE.
6126 ****************************************************************************/
6127boolean_t
6128e1000_check_mng_mode(
6129 struct e1000_hw *hw)
6130{
6131 uint32_t fwsm;
6132
6133 fwsm = E1000_READ_REG(hw, FWSM);
6134
6135 if((fwsm & E1000_FWSM_MODE_MASK) ==
6136 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6137 return TRUE;
6138
6139 return FALSE;
6140}
6141
6142
6143/*****************************************************************************
6144 * This function writes the dhcp info .
6145 ****************************************************************************/
6146int32_t
6147e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
6148 uint16_t length)
6149{
6150 int32_t ret_val;
6151 struct e1000_host_mng_command_header hdr;
6152
6153 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6154 hdr.command_length = length;
6155 hdr.reserved1 = 0;
6156 hdr.reserved2 = 0;
6157 hdr.checksum = 0;
6158
6159 ret_val = e1000_mng_enable_host_if(hw);
6160 if (ret_val == E1000_SUCCESS) {
6161 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6162 &(hdr.checksum));
6163 if (ret_val == E1000_SUCCESS) {
6164 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
6165 if (ret_val == E1000_SUCCESS)
6166 ret_val = e1000_mng_write_commit(hw);
6167 }
6168 }
6169 return ret_val;
6170}
6171
6172
6173/*****************************************************************************
6174 * This function calculates the checksum.
6175 *
6176 * returns - checksum of buffer contents.
6177 ****************************************************************************/
6178uint8_t
6179e1000_calculate_mng_checksum(char *buffer, uint32_t length)
6180{
6181 uint8_t sum = 0;
6182 uint32_t i;
6183
6184 if (!buffer)
6185 return 0;
6186
6187 for (i=0; i < length; i++)
6188 sum += buffer[i];
6189
6190 return (uint8_t) (0 - sum);
6191}
6192
6193/*****************************************************************************
6194 * This function checks whether tx pkt filtering needs to be enabled or not.
6195 *
6196 * returns - TRUE for packet filtering or FALSE.
6197 ****************************************************************************/
6198boolean_t
6199e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
6200{
6201 /* called in init as well as watchdog timer functions */
6202
6203 int32_t ret_val, checksum;
6204 boolean_t tx_filter = FALSE;
6205 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
6206 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
6207
6208 if (e1000_check_mng_mode(hw)) {
6209 ret_val = e1000_mng_enable_host_if(hw);
6210 if (ret_val == E1000_SUCCESS) {
6211 ret_val = e1000_host_if_read_cookie(hw, buffer);
6212 if (ret_val == E1000_SUCCESS) {
6213 checksum = hdr->checksum;
6214 hdr->checksum = 0;
6215 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
6216 checksum == e1000_calculate_mng_checksum((char *)buffer,
6217 E1000_MNG_DHCP_COOKIE_LENGTH)) {
6218 if (hdr->status &
6219 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
6220 tx_filter = TRUE;
6221 } else
6222 tx_filter = TRUE;
6223 } else
6224 tx_filter = TRUE;
6225 }
6226 }
6227
6228 hw->tx_pkt_filtering = tx_filter;
6229 return tx_filter;
6230}
6231
6232/******************************************************************************
6233 * Verifies the hardware needs to allow ARPs to be processed by the host
6234 *
6235 * hw - Struct containing variables accessed by shared code
6236 *
6237 * returns: - TRUE/FALSE
6238 *
6239 *****************************************************************************/
6240uint32_t
6241e1000_enable_mng_pass_thru(struct e1000_hw *hw)
6242{
6243 uint32_t manc;
6244 uint32_t fwsm, factps;
6245
6246 if (hw->asf_firmware_present) {
6247 manc = E1000_READ_REG(hw, MANC);
6248
6249 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
6250 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
6251 return FALSE;
6252 if (e1000_arc_subsystem_valid(hw) == TRUE) {
6253 fwsm = E1000_READ_REG(hw, FWSM);
6254 factps = E1000_READ_REG(hw, FACTPS);
6255
6256 if (((fwsm & E1000_FWSM_MODE_MASK) ==
6257 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
6258 (factps & E1000_FACTPS_MNGCG))
6259 return TRUE;
6260 } else
6261 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
6262 return TRUE;
6263 }
6264 return FALSE;
6265}
6266
5321static int32_t 6267static int32_t
5322e1000_polarity_reversal_workaround(struct e1000_hw *hw) 6268e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5323{ 6269{
@@ -5403,3 +6349,265 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5403 return E1000_SUCCESS; 6349 return E1000_SUCCESS;
5404} 6350}
5405 6351
6352/***************************************************************************
6353 *
6354 * Disables PCI-Express master access.
6355 *
6356 * hw: Struct containing variables accessed by shared code
6357 *
6358 * returns: - none.
6359 *
6360 ***************************************************************************/
6361void
6362e1000_set_pci_express_master_disable(struct e1000_hw *hw)
6363{
6364 uint32_t ctrl;
6365
6366 DEBUGFUNC("e1000_set_pci_express_master_disable");
6367
6368 if (hw->bus_type != e1000_bus_type_pci_express)
6369 return;
6370
6371 ctrl = E1000_READ_REG(hw, CTRL);
6372 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
6373 E1000_WRITE_REG(hw, CTRL, ctrl);
6374}
6375
6376/***************************************************************************
6377 *
6378 * Enables PCI-Express master access.
6379 *
6380 * hw: Struct containing variables accessed by shared code
6381 *
6382 * returns: - none.
6383 *
6384 ***************************************************************************/
6385void
6386e1000_enable_pciex_master(struct e1000_hw *hw)
6387{
6388 uint32_t ctrl;
6389
6390 DEBUGFUNC("e1000_enable_pciex_master");
6391
6392 if (hw->bus_type != e1000_bus_type_pci_express)
6393 return;
6394
6395 ctrl = E1000_READ_REG(hw, CTRL);
6396 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
6397 E1000_WRITE_REG(hw, CTRL, ctrl);
6398}
6399
6400/*******************************************************************************
6401 *
6402 * Disables PCI-Express master access and verifies there are no pending requests
6403 *
6404 * hw: Struct containing variables accessed by shared code
6405 *
6406 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6407 * caused the master requests to be disabled.
6408 * E1000_SUCCESS master requests disabled.
6409 *
6410 ******************************************************************************/
6411int32_t
6412e1000_disable_pciex_master(struct e1000_hw *hw)
6413{
6414 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
6415
6416 DEBUGFUNC("e1000_disable_pciex_master");
6417
6418 if (hw->bus_type != e1000_bus_type_pci_express)
6419 return E1000_SUCCESS;
6420
6421 e1000_set_pci_express_master_disable(hw);
6422
6423 while(timeout) {
6424 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
6425 break;
6426 else
6427 udelay(100);
6428 timeout--;
6429 }
6430
6431 if(!timeout) {
6432 DEBUGOUT("Master requests are pending.\n");
6433 return -E1000_ERR_MASTER_REQUESTS_PENDING;
6434 }
6435
6436 return E1000_SUCCESS;
6437}
6438
6439/*******************************************************************************
6440 *
6441 * Check for EEPROM Auto Read bit done.
6442 *
6443 * hw: Struct containing variables accessed by shared code
6444 *
6445 * returns: - E1000_ERR_RESET if fail to reset MAC
6446 * E1000_SUCCESS at any other case.
6447 *
6448 ******************************************************************************/
6449int32_t
6450e1000_get_auto_rd_done(struct e1000_hw *hw)
6451{
6452 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
6453
6454 DEBUGFUNC("e1000_get_auto_rd_done");
6455
6456 switch (hw->mac_type) {
6457 default:
6458 msec_delay(5);
6459 break;
6460 case e1000_82573:
6461 while(timeout) {
6462 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
6463 else msec_delay(1);
6464 timeout--;
6465 }
6466
6467 if(!timeout) {
6468 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6469 return -E1000_ERR_RESET;
6470 }
6471 break;
6472 }
6473
6474 return E1000_SUCCESS;
6475}
6476
6477/***************************************************************************
6478 * Checks if the PHY configuration is done
6479 *
6480 * hw: Struct containing variables accessed by shared code
6481 *
6482 * returns: - E1000_ERR_RESET if fail to reset MAC
6483 * E1000_SUCCESS at any other case.
6484 *
6485 ***************************************************************************/
6486int32_t
6487e1000_get_phy_cfg_done(struct e1000_hw *hw)
6488{
6489 DEBUGFUNC("e1000_get_phy_cfg_done");
6490
6491 /* Simply wait for 10ms */
6492 msec_delay(10);
6493
6494 return E1000_SUCCESS;
6495}
6496
6497/***************************************************************************
6498 *
6499 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6500 * adapter or Eeprom access.
6501 *
6502 * hw: Struct containing variables accessed by shared code
6503 *
6504 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6505 * E1000_SUCCESS at any other case.
6506 *
6507 ***************************************************************************/
6508int32_t
6509e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
6510{
6511 int32_t timeout;
6512 uint32_t swsm;
6513
6514 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6515
6516 if(!hw->eeprom_semaphore_present)
6517 return E1000_SUCCESS;
6518
6519
6520 /* Get the FW semaphore. */
6521 timeout = hw->eeprom.word_size + 1;
6522 while(timeout) {
6523 swsm = E1000_READ_REG(hw, SWSM);
6524 swsm |= E1000_SWSM_SWESMBI;
6525 E1000_WRITE_REG(hw, SWSM, swsm);
6526 /* if we managed to set the bit we got the semaphore. */
6527 swsm = E1000_READ_REG(hw, SWSM);
6528 if(swsm & E1000_SWSM_SWESMBI)
6529 break;
6530
6531 udelay(50);
6532 timeout--;
6533 }
6534
6535 if(!timeout) {
6536 /* Release semaphores */
6537 e1000_put_hw_eeprom_semaphore(hw);
6538 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6539 return -E1000_ERR_EEPROM;
6540 }
6541
6542 return E1000_SUCCESS;
6543}
6544
6545/***************************************************************************
6546 * This function clears HW semaphore bits.
6547 *
6548 * hw: Struct containing variables accessed by shared code
6549 *
6550 * returns: - None.
6551 *
6552 ***************************************************************************/
6553void
6554e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
6555{
6556 uint32_t swsm;
6557
6558 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6559
6560 if(!hw->eeprom_semaphore_present)
6561 return;
6562
6563 swsm = E1000_READ_REG(hw, SWSM);
6564 /* Release both semaphores. */
6565 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
6566 E1000_WRITE_REG(hw, SWSM, swsm);
6567}
6568
6569/******************************************************************************
6570 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6571 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6572 * the caller to figure out how to deal with it.
6573 *
6574 * hw - Struct containing variables accessed by shared code
6575 *
6576 * returns: - E1000_BLK_PHY_RESET
6577 * E1000_SUCCESS
6578 *
6579 *****************************************************************************/
6580int32_t
6581e1000_check_phy_reset_block(struct e1000_hw *hw)
6582{
6583 uint32_t manc = 0;
6584 if(hw->mac_type > e1000_82547_rev_2)
6585 manc = E1000_READ_REG(hw, MANC);
6586 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
6587 E1000_BLK_PHY_RESET : E1000_SUCCESS;
6588}
6589
6590uint8_t
6591e1000_arc_subsystem_valid(struct e1000_hw *hw)
6592{
6593 uint32_t fwsm;
6594
6595 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6596 * may not be provided a DMA clock when no manageability features are
6597 * enabled. We do not want to perform any reads/writes to these registers
6598 * if this is the case. We read FWSM to determine the manageability mode.
6599 */
6600 switch (hw->mac_type) {
6601 case e1000_82573:
6602 fwsm = E1000_READ_REG(hw, FWSM);
6603 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
6604 return TRUE;
6605 break;
6606 default:
6607 break;
6608 }
6609 return FALSE;
6610}
6611
6612
6613
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 06:21:45 -0500