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path: root/drivers/net/e1000/e1000_hw.c
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c1819
1 files changed, 1701 insertions, 118 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 3959039b16ec..b3b919116e0f 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -101,9 +101,37 @@ static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 101
102#define E1000_WRITE_REG_IO(a, reg, val) \ 102#define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val) 103 e1000_write_reg_io((a), E1000_##reg, val)
104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw); 104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
105 uint16_t duplex);
105static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 106static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
106 107
108static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw,
109 uint32_t segment);
110static int32_t e1000_get_software_flag(struct e1000_hw *hw);
111static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
112static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
113static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
114static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
115 uint16_t words, uint16_t *data);
116static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
117 uint8_t* data);
118static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
119 uint16_t *data);
120static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
121 uint16_t *data);
122static void e1000_release_software_flag(struct e1000_hw *hw);
123static void e1000_release_software_semaphore(struct e1000_hw *hw);
124static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw,
125 uint32_t no_snoop);
126static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw,
127 uint32_t index, uint8_t byte);
128static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
129 uint16_t words, uint16_t *data);
130static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
131 uint8_t data);
132static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
133 uint16_t data);
134
107/* IGP cable length table */ 135/* IGP cable length table */
108static const 136static const
109uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 137uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
@@ -156,6 +184,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
156 hw->phy_type = e1000_phy_igp; 184 hw->phy_type = e1000_phy_igp;
157 break; 185 break;
158 } 186 }
187 case IGP03E1000_E_PHY_ID:
188 hw->phy_type = e1000_phy_igp_3;
189 break;
190 case IFE_E_PHY_ID:
191 case IFE_PLUS_E_PHY_ID:
192 case IFE_C_E_PHY_ID:
193 hw->phy_type = e1000_phy_ife;
194 break;
159 case GG82563_E_PHY_ID: 195 case GG82563_E_PHY_ID:
160 if (hw->mac_type == e1000_80003es2lan) { 196 if (hw->mac_type == e1000_80003es2lan) {
161 hw->phy_type = e1000_phy_gg82563; 197 hw->phy_type = e1000_phy_gg82563;
@@ -332,6 +368,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
332 break; 368 break;
333 case E1000_DEV_ID_82541EI: 369 case E1000_DEV_ID_82541EI:
334 case E1000_DEV_ID_82541EI_MOBILE: 370 case E1000_DEV_ID_82541EI_MOBILE:
371 case E1000_DEV_ID_82541ER_LOM:
335 hw->mac_type = e1000_82541; 372 hw->mac_type = e1000_82541;
336 break; 373 break;
337 case E1000_DEV_ID_82541ER: 374 case E1000_DEV_ID_82541ER:
@@ -341,6 +378,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
341 hw->mac_type = e1000_82541_rev_2; 378 hw->mac_type = e1000_82541_rev_2;
342 break; 379 break;
343 case E1000_DEV_ID_82547EI: 380 case E1000_DEV_ID_82547EI:
381 case E1000_DEV_ID_82547EI_MOBILE:
344 hw->mac_type = e1000_82547; 382 hw->mac_type = e1000_82547;
345 break; 383 break;
346 case E1000_DEV_ID_82547GI: 384 case E1000_DEV_ID_82547GI:
@@ -354,6 +392,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
354 case E1000_DEV_ID_82572EI_COPPER: 392 case E1000_DEV_ID_82572EI_COPPER:
355 case E1000_DEV_ID_82572EI_FIBER: 393 case E1000_DEV_ID_82572EI_FIBER:
356 case E1000_DEV_ID_82572EI_SERDES: 394 case E1000_DEV_ID_82572EI_SERDES:
395 case E1000_DEV_ID_82572EI:
357 hw->mac_type = e1000_82572; 396 hw->mac_type = e1000_82572;
358 break; 397 break;
359 case E1000_DEV_ID_82573E: 398 case E1000_DEV_ID_82573E:
@@ -361,16 +400,29 @@ e1000_set_mac_type(struct e1000_hw *hw)
361 case E1000_DEV_ID_82573L: 400 case E1000_DEV_ID_82573L:
362 hw->mac_type = e1000_82573; 401 hw->mac_type = e1000_82573;
363 break; 402 break;
403 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
404 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
364 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 405 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
365 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 406 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
366 hw->mac_type = e1000_80003es2lan; 407 hw->mac_type = e1000_80003es2lan;
367 break; 408 break;
409 case E1000_DEV_ID_ICH8_IGP_M_AMT:
410 case E1000_DEV_ID_ICH8_IGP_AMT:
411 case E1000_DEV_ID_ICH8_IGP_C:
412 case E1000_DEV_ID_ICH8_IFE:
413 case E1000_DEV_ID_ICH8_IGP_M:
414 hw->mac_type = e1000_ich8lan;
415 break;
368 default: 416 default:
369 /* Should never have loaded on this device */ 417 /* Should never have loaded on this device */
370 return -E1000_ERR_MAC_TYPE; 418 return -E1000_ERR_MAC_TYPE;
371 } 419 }
372 420
373 switch(hw->mac_type) { 421 switch(hw->mac_type) {
422 case e1000_ich8lan:
423 hw->swfwhw_semaphore_present = TRUE;
424 hw->asf_firmware_present = TRUE;
425 break;
374 case e1000_80003es2lan: 426 case e1000_80003es2lan:
375 hw->swfw_sync_present = TRUE; 427 hw->swfw_sync_present = TRUE;
376 /* fall through */ 428 /* fall through */
@@ -423,6 +475,7 @@ e1000_set_media_type(struct e1000_hw *hw)
423 case e1000_82542_rev2_1: 475 case e1000_82542_rev2_1:
424 hw->media_type = e1000_media_type_fiber; 476 hw->media_type = e1000_media_type_fiber;
425 break; 477 break;
478 case e1000_ich8lan:
426 case e1000_82573: 479 case e1000_82573:
427 /* The STATUS_TBIMODE bit is reserved or reused for the this 480 /* The STATUS_TBIMODE bit is reserved or reused for the this
428 * device. 481 * device.
@@ -527,6 +580,14 @@ e1000_reset_hw(struct e1000_hw *hw)
527 } while(timeout); 580 } while(timeout);
528 } 581 }
529 582
583 /* Workaround for ICH8 bit corruption issue in FIFO memory */
584 if (hw->mac_type == e1000_ich8lan) {
585 /* Set Tx and Rx buffer allocation to 8k apiece. */
586 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
587 /* Set Packet Buffer Size to 16k. */
588 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
589 }
590
530 /* Issue a global reset to the MAC. This will reset the chip's 591 /* Issue a global reset to the MAC. This will reset the chip's
531 * transmit, receive, DMA, and link units. It will not effect 592 * transmit, receive, DMA, and link units. It will not effect
532 * the current PCI configuration. The global reset bit is self- 593 * the current PCI configuration. The global reset bit is self-
@@ -550,6 +611,20 @@ e1000_reset_hw(struct e1000_hw *hw)
550 /* Reset is performed on a shadow of the control register */ 611 /* Reset is performed on a shadow of the control register */
551 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 612 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
552 break; 613 break;
614 case e1000_ich8lan:
615 if (!hw->phy_reset_disable &&
616 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
617 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
618 * at the same time to make sure the interface between
619 * MAC and the external PHY is reset.
620 */
621 ctrl |= E1000_CTRL_PHY_RST;
622 }
623
624 e1000_get_software_flag(hw);
625 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
626 msec_delay(5);
627 break;
553 default: 628 default:
554 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 629 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
555 break; 630 break;
@@ -591,6 +666,7 @@ e1000_reset_hw(struct e1000_hw *hw)
591 /* fall through */ 666 /* fall through */
592 case e1000_82571: 667 case e1000_82571:
593 case e1000_82572: 668 case e1000_82572:
669 case e1000_ich8lan:
594 case e1000_80003es2lan: 670 case e1000_80003es2lan:
595 ret_val = e1000_get_auto_rd_done(hw); 671 ret_val = e1000_get_auto_rd_done(hw);
596 if(ret_val) 672 if(ret_val)
@@ -633,6 +709,12 @@ e1000_reset_hw(struct e1000_hw *hw)
633 e1000_pci_set_mwi(hw); 709 e1000_pci_set_mwi(hw);
634 } 710 }
635 711
712 if (hw->mac_type == e1000_ich8lan) {
713 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
714 kab |= E1000_KABGTXD_BGSQLBIAS;
715 E1000_WRITE_REG(hw, KABGTXD, kab);
716 }
717
636 return E1000_SUCCESS; 718 return E1000_SUCCESS;
637} 719}
638 720
@@ -675,9 +757,12 @@ e1000_init_hw(struct e1000_hw *hw)
675 757
676 /* Disabling VLAN filtering. */ 758 /* Disabling VLAN filtering. */
677 DEBUGOUT("Initializing the IEEE VLAN\n"); 759 DEBUGOUT("Initializing the IEEE VLAN\n");
678 if (hw->mac_type < e1000_82545_rev_3) 760 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
679 E1000_WRITE_REG(hw, VET, 0); 761 if (hw->mac_type != e1000_ich8lan) {
680 e1000_clear_vfta(hw); 762 if (hw->mac_type < e1000_82545_rev_3)
763 E1000_WRITE_REG(hw, VET, 0);
764 e1000_clear_vfta(hw);
765 }
681 766
682 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 767 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
683 if(hw->mac_type == e1000_82542_rev2_0) { 768 if(hw->mac_type == e1000_82542_rev2_0) {
@@ -705,8 +790,14 @@ e1000_init_hw(struct e1000_hw *hw)
705 /* Zero out the Multicast HASH table */ 790 /* Zero out the Multicast HASH table */
706 DEBUGOUT("Zeroing the MTA\n"); 791 DEBUGOUT("Zeroing the MTA\n");
707 mta_size = E1000_MC_TBL_SIZE; 792 mta_size = E1000_MC_TBL_SIZE;
708 for(i = 0; i < mta_size; i++) 793 if (hw->mac_type == e1000_ich8lan)
794 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
795 for(i = 0; i < mta_size; i++) {
709 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 796 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
797 /* use write flush to prevent Memory Write Block (MWB) from
798 * occuring when accessing our register space */
799 E1000_WRITE_FLUSH(hw);
800 }
710 801
711 /* Set the PCI priority bit correctly in the CTRL register. This 802 /* Set the PCI priority bit correctly in the CTRL register. This
712 * determines if the adapter gives priority to receives, or if it 803 * determines if the adapter gives priority to receives, or if it
@@ -744,6 +835,10 @@ e1000_init_hw(struct e1000_hw *hw)
744 break; 835 break;
745 } 836 }
746 837
838 /* More time needed for PHY to initialize */
839 if (hw->mac_type == e1000_ich8lan)
840 msec_delay(15);
841
747 /* Call a subroutine to configure the link and setup flow control. */ 842 /* Call a subroutine to configure the link and setup flow control. */
748 ret_val = e1000_setup_link(hw); 843 ret_val = e1000_setup_link(hw);
749 844
@@ -757,6 +852,7 @@ e1000_init_hw(struct e1000_hw *hw)
757 case e1000_82571: 852 case e1000_82571:
758 case e1000_82572: 853 case e1000_82572:
759 case e1000_82573: 854 case e1000_82573:
855 case e1000_ich8lan:
760 case e1000_80003es2lan: 856 case e1000_80003es2lan:
761 ctrl |= E1000_TXDCTL_COUNT_DESC; 857 ctrl |= E1000_TXDCTL_COUNT_DESC;
762 break; 858 break;
@@ -795,6 +891,7 @@ e1000_init_hw(struct e1000_hw *hw)
795 /* Fall through */ 891 /* Fall through */
796 case e1000_82571: 892 case e1000_82571:
797 case e1000_82572: 893 case e1000_82572:
894 case e1000_ich8lan:
798 ctrl = E1000_READ_REG(hw, TXDCTL1); 895 ctrl = E1000_READ_REG(hw, TXDCTL1);
799 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 896 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
800 if(hw->mac_type >= e1000_82571) 897 if(hw->mac_type >= e1000_82571)
@@ -818,6 +915,11 @@ e1000_init_hw(struct e1000_hw *hw)
818 */ 915 */
819 e1000_clear_hw_cntrs(hw); 916 e1000_clear_hw_cntrs(hw);
820 917
918 /* ICH8 No-snoop bits are opposite polarity.
919 * Set to snoop by default after reset. */
920 if (hw->mac_type == e1000_ich8lan)
921 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
922
821 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 923 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
822 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 924 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
823 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 925 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
@@ -905,6 +1007,7 @@ e1000_setup_link(struct e1000_hw *hw)
905 */ 1007 */
906 if (hw->fc == e1000_fc_default) { 1008 if (hw->fc == e1000_fc_default) {
907 switch (hw->mac_type) { 1009 switch (hw->mac_type) {
1010 case e1000_ich8lan:
908 case e1000_82573: 1011 case e1000_82573:
909 hw->fc = e1000_fc_full; 1012 hw->fc = e1000_fc_full;
910 break; 1013 break;
@@ -971,9 +1074,12 @@ e1000_setup_link(struct e1000_hw *hw)
971 */ 1074 */
972 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1075 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
973 1076
974 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1077 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
975 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1078 if (hw->mac_type != e1000_ich8lan) {
976 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1079 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1080 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1081 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1082 }
977 1083
978 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1084 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
979 1085
@@ -1237,12 +1343,13 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1237 1343
1238 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1344 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1239 msec_delay(15); 1345 msec_delay(15);
1240 1346 if (hw->mac_type != e1000_ich8lan) {
1241 /* Configure activity LED after PHY reset */ 1347 /* Configure activity LED after PHY reset */
1242 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1348 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1243 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1349 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1244 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1350 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1245 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1351 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1352 }
1246 1353
1247 /* disable lplu d3 during driver init */ 1354 /* disable lplu d3 during driver init */
1248 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1355 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
@@ -1478,8 +1585,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1478 if (ret_val) 1585 if (ret_val)
1479 return ret_val; 1586 return ret_val;
1480 1587
1481 /* Enable Pass False Carrier on the PHY */ 1588 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1482 phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1483 1589
1484 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1590 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1485 phy_data); 1591 phy_data);
@@ -1561,28 +1667,40 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1561 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1667 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1562 if(hw->disable_polarity_correction == 1) 1668 if(hw->disable_polarity_correction == 1)
1563 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1669 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1564 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1670 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1565 if(ret_val) 1671 if (ret_val)
1566 return ret_val;
1567
1568 /* Force TX_CLK in the Extended PHY Specific Control Register
1569 * to 25MHz clock.
1570 */
1571 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1572 if(ret_val)
1573 return ret_val; 1672 return ret_val;
1574 1673
1575 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1576
1577 if (hw->phy_revision < M88E1011_I_REV_4) { 1674 if (hw->phy_revision < M88E1011_I_REV_4) {
1578 /* Configure Master and Slave downshift values */ 1675 /* Force TX_CLK in the Extended PHY Specific Control Register
1579 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1676 * to 25MHz clock.
1677 */
1678 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1679 if (ret_val)
1680 return ret_val;
1681
1682 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1683
1684 if ((hw->phy_revision == E1000_REVISION_2) &&
1685 (hw->phy_id == M88E1111_I_PHY_ID)) {
1686 /* Vidalia Phy, set the downshift counter to 5x */
1687 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1688 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1689 ret_val = e1000_write_phy_reg(hw,
1690 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1691 if (ret_val)
1692 return ret_val;
1693 } else {
1694 /* Configure Master and Slave downshift values */
1695 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1580 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1696 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1581 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1697 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1582 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1698 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1583 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1699 ret_val = e1000_write_phy_reg(hw,
1584 if(ret_val) 1700 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1585 return ret_val; 1701 if (ret_val)
1702 return ret_val;
1703 }
1586 } 1704 }
1587 1705
1588 /* SW Reset the PHY so all changes take effect */ 1706 /* SW Reset the PHY so all changes take effect */
@@ -1620,6 +1738,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1620 if(hw->autoneg_advertised == 0) 1738 if(hw->autoneg_advertised == 0)
1621 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1739 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1622 1740
1741 /* IFE phy only supports 10/100 */
1742 if (hw->phy_type == e1000_phy_ife)
1743 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1744
1623 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1745 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1624 ret_val = e1000_phy_setup_autoneg(hw); 1746 ret_val = e1000_phy_setup_autoneg(hw);
1625 if(ret_val) { 1747 if(ret_val) {
@@ -1717,6 +1839,26 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1717 1839
1718 DEBUGFUNC("e1000_setup_copper_link"); 1840 DEBUGFUNC("e1000_setup_copper_link");
1719 1841
1842 switch (hw->mac_type) {
1843 case e1000_80003es2lan:
1844 case e1000_ich8lan:
1845 /* Set the mac to wait the maximum time between each
1846 * iteration and increase the max iterations when
1847 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1848 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1849 if (ret_val)
1850 return ret_val;
1851 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1852 if (ret_val)
1853 return ret_val;
1854 reg_data |= 0x3F;
1855 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1856 if (ret_val)
1857 return ret_val;
1858 default:
1859 break;
1860 }
1861
1720 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1862 /* Check if it is a valid PHY and set PHY mode if necessary. */
1721 ret_val = e1000_copper_link_preconfig(hw); 1863 ret_val = e1000_copper_link_preconfig(hw);
1722 if(ret_val) 1864 if(ret_val)
@@ -1724,10 +1866,8 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1724 1866
1725 switch (hw->mac_type) { 1867 switch (hw->mac_type) {
1726 case e1000_80003es2lan: 1868 case e1000_80003es2lan:
1727 ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1869 /* Kumeran registers are written-only */
1728 &reg_data); 1870 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1729 if (ret_val)
1730 return ret_val;
1731 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 1871 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1732 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1872 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1733 reg_data); 1873 reg_data);
@@ -1739,6 +1879,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1739 } 1879 }
1740 1880
1741 if (hw->phy_type == e1000_phy_igp || 1881 if (hw->phy_type == e1000_phy_igp ||
1882 hw->phy_type == e1000_phy_igp_3 ||
1742 hw->phy_type == e1000_phy_igp_2) { 1883 hw->phy_type == e1000_phy_igp_2) {
1743 ret_val = e1000_copper_link_igp_setup(hw); 1884 ret_val = e1000_copper_link_igp_setup(hw);
1744 if(ret_val) 1885 if(ret_val)
@@ -1803,7 +1944,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1803* hw - Struct containing variables accessed by shared code 1944* hw - Struct containing variables accessed by shared code
1804******************************************************************************/ 1945******************************************************************************/
1805static int32_t 1946static int32_t
1806e1000_configure_kmrn_for_10_100(struct e1000_hw *hw) 1947e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1807{ 1948{
1808 int32_t ret_val = E1000_SUCCESS; 1949 int32_t ret_val = E1000_SUCCESS;
1809 uint32_t tipg; 1950 uint32_t tipg;
@@ -1823,6 +1964,18 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw)
1823 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 1964 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1824 E1000_WRITE_REG(hw, TIPG, tipg); 1965 E1000_WRITE_REG(hw, TIPG, tipg);
1825 1966
1967 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1968
1969 if (ret_val)
1970 return ret_val;
1971
1972 if (duplex == HALF_DUPLEX)
1973 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1974 else
1975 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1976
1977 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1978
1826 return ret_val; 1979 return ret_val;
1827} 1980}
1828 1981
@@ -1847,6 +2000,14 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1847 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2000 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1848 E1000_WRITE_REG(hw, TIPG, tipg); 2001 E1000_WRITE_REG(hw, TIPG, tipg);
1849 2002
2003 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2004
2005 if (ret_val)
2006 return ret_val;
2007
2008 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2009 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2010
1850 return ret_val; 2011 return ret_val;
1851} 2012}
1852 2013
@@ -1869,10 +2030,13 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1869 if(ret_val) 2030 if(ret_val)
1870 return ret_val; 2031 return ret_val;
1871 2032
1872 /* Read the MII 1000Base-T Control Register (Address 9). */ 2033 if (hw->phy_type != e1000_phy_ife) {
1873 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 2034 /* Read the MII 1000Base-T Control Register (Address 9). */
1874 if(ret_val) 2035 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1875 return ret_val; 2036 if (ret_val)
2037 return ret_val;
2038 } else
2039 mii_1000t_ctrl_reg=0;
1876 2040
1877 /* Need to parse both autoneg_advertised and fc and set up 2041 /* Need to parse both autoneg_advertised and fc and set up
1878 * the appropriate PHY registers. First we will parse for 2042 * the appropriate PHY registers. First we will parse for
@@ -1923,6 +2087,9 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1923 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2087 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1924 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2088 DEBUGOUT("Advertise 1000mb Full duplex\n");
1925 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2089 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2090 if (hw->phy_type == e1000_phy_ife) {
2091 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2092 }
1926 } 2093 }
1927 2094
1928 /* Check for a software override of the flow control settings, and 2095 /* Check for a software override of the flow control settings, and
@@ -1984,9 +2151,11 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1984 2151
1985 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2152 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1986 2153
1987 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 2154 if (hw->phy_type != e1000_phy_ife) {
1988 if(ret_val) 2155 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1989 return ret_val; 2156 if (ret_val)
2157 return ret_val;
2158 }
1990 2159
1991 return E1000_SUCCESS; 2160 return E1000_SUCCESS;
1992} 2161}
@@ -2089,6 +2258,18 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2089 2258
2090 /* Need to reset the PHY or these changes will be ignored */ 2259 /* Need to reset the PHY or these changes will be ignored */
2091 mii_ctrl_reg |= MII_CR_RESET; 2260 mii_ctrl_reg |= MII_CR_RESET;
2261 /* Disable MDI-X support for 10/100 */
2262 } else if (hw->phy_type == e1000_phy_ife) {
2263 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2264 if (ret_val)
2265 return ret_val;
2266
2267 phy_data &= ~IFE_PMC_AUTO_MDIX;
2268 phy_data &= ~IFE_PMC_FORCE_MDIX;
2269
2270 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2271 if (ret_val)
2272 return ret_val;
2092 } else { 2273 } else {
2093 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2274 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2094 * forced whenever speed or duplex are forced. 2275 * forced whenever speed or duplex are forced.
@@ -2721,8 +2902,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2721 */ 2902 */
2722 if(hw->tbi_compatibility_en) { 2903 if(hw->tbi_compatibility_en) {
2723 uint16_t speed, duplex; 2904 uint16_t speed, duplex;
2724 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2905 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2725 if(speed != SPEED_1000) { 2906 if (ret_val) {
2907 DEBUGOUT("Error getting link speed and duplex\n");
2908 return ret_val;
2909 }
2910 if (speed != SPEED_1000) {
2726 /* If link speed is not set to gigabit speed, we do not need 2911 /* If link speed is not set to gigabit speed, we do not need
2727 * to enable TBI compatibility. 2912 * to enable TBI compatibility.
2728 */ 2913 */
@@ -2889,7 +3074,13 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2889 if (*speed == SPEED_1000) 3074 if (*speed == SPEED_1000)
2890 ret_val = e1000_configure_kmrn_for_1000(hw); 3075 ret_val = e1000_configure_kmrn_for_1000(hw);
2891 else 3076 else
2892 ret_val = e1000_configure_kmrn_for_10_100(hw); 3077 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3078 if (ret_val)
3079 return ret_val;
3080 }
3081
3082 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3083 ret_val = e1000_kumeran_lock_loss_workaround(hw);
2893 if (ret_val) 3084 if (ret_val)
2894 return ret_val; 3085 return ret_val;
2895 } 3086 }
@@ -3069,7 +3260,7 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3069 return data; 3260 return data;
3070} 3261}
3071 3262
3072int32_t 3263static int32_t
3073e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 3264e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3074{ 3265{
3075 uint32_t swfw_sync = 0; 3266 uint32_t swfw_sync = 0;
@@ -3079,6 +3270,9 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3079 3270
3080 DEBUGFUNC("e1000_swfw_sync_acquire"); 3271 DEBUGFUNC("e1000_swfw_sync_acquire");
3081 3272
3273 if (hw->swfwhw_semaphore_present)
3274 return e1000_get_software_flag(hw);
3275
3082 if (!hw->swfw_sync_present) 3276 if (!hw->swfw_sync_present)
3083 return e1000_get_hw_eeprom_semaphore(hw); 3277 return e1000_get_hw_eeprom_semaphore(hw);
3084 3278
@@ -3110,7 +3304,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3110 return E1000_SUCCESS; 3304 return E1000_SUCCESS;
3111} 3305}
3112 3306
3113void 3307static void
3114e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 3308e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3115{ 3309{
3116 uint32_t swfw_sync; 3310 uint32_t swfw_sync;
@@ -3118,6 +3312,11 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3118 3312
3119 DEBUGFUNC("e1000_swfw_sync_release"); 3313 DEBUGFUNC("e1000_swfw_sync_release");
3120 3314
3315 if (hw->swfwhw_semaphore_present) {
3316 e1000_release_software_flag(hw);
3317 return;
3318 }
3319
3121 if (!hw->swfw_sync_present) { 3320 if (!hw->swfw_sync_present) {
3122 e1000_put_hw_eeprom_semaphore(hw); 3321 e1000_put_hw_eeprom_semaphore(hw);
3123 return; 3322 return;
@@ -3160,7 +3359,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3160 if (e1000_swfw_sync_acquire(hw, swfw)) 3359 if (e1000_swfw_sync_acquire(hw, swfw))
3161 return -E1000_ERR_SWFW_SYNC; 3360 return -E1000_ERR_SWFW_SYNC;
3162 3361
3163 if((hw->phy_type == e1000_phy_igp || 3362 if ((hw->phy_type == e1000_phy_igp ||
3363 hw->phy_type == e1000_phy_igp_3 ||
3164 hw->phy_type == e1000_phy_igp_2) && 3364 hw->phy_type == e1000_phy_igp_2) &&
3165 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3365 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3166 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3366 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3299,7 +3499,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3299 if (e1000_swfw_sync_acquire(hw, swfw)) 3499 if (e1000_swfw_sync_acquire(hw, swfw))
3300 return -E1000_ERR_SWFW_SYNC; 3500 return -E1000_ERR_SWFW_SYNC;
3301 3501
3302 if((hw->phy_type == e1000_phy_igp || 3502 if ((hw->phy_type == e1000_phy_igp ||
3503 hw->phy_type == e1000_phy_igp_3 ||
3303 hw->phy_type == e1000_phy_igp_2) && 3504 hw->phy_type == e1000_phy_igp_2) &&
3304 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3505 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3305 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3506 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3401,7 +3602,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3401 return E1000_SUCCESS; 3602 return E1000_SUCCESS;
3402} 3603}
3403 3604
3404int32_t 3605static int32_t
3405e1000_read_kmrn_reg(struct e1000_hw *hw, 3606e1000_read_kmrn_reg(struct e1000_hw *hw,
3406 uint32_t reg_addr, 3607 uint32_t reg_addr,
3407 uint16_t *data) 3608 uint16_t *data)
@@ -3434,7 +3635,7 @@ e1000_read_kmrn_reg(struct e1000_hw *hw,
3434 return E1000_SUCCESS; 3635 return E1000_SUCCESS;
3435} 3636}
3436 3637
3437int32_t 3638static int32_t
3438e1000_write_kmrn_reg(struct e1000_hw *hw, 3639e1000_write_kmrn_reg(struct e1000_hw *hw,
3439 uint32_t reg_addr, 3640 uint32_t reg_addr,
3440 uint16_t data) 3641 uint16_t data)
@@ -3514,7 +3715,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3514 E1000_WRITE_FLUSH(hw); 3715 E1000_WRITE_FLUSH(hw);
3515 3716
3516 if (hw->mac_type >= e1000_82571) 3717 if (hw->mac_type >= e1000_82571)
3517 msec_delay(10); 3718 msec_delay_irq(10);
3518 e1000_swfw_sync_release(hw, swfw); 3719 e1000_swfw_sync_release(hw, swfw);
3519 } else { 3720 } else {
3520 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3721 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3544,6 +3745,12 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3544 ret_val = e1000_get_phy_cfg_done(hw); 3745 ret_val = e1000_get_phy_cfg_done(hw);
3545 e1000_release_software_semaphore(hw); 3746 e1000_release_software_semaphore(hw);
3546 3747
3748 if ((hw->mac_type == e1000_ich8lan) &&
3749 (hw->phy_type == e1000_phy_igp_3)) {
3750 ret_val = e1000_init_lcd_from_nvm(hw);
3751 if (ret_val)
3752 return ret_val;
3753 }
3547 return ret_val; 3754 return ret_val;
3548} 3755}
3549 3756
@@ -3572,9 +3779,11 @@ e1000_phy_reset(struct e1000_hw *hw)
3572 case e1000_82541_rev_2: 3779 case e1000_82541_rev_2:
3573 case e1000_82571: 3780 case e1000_82571:
3574 case e1000_82572: 3781 case e1000_82572:
3782 case e1000_ich8lan:
3575 ret_val = e1000_phy_hw_reset(hw); 3783 ret_val = e1000_phy_hw_reset(hw);
3576 if(ret_val) 3784 if(ret_val)
3577 return ret_val; 3785 return ret_val;
3786
3578 break; 3787 break;
3579 default: 3788 default:
3580 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3789 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
@@ -3597,11 +3806,120 @@ e1000_phy_reset(struct e1000_hw *hw)
3597} 3806}
3598 3807
3599/****************************************************************************** 3808/******************************************************************************
3809* Work-around for 82566 power-down: on D3 entry-
3810* 1) disable gigabit link
3811* 2) write VR power-down enable
3812* 3) read it back
3813* if successful continue, else issue LCD reset and repeat
3814*
3815* hw - struct containing variables accessed by shared code
3816******************************************************************************/
3817void
3818e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3819{
3820 int32_t reg;
3821 uint16_t phy_data;
3822 int32_t retry = 0;
3823
3824 DEBUGFUNC("e1000_phy_powerdown_workaround");
3825
3826 if (hw->phy_type != e1000_phy_igp_3)
3827 return;
3828
3829 do {
3830 /* Disable link */
3831 reg = E1000_READ_REG(hw, PHY_CTRL);
3832 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3833 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3834
3835 /* Write VR power-down enable */
3836 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3837 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3838 IGP3_VR_CTRL_MODE_SHUT);
3839
3840 /* Read it back and test */
3841 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3842 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3843 break;
3844
3845 /* Issue PHY reset and repeat at most one more time */
3846 reg = E1000_READ_REG(hw, CTRL);
3847 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3848 retry++;
3849 } while (retry);
3850
3851 return;
3852
3853}
3854
3855/******************************************************************************
3856* Work-around for 82566 Kumeran PCS lock loss:
3857* On link status change (i.e. PCI reset, speed change) and link is up and
3858* speed is gigabit-
3859* 0) if workaround is optionally disabled do nothing
3860* 1) wait 1ms for Kumeran link to come up
3861* 2) check Kumeran Diagnostic register PCS lock loss bit
3862* 3) if not set the link is locked (all is good), otherwise...
3863* 4) reset the PHY
3864* 5) repeat up to 10 times
3865* Note: this is only called for IGP3 copper when speed is 1gb.
3866*
3867* hw - struct containing variables accessed by shared code
3868******************************************************************************/
3869static int32_t
3870e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3871{
3872 int32_t ret_val;
3873 int32_t reg;
3874 int32_t cnt;
3875 uint16_t phy_data;
3876
3877 if (hw->kmrn_lock_loss_workaround_disabled)
3878 return E1000_SUCCESS;
3879
3880 /* Make sure link is up before proceeding. If not just return.
3881 * Attempting this while link is negotiating fouls up link
3882 * stability */
3883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3884 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3885
3886 if (phy_data & MII_SR_LINK_STATUS) {
3887 for (cnt = 0; cnt < 10; cnt++) {
3888 /* read once to clear */
3889 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3890 if (ret_val)
3891 return ret_val;
3892 /* and again to get new status */
3893 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3894 if (ret_val)
3895 return ret_val;
3896
3897 /* check for PCS lock */
3898 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3899 return E1000_SUCCESS;
3900
3901 /* Issue PHY reset */
3902 e1000_phy_hw_reset(hw);
3903 msec_delay_irq(5);
3904 }
3905 /* Disable GigE link negotiation */
3906 reg = E1000_READ_REG(hw, PHY_CTRL);
3907 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3908 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3909
3910 /* unable to acquire PCS lock */
3911 return E1000_ERR_PHY;
3912 }
3913
3914 return E1000_SUCCESS;
3915}
3916
3917/******************************************************************************
3600* Probes the expected PHY address for known PHY IDs 3918* Probes the expected PHY address for known PHY IDs
3601* 3919*
3602* hw - Struct containing variables accessed by shared code 3920* hw - Struct containing variables accessed by shared code
3603******************************************************************************/ 3921******************************************************************************/
3604static int32_t 3922int32_t
3605e1000_detect_gig_phy(struct e1000_hw *hw) 3923e1000_detect_gig_phy(struct e1000_hw *hw)
3606{ 3924{
3607 int32_t phy_init_status, ret_val; 3925 int32_t phy_init_status, ret_val;
@@ -3613,8 +3931,8 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3613 /* The 82571 firmware may still be configuring the PHY. In this 3931 /* The 82571 firmware may still be configuring the PHY. In this
3614 * case, we cannot access the PHY until the configuration is done. So 3932 * case, we cannot access the PHY until the configuration is done. So
3615 * we explicitly set the PHY values. */ 3933 * we explicitly set the PHY values. */
3616 if(hw->mac_type == e1000_82571 || 3934 if (hw->mac_type == e1000_82571 ||
3617 hw->mac_type == e1000_82572) { 3935 hw->mac_type == e1000_82572) {
3618 hw->phy_id = IGP01E1000_I_PHY_ID; 3936 hw->phy_id = IGP01E1000_I_PHY_ID;
3619 hw->phy_type = e1000_phy_igp_2; 3937 hw->phy_type = e1000_phy_igp_2;
3620 return E1000_SUCCESS; 3938 return E1000_SUCCESS;
@@ -3631,7 +3949,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3631 3949
3632 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3950 /* Read the PHY ID Registers to identify which PHY is onboard. */
3633 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3951 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3634 if(ret_val) 3952 if (ret_val)
3635 return ret_val; 3953 return ret_val;
3636 3954
3637 hw->phy_id = (uint32_t) (phy_id_high << 16); 3955 hw->phy_id = (uint32_t) (phy_id_high << 16);
@@ -3669,6 +3987,12 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3669 case e1000_80003es2lan: 3987 case e1000_80003es2lan:
3670 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 3988 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3671 break; 3989 break;
3990 case e1000_ich8lan:
3991 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
3992 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
3993 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
3994 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
3995 break;
3672 default: 3996 default:
3673 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3997 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3674 return -E1000_ERR_CONFIG; 3998 return -E1000_ERR_CONFIG;
@@ -3784,6 +4108,53 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
3784} 4108}
3785 4109
3786/****************************************************************************** 4110/******************************************************************************
4111* Get PHY information from various PHY registers for ife PHY only.
4112*
4113* hw - Struct containing variables accessed by shared code
4114* phy_info - PHY information structure
4115******************************************************************************/
4116static int32_t
4117e1000_phy_ife_get_info(struct e1000_hw *hw,
4118 struct e1000_phy_info *phy_info)
4119{
4120 int32_t ret_val;
4121 uint16_t phy_data, polarity;
4122
4123 DEBUGFUNC("e1000_phy_ife_get_info");
4124
4125 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4126 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4127
4128 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4129 if (ret_val)
4130 return ret_val;
4131 phy_info->polarity_correction =
4132 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4133 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4134
4135 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4136 ret_val = e1000_check_polarity(hw, &polarity);
4137 if (ret_val)
4138 return ret_val;
4139 } else {
4140 /* Polarity is forced. */
4141 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4142 IFE_PSC_FORCE_POLARITY_SHIFT;
4143 }
4144 phy_info->cable_polarity = polarity;
4145
4146 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4147 if (ret_val)
4148 return ret_val;
4149
4150 phy_info->mdix_mode =
4151 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4152 IFE_PMC_MDIX_MODE_SHIFT;
4153
4154 return E1000_SUCCESS;
4155}
4156
4157/******************************************************************************
3787* Get PHY information from various PHY registers fot m88 PHY only. 4158* Get PHY information from various PHY registers fot m88 PHY only.
3788* 4159*
3789* hw - Struct containing variables accessed by shared code 4160* hw - Struct containing variables accessed by shared code
@@ -3898,9 +4269,12 @@ e1000_phy_get_info(struct e1000_hw *hw,
3898 return -E1000_ERR_CONFIG; 4269 return -E1000_ERR_CONFIG;
3899 } 4270 }
3900 4271
3901 if(hw->phy_type == e1000_phy_igp || 4272 if (hw->phy_type == e1000_phy_igp ||
4273 hw->phy_type == e1000_phy_igp_3 ||
3902 hw->phy_type == e1000_phy_igp_2) 4274 hw->phy_type == e1000_phy_igp_2)
3903 return e1000_phy_igp_get_info(hw, phy_info); 4275 return e1000_phy_igp_get_info(hw, phy_info);
4276 else if (hw->phy_type == e1000_phy_ife)
4277 return e1000_phy_ife_get_info(hw, phy_info);
3904 else 4278 else
3905 return e1000_phy_m88_get_info(hw, phy_info); 4279 return e1000_phy_m88_get_info(hw, phy_info);
3906} 4280}
@@ -4049,6 +4423,35 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4049 eeprom->use_eerd = TRUE; 4423 eeprom->use_eerd = TRUE;
4050 eeprom->use_eewr = FALSE; 4424 eeprom->use_eewr = FALSE;
4051 break; 4425 break;
4426 case e1000_ich8lan:
4427 {
4428 int32_t i = 0;
4429 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4430
4431 eeprom->type = e1000_eeprom_ich8;
4432 eeprom->use_eerd = FALSE;
4433 eeprom->use_eewr = FALSE;
4434 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4435
4436 /* Zero the shadow RAM structure. But don't load it from NVM
4437 * so as to save time for driver init */
4438 if (hw->eeprom_shadow_ram != NULL) {
4439 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4440 hw->eeprom_shadow_ram[i].modified = FALSE;
4441 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4442 }
4443 }
4444
4445 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4446 ICH8_FLASH_SECTOR_SIZE;
4447
4448 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4449 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4450 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4451 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4452
4453 break;
4454 }
4052 default: 4455 default:
4053 break; 4456 break;
4054 } 4457 }
@@ -4469,7 +4872,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
4469 return ret_val; 4872 return ret_val;
4470 } 4873 }
4471 4874
4472 if(eeprom->type == e1000_eeprom_spi) { 4875 if (eeprom->type == e1000_eeprom_ich8)
4876 return e1000_read_eeprom_ich8(hw, offset, words, data);
4877
4878 if (eeprom->type == e1000_eeprom_spi) {
4473 uint16_t word_in; 4879 uint16_t word_in;
4474 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4880 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4475 4881
@@ -4636,7 +5042,10 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4636 5042
4637 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5043 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
4638 5044
4639 if(hw->mac_type == e1000_82573) { 5045 if (hw->mac_type == e1000_ich8lan)
5046 return FALSE;
5047
5048 if (hw->mac_type == e1000_82573) {
4640 eecd = E1000_READ_REG(hw, EECD); 5049 eecd = E1000_READ_REG(hw, EECD);
4641 5050
4642 /* Isolate bits 15 & 16 */ 5051 /* Isolate bits 15 & 16 */
@@ -4686,8 +5095,22 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4686 } 5095 }
4687 } 5096 }
4688 5097
4689 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 5098 if (hw->mac_type == e1000_ich8lan) {
4690 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5099 /* Drivers must allocate the shadow ram structure for the
5100 * EEPROM checksum to be updated. Otherwise, this bit as well
5101 * as the checksum must both be set correctly for this
5102 * validation to pass.
5103 */
5104 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5105 if ((eeprom_data & 0x40) == 0) {
5106 eeprom_data |= 0x40;
5107 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5108 e1000_update_eeprom_checksum(hw);
5109 }
5110 }
5111
5112 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5113 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4691 DEBUGOUT("EEPROM Read Error\n"); 5114 DEBUGOUT("EEPROM Read Error\n");
4692 return -E1000_ERR_EEPROM; 5115 return -E1000_ERR_EEPROM;
4693 } 5116 }
@@ -4713,6 +5136,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4713int32_t 5136int32_t
4714e1000_update_eeprom_checksum(struct e1000_hw *hw) 5137e1000_update_eeprom_checksum(struct e1000_hw *hw)
4715{ 5138{
5139 uint32_t ctrl_ext;
4716 uint16_t checksum = 0; 5140 uint16_t checksum = 0;
4717 uint16_t i, eeprom_data; 5141 uint16_t i, eeprom_data;
4718 5142
@@ -4731,6 +5155,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
4731 return -E1000_ERR_EEPROM; 5155 return -E1000_ERR_EEPROM;
4732 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5156 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4733 e1000_commit_shadow_ram(hw); 5157 e1000_commit_shadow_ram(hw);
5158 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5159 e1000_commit_shadow_ram(hw);
5160 /* Reload the EEPROM, or else modifications will not appear
5161 * until after next adapter reset. */
5162 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5163 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5164 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5165 msec_delay(10);
4734 } 5166 }
4735 return E1000_SUCCESS; 5167 return E1000_SUCCESS;
4736} 5168}
@@ -4770,6 +5202,9 @@ e1000_write_eeprom(struct e1000_hw *hw,
4770 if(eeprom->use_eewr == TRUE) 5202 if(eeprom->use_eewr == TRUE)
4771 return e1000_write_eeprom_eewr(hw, offset, words, data); 5203 return e1000_write_eeprom_eewr(hw, offset, words, data);
4772 5204
5205 if (eeprom->type == e1000_eeprom_ich8)
5206 return e1000_write_eeprom_ich8(hw, offset, words, data);
5207
4773 /* Prepare the EEPROM for writing */ 5208 /* Prepare the EEPROM for writing */
4774 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5209 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4775 return -E1000_ERR_EEPROM; 5210 return -E1000_ERR_EEPROM;
@@ -4957,11 +5392,17 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4957 uint32_t flop = 0; 5392 uint32_t flop = 0;
4958 uint32_t i = 0; 5393 uint32_t i = 0;
4959 int32_t error = E1000_SUCCESS; 5394 int32_t error = E1000_SUCCESS;
4960 5395 uint32_t old_bank_offset = 0;
4961 /* The flop register will be used to determine if flash type is STM */ 5396 uint32_t new_bank_offset = 0;
4962 flop = E1000_READ_REG(hw, FLOP); 5397 uint32_t sector_retries = 0;
5398 uint8_t low_byte = 0;
5399 uint8_t high_byte = 0;
5400 uint8_t temp_byte = 0;
5401 boolean_t sector_write_failed = FALSE;
4963 5402
4964 if (hw->mac_type == e1000_82573) { 5403 if (hw->mac_type == e1000_82573) {
5404 /* The flop register will be used to determine if flash type is STM */
5405 flop = E1000_READ_REG(hw, FLOP);
4965 for (i=0; i < attempts; i++) { 5406 for (i=0; i < attempts; i++) {
4966 eecd = E1000_READ_REG(hw, EECD); 5407 eecd = E1000_READ_REG(hw, EECD);
4967 if ((eecd & E1000_EECD_FLUPD) == 0) { 5408 if ((eecd & E1000_EECD_FLUPD) == 0) {
@@ -4995,6 +5436,106 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4995 } 5436 }
4996 } 5437 }
4997 5438
5439 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5440 /* We're writing to the opposite bank so if we're on bank 1,
5441 * write to bank 0 etc. We also need to erase the segment that
5442 * is going to be written */
5443 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5444 new_bank_offset = hw->flash_bank_size * 2;
5445 old_bank_offset = 0;
5446 e1000_erase_ich8_4k_segment(hw, 1);
5447 } else {
5448 old_bank_offset = hw->flash_bank_size * 2;
5449 new_bank_offset = 0;
5450 e1000_erase_ich8_4k_segment(hw, 0);
5451 }
5452
5453 do {
5454 sector_write_failed = FALSE;
5455 /* Loop for every byte in the shadow RAM,
5456 * which is in units of words. */
5457 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5458 /* Determine whether to write the value stored
5459 * in the other NVM bank or a modified value stored
5460 * in the shadow RAM */
5461 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5462 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5463 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5464 &temp_byte);
5465 udelay(100);
5466 error = e1000_verify_write_ich8_byte(hw,
5467 (i << 1) + new_bank_offset,
5468 low_byte);
5469 if (error != E1000_SUCCESS)
5470 sector_write_failed = TRUE;
5471 high_byte =
5472 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5473 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5474 &temp_byte);
5475 udelay(100);
5476 } else {
5477 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5478 &low_byte);
5479 udelay(100);
5480 error = e1000_verify_write_ich8_byte(hw,
5481 (i << 1) + new_bank_offset, low_byte);
5482 if (error != E1000_SUCCESS)
5483 sector_write_failed = TRUE;
5484 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5485 &high_byte);
5486 }
5487
5488 /* If the word is 0x13, then make sure the signature bits
5489 * (15:14) are 11b until the commit has completed.
5490 * This will allow us to write 10b which indicates the
5491 * signature is valid. We want to do this after the write
5492 * has completed so that we don't mark the segment valid
5493 * while the write is still in progress */
5494 if (i == E1000_ICH8_NVM_SIG_WORD)
5495 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5496
5497 error = e1000_verify_write_ich8_byte(hw,
5498 (i << 1) + new_bank_offset + 1, high_byte);
5499 if (error != E1000_SUCCESS)
5500 sector_write_failed = TRUE;
5501
5502 if (sector_write_failed == FALSE) {
5503 /* Clear the now not used entry in the cache */
5504 hw->eeprom_shadow_ram[i].modified = FALSE;
5505 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5506 }
5507 }
5508
5509 /* Don't bother writing the segment valid bits if sector
5510 * programming failed. */
5511 if (sector_write_failed == FALSE) {
5512 /* Finally validate the new segment by setting bit 15:14
5513 * to 10b in word 0x13 , this can be done without an
5514 * erase as well since these bits are 11 to start with
5515 * and we need to change bit 14 to 0b */
5516 e1000_read_ich8_byte(hw,
5517 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5518 &high_byte);
5519 high_byte &= 0xBF;
5520 error = e1000_verify_write_ich8_byte(hw,
5521 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5522 high_byte);
5523 if (error != E1000_SUCCESS)
5524 sector_write_failed = TRUE;
5525
5526 /* And invalidate the previously valid segment by setting
5527 * its signature word (0x13) high_byte to 0b. This can be
5528 * done without an erase because flash erase sets all bits
5529 * to 1's. We can write 1's to 0's without an erase */
5530 error = e1000_verify_write_ich8_byte(hw,
5531 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5532 0);
5533 if (error != E1000_SUCCESS)
5534 sector_write_failed = TRUE;
5535 }
5536 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5537 }
5538
4998 return error; 5539 return error;
4999} 5540}
5000 5541
@@ -5102,15 +5643,19 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5102 * the other port. */ 5643 * the other port. */
5103 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5644 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5104 rar_num -= 1; 5645 rar_num -= 1;
5646 if (hw->mac_type == e1000_ich8lan)
5647 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5648
5105 /* Zero out the other 15 receive addresses. */ 5649 /* Zero out the other 15 receive addresses. */
5106 DEBUGOUT("Clearing RAR[1-15]\n"); 5650 DEBUGOUT("Clearing RAR[1-15]\n");
5107 for(i = 1; i < rar_num; i++) { 5651 for(i = 1; i < rar_num; i++) {
5108 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5652 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5653 E1000_WRITE_FLUSH(hw);
5109 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5654 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5655 E1000_WRITE_FLUSH(hw);
5110 } 5656 }
5111} 5657}
5112 5658
5113#if 0
5114/****************************************************************************** 5659/******************************************************************************
5115 * Updates the MAC's list of multicast addresses. 5660 * Updates the MAC's list of multicast addresses.
5116 * 5661 *
@@ -5125,6 +5670,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5125 * for the first 15 multicast addresses, and hashes the rest into the 5670 * for the first 15 multicast addresses, and hashes the rest into the
5126 * multicast table. 5671 * multicast table.
5127 *****************************************************************************/ 5672 *****************************************************************************/
5673#if 0
5128void 5674void
5129e1000_mc_addr_list_update(struct e1000_hw *hw, 5675e1000_mc_addr_list_update(struct e1000_hw *hw,
5130 uint8_t *mc_addr_list, 5676 uint8_t *mc_addr_list,
@@ -5145,6 +5691,8 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5145 /* Clear RAR[1-15] */ 5691 /* Clear RAR[1-15] */
5146 DEBUGOUT(" Clearing RAR[1-15]\n"); 5692 DEBUGOUT(" Clearing RAR[1-15]\n");
5147 num_rar_entry = E1000_RAR_ENTRIES; 5693 num_rar_entry = E1000_RAR_ENTRIES;
5694 if (hw->mac_type == e1000_ich8lan)
5695 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5148 /* Reserve a spot for the Locally Administered Address to work around 5696 /* Reserve a spot for the Locally Administered Address to work around
5149 * an 82571 issue in which a reset on one port will reload the MAC on 5697 * an 82571 issue in which a reset on one port will reload the MAC on
5150 * the other port. */ 5698 * the other port. */
@@ -5153,14 +5701,19 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5153 5701
5154 for(i = rar_used_count; i < num_rar_entry; i++) { 5702 for(i = rar_used_count; i < num_rar_entry; i++) {
5155 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5703 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5704 E1000_WRITE_FLUSH(hw);
5156 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5705 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5706 E1000_WRITE_FLUSH(hw);
5157 } 5707 }
5158 5708
5159 /* Clear the MTA */ 5709 /* Clear the MTA */
5160 DEBUGOUT(" Clearing MTA\n"); 5710 DEBUGOUT(" Clearing MTA\n");
5161 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5711 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5712 if (hw->mac_type == e1000_ich8lan)
5713 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5162 for(i = 0; i < num_mta_entry; i++) { 5714 for(i = 0; i < num_mta_entry; i++) {
5163 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5715 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5716 E1000_WRITE_FLUSH(hw);
5164 } 5717 }
5165 5718
5166 /* Add the new addresses */ 5719 /* Add the new addresses */
@@ -5217,24 +5770,46 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5217 * LSB MSB 5770 * LSB MSB
5218 */ 5771 */
5219 case 0: 5772 case 0:
5220 /* [47:36] i.e. 0x563 for above example address */ 5773 if (hw->mac_type == e1000_ich8lan) {
5221 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5774 /* [47:38] i.e. 0x158 for above example address */
5775 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5776 } else {
5777 /* [47:36] i.e. 0x563 for above example address */
5778 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5779 }
5222 break; 5780 break;
5223 case 1: 5781 case 1:
5224 /* [46:35] i.e. 0xAC6 for above example address */ 5782 if (hw->mac_type == e1000_ich8lan) {
5225 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5783 /* [46:37] i.e. 0x2B1 for above example address */
5784 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5785 } else {
5786 /* [46:35] i.e. 0xAC6 for above example address */
5787 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5788 }
5226 break; 5789 break;
5227 case 2: 5790 case 2:
5228 /* [45:34] i.e. 0x5D8 for above example address */ 5791 if (hw->mac_type == e1000_ich8lan) {
5229 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5792 /*[45:36] i.e. 0x163 for above example address */
5793 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5794 } else {
5795 /* [45:34] i.e. 0x5D8 for above example address */
5796 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5797 }
5230 break; 5798 break;
5231 case 3: 5799 case 3:
5232 /* [43:32] i.e. 0x634 for above example address */ 5800 if (hw->mac_type == e1000_ich8lan) {
5233 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5801 /* [43:34] i.e. 0x18D for above example address */
5802 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5803 } else {
5804 /* [43:32] i.e. 0x634 for above example address */
5805 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5806 }
5234 break; 5807 break;
5235 } 5808 }
5236 5809
5237 hash_value &= 0xFFF; 5810 hash_value &= 0xFFF;
5811 if (hw->mac_type == e1000_ich8lan)
5812 hash_value &= 0x3FF;
5238 5813
5239 return hash_value; 5814 return hash_value;
5240} 5815}
@@ -5262,6 +5837,8 @@ e1000_mta_set(struct e1000_hw *hw,
5262 * register are determined by the lower 5 bits of the value. 5837 * register are determined by the lower 5 bits of the value.
5263 */ 5838 */
5264 hash_reg = (hash_value >> 5) & 0x7F; 5839 hash_reg = (hash_value >> 5) & 0x7F;
5840 if (hw->mac_type == e1000_ich8lan)
5841 hash_reg &= 0x1F;
5265 hash_bit = hash_value & 0x1F; 5842 hash_bit = hash_value & 0x1F;
5266 5843
5267 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5844 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -5275,9 +5852,12 @@ e1000_mta_set(struct e1000_hw *hw,
5275 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5852 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5276 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5853 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5277 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5854 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5855 E1000_WRITE_FLUSH(hw);
5278 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5856 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5857 E1000_WRITE_FLUSH(hw);
5279 } else { 5858 } else {
5280 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5859 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5860 E1000_WRITE_FLUSH(hw);
5281 } 5861 }
5282} 5862}
5283 5863
@@ -5334,7 +5914,9 @@ e1000_rar_set(struct e1000_hw *hw,
5334 } 5914 }
5335 5915
5336 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5916 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5917 E1000_WRITE_FLUSH(hw);
5337 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5918 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5919 E1000_WRITE_FLUSH(hw);
5338} 5920}
5339 5921
5340/****************************************************************************** 5922/******************************************************************************
@@ -5351,12 +5933,18 @@ e1000_write_vfta(struct e1000_hw *hw,
5351{ 5933{
5352 uint32_t temp; 5934 uint32_t temp;
5353 5935
5354 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5936 if (hw->mac_type == e1000_ich8lan)
5937 return;
5938
5939 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5355 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5940 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5356 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5941 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5942 E1000_WRITE_FLUSH(hw);
5357 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 5943 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5944 E1000_WRITE_FLUSH(hw);
5358 } else { 5945 } else {
5359 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5946 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5947 E1000_WRITE_FLUSH(hw);
5360 } 5948 }
5361} 5949}
5362 5950
@@ -5373,6 +5961,9 @@ e1000_clear_vfta(struct e1000_hw *hw)
5373 uint32_t vfta_offset = 0; 5961 uint32_t vfta_offset = 0;
5374 uint32_t vfta_bit_in_reg = 0; 5962 uint32_t vfta_bit_in_reg = 0;
5375 5963
5964 if (hw->mac_type == e1000_ich8lan)
5965 return;
5966
5376 if (hw->mac_type == e1000_82573) { 5967 if (hw->mac_type == e1000_82573) {
5377 if (hw->mng_cookie.vlan_id != 0) { 5968 if (hw->mng_cookie.vlan_id != 0) {
5378 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 5969 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
@@ -5392,6 +5983,7 @@ e1000_clear_vfta(struct e1000_hw *hw)
5392 * manageability unit */ 5983 * manageability unit */
5393 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5984 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5394 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5985 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5986 E1000_WRITE_FLUSH(hw);
5395 } 5987 }
5396} 5988}
5397 5989
@@ -5421,9 +6013,18 @@ e1000_id_led_init(struct e1000_hw * hw)
5421 DEBUGOUT("EEPROM Read Error\n"); 6013 DEBUGOUT("EEPROM Read Error\n");
5422 return -E1000_ERR_EEPROM; 6014 return -E1000_ERR_EEPROM;
5423 } 6015 }
5424 if((eeprom_data== ID_LED_RESERVED_0000) || 6016
5425 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; 6017 if ((hw->mac_type == e1000_82573) &&
5426 for(i = 0; i < 4; i++) { 6018 (eeprom_data == ID_LED_RESERVED_82573))
6019 eeprom_data = ID_LED_DEFAULT_82573;
6020 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6021 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6022 if (hw->mac_type == e1000_ich8lan)
6023 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6024 else
6025 eeprom_data = ID_LED_DEFAULT;
6026 }
6027 for (i = 0; i < 4; i++) {
5427 temp = (eeprom_data >> (i << 2)) & led_mask; 6028 temp = (eeprom_data >> (i << 2)) & led_mask;
5428 switch(temp) { 6029 switch(temp) {
5429 case ID_LED_ON1_DEF2: 6030 case ID_LED_ON1_DEF2:
@@ -5519,6 +6120,44 @@ e1000_setup_led(struct e1000_hw *hw)
5519} 6120}
5520 6121
5521/****************************************************************************** 6122/******************************************************************************
6123 * Used on 82571 and later Si that has LED blink bits.
6124 * Callers must use their own timer and should have already called
6125 * e1000_id_led_init()
6126 * Call e1000_cleanup led() to stop blinking
6127 *
6128 * hw - Struct containing variables accessed by shared code
6129 *****************************************************************************/
6130int32_t
6131e1000_blink_led_start(struct e1000_hw *hw)
6132{
6133 int16_t i;
6134 uint32_t ledctl_blink = 0;
6135
6136 DEBUGFUNC("e1000_id_led_blink_on");
6137
6138 if (hw->mac_type < e1000_82571) {
6139 /* Nothing to do */
6140 return E1000_SUCCESS;
6141 }
6142 if (hw->media_type == e1000_media_type_fiber) {
6143 /* always blink LED0 for PCI-E fiber */
6144 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6145 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6146 } else {
6147 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6148 ledctl_blink = hw->ledctl_mode2;
6149 for (i=0; i < 4; i++)
6150 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6151 E1000_LEDCTL_MODE_LED_ON)
6152 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6153 }
6154
6155 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6156
6157 return E1000_SUCCESS;
6158}
6159
6160/******************************************************************************
5522 * Restores the saved state of the SW controlable LED. 6161 * Restores the saved state of the SW controlable LED.
5523 * 6162 *
5524 * hw - Struct containing variables accessed by shared code 6163 * hw - Struct containing variables accessed by shared code
@@ -5548,6 +6187,10 @@ e1000_cleanup_led(struct e1000_hw *hw)
5548 return ret_val; 6187 return ret_val;
5549 /* Fall Through */ 6188 /* Fall Through */
5550 default: 6189 default:
6190 if (hw->phy_type == e1000_phy_ife) {
6191 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6192 break;
6193 }
5551 /* Restore LEDCTL settings */ 6194 /* Restore LEDCTL settings */
5552 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6195 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
5553 break; 6196 break;
@@ -5592,7 +6235,10 @@ e1000_led_on(struct e1000_hw *hw)
5592 /* Clear SW Defineable Pin 0 to turn on the LED */ 6235 /* Clear SW Defineable Pin 0 to turn on the LED */
5593 ctrl &= ~E1000_CTRL_SWDPIN0; 6236 ctrl &= ~E1000_CTRL_SWDPIN0;
5594 ctrl |= E1000_CTRL_SWDPIO0; 6237 ctrl |= E1000_CTRL_SWDPIO0;
5595 } else if(hw->media_type == e1000_media_type_copper) { 6238 } else if (hw->phy_type == e1000_phy_ife) {
6239 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6240 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6241 } else if (hw->media_type == e1000_media_type_copper) {
5596 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6242 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5597 return E1000_SUCCESS; 6243 return E1000_SUCCESS;
5598 } 6244 }
@@ -5640,7 +6286,10 @@ e1000_led_off(struct e1000_hw *hw)
5640 /* Set SW Defineable Pin 0 to turn off the LED */ 6286 /* Set SW Defineable Pin 0 to turn off the LED */
5641 ctrl |= E1000_CTRL_SWDPIN0; 6287 ctrl |= E1000_CTRL_SWDPIN0;
5642 ctrl |= E1000_CTRL_SWDPIO0; 6288 ctrl |= E1000_CTRL_SWDPIO0;
5643 } else if(hw->media_type == e1000_media_type_copper) { 6289 } else if (hw->phy_type == e1000_phy_ife) {
6290 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6291 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6292 } else if (hw->media_type == e1000_media_type_copper) {
5644 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6293 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5645 return E1000_SUCCESS; 6294 return E1000_SUCCESS;
5646 } 6295 }
@@ -5678,12 +6327,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5678 temp = E1000_READ_REG(hw, XOFFRXC); 6327 temp = E1000_READ_REG(hw, XOFFRXC);
5679 temp = E1000_READ_REG(hw, XOFFTXC); 6328 temp = E1000_READ_REG(hw, XOFFTXC);
5680 temp = E1000_READ_REG(hw, FCRUC); 6329 temp = E1000_READ_REG(hw, FCRUC);
6330
6331 if (hw->mac_type != e1000_ich8lan) {
5681 temp = E1000_READ_REG(hw, PRC64); 6332 temp = E1000_READ_REG(hw, PRC64);
5682 temp = E1000_READ_REG(hw, PRC127); 6333 temp = E1000_READ_REG(hw, PRC127);
5683 temp = E1000_READ_REG(hw, PRC255); 6334 temp = E1000_READ_REG(hw, PRC255);
5684 temp = E1000_READ_REG(hw, PRC511); 6335 temp = E1000_READ_REG(hw, PRC511);
5685 temp = E1000_READ_REG(hw, PRC1023); 6336 temp = E1000_READ_REG(hw, PRC1023);
5686 temp = E1000_READ_REG(hw, PRC1522); 6337 temp = E1000_READ_REG(hw, PRC1522);
6338 }
6339
5687 temp = E1000_READ_REG(hw, GPRC); 6340 temp = E1000_READ_REG(hw, GPRC);
5688 temp = E1000_READ_REG(hw, BPRC); 6341 temp = E1000_READ_REG(hw, BPRC);
5689 temp = E1000_READ_REG(hw, MPRC); 6342 temp = E1000_READ_REG(hw, MPRC);
@@ -5703,12 +6356,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5703 temp = E1000_READ_REG(hw, TOTH); 6356 temp = E1000_READ_REG(hw, TOTH);
5704 temp = E1000_READ_REG(hw, TPR); 6357 temp = E1000_READ_REG(hw, TPR);
5705 temp = E1000_READ_REG(hw, TPT); 6358 temp = E1000_READ_REG(hw, TPT);
6359
6360 if (hw->mac_type != e1000_ich8lan) {
5706 temp = E1000_READ_REG(hw, PTC64); 6361 temp = E1000_READ_REG(hw, PTC64);
5707 temp = E1000_READ_REG(hw, PTC127); 6362 temp = E1000_READ_REG(hw, PTC127);
5708 temp = E1000_READ_REG(hw, PTC255); 6363 temp = E1000_READ_REG(hw, PTC255);
5709 temp = E1000_READ_REG(hw, PTC511); 6364 temp = E1000_READ_REG(hw, PTC511);
5710 temp = E1000_READ_REG(hw, PTC1023); 6365 temp = E1000_READ_REG(hw, PTC1023);
5711 temp = E1000_READ_REG(hw, PTC1522); 6366 temp = E1000_READ_REG(hw, PTC1522);
6367 }
6368
5712 temp = E1000_READ_REG(hw, MPTC); 6369 temp = E1000_READ_REG(hw, MPTC);
5713 temp = E1000_READ_REG(hw, BPTC); 6370 temp = E1000_READ_REG(hw, BPTC);
5714 6371
@@ -5731,6 +6388,9 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5731 6388
5732 temp = E1000_READ_REG(hw, IAC); 6389 temp = E1000_READ_REG(hw, IAC);
5733 temp = E1000_READ_REG(hw, ICRXOC); 6390 temp = E1000_READ_REG(hw, ICRXOC);
6391
6392 if (hw->mac_type == e1000_ich8lan) return;
6393
5734 temp = E1000_READ_REG(hw, ICRXPTC); 6394 temp = E1000_READ_REG(hw, ICRXPTC);
5735 temp = E1000_READ_REG(hw, ICRXATC); 6395 temp = E1000_READ_REG(hw, ICRXATC);
5736 temp = E1000_READ_REG(hw, ICTXPTC); 6396 temp = E1000_READ_REG(hw, ICTXPTC);
@@ -5911,6 +6571,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
5911 hw->bus_width = e1000_bus_width_pciex_1; 6571 hw->bus_width = e1000_bus_width_pciex_1;
5912 break; 6572 break;
5913 case e1000_82571: 6573 case e1000_82571:
6574 case e1000_ich8lan:
5914 case e1000_80003es2lan: 6575 case e1000_80003es2lan:
5915 hw->bus_type = e1000_bus_type_pci_express; 6576 hw->bus_type = e1000_bus_type_pci_express;
5916 hw->bus_speed = e1000_bus_speed_2500; 6577 hw->bus_speed = e1000_bus_speed_2500;
@@ -5948,8 +6609,6 @@ e1000_get_bus_info(struct e1000_hw *hw)
5948 break; 6609 break;
5949 } 6610 }
5950} 6611}
5951
5952#if 0
5953/****************************************************************************** 6612/******************************************************************************
5954 * Reads a value from one of the devices registers using port I/O (as opposed 6613 * Reads a value from one of the devices registers using port I/O (as opposed
5955 * memory mapped I/O). Only 82544 and newer devices support port I/O. 6614 * memory mapped I/O). Only 82544 and newer devices support port I/O.
@@ -5957,6 +6616,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
5957 * hw - Struct containing variables accessed by shared code 6616 * hw - Struct containing variables accessed by shared code
5958 * offset - offset to read from 6617 * offset - offset to read from
5959 *****************************************************************************/ 6618 *****************************************************************************/
6619#if 0
5960uint32_t 6620uint32_t
5961e1000_read_reg_io(struct e1000_hw *hw, 6621e1000_read_reg_io(struct e1000_hw *hw,
5962 uint32_t offset) 6622 uint32_t offset)
@@ -6012,8 +6672,6 @@ e1000_get_cable_length(struct e1000_hw *hw,
6012{ 6672{
6013 int32_t ret_val; 6673 int32_t ret_val;
6014 uint16_t agc_value = 0; 6674 uint16_t agc_value = 0;
6015 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6016 uint16_t max_agc = 0;
6017 uint16_t i, phy_data; 6675 uint16_t i, phy_data;
6018 uint16_t cable_length; 6676 uint16_t cable_length;
6019 6677
@@ -6086,6 +6744,8 @@ e1000_get_cable_length(struct e1000_hw *hw,
6086 break; 6744 break;
6087 } 6745 }
6088 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6746 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6747 uint16_t cur_agc_value;
6748 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6089 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6749 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6090 {IGP01E1000_PHY_AGC_A, 6750 {IGP01E1000_PHY_AGC_A,
6091 IGP01E1000_PHY_AGC_B, 6751 IGP01E1000_PHY_AGC_B,
@@ -6098,23 +6758,23 @@ e1000_get_cable_length(struct e1000_hw *hw,
6098 if(ret_val) 6758 if(ret_val)
6099 return ret_val; 6759 return ret_val;
6100 6760
6101 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6761 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6102 6762
6103 /* Array bound check. */ 6763 /* Value bound check. */
6104 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 6764 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6105 (cur_agc == 0)) 6765 (cur_agc_value == 0))
6106 return -E1000_ERR_PHY; 6766 return -E1000_ERR_PHY;
6107 6767
6108 agc_value += cur_agc; 6768 agc_value += cur_agc_value;
6109 6769
6110 /* Update minimal AGC value. */ 6770 /* Update minimal AGC value. */
6111 if(min_agc > cur_agc) 6771 if (min_agc_value > cur_agc_value)
6112 min_agc = cur_agc; 6772 min_agc_value = cur_agc_value;
6113 } 6773 }
6114 6774
6115 /* Remove the minimal AGC result for length < 50m */ 6775 /* Remove the minimal AGC result for length < 50m */
6116 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 6776 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6117 agc_value -= min_agc; 6777 agc_value -= min_agc_value;
6118 6778
6119 /* Get the average length of the remaining 3 channels */ 6779 /* Get the average length of the remaining 3 channels */
6120 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 6780 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
@@ -6130,7 +6790,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6130 IGP01E1000_AGC_RANGE) : 0; 6790 IGP01E1000_AGC_RANGE) : 0;
6131 *max_length = e1000_igp_cable_length_table[agc_value] + 6791 *max_length = e1000_igp_cable_length_table[agc_value] +
6132 IGP01E1000_AGC_RANGE; 6792 IGP01E1000_AGC_RANGE;
6133 } else if (hw->phy_type == e1000_phy_igp_2) { 6793 } else if (hw->phy_type == e1000_phy_igp_2 ||
6794 hw->phy_type == e1000_phy_igp_3) {
6795 uint16_t cur_agc_index, max_agc_index = 0;
6796 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6134 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6797 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6135 {IGP02E1000_PHY_AGC_A, 6798 {IGP02E1000_PHY_AGC_A,
6136 IGP02E1000_PHY_AGC_B, 6799 IGP02E1000_PHY_AGC_B,
@@ -6145,19 +6808,27 @@ e1000_get_cable_length(struct e1000_hw *hw,
6145 /* Getting bits 15:9, which represent the combination of course and 6808 /* Getting bits 15:9, which represent the combination of course and
6146 * fine gain values. The result is a number that can be put into 6809 * fine gain values. The result is a number that can be put into
6147 * the lookup table to obtain the approximate cable length. */ 6810 * the lookup table to obtain the approximate cable length. */
6148 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6811 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6149 IGP02E1000_AGC_LENGTH_MASK; 6812 IGP02E1000_AGC_LENGTH_MASK;
6150 6813
6151 /* Remove min & max AGC values from calculation. */ 6814 /* Array index bound check. */
6152 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) 6815 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6153 min_agc = cur_agc; 6816 (cur_agc_index == 0))
6154 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) 6817 return -E1000_ERR_PHY;
6155 max_agc = cur_agc;
6156 6818
6157 agc_value += e1000_igp_2_cable_length_table[cur_agc]; 6819 /* Remove min & max AGC values from calculation. */
6820 if (e1000_igp_2_cable_length_table[min_agc_index] >
6821 e1000_igp_2_cable_length_table[cur_agc_index])
6822 min_agc_index = cur_agc_index;
6823 if (e1000_igp_2_cable_length_table[max_agc_index] <
6824 e1000_igp_2_cable_length_table[cur_agc_index])
6825 max_agc_index = cur_agc_index;
6826
6827 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6158 } 6828 }
6159 6829
6160 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); 6830 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6831 e1000_igp_2_cable_length_table[max_agc_index]);
6161 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 6832 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6162 6833
6163 /* Calculate cable length with the error range of +/- 10 meters. */ 6834 /* Calculate cable length with the error range of +/- 10 meters. */
@@ -6203,7 +6874,8 @@ e1000_check_polarity(struct e1000_hw *hw,
6203 return ret_val; 6874 return ret_val;
6204 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6875 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6205 M88E1000_PSSR_REV_POLARITY_SHIFT; 6876 M88E1000_PSSR_REV_POLARITY_SHIFT;
6206 } else if(hw->phy_type == e1000_phy_igp || 6877 } else if (hw->phy_type == e1000_phy_igp ||
6878 hw->phy_type == e1000_phy_igp_3 ||
6207 hw->phy_type == e1000_phy_igp_2) { 6879 hw->phy_type == e1000_phy_igp_2) {
6208 /* Read the Status register to check the speed */ 6880 /* Read the Status register to check the speed */
6209 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6881 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
@@ -6229,6 +6901,13 @@ e1000_check_polarity(struct e1000_hw *hw,
6229 * 100 Mbps this bit is always 0) */ 6901 * 100 Mbps this bit is always 0) */
6230 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; 6902 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6231 } 6903 }
6904 } else if (hw->phy_type == e1000_phy_ife) {
6905 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6906 &phy_data);
6907 if (ret_val)
6908 return ret_val;
6909 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6910 IFE_PESC_POLARITY_REVERSED_SHIFT;
6232 } 6911 }
6233 return E1000_SUCCESS; 6912 return E1000_SUCCESS;
6234} 6913}
@@ -6256,7 +6935,8 @@ e1000_check_downshift(struct e1000_hw *hw)
6256 6935
6257 DEBUGFUNC("e1000_check_downshift"); 6936 DEBUGFUNC("e1000_check_downshift");
6258 6937
6259 if(hw->phy_type == e1000_phy_igp || 6938 if (hw->phy_type == e1000_phy_igp ||
6939 hw->phy_type == e1000_phy_igp_3 ||
6260 hw->phy_type == e1000_phy_igp_2) { 6940 hw->phy_type == e1000_phy_igp_2) {
6261 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6941 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6262 &phy_data); 6942 &phy_data);
@@ -6273,6 +6953,9 @@ e1000_check_downshift(struct e1000_hw *hw)
6273 6953
6274 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6954 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6275 M88E1000_PSSR_DOWNSHIFT_SHIFT; 6955 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6956 } else if (hw->phy_type == e1000_phy_ife) {
6957 /* e1000_phy_ife supports 10/100 speed only */
6958 hw->speed_downgraded = FALSE;
6276 } 6959 }
6277 6960
6278 return E1000_SUCCESS; 6961 return E1000_SUCCESS;
@@ -6317,7 +7000,9 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6317 7000
6318 if(speed == SPEED_1000) { 7001 if(speed == SPEED_1000) {
6319 7002
6320 e1000_get_cable_length(hw, &min_length, &max_length); 7003 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7004 if (ret_val)
7005 return ret_val;
6321 7006
6322 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 7007 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6323 min_length >= e1000_igp_cable_length_50) { 7008 min_length >= e1000_igp_cable_length_50) {
@@ -6525,20 +7210,27 @@ static int32_t
6525e1000_set_d3_lplu_state(struct e1000_hw *hw, 7210e1000_set_d3_lplu_state(struct e1000_hw *hw,
6526 boolean_t active) 7211 boolean_t active)
6527{ 7212{
7213 uint32_t phy_ctrl = 0;
6528 int32_t ret_val; 7214 int32_t ret_val;
6529 uint16_t phy_data; 7215 uint16_t phy_data;
6530 DEBUGFUNC("e1000_set_d3_lplu_state"); 7216 DEBUGFUNC("e1000_set_d3_lplu_state");
6531 7217
6532 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) 7218 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7219 && hw->phy_type != e1000_phy_igp_3)
6533 return E1000_SUCCESS; 7220 return E1000_SUCCESS;
6534 7221
6535 /* During driver activity LPLU should not be used or it will attain link 7222 /* During driver activity LPLU should not be used or it will attain link
6536 * from the lowest speeds starting from 10Mbps. The capability is used for 7223 * from the lowest speeds starting from 10Mbps. The capability is used for
6537 * Dx transitions and states */ 7224 * Dx transitions and states */
6538 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 7225 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
6539 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 7226 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
6540 if(ret_val) 7227 if (ret_val)
6541 return ret_val; 7228 return ret_val;
7229 } else if (hw->mac_type == e1000_ich8lan) {
7230 /* MAC writes into PHY register based on the state transition
7231 * and start auto-negotiation. SW driver can overwrite the settings
7232 * in CSR PHY power control E1000_PHY_CTRL register. */
7233 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
6542 } else { 7234 } else {
6543 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7235 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6544 if(ret_val) 7236 if(ret_val)
@@ -6553,11 +7245,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6553 if(ret_val) 7245 if(ret_val)
6554 return ret_val; 7246 return ret_val;
6555 } else { 7247 } else {
7248 if (hw->mac_type == e1000_ich8lan) {
7249 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7250 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7251 } else {
6556 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7252 phy_data &= ~IGP02E1000_PM_D3_LPLU;
6557 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7253 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6558 phy_data); 7254 phy_data);
6559 if (ret_val) 7255 if (ret_val)
6560 return ret_val; 7256 return ret_val;
7257 }
6561 } 7258 }
6562 7259
6563 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7260 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
@@ -6593,17 +7290,22 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6593 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7290 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
6594 7291
6595 if(hw->mac_type == e1000_82541_rev_2 || 7292 if(hw->mac_type == e1000_82541_rev_2 ||
6596 hw->mac_type == e1000_82547_rev_2) { 7293 hw->mac_type == e1000_82547_rev_2) {
6597 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7294 phy_data |= IGP01E1000_GMII_FLEX_SPD;
6598 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7295 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6599 if(ret_val) 7296 if(ret_val)
6600 return ret_val; 7297 return ret_val;
6601 } else { 7298 } else {
7299 if (hw->mac_type == e1000_ich8lan) {
7300 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7301 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7302 } else {
6602 phy_data |= IGP02E1000_PM_D3_LPLU; 7303 phy_data |= IGP02E1000_PM_D3_LPLU;
6603 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7304 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6604 phy_data); 7305 phy_data);
6605 if (ret_val) 7306 if (ret_val)
6606 return ret_val; 7307 return ret_val;
7308 }
6607 } 7309 }
6608 7310
6609 /* When LPLU is enabled we should disable SmartSpeed */ 7311 /* When LPLU is enabled we should disable SmartSpeed */
@@ -6638,6 +7340,7 @@ static int32_t
6638e1000_set_d0_lplu_state(struct e1000_hw *hw, 7340e1000_set_d0_lplu_state(struct e1000_hw *hw,
6639 boolean_t active) 7341 boolean_t active)
6640{ 7342{
7343 uint32_t phy_ctrl = 0;
6641 int32_t ret_val; 7344 int32_t ret_val;
6642 uint16_t phy_data; 7345 uint16_t phy_data;
6643 DEBUGFUNC("e1000_set_d0_lplu_state"); 7346 DEBUGFUNC("e1000_set_d0_lplu_state");
@@ -6645,15 +7348,24 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6645 if(hw->mac_type <= e1000_82547_rev_2) 7348 if(hw->mac_type <= e1000_82547_rev_2)
6646 return E1000_SUCCESS; 7349 return E1000_SUCCESS;
6647 7350
7351 if (hw->mac_type == e1000_ich8lan) {
7352 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7353 } else {
6648 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7354 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6649 if(ret_val) 7355 if(ret_val)
6650 return ret_val; 7356 return ret_val;
7357 }
6651 7358
6652 if (!active) { 7359 if (!active) {
7360 if (hw->mac_type == e1000_ich8lan) {
7361 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7362 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7363 } else {
6653 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7364 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6654 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7365 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6655 if (ret_val) 7366 if (ret_val)
6656 return ret_val; 7367 return ret_val;
7368 }
6657 7369
6658 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7370 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6659 * Dx states where the power conservation is most important. During 7371 * Dx states where the power conservation is most important. During
@@ -6686,10 +7398,15 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6686 7398
6687 } else { 7399 } else {
6688 7400
7401 if (hw->mac_type == e1000_ich8lan) {
7402 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7403 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7404 } else {
6689 phy_data |= IGP02E1000_PM_D0_LPLU; 7405 phy_data |= IGP02E1000_PM_D0_LPLU;
6690 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7406 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6691 if (ret_val) 7407 if (ret_val)
6692 return ret_val; 7408 return ret_val;
7409 }
6693 7410
6694 /* When LPLU is enabled we should disable SmartSpeed */ 7411 /* When LPLU is enabled we should disable SmartSpeed */
6695 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
@@ -6928,8 +7645,10 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
6928 7645
6929 length >>= 2; 7646 length >>= 2;
6930 /* The device driver writes the relevant command block into the ram area. */ 7647 /* The device driver writes the relevant command block into the ram area. */
6931 for (i = 0; i < length; i++) 7648 for (i = 0; i < length; i++) {
6932 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); 7649 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7650 E1000_WRITE_FLUSH(hw);
7651 }
6933 7652
6934 return E1000_SUCCESS; 7653 return E1000_SUCCESS;
6935} 7654}
@@ -6961,15 +7680,18 @@ e1000_mng_write_commit(
6961 * returns - TRUE when the mode is IAMT or FALSE. 7680 * returns - TRUE when the mode is IAMT or FALSE.
6962 ****************************************************************************/ 7681 ****************************************************************************/
6963boolean_t 7682boolean_t
6964e1000_check_mng_mode( 7683e1000_check_mng_mode(struct e1000_hw *hw)
6965 struct e1000_hw *hw)
6966{ 7684{
6967 uint32_t fwsm; 7685 uint32_t fwsm;
6968 7686
6969 fwsm = E1000_READ_REG(hw, FWSM); 7687 fwsm = E1000_READ_REG(hw, FWSM);
6970 7688
6971 if((fwsm & E1000_FWSM_MODE_MASK) == 7689 if (hw->mac_type == e1000_ich8lan) {
6972 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7690 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7691 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7692 return TRUE;
7693 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7694 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6973 return TRUE; 7695 return TRUE;
6974 7696
6975 return FALSE; 7697 return FALSE;
@@ -7209,7 +7931,6 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7209 E1000_WRITE_REG(hw, CTRL, ctrl); 7931 E1000_WRITE_REG(hw, CTRL, ctrl);
7210} 7932}
7211 7933
7212#if 0
7213/*************************************************************************** 7934/***************************************************************************
7214 * 7935 *
7215 * Enables PCI-Express master access. 7936 * Enables PCI-Express master access.
@@ -7219,6 +7940,7 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7219 * returns: - none. 7940 * returns: - none.
7220 * 7941 *
7221 ***************************************************************************/ 7942 ***************************************************************************/
7943#if 0
7222void 7944void
7223e1000_enable_pciex_master(struct e1000_hw *hw) 7945e1000_enable_pciex_master(struct e1000_hw *hw)
7224{ 7946{
@@ -7299,8 +8021,10 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
7299 case e1000_82572: 8021 case e1000_82572:
7300 case e1000_82573: 8022 case e1000_82573:
7301 case e1000_80003es2lan: 8023 case e1000_80003es2lan:
7302 while(timeout) { 8024 case e1000_ich8lan:
7303 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; 8025 while (timeout) {
8026 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8027 break;
7304 else msec_delay(1); 8028 else msec_delay(1);
7305 timeout--; 8029 timeout--;
7306 } 8030 }
@@ -7340,7 +8064,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
7340 8064
7341 switch (hw->mac_type) { 8065 switch (hw->mac_type) {
7342 default: 8066 default:
7343 msec_delay(10); 8067 msec_delay_irq(10);
7344 break; 8068 break;
7345 case e1000_80003es2lan: 8069 case e1000_80003es2lan:
7346 /* Separate *_CFG_DONE_* bit for each port */ 8070 /* Separate *_CFG_DONE_* bit for each port */
@@ -7457,7 +8181,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7457 * E1000_SUCCESS at any other case. 8181 * E1000_SUCCESS at any other case.
7458 * 8182 *
7459 ***************************************************************************/ 8183 ***************************************************************************/
7460int32_t 8184static int32_t
7461e1000_get_software_semaphore(struct e1000_hw *hw) 8185e1000_get_software_semaphore(struct e1000_hw *hw)
7462{ 8186{
7463 int32_t timeout = hw->eeprom.word_size + 1; 8187 int32_t timeout = hw->eeprom.word_size + 1;
@@ -7492,7 +8216,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
7492 * hw: Struct containing variables accessed by shared code 8216 * hw: Struct containing variables accessed by shared code
7493 * 8217 *
7494 ***************************************************************************/ 8218 ***************************************************************************/
7495void 8219static void
7496e1000_release_software_semaphore(struct e1000_hw *hw) 8220e1000_release_software_semaphore(struct e1000_hw *hw)
7497{ 8221{
7498 uint32_t swsm; 8222 uint32_t swsm;
@@ -7523,6 +8247,13 @@ int32_t
7523e1000_check_phy_reset_block(struct e1000_hw *hw) 8247e1000_check_phy_reset_block(struct e1000_hw *hw)
7524{ 8248{
7525 uint32_t manc = 0; 8249 uint32_t manc = 0;
8250 uint32_t fwsm = 0;
8251
8252 if (hw->mac_type == e1000_ich8lan) {
8253 fwsm = E1000_READ_REG(hw, FWSM);
8254 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8255 : E1000_BLK_PHY_RESET;
8256 }
7526 8257
7527 if (hw->mac_type > e1000_82547_rev_2) 8258 if (hw->mac_type > e1000_82547_rev_2)
7528 manc = E1000_READ_REG(hw, MANC); 8259 manc = E1000_READ_REG(hw, MANC);
@@ -7549,6 +8280,8 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7549 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8280 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
7550 return TRUE; 8281 return TRUE;
7551 break; 8282 break;
8283 case e1000_ich8lan:
8284 return TRUE;
7552 default: 8285 default:
7553 break; 8286 break;
7554 } 8287 }
@@ -7556,4 +8289,854 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7556} 8289}
7557 8290
7558 8291
8292/******************************************************************************
8293 * Configure PCI-Ex no-snoop
8294 *
8295 * hw - Struct containing variables accessed by shared code.
8296 * no_snoop - Bitmap of no-snoop events.
8297 *
8298 * returns: E1000_SUCCESS
8299 *
8300 *****************************************************************************/
8301static int32_t
8302e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8303{
8304 uint32_t gcr_reg = 0;
8305
8306 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8307
8308 if (hw->bus_type == e1000_bus_type_unknown)
8309 e1000_get_bus_info(hw);
8310
8311 if (hw->bus_type != e1000_bus_type_pci_express)
8312 return E1000_SUCCESS;
8313
8314 if (no_snoop) {
8315 gcr_reg = E1000_READ_REG(hw, GCR);
8316 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8317 gcr_reg |= no_snoop;
8318 E1000_WRITE_REG(hw, GCR, gcr_reg);
8319 }
8320 if (hw->mac_type == e1000_ich8lan) {
8321 uint32_t ctrl_ext;
8322
8323 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8324
8325 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8326 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8327 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8328 }
8329
8330 return E1000_SUCCESS;
8331}
8332
8333/***************************************************************************
8334 *
8335 * Get software semaphore FLAG bit (SWFLAG).
8336 * SWFLAG is used to synchronize the access to all shared resource between
8337 * SW, FW and HW.
8338 *
8339 * hw: Struct containing variables accessed by shared code
8340 *
8341 ***************************************************************************/
8342static int32_t
8343e1000_get_software_flag(struct e1000_hw *hw)
8344{
8345 int32_t timeout = PHY_CFG_TIMEOUT;
8346 uint32_t extcnf_ctrl;
8347
8348 DEBUGFUNC("e1000_get_software_flag");
8349
8350 if (hw->mac_type == e1000_ich8lan) {
8351 while (timeout) {
8352 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8353 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8354 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8355
8356 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8357 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8358 break;
8359 msec_delay_irq(1);
8360 timeout--;
8361 }
8362
8363 if (!timeout) {
8364 DEBUGOUT("FW or HW locks the resource too long.\n");
8365 return -E1000_ERR_CONFIG;
8366 }
8367 }
8368
8369 return E1000_SUCCESS;
8370}
8371
8372/***************************************************************************
8373 *
8374 * Release software semaphore FLAG bit (SWFLAG).
8375 * SWFLAG is used to synchronize the access to all shared resource between
8376 * SW, FW and HW.
8377 *
8378 * hw: Struct containing variables accessed by shared code
8379 *
8380 ***************************************************************************/
8381static void
8382e1000_release_software_flag(struct e1000_hw *hw)
8383{
8384 uint32_t extcnf_ctrl;
8385
8386 DEBUGFUNC("e1000_release_software_flag");
8387
8388 if (hw->mac_type == e1000_ich8lan) {
8389 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8390 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8391 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8392 }
8393
8394 return;
8395}
8396
8397/***************************************************************************
8398 *
8399 * Disable dynamic power down mode in ife PHY.
8400 * It can be used to workaround band-gap problem.
8401 *
8402 * hw: Struct containing variables accessed by shared code
8403 *
8404 ***************************************************************************/
8405#if 0
8406int32_t
8407e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8408{
8409 uint16_t phy_data;
8410 int32_t ret_val = E1000_SUCCESS;
8411
8412 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8413
8414 if (hw->phy_type == e1000_phy_ife) {
8415 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8416 if (ret_val)
8417 return ret_val;
8418
8419 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8420 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8421 }
8422
8423 return ret_val;
8424}
8425#endif /* 0 */
8426
8427/***************************************************************************
8428 *
8429 * Enable dynamic power down mode in ife PHY.
8430 * It can be used to workaround band-gap problem.
8431 *
8432 * hw: Struct containing variables accessed by shared code
8433 *
8434 ***************************************************************************/
8435#if 0
8436int32_t
8437e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8438{
8439 uint16_t phy_data;
8440 int32_t ret_val = E1000_SUCCESS;
8441
8442 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8443
8444 if (hw->phy_type == e1000_phy_ife) {
8445 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8446 if (ret_val)
8447 return ret_val;
8448
8449 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8450 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8451 }
8452
8453 return ret_val;
8454}
8455#endif /* 0 */
8456
8457/******************************************************************************
8458 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8459 * register.
8460 *
8461 * hw - Struct containing variables accessed by shared code
8462 * offset - offset of word in the EEPROM to read
8463 * data - word read from the EEPROM
8464 * words - number of words to read
8465 *****************************************************************************/
8466static int32_t
8467e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8468 uint16_t *data)
8469{
8470 int32_t error = E1000_SUCCESS;
8471 uint32_t flash_bank = 0;
8472 uint32_t act_offset = 0;
8473 uint32_t bank_offset = 0;
8474 uint16_t word = 0;
8475 uint16_t i = 0;
8476
8477 /* We need to know which is the valid flash bank. In the event
8478 * that we didn't allocate eeprom_shadow_ram, we may not be
8479 * managing flash_bank. So it cannot be trusted and needs
8480 * to be updated with each read.
8481 */
8482 /* Value of bit 22 corresponds to the flash bank we're on. */
8483 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8484
8485 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8486 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8487
8488 error = e1000_get_software_flag(hw);
8489 if (error != E1000_SUCCESS)
8490 return error;
8491
8492 for (i = 0; i < words; i++) {
8493 if (hw->eeprom_shadow_ram != NULL &&
8494 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8495 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8496 } else {
8497 /* The NVM part needs a byte offset, hence * 2 */
8498 act_offset = bank_offset + ((offset + i) * 2);
8499 error = e1000_read_ich8_word(hw, act_offset, &word);
8500 if (error != E1000_SUCCESS)
8501 break;
8502 data[i] = word;
8503 }
8504 }
8505
8506 e1000_release_software_flag(hw);
8507
8508 return error;
8509}
8510
8511/******************************************************************************
8512 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8513 * register. Actually, writes are written to the shadow ram cache in the hw
8514 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8515 * the NVM, which occurs when the NVM checksum is updated.
8516 *
8517 * hw - Struct containing variables accessed by shared code
8518 * offset - offset of word in the EEPROM to write
8519 * words - number of words to write
8520 * data - words to write to the EEPROM
8521 *****************************************************************************/
8522static int32_t
8523e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8524 uint16_t *data)
8525{
8526 uint32_t i = 0;
8527 int32_t error = E1000_SUCCESS;
8528
8529 error = e1000_get_software_flag(hw);
8530 if (error != E1000_SUCCESS)
8531 return error;
8532
8533 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8534 * allocated. Subsequent reads to the modified words are read from
8535 * this cached structure as well. Writes will only go into this
8536 * cached structure unless it's followed by a call to
8537 * e1000_update_eeprom_checksum() where it will commit the changes
8538 * and clear the "modified" field.
8539 */
8540 if (hw->eeprom_shadow_ram != NULL) {
8541 for (i = 0; i < words; i++) {
8542 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8543 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8544 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8545 } else {
8546 error = -E1000_ERR_EEPROM;
8547 break;
8548 }
8549 }
8550 } else {
8551 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8552 * as they don't perform any NVM writes. An attempt in doing so
8553 * will result in this error.
8554 */
8555 error = -E1000_ERR_EEPROM;
8556 }
8557
8558 e1000_release_software_flag(hw);
8559
8560 return error;
8561}
8562
8563/******************************************************************************
8564 * This function does initial flash setup so that a new read/write/erase cycle
8565 * can be started.
8566 *
8567 * hw - The pointer to the hw structure
8568 ****************************************************************************/
8569static int32_t
8570e1000_ich8_cycle_init(struct e1000_hw *hw)
8571{
8572 union ich8_hws_flash_status hsfsts;
8573 int32_t error = E1000_ERR_EEPROM;
8574 int32_t i = 0;
8575
8576 DEBUGFUNC("e1000_ich8_cycle_init");
8577
8578 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8579
8580 /* May be check the Flash Des Valid bit in Hw status */
8581 if (hsfsts.hsf_status.fldesvalid == 0) {
8582 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8583 return error;
8584 }
8585
8586 /* Clear FCERR in Hw status by writing 1 */
8587 /* Clear DAEL in Hw status by writing a 1 */
8588 hsfsts.hsf_status.flcerr = 1;
8589 hsfsts.hsf_status.dael = 1;
8590
8591 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8592
8593 /* Either we should have a hardware SPI cycle in progress bit to check
8594 * against, in order to start a new cycle or FDONE bit should be changed
8595 * in the hardware so that it is 1 after harware reset, which can then be
8596 * used as an indication whether a cycle is in progress or has been
8597 * completed .. we should also have some software semaphore mechanism to
8598 * guard FDONE or the cycle in progress bit so that two threads access to
8599 * those bits can be sequentiallized or a way so that 2 threads dont
8600 * start the cycle at the same time */
8601
8602 if (hsfsts.hsf_status.flcinprog == 0) {
8603 /* There is no cycle running at present, so we can start a cycle */
8604 /* Begin by setting Flash Cycle Done. */
8605 hsfsts.hsf_status.flcdone = 1;
8606 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8607 error = E1000_SUCCESS;
8608 } else {
8609 /* otherwise poll for sometime so the current cycle has a chance
8610 * to end before giving up. */
8611 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8612 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8613 if (hsfsts.hsf_status.flcinprog == 0) {
8614 error = E1000_SUCCESS;
8615 break;
8616 }
8617 udelay(1);
8618 }
8619 if (error == E1000_SUCCESS) {
8620 /* Successful in waiting for previous cycle to timeout,
8621 * now set the Flash Cycle Done. */
8622 hsfsts.hsf_status.flcdone = 1;
8623 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8624 } else {
8625 DEBUGOUT("Flash controller busy, cannot get access");
8626 }
8627 }
8628 return error;
8629}
8630
8631/******************************************************************************
8632 * This function starts a flash cycle and waits for its completion
8633 *
8634 * hw - The pointer to the hw structure
8635 ****************************************************************************/
8636static int32_t
8637e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8638{
8639 union ich8_hws_flash_ctrl hsflctl;
8640 union ich8_hws_flash_status hsfsts;
8641 int32_t error = E1000_ERR_EEPROM;
8642 uint32_t i = 0;
8643
8644 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8645 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8646 hsflctl.hsf_ctrl.flcgo = 1;
8647 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8648
8649 /* wait till FDONE bit is set to 1 */
8650 do {
8651 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8652 if (hsfsts.hsf_status.flcdone == 1)
8653 break;
8654 udelay(1);
8655 i++;
8656 } while (i < timeout);
8657 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8658 error = E1000_SUCCESS;
8659 }
8660 return error;
8661}
8662
8663/******************************************************************************
8664 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8665 *
8666 * hw - The pointer to the hw structure
8667 * index - The index of the byte or word to read.
8668 * size - Size of data to read, 1=byte 2=word
8669 * data - Pointer to the word to store the value read.
8670 *****************************************************************************/
8671static int32_t
8672e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8673 uint32_t size, uint16_t* data)
8674{
8675 union ich8_hws_flash_status hsfsts;
8676 union ich8_hws_flash_ctrl hsflctl;
8677 uint32_t flash_linear_address;
8678 uint32_t flash_data = 0;
8679 int32_t error = -E1000_ERR_EEPROM;
8680 int32_t count = 0;
8681
8682 DEBUGFUNC("e1000_read_ich8_data");
8683
8684 if (size < 1 || size > 2 || data == 0x0 ||
8685 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8686 return error;
8687
8688 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8689 hw->flash_base_addr;
8690
8691 do {
8692 udelay(1);
8693 /* Steps */
8694 error = e1000_ich8_cycle_init(hw);
8695 if (error != E1000_SUCCESS)
8696 break;
8697
8698 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8699 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8700 hsflctl.hsf_ctrl.fldbcount = size - 1;
8701 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8702 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8703
8704 /* Write the last 24 bits of index into Flash Linear address field in
8705 * Flash Address */
8706 /* TODO: TBD maybe check the index against the size of flash */
8707
8708 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8709
8710 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8711
8712 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8713 * sequence a few more times, else read in (shift in) the Flash Data0,
8714 * the order is least significant byte first msb to lsb */
8715 if (error == E1000_SUCCESS) {
8716 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8717 if (size == 1) {
8718 *data = (uint8_t)(flash_data & 0x000000FF);
8719 } else if (size == 2) {
8720 *data = (uint16_t)(flash_data & 0x0000FFFF);
8721 }
8722 break;
8723 } else {
8724 /* If we've gotten here, then things are probably completely hosed,
8725 * but if the error condition is detected, it won't hurt to give
8726 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8727 */
8728 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8729 if (hsfsts.hsf_status.flcerr == 1) {
8730 /* Repeat for some time before giving up. */
8731 continue;
8732 } else if (hsfsts.hsf_status.flcdone == 0) {
8733 DEBUGOUT("Timeout error - flash cycle did not complete.");
8734 break;
8735 }
8736 }
8737 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8738
8739 return error;
8740}
8741
8742/******************************************************************************
8743 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8744 *
8745 * hw - The pointer to the hw structure
8746 * index - The index of the byte/word to read.
8747 * size - Size of data to read, 1=byte 2=word
8748 * data - The byte(s) to write to the NVM.
8749 *****************************************************************************/
8750static int32_t
8751e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8752 uint16_t data)
8753{
8754 union ich8_hws_flash_status hsfsts;
8755 union ich8_hws_flash_ctrl hsflctl;
8756 uint32_t flash_linear_address;
8757 uint32_t flash_data = 0;
8758 int32_t error = -E1000_ERR_EEPROM;
8759 int32_t count = 0;
8760
8761 DEBUGFUNC("e1000_write_ich8_data");
8762
8763 if (size < 1 || size > 2 || data > size * 0xff ||
8764 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8765 return error;
8766
8767 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8768 hw->flash_base_addr;
8769
8770 do {
8771 udelay(1);
8772 /* Steps */
8773 error = e1000_ich8_cycle_init(hw);
8774 if (error != E1000_SUCCESS)
8775 break;
8776
8777 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8778 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8779 hsflctl.hsf_ctrl.fldbcount = size -1;
8780 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8781 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8782
8783 /* Write the last 24 bits of index into Flash Linear address field in
8784 * Flash Address */
8785 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8786
8787 if (size == 1)
8788 flash_data = (uint32_t)data & 0x00FF;
8789 else
8790 flash_data = (uint32_t)data;
8791
8792 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8793
8794 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8795 * sequence a few more times else done */
8796 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8797 if (error == E1000_SUCCESS) {
8798 break;
8799 } else {
8800 /* If we're here, then things are most likely completely hosed,
8801 * but if the error condition is detected, it won't hurt to give
8802 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8803 */
8804 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8805 if (hsfsts.hsf_status.flcerr == 1) {
8806 /* Repeat for some time before giving up. */
8807 continue;
8808 } else if (hsfsts.hsf_status.flcdone == 0) {
8809 DEBUGOUT("Timeout error - flash cycle did not complete.");
8810 break;
8811 }
8812 }
8813 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8814
8815 return error;
8816}
8817
8818/******************************************************************************
8819 * Reads a single byte from the NVM using the ICH8 flash access registers.
8820 *
8821 * hw - pointer to e1000_hw structure
8822 * index - The index of the byte to read.
8823 * data - Pointer to a byte to store the value read.
8824 *****************************************************************************/
8825static int32_t
8826e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8827{
8828 int32_t status = E1000_SUCCESS;
8829 uint16_t word = 0;
8830
8831 status = e1000_read_ich8_data(hw, index, 1, &word);
8832 if (status == E1000_SUCCESS) {
8833 *data = (uint8_t)word;
8834 }
8835
8836 return status;
8837}
8838
8839/******************************************************************************
8840 * Writes a single byte to the NVM using the ICH8 flash access registers.
8841 * Performs verification by reading back the value and then going through
8842 * a retry algorithm before giving up.
8843 *
8844 * hw - pointer to e1000_hw structure
8845 * index - The index of the byte to write.
8846 * byte - The byte to write to the NVM.
8847 *****************************************************************************/
8848static int32_t
8849e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8850{
8851 int32_t error = E1000_SUCCESS;
8852 int32_t program_retries;
8853 uint8_t temp_byte;
8854
8855 e1000_write_ich8_byte(hw, index, byte);
8856 udelay(100);
8857
8858 for (program_retries = 0; program_retries < 100; program_retries++) {
8859 e1000_read_ich8_byte(hw, index, &temp_byte);
8860 if (temp_byte == byte)
8861 break;
8862 udelay(10);
8863 e1000_write_ich8_byte(hw, index, byte);
8864 udelay(100);
8865 }
8866 if (program_retries == 100)
8867 error = E1000_ERR_EEPROM;
8868
8869 return error;
8870}
8871
8872/******************************************************************************
8873 * Writes a single byte to the NVM using the ICH8 flash access registers.
8874 *
8875 * hw - pointer to e1000_hw structure
8876 * index - The index of the byte to read.
8877 * data - The byte to write to the NVM.
8878 *****************************************************************************/
8879static int32_t
8880e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8881{
8882 int32_t status = E1000_SUCCESS;
8883 uint16_t word = (uint16_t)data;
8884
8885 status = e1000_write_ich8_data(hw, index, 1, word);
8886
8887 return status;
8888}
8889
8890/******************************************************************************
8891 * Reads a word from the NVM using the ICH8 flash access registers.
8892 *
8893 * hw - pointer to e1000_hw structure
8894 * index - The starting byte index of the word to read.
8895 * data - Pointer to a word to store the value read.
8896 *****************************************************************************/
8897static int32_t
8898e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8899{
8900 int32_t status = E1000_SUCCESS;
8901 status = e1000_read_ich8_data(hw, index, 2, data);
8902 return status;
8903}
8904
8905/******************************************************************************
8906 * Writes a word to the NVM using the ICH8 flash access registers.
8907 *
8908 * hw - pointer to e1000_hw structure
8909 * index - The starting byte index of the word to read.
8910 * data - The word to write to the NVM.
8911 *****************************************************************************/
8912#if 0
8913int32_t
8914e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8915{
8916 int32_t status = E1000_SUCCESS;
8917 status = e1000_write_ich8_data(hw, index, 2, data);
8918 return status;
8919}
8920#endif /* 0 */
8921
8922/******************************************************************************
8923 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8924 * segment N is 4096 * N + flash_reg_addr.
8925 *
8926 * hw - pointer to e1000_hw structure
8927 * segment - 0 for first segment, 1 for second segment, etc.
8928 *****************************************************************************/
8929static int32_t
8930e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8931{
8932 union ich8_hws_flash_status hsfsts;
8933 union ich8_hws_flash_ctrl hsflctl;
8934 uint32_t flash_linear_address;
8935 int32_t count = 0;
8936 int32_t error = E1000_ERR_EEPROM;
8937 int32_t iteration, seg_size;
8938 int32_t sector_size;
8939 int32_t j = 0;
8940 int32_t error_flag = 0;
8941
8942 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8943
8944 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8945 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8946 * consecutive sectors. The start index for the nth Hw sector can be
8947 * calculated as = segment * 4096 + n * 256
8948 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8949 * The start index for the nth Hw sector can be calculated
8950 * as = segment * 4096
8951 * 10: Error condition
8952 * 11: The Hw sector size is much bigger than the size asked to
8953 * erase...error condition */
8954 if (hsfsts.hsf_status.berasesz == 0x0) {
8955 /* Hw sector size 256 */
8956 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8957 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8958 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8959 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8960 iteration = 1;
8961 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8962 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8963 iteration = 1;
8964 } else {
8965 return error;
8966 }
8967
8968 for (j = 0; j < iteration ; j++) {
8969 do {
8970 count++;
8971 /* Steps */
8972 error = e1000_ich8_cycle_init(hw);
8973 if (error != E1000_SUCCESS) {
8974 error_flag = 1;
8975 break;
8976 }
8977
8978 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8979 * Control */
8980 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8981 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8982 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8983
8984 /* Write the last 24 bits of an index within the block into Flash
8985 * Linear address field in Flash Address. This probably needs to
8986 * be calculated here based off the on-chip segment size and the
8987 * software segment size assumed (4K) */
8988 /* TBD */
8989 flash_linear_address = segment * sector_size + j * seg_size;
8990 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8991 flash_linear_address += hw->flash_base_addr;
8992
8993 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8994
8995 error = e1000_ich8_flash_cycle(hw, 1000000);
8996 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8997 * sequence a few more times else Done */
8998 if (error == E1000_SUCCESS) {
8999 break;
9000 } else {
9001 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
9002 if (hsfsts.hsf_status.flcerr == 1) {
9003 /* repeat for some time before giving up */
9004 continue;
9005 } else if (hsfsts.hsf_status.flcdone == 0) {
9006 error_flag = 1;
9007 break;
9008 }
9009 }
9010 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
9011 if (error_flag == 1)
9012 break;
9013 }
9014 if (error_flag != 1)
9015 error = E1000_SUCCESS;
9016 return error;
9017}
9018
9019/******************************************************************************
9020 *
9021 * Reverse duplex setting without breaking the link.
9022 *
9023 * hw: Struct containing variables accessed by shared code
9024 *
9025 *****************************************************************************/
9026#if 0
9027int32_t
9028e1000_duplex_reversal(struct e1000_hw *hw)
9029{
9030 int32_t ret_val;
9031 uint16_t phy_data;
9032
9033 if (hw->phy_type != e1000_phy_igp_3)
9034 return E1000_SUCCESS;
9035
9036 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
9037 if (ret_val)
9038 return ret_val;
9039
9040 phy_data ^= MII_CR_FULL_DUPLEX;
9041
9042 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9043 if (ret_val)
9044 return ret_val;
9045
9046 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9047 if (ret_val)
9048 return ret_val;
9049
9050 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9051 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9052
9053 return ret_val;
9054}
9055#endif /* 0 */
9056
9057static int32_t
9058e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9059 uint32_t cnf_base_addr, uint32_t cnf_size)
9060{
9061 uint32_t ret_val = E1000_SUCCESS;
9062 uint16_t word_addr, reg_data, reg_addr;
9063 uint16_t i;
9064
9065 /* cnf_base_addr is in DWORD */
9066 word_addr = (uint16_t)(cnf_base_addr << 1);
9067
9068 /* cnf_size is returned in size of dwords */
9069 for (i = 0; i < cnf_size; i++) {
9070 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9071 if (ret_val)
9072 return ret_val;
9073
9074 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9075 if (ret_val)
9076 return ret_val;
9077
9078 ret_val = e1000_get_software_flag(hw);
9079 if (ret_val != E1000_SUCCESS)
9080 return ret_val;
9081
9082 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9083
9084 e1000_release_software_flag(hw);
9085 }
9086
9087 return ret_val;
9088}
9089
9090
9091static int32_t
9092e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9093{
9094 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9095
9096 if (hw->phy_type != e1000_phy_igp_3)
9097 return E1000_SUCCESS;
9098
9099 /* Check if SW needs configure the PHY */
9100 reg_data = E1000_READ_REG(hw, FEXTNVM);
9101 if (!(reg_data & FEXTNVM_SW_CONFIG))
9102 return E1000_SUCCESS;
9103
9104 /* Wait for basic configuration completes before proceeding*/
9105 loop = 0;
9106 do {
9107 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9108 udelay(100);
9109 loop++;
9110 } while ((!reg_data) && (loop < 50));
9111
9112 /* Clear the Init Done bit for the next init event */
9113 reg_data = E1000_READ_REG(hw, STATUS);
9114 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9115 E1000_WRITE_REG(hw, STATUS, reg_data);
9116
9117 /* Make sure HW does not configure LCD from PHY extended configuration
9118 before SW configuration */
9119 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9120 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9121 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9122 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9123 cnf_size >>= 16;
9124 if (cnf_size) {
9125 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9126 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9127 /* cnf_base_addr is in DWORD */
9128 cnf_base_addr >>= 16;
9129
9130 /* Configure LCD from extended configuration region. */
9131 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9132 cnf_size);
9133 if (ret_val)
9134 return ret_val;
9135 }
9136 }
9137
9138 return E1000_SUCCESS;
9139}
9140
9141
7559 9142
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 18:34:41 -0500