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path: root/drivers/net/e1000/e1000_hw.c
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c1772
1 files changed, 1657 insertions, 115 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 3959039b16ec..583518ae49ce 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -101,7 +101,8 @@ static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 101
102#define E1000_WRITE_REG_IO(a, reg, val) \ 102#define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val) 103 e1000_write_reg_io((a), E1000_##reg, val)
104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw); 104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
105 uint16_t duplex);
105static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 106static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
106 107
107/* IGP cable length table */ 108/* IGP cable length table */
@@ -156,6 +157,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
156 hw->phy_type = e1000_phy_igp; 157 hw->phy_type = e1000_phy_igp;
157 break; 158 break;
158 } 159 }
160 case IGP03E1000_E_PHY_ID:
161 hw->phy_type = e1000_phy_igp_3;
162 break;
163 case IFE_E_PHY_ID:
164 case IFE_PLUS_E_PHY_ID:
165 case IFE_C_E_PHY_ID:
166 hw->phy_type = e1000_phy_ife;
167 break;
159 case GG82563_E_PHY_ID: 168 case GG82563_E_PHY_ID:
160 if (hw->mac_type == e1000_80003es2lan) { 169 if (hw->mac_type == e1000_80003es2lan) {
161 hw->phy_type = e1000_phy_gg82563; 170 hw->phy_type = e1000_phy_gg82563;
@@ -332,6 +341,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
332 break; 341 break;
333 case E1000_DEV_ID_82541EI: 342 case E1000_DEV_ID_82541EI:
334 case E1000_DEV_ID_82541EI_MOBILE: 343 case E1000_DEV_ID_82541EI_MOBILE:
344 case E1000_DEV_ID_82541ER_LOM:
335 hw->mac_type = e1000_82541; 345 hw->mac_type = e1000_82541;
336 break; 346 break;
337 case E1000_DEV_ID_82541ER: 347 case E1000_DEV_ID_82541ER:
@@ -341,6 +351,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
341 hw->mac_type = e1000_82541_rev_2; 351 hw->mac_type = e1000_82541_rev_2;
342 break; 352 break;
343 case E1000_DEV_ID_82547EI: 353 case E1000_DEV_ID_82547EI:
354 case E1000_DEV_ID_82547EI_MOBILE:
344 hw->mac_type = e1000_82547; 355 hw->mac_type = e1000_82547;
345 break; 356 break;
346 case E1000_DEV_ID_82547GI: 357 case E1000_DEV_ID_82547GI:
@@ -354,6 +365,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
354 case E1000_DEV_ID_82572EI_COPPER: 365 case E1000_DEV_ID_82572EI_COPPER:
355 case E1000_DEV_ID_82572EI_FIBER: 366 case E1000_DEV_ID_82572EI_FIBER:
356 case E1000_DEV_ID_82572EI_SERDES: 367 case E1000_DEV_ID_82572EI_SERDES:
368 case E1000_DEV_ID_82572EI:
357 hw->mac_type = e1000_82572; 369 hw->mac_type = e1000_82572;
358 break; 370 break;
359 case E1000_DEV_ID_82573E: 371 case E1000_DEV_ID_82573E:
@@ -361,16 +373,29 @@ e1000_set_mac_type(struct e1000_hw *hw)
361 case E1000_DEV_ID_82573L: 373 case E1000_DEV_ID_82573L:
362 hw->mac_type = e1000_82573; 374 hw->mac_type = e1000_82573;
363 break; 375 break;
376 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
377 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
364 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 378 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
365 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 379 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
366 hw->mac_type = e1000_80003es2lan; 380 hw->mac_type = e1000_80003es2lan;
367 break; 381 break;
382 case E1000_DEV_ID_ICH8_IGP_M_AMT:
383 case E1000_DEV_ID_ICH8_IGP_AMT:
384 case E1000_DEV_ID_ICH8_IGP_C:
385 case E1000_DEV_ID_ICH8_IFE:
386 case E1000_DEV_ID_ICH8_IGP_M:
387 hw->mac_type = e1000_ich8lan;
388 break;
368 default: 389 default:
369 /* Should never have loaded on this device */ 390 /* Should never have loaded on this device */
370 return -E1000_ERR_MAC_TYPE; 391 return -E1000_ERR_MAC_TYPE;
371 } 392 }
372 393
373 switch(hw->mac_type) { 394 switch(hw->mac_type) {
395 case e1000_ich8lan:
396 hw->swfwhw_semaphore_present = TRUE;
397 hw->asf_firmware_present = TRUE;
398 break;
374 case e1000_80003es2lan: 399 case e1000_80003es2lan:
375 hw->swfw_sync_present = TRUE; 400 hw->swfw_sync_present = TRUE;
376 /* fall through */ 401 /* fall through */
@@ -423,6 +448,7 @@ e1000_set_media_type(struct e1000_hw *hw)
423 case e1000_82542_rev2_1: 448 case e1000_82542_rev2_1:
424 hw->media_type = e1000_media_type_fiber; 449 hw->media_type = e1000_media_type_fiber;
425 break; 450 break;
451 case e1000_ich8lan:
426 case e1000_82573: 452 case e1000_82573:
427 /* The STATUS_TBIMODE bit is reserved or reused for the this 453 /* The STATUS_TBIMODE bit is reserved or reused for the this
428 * device. 454 * device.
@@ -527,6 +553,14 @@ e1000_reset_hw(struct e1000_hw *hw)
527 } while(timeout); 553 } while(timeout);
528 } 554 }
529 555
556 /* Workaround for ICH8 bit corruption issue in FIFO memory */
557 if (hw->mac_type == e1000_ich8lan) {
558 /* Set Tx and Rx buffer allocation to 8k apiece. */
559 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
560 /* Set Packet Buffer Size to 16k. */
561 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
562 }
563
530 /* Issue a global reset to the MAC. This will reset the chip's 564 /* Issue a global reset to the MAC. This will reset the chip's
531 * transmit, receive, DMA, and link units. It will not effect 565 * transmit, receive, DMA, and link units. It will not effect
532 * the current PCI configuration. The global reset bit is self- 566 * the current PCI configuration. The global reset bit is self-
@@ -550,6 +584,20 @@ e1000_reset_hw(struct e1000_hw *hw)
550 /* Reset is performed on a shadow of the control register */ 584 /* Reset is performed on a shadow of the control register */
551 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 585 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
552 break; 586 break;
587 case e1000_ich8lan:
588 if (!hw->phy_reset_disable &&
589 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
590 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
591 * at the same time to make sure the interface between
592 * MAC and the external PHY is reset.
593 */
594 ctrl |= E1000_CTRL_PHY_RST;
595 }
596
597 e1000_get_software_flag(hw);
598 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
599 msec_delay(5);
600 break;
553 default: 601 default:
554 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 602 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
555 break; 603 break;
@@ -591,6 +639,7 @@ e1000_reset_hw(struct e1000_hw *hw)
591 /* fall through */ 639 /* fall through */
592 case e1000_82571: 640 case e1000_82571:
593 case e1000_82572: 641 case e1000_82572:
642 case e1000_ich8lan:
594 case e1000_80003es2lan: 643 case e1000_80003es2lan:
595 ret_val = e1000_get_auto_rd_done(hw); 644 ret_val = e1000_get_auto_rd_done(hw);
596 if(ret_val) 645 if(ret_val)
@@ -633,6 +682,12 @@ e1000_reset_hw(struct e1000_hw *hw)
633 e1000_pci_set_mwi(hw); 682 e1000_pci_set_mwi(hw);
634 } 683 }
635 684
685 if (hw->mac_type == e1000_ich8lan) {
686 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
687 kab |= E1000_KABGTXD_BGSQLBIAS;
688 E1000_WRITE_REG(hw, KABGTXD, kab);
689 }
690
636 return E1000_SUCCESS; 691 return E1000_SUCCESS;
637} 692}
638 693
@@ -675,9 +730,12 @@ e1000_init_hw(struct e1000_hw *hw)
675 730
676 /* Disabling VLAN filtering. */ 731 /* Disabling VLAN filtering. */
677 DEBUGOUT("Initializing the IEEE VLAN\n"); 732 DEBUGOUT("Initializing the IEEE VLAN\n");
678 if (hw->mac_type < e1000_82545_rev_3) 733 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
679 E1000_WRITE_REG(hw, VET, 0); 734 if (hw->mac_type != e1000_ich8lan) {
680 e1000_clear_vfta(hw); 735 if (hw->mac_type < e1000_82545_rev_3)
736 E1000_WRITE_REG(hw, VET, 0);
737 e1000_clear_vfta(hw);
738 }
681 739
682 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 740 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
683 if(hw->mac_type == e1000_82542_rev2_0) { 741 if(hw->mac_type == e1000_82542_rev2_0) {
@@ -705,8 +763,14 @@ e1000_init_hw(struct e1000_hw *hw)
705 /* Zero out the Multicast HASH table */ 763 /* Zero out the Multicast HASH table */
706 DEBUGOUT("Zeroing the MTA\n"); 764 DEBUGOUT("Zeroing the MTA\n");
707 mta_size = E1000_MC_TBL_SIZE; 765 mta_size = E1000_MC_TBL_SIZE;
708 for(i = 0; i < mta_size; i++) 766 if (hw->mac_type == e1000_ich8lan)
767 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
768 for(i = 0; i < mta_size; i++) {
709 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 769 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
770 /* use write flush to prevent Memory Write Block (MWB) from
771 * occuring when accessing our register space */
772 E1000_WRITE_FLUSH(hw);
773 }
710 774
711 /* Set the PCI priority bit correctly in the CTRL register. This 775 /* Set the PCI priority bit correctly in the CTRL register. This
712 * determines if the adapter gives priority to receives, or if it 776 * determines if the adapter gives priority to receives, or if it
@@ -744,6 +808,10 @@ e1000_init_hw(struct e1000_hw *hw)
744 break; 808 break;
745 } 809 }
746 810
811 /* More time needed for PHY to initialize */
812 if (hw->mac_type == e1000_ich8lan)
813 msec_delay(15);
814
747 /* Call a subroutine to configure the link and setup flow control. */ 815 /* Call a subroutine to configure the link and setup flow control. */
748 ret_val = e1000_setup_link(hw); 816 ret_val = e1000_setup_link(hw);
749 817
@@ -757,6 +825,7 @@ e1000_init_hw(struct e1000_hw *hw)
757 case e1000_82571: 825 case e1000_82571:
758 case e1000_82572: 826 case e1000_82572:
759 case e1000_82573: 827 case e1000_82573:
828 case e1000_ich8lan:
760 case e1000_80003es2lan: 829 case e1000_80003es2lan:
761 ctrl |= E1000_TXDCTL_COUNT_DESC; 830 ctrl |= E1000_TXDCTL_COUNT_DESC;
762 break; 831 break;
@@ -795,6 +864,7 @@ e1000_init_hw(struct e1000_hw *hw)
795 /* Fall through */ 864 /* Fall through */
796 case e1000_82571: 865 case e1000_82571:
797 case e1000_82572: 866 case e1000_82572:
867 case e1000_ich8lan:
798 ctrl = E1000_READ_REG(hw, TXDCTL1); 868 ctrl = E1000_READ_REG(hw, TXDCTL1);
799 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 869 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
800 if(hw->mac_type >= e1000_82571) 870 if(hw->mac_type >= e1000_82571)
@@ -818,6 +888,11 @@ e1000_init_hw(struct e1000_hw *hw)
818 */ 888 */
819 e1000_clear_hw_cntrs(hw); 889 e1000_clear_hw_cntrs(hw);
820 890
891 /* ICH8 No-snoop bits are opposite polarity.
892 * Set to snoop by default after reset. */
893 if (hw->mac_type == e1000_ich8lan)
894 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
895
821 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 896 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
822 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 897 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
823 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 898 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
@@ -905,6 +980,7 @@ e1000_setup_link(struct e1000_hw *hw)
905 */ 980 */
906 if (hw->fc == e1000_fc_default) { 981 if (hw->fc == e1000_fc_default) {
907 switch (hw->mac_type) { 982 switch (hw->mac_type) {
983 case e1000_ich8lan:
908 case e1000_82573: 984 case e1000_82573:
909 hw->fc = e1000_fc_full; 985 hw->fc = e1000_fc_full;
910 break; 986 break;
@@ -971,9 +1047,12 @@ e1000_setup_link(struct e1000_hw *hw)
971 */ 1047 */
972 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1048 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
973 1049
974 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1050 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
975 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1051 if (hw->mac_type != e1000_ich8lan) {
976 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1052 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1053 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1054 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1055 }
977 1056
978 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1057 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
979 1058
@@ -1237,12 +1316,13 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1237 1316
1238 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1317 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1239 msec_delay(15); 1318 msec_delay(15);
1240 1319 if (hw->mac_type != e1000_ich8lan) {
1241 /* Configure activity LED after PHY reset */ 1320 /* Configure activity LED after PHY reset */
1242 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1321 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1243 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1322 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1244 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1323 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1245 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1324 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1325 }
1246 1326
1247 /* disable lplu d3 during driver init */ 1327 /* disable lplu d3 during driver init */
1248 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1328 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
@@ -1478,8 +1558,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1478 if (ret_val) 1558 if (ret_val)
1479 return ret_val; 1559 return ret_val;
1480 1560
1481 /* Enable Pass False Carrier on the PHY */ 1561 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1482 phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1483 1562
1484 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1563 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1485 phy_data); 1564 phy_data);
@@ -1561,28 +1640,40 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1561 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1640 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1562 if(hw->disable_polarity_correction == 1) 1641 if(hw->disable_polarity_correction == 1)
1563 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1642 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1564 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1643 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1565 if(ret_val) 1644 if (ret_val)
1566 return ret_val;
1567
1568 /* Force TX_CLK in the Extended PHY Specific Control Register
1569 * to 25MHz clock.
1570 */
1571 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1572 if(ret_val)
1573 return ret_val; 1645 return ret_val;
1574 1646
1575 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1576
1577 if (hw->phy_revision < M88E1011_I_REV_4) { 1647 if (hw->phy_revision < M88E1011_I_REV_4) {
1578 /* Configure Master and Slave downshift values */ 1648 /* Force TX_CLK in the Extended PHY Specific Control Register
1579 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1649 * to 25MHz clock.
1650 */
1651 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1652 if (ret_val)
1653 return ret_val;
1654
1655 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1656
1657 if ((hw->phy_revision == E1000_REVISION_2) &&
1658 (hw->phy_id == M88E1111_I_PHY_ID)) {
1659 /* Vidalia Phy, set the downshift counter to 5x */
1660 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1661 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1662 ret_val = e1000_write_phy_reg(hw,
1663 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1664 if (ret_val)
1665 return ret_val;
1666 } else {
1667 /* Configure Master and Slave downshift values */
1668 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1580 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1669 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1581 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1670 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1582 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1671 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1583 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1672 ret_val = e1000_write_phy_reg(hw,
1584 if(ret_val) 1673 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1585 return ret_val; 1674 if (ret_val)
1675 return ret_val;
1676 }
1586 } 1677 }
1587 1678
1588 /* SW Reset the PHY so all changes take effect */ 1679 /* SW Reset the PHY so all changes take effect */
@@ -1620,6 +1711,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1620 if(hw->autoneg_advertised == 0) 1711 if(hw->autoneg_advertised == 0)
1621 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1712 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1622 1713
1714 /* IFE phy only supports 10/100 */
1715 if (hw->phy_type == e1000_phy_ife)
1716 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1717
1623 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1718 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1624 ret_val = e1000_phy_setup_autoneg(hw); 1719 ret_val = e1000_phy_setup_autoneg(hw);
1625 if(ret_val) { 1720 if(ret_val) {
@@ -1717,6 +1812,26 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1717 1812
1718 DEBUGFUNC("e1000_setup_copper_link"); 1813 DEBUGFUNC("e1000_setup_copper_link");
1719 1814
1815 switch (hw->mac_type) {
1816 case e1000_80003es2lan:
1817 case e1000_ich8lan:
1818 /* Set the mac to wait the maximum time between each
1819 * iteration and increase the max iterations when
1820 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1821 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1822 if (ret_val)
1823 return ret_val;
1824 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1825 if (ret_val)
1826 return ret_val;
1827 reg_data |= 0x3F;
1828 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1829 if (ret_val)
1830 return ret_val;
1831 default:
1832 break;
1833 }
1834
1720 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1835 /* Check if it is a valid PHY and set PHY mode if necessary. */
1721 ret_val = e1000_copper_link_preconfig(hw); 1836 ret_val = e1000_copper_link_preconfig(hw);
1722 if(ret_val) 1837 if(ret_val)
@@ -1724,10 +1839,8 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1724 1839
1725 switch (hw->mac_type) { 1840 switch (hw->mac_type) {
1726 case e1000_80003es2lan: 1841 case e1000_80003es2lan:
1727 ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1842 /* Kumeran registers are written-only */
1728 &reg_data); 1843 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1729 if (ret_val)
1730 return ret_val;
1731 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 1844 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1732 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1845 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1733 reg_data); 1846 reg_data);
@@ -1739,6 +1852,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1739 } 1852 }
1740 1853
1741 if (hw->phy_type == e1000_phy_igp || 1854 if (hw->phy_type == e1000_phy_igp ||
1855 hw->phy_type == e1000_phy_igp_3 ||
1742 hw->phy_type == e1000_phy_igp_2) { 1856 hw->phy_type == e1000_phy_igp_2) {
1743 ret_val = e1000_copper_link_igp_setup(hw); 1857 ret_val = e1000_copper_link_igp_setup(hw);
1744 if(ret_val) 1858 if(ret_val)
@@ -1803,7 +1917,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1803* hw - Struct containing variables accessed by shared code 1917* hw - Struct containing variables accessed by shared code
1804******************************************************************************/ 1918******************************************************************************/
1805static int32_t 1919static int32_t
1806e1000_configure_kmrn_for_10_100(struct e1000_hw *hw) 1920e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1807{ 1921{
1808 int32_t ret_val = E1000_SUCCESS; 1922 int32_t ret_val = E1000_SUCCESS;
1809 uint32_t tipg; 1923 uint32_t tipg;
@@ -1823,6 +1937,18 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw)
1823 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 1937 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1824 E1000_WRITE_REG(hw, TIPG, tipg); 1938 E1000_WRITE_REG(hw, TIPG, tipg);
1825 1939
1940 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1941
1942 if (ret_val)
1943 return ret_val;
1944
1945 if (duplex == HALF_DUPLEX)
1946 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1947 else
1948 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1949
1950 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1951
1826 return ret_val; 1952 return ret_val;
1827} 1953}
1828 1954
@@ -1847,6 +1973,14 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1847 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1973 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1848 E1000_WRITE_REG(hw, TIPG, tipg); 1974 E1000_WRITE_REG(hw, TIPG, tipg);
1849 1975
1976 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1977
1978 if (ret_val)
1979 return ret_val;
1980
1981 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1982 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1983
1850 return ret_val; 1984 return ret_val;
1851} 1985}
1852 1986
@@ -1869,10 +2003,13 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1869 if(ret_val) 2003 if(ret_val)
1870 return ret_val; 2004 return ret_val;
1871 2005
1872 /* Read the MII 1000Base-T Control Register (Address 9). */ 2006 if (hw->phy_type != e1000_phy_ife) {
1873 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 2007 /* Read the MII 1000Base-T Control Register (Address 9). */
1874 if(ret_val) 2008 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1875 return ret_val; 2009 if (ret_val)
2010 return ret_val;
2011 } else
2012 mii_1000t_ctrl_reg=0;
1876 2013
1877 /* Need to parse both autoneg_advertised and fc and set up 2014 /* Need to parse both autoneg_advertised and fc and set up
1878 * the appropriate PHY registers. First we will parse for 2015 * the appropriate PHY registers. First we will parse for
@@ -1923,6 +2060,9 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1923 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2060 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1924 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2061 DEBUGOUT("Advertise 1000mb Full duplex\n");
1925 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2062 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2063 if (hw->phy_type == e1000_phy_ife) {
2064 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2065 }
1926 } 2066 }
1927 2067
1928 /* Check for a software override of the flow control settings, and 2068 /* Check for a software override of the flow control settings, and
@@ -1984,9 +2124,11 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1984 2124
1985 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2125 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1986 2126
1987 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 2127 if (hw->phy_type != e1000_phy_ife) {
1988 if(ret_val) 2128 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1989 return ret_val; 2129 if (ret_val)
2130 return ret_val;
2131 }
1990 2132
1991 return E1000_SUCCESS; 2133 return E1000_SUCCESS;
1992} 2134}
@@ -2089,6 +2231,18 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2089 2231
2090 /* Need to reset the PHY or these changes will be ignored */ 2232 /* Need to reset the PHY or these changes will be ignored */
2091 mii_ctrl_reg |= MII_CR_RESET; 2233 mii_ctrl_reg |= MII_CR_RESET;
2234 /* Disable MDI-X support for 10/100 */
2235 } else if (hw->phy_type == e1000_phy_ife) {
2236 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2237 if (ret_val)
2238 return ret_val;
2239
2240 phy_data &= ~IFE_PMC_AUTO_MDIX;
2241 phy_data &= ~IFE_PMC_FORCE_MDIX;
2242
2243 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2244 if (ret_val)
2245 return ret_val;
2092 } else { 2246 } else {
2093 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2247 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2094 * forced whenever speed or duplex are forced. 2248 * forced whenever speed or duplex are forced.
@@ -2721,8 +2875,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2721 */ 2875 */
2722 if(hw->tbi_compatibility_en) { 2876 if(hw->tbi_compatibility_en) {
2723 uint16_t speed, duplex; 2877 uint16_t speed, duplex;
2724 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2878 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2725 if(speed != SPEED_1000) { 2879 if (ret_val) {
2880 DEBUGOUT("Error getting link speed and duplex\n");
2881 return ret_val;
2882 }
2883 if (speed != SPEED_1000) {
2726 /* If link speed is not set to gigabit speed, we do not need 2884 /* If link speed is not set to gigabit speed, we do not need
2727 * to enable TBI compatibility. 2885 * to enable TBI compatibility.
2728 */ 2886 */
@@ -2889,7 +3047,13 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2889 if (*speed == SPEED_1000) 3047 if (*speed == SPEED_1000)
2890 ret_val = e1000_configure_kmrn_for_1000(hw); 3048 ret_val = e1000_configure_kmrn_for_1000(hw);
2891 else 3049 else
2892 ret_val = e1000_configure_kmrn_for_10_100(hw); 3050 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3051 if (ret_val)
3052 return ret_val;
3053 }
3054
3055 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3056 ret_val = e1000_kumeran_lock_loss_workaround(hw);
2893 if (ret_val) 3057 if (ret_val)
2894 return ret_val; 3058 return ret_val;
2895 } 3059 }
@@ -3079,6 +3243,9 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3079 3243
3080 DEBUGFUNC("e1000_swfw_sync_acquire"); 3244 DEBUGFUNC("e1000_swfw_sync_acquire");
3081 3245
3246 if (hw->swfwhw_semaphore_present)
3247 return e1000_get_software_flag(hw);
3248
3082 if (!hw->swfw_sync_present) 3249 if (!hw->swfw_sync_present)
3083 return e1000_get_hw_eeprom_semaphore(hw); 3250 return e1000_get_hw_eeprom_semaphore(hw);
3084 3251
@@ -3118,6 +3285,11 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3118 3285
3119 DEBUGFUNC("e1000_swfw_sync_release"); 3286 DEBUGFUNC("e1000_swfw_sync_release");
3120 3287
3288 if (hw->swfwhw_semaphore_present) {
3289 e1000_release_software_flag(hw);
3290 return;
3291 }
3292
3121 if (!hw->swfw_sync_present) { 3293 if (!hw->swfw_sync_present) {
3122 e1000_put_hw_eeprom_semaphore(hw); 3294 e1000_put_hw_eeprom_semaphore(hw);
3123 return; 3295 return;
@@ -3160,7 +3332,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3160 if (e1000_swfw_sync_acquire(hw, swfw)) 3332 if (e1000_swfw_sync_acquire(hw, swfw))
3161 return -E1000_ERR_SWFW_SYNC; 3333 return -E1000_ERR_SWFW_SYNC;
3162 3334
3163 if((hw->phy_type == e1000_phy_igp || 3335 if ((hw->phy_type == e1000_phy_igp ||
3336 hw->phy_type == e1000_phy_igp_3 ||
3164 hw->phy_type == e1000_phy_igp_2) && 3337 hw->phy_type == e1000_phy_igp_2) &&
3165 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3338 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3166 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3339 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3299,7 +3472,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3299 if (e1000_swfw_sync_acquire(hw, swfw)) 3472 if (e1000_swfw_sync_acquire(hw, swfw))
3300 return -E1000_ERR_SWFW_SYNC; 3473 return -E1000_ERR_SWFW_SYNC;
3301 3474
3302 if((hw->phy_type == e1000_phy_igp || 3475 if ((hw->phy_type == e1000_phy_igp ||
3476 hw->phy_type == e1000_phy_igp_3 ||
3303 hw->phy_type == e1000_phy_igp_2) && 3477 hw->phy_type == e1000_phy_igp_2) &&
3304 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3478 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3305 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3479 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3514,7 +3688,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3514 E1000_WRITE_FLUSH(hw); 3688 E1000_WRITE_FLUSH(hw);
3515 3689
3516 if (hw->mac_type >= e1000_82571) 3690 if (hw->mac_type >= e1000_82571)
3517 msec_delay(10); 3691 msec_delay_irq(10);
3518 e1000_swfw_sync_release(hw, swfw); 3692 e1000_swfw_sync_release(hw, swfw);
3519 } else { 3693 } else {
3520 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3694 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3544,6 +3718,12 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3544 ret_val = e1000_get_phy_cfg_done(hw); 3718 ret_val = e1000_get_phy_cfg_done(hw);
3545 e1000_release_software_semaphore(hw); 3719 e1000_release_software_semaphore(hw);
3546 3720
3721 if ((hw->mac_type == e1000_ich8lan) &&
3722 (hw->phy_type == e1000_phy_igp_3)) {
3723 ret_val = e1000_init_lcd_from_nvm(hw);
3724 if (ret_val)
3725 return ret_val;
3726 }
3547 return ret_val; 3727 return ret_val;
3548} 3728}
3549 3729
@@ -3572,9 +3752,11 @@ e1000_phy_reset(struct e1000_hw *hw)
3572 case e1000_82541_rev_2: 3752 case e1000_82541_rev_2:
3573 case e1000_82571: 3753 case e1000_82571:
3574 case e1000_82572: 3754 case e1000_82572:
3755 case e1000_ich8lan:
3575 ret_val = e1000_phy_hw_reset(hw); 3756 ret_val = e1000_phy_hw_reset(hw);
3576 if(ret_val) 3757 if(ret_val)
3577 return ret_val; 3758 return ret_val;
3759
3578 break; 3760 break;
3579 default: 3761 default:
3580 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3762 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
@@ -3597,11 +3779,120 @@ e1000_phy_reset(struct e1000_hw *hw)
3597} 3779}
3598 3780
3599/****************************************************************************** 3781/******************************************************************************
3782* Work-around for 82566 power-down: on D3 entry-
3783* 1) disable gigabit link
3784* 2) write VR power-down enable
3785* 3) read it back
3786* if successful continue, else issue LCD reset and repeat
3787*
3788* hw - struct containing variables accessed by shared code
3789******************************************************************************/
3790void
3791e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3792{
3793 int32_t reg;
3794 uint16_t phy_data;
3795 int32_t retry = 0;
3796
3797 DEBUGFUNC("e1000_phy_powerdown_workaround");
3798
3799 if (hw->phy_type != e1000_phy_igp_3)
3800 return;
3801
3802 do {
3803 /* Disable link */
3804 reg = E1000_READ_REG(hw, PHY_CTRL);
3805 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3806 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3807
3808 /* Write VR power-down enable */
3809 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3810 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3811 IGP3_VR_CTRL_MODE_SHUT);
3812
3813 /* Read it back and test */
3814 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3815 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3816 break;
3817
3818 /* Issue PHY reset and repeat at most one more time */
3819 reg = E1000_READ_REG(hw, CTRL);
3820 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3821 retry++;
3822 } while (retry);
3823
3824 return;
3825
3826}
3827
3828/******************************************************************************
3829* Work-around for 82566 Kumeran PCS lock loss:
3830* On link status change (i.e. PCI reset, speed change) and link is up and
3831* speed is gigabit-
3832* 0) if workaround is optionally disabled do nothing
3833* 1) wait 1ms for Kumeran link to come up
3834* 2) check Kumeran Diagnostic register PCS lock loss bit
3835* 3) if not set the link is locked (all is good), otherwise...
3836* 4) reset the PHY
3837* 5) repeat up to 10 times
3838* Note: this is only called for IGP3 copper when speed is 1gb.
3839*
3840* hw - struct containing variables accessed by shared code
3841******************************************************************************/
3842int32_t
3843e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3844{
3845 int32_t ret_val;
3846 int32_t reg;
3847 int32_t cnt;
3848 uint16_t phy_data;
3849
3850 if (hw->kmrn_lock_loss_workaround_disabled)
3851 return E1000_SUCCESS;
3852
3853 /* Make sure link is up before proceeding. If not just return.
3854 * Attempting this while link is negotiating fouls up link
3855 * stability */
3856 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3857 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3858
3859 if (phy_data & MII_SR_LINK_STATUS) {
3860 for (cnt = 0; cnt < 10; cnt++) {
3861 /* read once to clear */
3862 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3863 if (ret_val)
3864 return ret_val;
3865 /* and again to get new status */
3866 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3867 if (ret_val)
3868 return ret_val;
3869
3870 /* check for PCS lock */
3871 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3872 return E1000_SUCCESS;
3873
3874 /* Issue PHY reset */
3875 e1000_phy_hw_reset(hw);
3876 msec_delay_irq(5);
3877 }
3878 /* Disable GigE link negotiation */
3879 reg = E1000_READ_REG(hw, PHY_CTRL);
3880 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3881 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3882
3883 /* unable to acquire PCS lock */
3884 return E1000_ERR_PHY;
3885 }
3886
3887 return E1000_SUCCESS;
3888}
3889
3890/******************************************************************************
3600* Probes the expected PHY address for known PHY IDs 3891* Probes the expected PHY address for known PHY IDs
3601* 3892*
3602* hw - Struct containing variables accessed by shared code 3893* hw - Struct containing variables accessed by shared code
3603******************************************************************************/ 3894******************************************************************************/
3604static int32_t 3895int32_t
3605e1000_detect_gig_phy(struct e1000_hw *hw) 3896e1000_detect_gig_phy(struct e1000_hw *hw)
3606{ 3897{
3607 int32_t phy_init_status, ret_val; 3898 int32_t phy_init_status, ret_val;
@@ -3613,8 +3904,8 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3613 /* The 82571 firmware may still be configuring the PHY. In this 3904 /* The 82571 firmware may still be configuring the PHY. In this
3614 * case, we cannot access the PHY until the configuration is done. So 3905 * case, we cannot access the PHY until the configuration is done. So
3615 * we explicitly set the PHY values. */ 3906 * we explicitly set the PHY values. */
3616 if(hw->mac_type == e1000_82571 || 3907 if (hw->mac_type == e1000_82571 ||
3617 hw->mac_type == e1000_82572) { 3908 hw->mac_type == e1000_82572) {
3618 hw->phy_id = IGP01E1000_I_PHY_ID; 3909 hw->phy_id = IGP01E1000_I_PHY_ID;
3619 hw->phy_type = e1000_phy_igp_2; 3910 hw->phy_type = e1000_phy_igp_2;
3620 return E1000_SUCCESS; 3911 return E1000_SUCCESS;
@@ -3631,7 +3922,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3631 3922
3632 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3923 /* Read the PHY ID Registers to identify which PHY is onboard. */
3633 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3924 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3634 if(ret_val) 3925 if (ret_val)
3635 return ret_val; 3926 return ret_val;
3636 3927
3637 hw->phy_id = (uint32_t) (phy_id_high << 16); 3928 hw->phy_id = (uint32_t) (phy_id_high << 16);
@@ -3669,6 +3960,12 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3669 case e1000_80003es2lan: 3960 case e1000_80003es2lan:
3670 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 3961 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3671 break; 3962 break;
3963 case e1000_ich8lan:
3964 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
3965 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
3966 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
3967 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
3968 break;
3672 default: 3969 default:
3673 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3970 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3674 return -E1000_ERR_CONFIG; 3971 return -E1000_ERR_CONFIG;
@@ -3784,6 +4081,53 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
3784} 4081}
3785 4082
3786/****************************************************************************** 4083/******************************************************************************
4084* Get PHY information from various PHY registers for ife PHY only.
4085*
4086* hw - Struct containing variables accessed by shared code
4087* phy_info - PHY information structure
4088******************************************************************************/
4089int32_t
4090e1000_phy_ife_get_info(struct e1000_hw *hw,
4091 struct e1000_phy_info *phy_info)
4092{
4093 int32_t ret_val;
4094 uint16_t phy_data, polarity;
4095
4096 DEBUGFUNC("e1000_phy_ife_get_info");
4097
4098 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4099 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4100
4101 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4102 if (ret_val)
4103 return ret_val;
4104 phy_info->polarity_correction =
4105 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4106 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4107
4108 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4109 ret_val = e1000_check_polarity(hw, &polarity);
4110 if (ret_val)
4111 return ret_val;
4112 } else {
4113 /* Polarity is forced. */
4114 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4115 IFE_PSC_FORCE_POLARITY_SHIFT;
4116 }
4117 phy_info->cable_polarity = polarity;
4118
4119 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4120 if (ret_val)
4121 return ret_val;
4122
4123 phy_info->mdix_mode =
4124 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4125 IFE_PMC_MDIX_MODE_SHIFT;
4126
4127 return E1000_SUCCESS;
4128}
4129
4130/******************************************************************************
3787* Get PHY information from various PHY registers fot m88 PHY only. 4131* Get PHY information from various PHY registers fot m88 PHY only.
3788* 4132*
3789* hw - Struct containing variables accessed by shared code 4133* hw - Struct containing variables accessed by shared code
@@ -3898,9 +4242,12 @@ e1000_phy_get_info(struct e1000_hw *hw,
3898 return -E1000_ERR_CONFIG; 4242 return -E1000_ERR_CONFIG;
3899 } 4243 }
3900 4244
3901 if(hw->phy_type == e1000_phy_igp || 4245 if (hw->phy_type == e1000_phy_igp ||
4246 hw->phy_type == e1000_phy_igp_3 ||
3902 hw->phy_type == e1000_phy_igp_2) 4247 hw->phy_type == e1000_phy_igp_2)
3903 return e1000_phy_igp_get_info(hw, phy_info); 4248 return e1000_phy_igp_get_info(hw, phy_info);
4249 else if (hw->phy_type == e1000_phy_ife)
4250 return e1000_phy_ife_get_info(hw, phy_info);
3904 else 4251 else
3905 return e1000_phy_m88_get_info(hw, phy_info); 4252 return e1000_phy_m88_get_info(hw, phy_info);
3906} 4253}
@@ -4049,6 +4396,35 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4049 eeprom->use_eerd = TRUE; 4396 eeprom->use_eerd = TRUE;
4050 eeprom->use_eewr = FALSE; 4397 eeprom->use_eewr = FALSE;
4051 break; 4398 break;
4399 case e1000_ich8lan:
4400 {
4401 int32_t i = 0;
4402 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4403
4404 eeprom->type = e1000_eeprom_ich8;
4405 eeprom->use_eerd = FALSE;
4406 eeprom->use_eewr = FALSE;
4407 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4408
4409 /* Zero the shadow RAM structure. But don't load it from NVM
4410 * so as to save time for driver init */
4411 if (hw->eeprom_shadow_ram != NULL) {
4412 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4413 hw->eeprom_shadow_ram[i].modified = FALSE;
4414 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4415 }
4416 }
4417
4418 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4419 ICH8_FLASH_SECTOR_SIZE;
4420
4421 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4422 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4423 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4424 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4425
4426 break;
4427 }
4052 default: 4428 default:
4053 break; 4429 break;
4054 } 4430 }
@@ -4469,7 +4845,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
4469 return ret_val; 4845 return ret_val;
4470 } 4846 }
4471 4847
4472 if(eeprom->type == e1000_eeprom_spi) { 4848 if (eeprom->type == e1000_eeprom_ich8)
4849 return e1000_read_eeprom_ich8(hw, offset, words, data);
4850
4851 if (eeprom->type == e1000_eeprom_spi) {
4473 uint16_t word_in; 4852 uint16_t word_in;
4474 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4853 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4475 4854
@@ -4636,7 +5015,10 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4636 5015
4637 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5016 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
4638 5017
4639 if(hw->mac_type == e1000_82573) { 5018 if (hw->mac_type == e1000_ich8lan)
5019 return FALSE;
5020
5021 if (hw->mac_type == e1000_82573) {
4640 eecd = E1000_READ_REG(hw, EECD); 5022 eecd = E1000_READ_REG(hw, EECD);
4641 5023
4642 /* Isolate bits 15 & 16 */ 5024 /* Isolate bits 15 & 16 */
@@ -4686,8 +5068,22 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4686 } 5068 }
4687 } 5069 }
4688 5070
4689 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 5071 if (hw->mac_type == e1000_ich8lan) {
4690 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5072 /* Drivers must allocate the shadow ram structure for the
5073 * EEPROM checksum to be updated. Otherwise, this bit as well
5074 * as the checksum must both be set correctly for this
5075 * validation to pass.
5076 */
5077 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5078 if ((eeprom_data & 0x40) == 0) {
5079 eeprom_data |= 0x40;
5080 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5081 e1000_update_eeprom_checksum(hw);
5082 }
5083 }
5084
5085 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5086 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4691 DEBUGOUT("EEPROM Read Error\n"); 5087 DEBUGOUT("EEPROM Read Error\n");
4692 return -E1000_ERR_EEPROM; 5088 return -E1000_ERR_EEPROM;
4693 } 5089 }
@@ -4713,6 +5109,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4713int32_t 5109int32_t
4714e1000_update_eeprom_checksum(struct e1000_hw *hw) 5110e1000_update_eeprom_checksum(struct e1000_hw *hw)
4715{ 5111{
5112 uint32_t ctrl_ext;
4716 uint16_t checksum = 0; 5113 uint16_t checksum = 0;
4717 uint16_t i, eeprom_data; 5114 uint16_t i, eeprom_data;
4718 5115
@@ -4731,6 +5128,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
4731 return -E1000_ERR_EEPROM; 5128 return -E1000_ERR_EEPROM;
4732 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5129 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4733 e1000_commit_shadow_ram(hw); 5130 e1000_commit_shadow_ram(hw);
5131 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5132 e1000_commit_shadow_ram(hw);
5133 /* Reload the EEPROM, or else modifications will not appear
5134 * until after next adapter reset. */
5135 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5136 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5137 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5138 msec_delay(10);
4734 } 5139 }
4735 return E1000_SUCCESS; 5140 return E1000_SUCCESS;
4736} 5141}
@@ -4770,6 +5175,9 @@ e1000_write_eeprom(struct e1000_hw *hw,
4770 if(eeprom->use_eewr == TRUE) 5175 if(eeprom->use_eewr == TRUE)
4771 return e1000_write_eeprom_eewr(hw, offset, words, data); 5176 return e1000_write_eeprom_eewr(hw, offset, words, data);
4772 5177
5178 if (eeprom->type == e1000_eeprom_ich8)
5179 return e1000_write_eeprom_ich8(hw, offset, words, data);
5180
4773 /* Prepare the EEPROM for writing */ 5181 /* Prepare the EEPROM for writing */
4774 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5182 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4775 return -E1000_ERR_EEPROM; 5183 return -E1000_ERR_EEPROM;
@@ -4957,11 +5365,17 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4957 uint32_t flop = 0; 5365 uint32_t flop = 0;
4958 uint32_t i = 0; 5366 uint32_t i = 0;
4959 int32_t error = E1000_SUCCESS; 5367 int32_t error = E1000_SUCCESS;
4960 5368 uint32_t old_bank_offset = 0;
4961 /* The flop register will be used to determine if flash type is STM */ 5369 uint32_t new_bank_offset = 0;
4962 flop = E1000_READ_REG(hw, FLOP); 5370 uint32_t sector_retries = 0;
5371 uint8_t low_byte = 0;
5372 uint8_t high_byte = 0;
5373 uint8_t temp_byte = 0;
5374 boolean_t sector_write_failed = FALSE;
4963 5375
4964 if (hw->mac_type == e1000_82573) { 5376 if (hw->mac_type == e1000_82573) {
5377 /* The flop register will be used to determine if flash type is STM */
5378 flop = E1000_READ_REG(hw, FLOP);
4965 for (i=0; i < attempts; i++) { 5379 for (i=0; i < attempts; i++) {
4966 eecd = E1000_READ_REG(hw, EECD); 5380 eecd = E1000_READ_REG(hw, EECD);
4967 if ((eecd & E1000_EECD_FLUPD) == 0) { 5381 if ((eecd & E1000_EECD_FLUPD) == 0) {
@@ -4995,6 +5409,106 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4995 } 5409 }
4996 } 5410 }
4997 5411
5412 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5413 /* We're writing to the opposite bank so if we're on bank 1,
5414 * write to bank 0 etc. We also need to erase the segment that
5415 * is going to be written */
5416 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5417 new_bank_offset = hw->flash_bank_size * 2;
5418 old_bank_offset = 0;
5419 e1000_erase_ich8_4k_segment(hw, 1);
5420 } else {
5421 old_bank_offset = hw->flash_bank_size * 2;
5422 new_bank_offset = 0;
5423 e1000_erase_ich8_4k_segment(hw, 0);
5424 }
5425
5426 do {
5427 sector_write_failed = FALSE;
5428 /* Loop for every byte in the shadow RAM,
5429 * which is in units of words. */
5430 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5431 /* Determine whether to write the value stored
5432 * in the other NVM bank or a modified value stored
5433 * in the shadow RAM */
5434 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5435 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5436 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5437 &temp_byte);
5438 udelay(100);
5439 error = e1000_verify_write_ich8_byte(hw,
5440 (i << 1) + new_bank_offset,
5441 low_byte);
5442 if (error != E1000_SUCCESS)
5443 sector_write_failed = TRUE;
5444 high_byte =
5445 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5446 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5447 &temp_byte);
5448 udelay(100);
5449 } else {
5450 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5451 &low_byte);
5452 udelay(100);
5453 error = e1000_verify_write_ich8_byte(hw,
5454 (i << 1) + new_bank_offset, low_byte);
5455 if (error != E1000_SUCCESS)
5456 sector_write_failed = TRUE;
5457 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5458 &high_byte);
5459 }
5460
5461 /* If the word is 0x13, then make sure the signature bits
5462 * (15:14) are 11b until the commit has completed.
5463 * This will allow us to write 10b which indicates the
5464 * signature is valid. We want to do this after the write
5465 * has completed so that we don't mark the segment valid
5466 * while the write is still in progress */
5467 if (i == E1000_ICH8_NVM_SIG_WORD)
5468 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5469
5470 error = e1000_verify_write_ich8_byte(hw,
5471 (i << 1) + new_bank_offset + 1, high_byte);
5472 if (error != E1000_SUCCESS)
5473 sector_write_failed = TRUE;
5474
5475 if (sector_write_failed == FALSE) {
5476 /* Clear the now not used entry in the cache */
5477 hw->eeprom_shadow_ram[i].modified = FALSE;
5478 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5479 }
5480 }
5481
5482 /* Don't bother writing the segment valid bits if sector
5483 * programming failed. */
5484 if (sector_write_failed == FALSE) {
5485 /* Finally validate the new segment by setting bit 15:14
5486 * to 10b in word 0x13 , this can be done without an
5487 * erase as well since these bits are 11 to start with
5488 * and we need to change bit 14 to 0b */
5489 e1000_read_ich8_byte(hw,
5490 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5491 &high_byte);
5492 high_byte &= 0xBF;
5493 error = e1000_verify_write_ich8_byte(hw,
5494 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5495 high_byte);
5496 if (error != E1000_SUCCESS)
5497 sector_write_failed = TRUE;
5498
5499 /* And invalidate the previously valid segment by setting
5500 * its signature word (0x13) high_byte to 0b. This can be
5501 * done without an erase because flash erase sets all bits
5502 * to 1's. We can write 1's to 0's without an erase */
5503 error = e1000_verify_write_ich8_byte(hw,
5504 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5505 0);
5506 if (error != E1000_SUCCESS)
5507 sector_write_failed = TRUE;
5508 }
5509 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5510 }
5511
4998 return error; 5512 return error;
4999} 5513}
5000 5514
@@ -5102,15 +5616,19 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5102 * the other port. */ 5616 * the other port. */
5103 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5617 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5104 rar_num -= 1; 5618 rar_num -= 1;
5619 if (hw->mac_type == e1000_ich8lan)
5620 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5621
5105 /* Zero out the other 15 receive addresses. */ 5622 /* Zero out the other 15 receive addresses. */
5106 DEBUGOUT("Clearing RAR[1-15]\n"); 5623 DEBUGOUT("Clearing RAR[1-15]\n");
5107 for(i = 1; i < rar_num; i++) { 5624 for(i = 1; i < rar_num; i++) {
5108 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5625 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5626 E1000_WRITE_FLUSH(hw);
5109 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5627 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5628 E1000_WRITE_FLUSH(hw);
5110 } 5629 }
5111} 5630}
5112 5631
5113#if 0
5114/****************************************************************************** 5632/******************************************************************************
5115 * Updates the MAC's list of multicast addresses. 5633 * Updates the MAC's list of multicast addresses.
5116 * 5634 *
@@ -5145,6 +5663,8 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5145 /* Clear RAR[1-15] */ 5663 /* Clear RAR[1-15] */
5146 DEBUGOUT(" Clearing RAR[1-15]\n"); 5664 DEBUGOUT(" Clearing RAR[1-15]\n");
5147 num_rar_entry = E1000_RAR_ENTRIES; 5665 num_rar_entry = E1000_RAR_ENTRIES;
5666 if (hw->mac_type == e1000_ich8lan)
5667 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5148 /* Reserve a spot for the Locally Administered Address to work around 5668 /* Reserve a spot for the Locally Administered Address to work around
5149 * an 82571 issue in which a reset on one port will reload the MAC on 5669 * an 82571 issue in which a reset on one port will reload the MAC on
5150 * the other port. */ 5670 * the other port. */
@@ -5153,14 +5673,19 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5153 5673
5154 for(i = rar_used_count; i < num_rar_entry; i++) { 5674 for(i = rar_used_count; i < num_rar_entry; i++) {
5155 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5675 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5676 E1000_WRITE_FLUSH(hw);
5156 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5677 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5678 E1000_WRITE_FLUSH(hw);
5157 } 5679 }
5158 5680
5159 /* Clear the MTA */ 5681 /* Clear the MTA */
5160 DEBUGOUT(" Clearing MTA\n"); 5682 DEBUGOUT(" Clearing MTA\n");
5161 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5683 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5684 if (hw->mac_type == e1000_ich8lan)
5685 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5162 for(i = 0; i < num_mta_entry; i++) { 5686 for(i = 0; i < num_mta_entry; i++) {
5163 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5687 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5688 E1000_WRITE_FLUSH(hw);
5164 } 5689 }
5165 5690
5166 /* Add the new addresses */ 5691 /* Add the new addresses */
@@ -5194,7 +5719,6 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5194 } 5719 }
5195 DEBUGOUT("MC Update Complete\n"); 5720 DEBUGOUT("MC Update Complete\n");
5196} 5721}
5197#endif /* 0 */
5198 5722
5199/****************************************************************************** 5723/******************************************************************************
5200 * Hashes an address to determine its location in the multicast table 5724 * Hashes an address to determine its location in the multicast table
@@ -5217,24 +5741,46 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5217 * LSB MSB 5741 * LSB MSB
5218 */ 5742 */
5219 case 0: 5743 case 0:
5220 /* [47:36] i.e. 0x563 for above example address */ 5744 if (hw->mac_type == e1000_ich8lan) {
5221 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5745 /* [47:38] i.e. 0x158 for above example address */
5746 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5747 } else {
5748 /* [47:36] i.e. 0x563 for above example address */
5749 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5750 }
5222 break; 5751 break;
5223 case 1: 5752 case 1:
5224 /* [46:35] i.e. 0xAC6 for above example address */ 5753 if (hw->mac_type == e1000_ich8lan) {
5225 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5754 /* [46:37] i.e. 0x2B1 for above example address */
5755 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5756 } else {
5757 /* [46:35] i.e. 0xAC6 for above example address */
5758 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5759 }
5226 break; 5760 break;
5227 case 2: 5761 case 2:
5228 /* [45:34] i.e. 0x5D8 for above example address */ 5762 if (hw->mac_type == e1000_ich8lan) {
5229 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5763 /*[45:36] i.e. 0x163 for above example address */
5764 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5765 } else {
5766 /* [45:34] i.e. 0x5D8 for above example address */
5767 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5768 }
5230 break; 5769 break;
5231 case 3: 5770 case 3:
5232 /* [43:32] i.e. 0x634 for above example address */ 5771 if (hw->mac_type == e1000_ich8lan) {
5233 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5772 /* [43:34] i.e. 0x18D for above example address */
5773 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5774 } else {
5775 /* [43:32] i.e. 0x634 for above example address */
5776 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5777 }
5234 break; 5778 break;
5235 } 5779 }
5236 5780
5237 hash_value &= 0xFFF; 5781 hash_value &= 0xFFF;
5782 if (hw->mac_type == e1000_ich8lan)
5783 hash_value &= 0x3FF;
5238 5784
5239 return hash_value; 5785 return hash_value;
5240} 5786}
@@ -5262,6 +5808,8 @@ e1000_mta_set(struct e1000_hw *hw,
5262 * register are determined by the lower 5 bits of the value. 5808 * register are determined by the lower 5 bits of the value.
5263 */ 5809 */
5264 hash_reg = (hash_value >> 5) & 0x7F; 5810 hash_reg = (hash_value >> 5) & 0x7F;
5811 if (hw->mac_type == e1000_ich8lan)
5812 hash_reg &= 0x1F;
5265 hash_bit = hash_value & 0x1F; 5813 hash_bit = hash_value & 0x1F;
5266 5814
5267 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5815 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -5275,9 +5823,12 @@ e1000_mta_set(struct e1000_hw *hw,
5275 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5823 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5276 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5824 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5277 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5825 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5826 E1000_WRITE_FLUSH(hw);
5278 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5827 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5828 E1000_WRITE_FLUSH(hw);
5279 } else { 5829 } else {
5280 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5830 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5831 E1000_WRITE_FLUSH(hw);
5281 } 5832 }
5282} 5833}
5283 5834
@@ -5334,7 +5885,9 @@ e1000_rar_set(struct e1000_hw *hw,
5334 } 5885 }
5335 5886
5336 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5887 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5888 E1000_WRITE_FLUSH(hw);
5337 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5889 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5890 E1000_WRITE_FLUSH(hw);
5338} 5891}
5339 5892
5340/****************************************************************************** 5893/******************************************************************************
@@ -5351,12 +5904,18 @@ e1000_write_vfta(struct e1000_hw *hw,
5351{ 5904{
5352 uint32_t temp; 5905 uint32_t temp;
5353 5906
5354 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5907 if (hw->mac_type == e1000_ich8lan)
5908 return;
5909
5910 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5355 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5911 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5356 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5912 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5913 E1000_WRITE_FLUSH(hw);
5357 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 5914 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5915 E1000_WRITE_FLUSH(hw);
5358 } else { 5916 } else {
5359 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5917 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5918 E1000_WRITE_FLUSH(hw);
5360 } 5919 }
5361} 5920}
5362 5921
@@ -5373,6 +5932,9 @@ e1000_clear_vfta(struct e1000_hw *hw)
5373 uint32_t vfta_offset = 0; 5932 uint32_t vfta_offset = 0;
5374 uint32_t vfta_bit_in_reg = 0; 5933 uint32_t vfta_bit_in_reg = 0;
5375 5934
5935 if (hw->mac_type == e1000_ich8lan)
5936 return;
5937
5376 if (hw->mac_type == e1000_82573) { 5938 if (hw->mac_type == e1000_82573) {
5377 if (hw->mng_cookie.vlan_id != 0) { 5939 if (hw->mng_cookie.vlan_id != 0) {
5378 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 5940 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
@@ -5392,6 +5954,7 @@ e1000_clear_vfta(struct e1000_hw *hw)
5392 * manageability unit */ 5954 * manageability unit */
5393 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5955 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5394 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5956 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5957 E1000_WRITE_FLUSH(hw);
5395 } 5958 }
5396} 5959}
5397 5960
@@ -5421,9 +5984,18 @@ e1000_id_led_init(struct e1000_hw * hw)
5421 DEBUGOUT("EEPROM Read Error\n"); 5984 DEBUGOUT("EEPROM Read Error\n");
5422 return -E1000_ERR_EEPROM; 5985 return -E1000_ERR_EEPROM;
5423 } 5986 }
5424 if((eeprom_data== ID_LED_RESERVED_0000) || 5987
5425 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; 5988 if ((hw->mac_type == e1000_82573) &&
5426 for(i = 0; i < 4; i++) { 5989 (eeprom_data == ID_LED_RESERVED_82573))
5990 eeprom_data = ID_LED_DEFAULT_82573;
5991 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5992 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5993 if (hw->mac_type == e1000_ich8lan)
5994 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5995 else
5996 eeprom_data = ID_LED_DEFAULT;
5997 }
5998 for (i = 0; i < 4; i++) {
5427 temp = (eeprom_data >> (i << 2)) & led_mask; 5999 temp = (eeprom_data >> (i << 2)) & led_mask;
5428 switch(temp) { 6000 switch(temp) {
5429 case ID_LED_ON1_DEF2: 6001 case ID_LED_ON1_DEF2:
@@ -5519,6 +6091,44 @@ e1000_setup_led(struct e1000_hw *hw)
5519} 6091}
5520 6092
5521/****************************************************************************** 6093/******************************************************************************
6094 * Used on 82571 and later Si that has LED blink bits.
6095 * Callers must use their own timer and should have already called
6096 * e1000_id_led_init()
6097 * Call e1000_cleanup led() to stop blinking
6098 *
6099 * hw - Struct containing variables accessed by shared code
6100 *****************************************************************************/
6101int32_t
6102e1000_blink_led_start(struct e1000_hw *hw)
6103{
6104 int16_t i;
6105 uint32_t ledctl_blink = 0;
6106
6107 DEBUGFUNC("e1000_id_led_blink_on");
6108
6109 if (hw->mac_type < e1000_82571) {
6110 /* Nothing to do */
6111 return E1000_SUCCESS;
6112 }
6113 if (hw->media_type == e1000_media_type_fiber) {
6114 /* always blink LED0 for PCI-E fiber */
6115 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6116 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6117 } else {
6118 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6119 ledctl_blink = hw->ledctl_mode2;
6120 for (i=0; i < 4; i++)
6121 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6122 E1000_LEDCTL_MODE_LED_ON)
6123 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6124 }
6125
6126 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6127
6128 return E1000_SUCCESS;
6129}
6130
6131/******************************************************************************
5522 * Restores the saved state of the SW controlable LED. 6132 * Restores the saved state of the SW controlable LED.
5523 * 6133 *
5524 * hw - Struct containing variables accessed by shared code 6134 * hw - Struct containing variables accessed by shared code
@@ -5548,6 +6158,10 @@ e1000_cleanup_led(struct e1000_hw *hw)
5548 return ret_val; 6158 return ret_val;
5549 /* Fall Through */ 6159 /* Fall Through */
5550 default: 6160 default:
6161 if (hw->phy_type == e1000_phy_ife) {
6162 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6163 break;
6164 }
5551 /* Restore LEDCTL settings */ 6165 /* Restore LEDCTL settings */
5552 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6166 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
5553 break; 6167 break;
@@ -5592,7 +6206,10 @@ e1000_led_on(struct e1000_hw *hw)
5592 /* Clear SW Defineable Pin 0 to turn on the LED */ 6206 /* Clear SW Defineable Pin 0 to turn on the LED */
5593 ctrl &= ~E1000_CTRL_SWDPIN0; 6207 ctrl &= ~E1000_CTRL_SWDPIN0;
5594 ctrl |= E1000_CTRL_SWDPIO0; 6208 ctrl |= E1000_CTRL_SWDPIO0;
5595 } else if(hw->media_type == e1000_media_type_copper) { 6209 } else if (hw->phy_type == e1000_phy_ife) {
6210 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6211 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6212 } else if (hw->media_type == e1000_media_type_copper) {
5596 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6213 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5597 return E1000_SUCCESS; 6214 return E1000_SUCCESS;
5598 } 6215 }
@@ -5640,7 +6257,10 @@ e1000_led_off(struct e1000_hw *hw)
5640 /* Set SW Defineable Pin 0 to turn off the LED */ 6257 /* Set SW Defineable Pin 0 to turn off the LED */
5641 ctrl |= E1000_CTRL_SWDPIN0; 6258 ctrl |= E1000_CTRL_SWDPIN0;
5642 ctrl |= E1000_CTRL_SWDPIO0; 6259 ctrl |= E1000_CTRL_SWDPIO0;
5643 } else if(hw->media_type == e1000_media_type_copper) { 6260 } else if (hw->phy_type == e1000_phy_ife) {
6261 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6262 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6263 } else if (hw->media_type == e1000_media_type_copper) {
5644 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6264 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5645 return E1000_SUCCESS; 6265 return E1000_SUCCESS;
5646 } 6266 }
@@ -5678,12 +6298,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5678 temp = E1000_READ_REG(hw, XOFFRXC); 6298 temp = E1000_READ_REG(hw, XOFFRXC);
5679 temp = E1000_READ_REG(hw, XOFFTXC); 6299 temp = E1000_READ_REG(hw, XOFFTXC);
5680 temp = E1000_READ_REG(hw, FCRUC); 6300 temp = E1000_READ_REG(hw, FCRUC);
6301
6302 if (hw->mac_type != e1000_ich8lan) {
5681 temp = E1000_READ_REG(hw, PRC64); 6303 temp = E1000_READ_REG(hw, PRC64);
5682 temp = E1000_READ_REG(hw, PRC127); 6304 temp = E1000_READ_REG(hw, PRC127);
5683 temp = E1000_READ_REG(hw, PRC255); 6305 temp = E1000_READ_REG(hw, PRC255);
5684 temp = E1000_READ_REG(hw, PRC511); 6306 temp = E1000_READ_REG(hw, PRC511);
5685 temp = E1000_READ_REG(hw, PRC1023); 6307 temp = E1000_READ_REG(hw, PRC1023);
5686 temp = E1000_READ_REG(hw, PRC1522); 6308 temp = E1000_READ_REG(hw, PRC1522);
6309 }
6310
5687 temp = E1000_READ_REG(hw, GPRC); 6311 temp = E1000_READ_REG(hw, GPRC);
5688 temp = E1000_READ_REG(hw, BPRC); 6312 temp = E1000_READ_REG(hw, BPRC);
5689 temp = E1000_READ_REG(hw, MPRC); 6313 temp = E1000_READ_REG(hw, MPRC);
@@ -5703,12 +6327,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5703 temp = E1000_READ_REG(hw, TOTH); 6327 temp = E1000_READ_REG(hw, TOTH);
5704 temp = E1000_READ_REG(hw, TPR); 6328 temp = E1000_READ_REG(hw, TPR);
5705 temp = E1000_READ_REG(hw, TPT); 6329 temp = E1000_READ_REG(hw, TPT);
6330
6331 if (hw->mac_type != e1000_ich8lan) {
5706 temp = E1000_READ_REG(hw, PTC64); 6332 temp = E1000_READ_REG(hw, PTC64);
5707 temp = E1000_READ_REG(hw, PTC127); 6333 temp = E1000_READ_REG(hw, PTC127);
5708 temp = E1000_READ_REG(hw, PTC255); 6334 temp = E1000_READ_REG(hw, PTC255);
5709 temp = E1000_READ_REG(hw, PTC511); 6335 temp = E1000_READ_REG(hw, PTC511);
5710 temp = E1000_READ_REG(hw, PTC1023); 6336 temp = E1000_READ_REG(hw, PTC1023);
5711 temp = E1000_READ_REG(hw, PTC1522); 6337 temp = E1000_READ_REG(hw, PTC1522);
6338 }
6339
5712 temp = E1000_READ_REG(hw, MPTC); 6340 temp = E1000_READ_REG(hw, MPTC);
5713 temp = E1000_READ_REG(hw, BPTC); 6341 temp = E1000_READ_REG(hw, BPTC);
5714 6342
@@ -5731,6 +6359,9 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5731 6359
5732 temp = E1000_READ_REG(hw, IAC); 6360 temp = E1000_READ_REG(hw, IAC);
5733 temp = E1000_READ_REG(hw, ICRXOC); 6361 temp = E1000_READ_REG(hw, ICRXOC);
6362
6363 if (hw->mac_type == e1000_ich8lan) return;
6364
5734 temp = E1000_READ_REG(hw, ICRXPTC); 6365 temp = E1000_READ_REG(hw, ICRXPTC);
5735 temp = E1000_READ_REG(hw, ICRXATC); 6366 temp = E1000_READ_REG(hw, ICRXATC);
5736 temp = E1000_READ_REG(hw, ICTXPTC); 6367 temp = E1000_READ_REG(hw, ICTXPTC);
@@ -5911,6 +6542,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
5911 hw->bus_width = e1000_bus_width_pciex_1; 6542 hw->bus_width = e1000_bus_width_pciex_1;
5912 break; 6543 break;
5913 case e1000_82571: 6544 case e1000_82571:
6545 case e1000_ich8lan:
5914 case e1000_80003es2lan: 6546 case e1000_80003es2lan:
5915 hw->bus_type = e1000_bus_type_pci_express; 6547 hw->bus_type = e1000_bus_type_pci_express;
5916 hw->bus_speed = e1000_bus_speed_2500; 6548 hw->bus_speed = e1000_bus_speed_2500;
@@ -5948,8 +6580,6 @@ e1000_get_bus_info(struct e1000_hw *hw)
5948 break; 6580 break;
5949 } 6581 }
5950} 6582}
5951
5952#if 0
5953/****************************************************************************** 6583/******************************************************************************
5954 * Reads a value from one of the devices registers using port I/O (as opposed 6584 * Reads a value from one of the devices registers using port I/O (as opposed
5955 * memory mapped I/O). Only 82544 and newer devices support port I/O. 6585 * memory mapped I/O). Only 82544 and newer devices support port I/O.
@@ -5967,7 +6597,6 @@ e1000_read_reg_io(struct e1000_hw *hw,
5967 e1000_io_write(hw, io_addr, offset); 6597 e1000_io_write(hw, io_addr, offset);
5968 return e1000_io_read(hw, io_data); 6598 return e1000_io_read(hw, io_data);
5969} 6599}
5970#endif /* 0 */
5971 6600
5972/****************************************************************************** 6601/******************************************************************************
5973 * Writes a value to one of the devices registers using port I/O (as opposed to 6602 * Writes a value to one of the devices registers using port I/O (as opposed to
@@ -6012,8 +6641,6 @@ e1000_get_cable_length(struct e1000_hw *hw,
6012{ 6641{
6013 int32_t ret_val; 6642 int32_t ret_val;
6014 uint16_t agc_value = 0; 6643 uint16_t agc_value = 0;
6015 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6016 uint16_t max_agc = 0;
6017 uint16_t i, phy_data; 6644 uint16_t i, phy_data;
6018 uint16_t cable_length; 6645 uint16_t cable_length;
6019 6646
@@ -6086,6 +6713,8 @@ e1000_get_cable_length(struct e1000_hw *hw,
6086 break; 6713 break;
6087 } 6714 }
6088 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6715 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6716 uint16_t cur_agc_value;
6717 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6089 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6718 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6090 {IGP01E1000_PHY_AGC_A, 6719 {IGP01E1000_PHY_AGC_A,
6091 IGP01E1000_PHY_AGC_B, 6720 IGP01E1000_PHY_AGC_B,
@@ -6098,23 +6727,23 @@ e1000_get_cable_length(struct e1000_hw *hw,
6098 if(ret_val) 6727 if(ret_val)
6099 return ret_val; 6728 return ret_val;
6100 6729
6101 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6730 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6102 6731
6103 /* Array bound check. */ 6732 /* Value bound check. */
6104 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 6733 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6105 (cur_agc == 0)) 6734 (cur_agc_value == 0))
6106 return -E1000_ERR_PHY; 6735 return -E1000_ERR_PHY;
6107 6736
6108 agc_value += cur_agc; 6737 agc_value += cur_agc_value;
6109 6738
6110 /* Update minimal AGC value. */ 6739 /* Update minimal AGC value. */
6111 if(min_agc > cur_agc) 6740 if (min_agc_value > cur_agc_value)
6112 min_agc = cur_agc; 6741 min_agc_value = cur_agc_value;
6113 } 6742 }
6114 6743
6115 /* Remove the minimal AGC result for length < 50m */ 6744 /* Remove the minimal AGC result for length < 50m */
6116 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 6745 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6117 agc_value -= min_agc; 6746 agc_value -= min_agc_value;
6118 6747
6119 /* Get the average length of the remaining 3 channels */ 6748 /* Get the average length of the remaining 3 channels */
6120 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 6749 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
@@ -6130,7 +6759,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6130 IGP01E1000_AGC_RANGE) : 0; 6759 IGP01E1000_AGC_RANGE) : 0;
6131 *max_length = e1000_igp_cable_length_table[agc_value] + 6760 *max_length = e1000_igp_cable_length_table[agc_value] +
6132 IGP01E1000_AGC_RANGE; 6761 IGP01E1000_AGC_RANGE;
6133 } else if (hw->phy_type == e1000_phy_igp_2) { 6762 } else if (hw->phy_type == e1000_phy_igp_2 ||
6763 hw->phy_type == e1000_phy_igp_3) {
6764 uint16_t cur_agc_index, max_agc_index = 0;
6765 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6134 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6766 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6135 {IGP02E1000_PHY_AGC_A, 6767 {IGP02E1000_PHY_AGC_A,
6136 IGP02E1000_PHY_AGC_B, 6768 IGP02E1000_PHY_AGC_B,
@@ -6145,19 +6777,27 @@ e1000_get_cable_length(struct e1000_hw *hw,
6145 /* Getting bits 15:9, which represent the combination of course and 6777 /* Getting bits 15:9, which represent the combination of course and
6146 * fine gain values. The result is a number that can be put into 6778 * fine gain values. The result is a number that can be put into
6147 * the lookup table to obtain the approximate cable length. */ 6779 * the lookup table to obtain the approximate cable length. */
6148 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6780 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6149 IGP02E1000_AGC_LENGTH_MASK; 6781 IGP02E1000_AGC_LENGTH_MASK;
6150 6782
6151 /* Remove min & max AGC values from calculation. */ 6783 /* Array index bound check. */
6152 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) 6784 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6153 min_agc = cur_agc; 6785 (cur_agc_index == 0))
6154 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) 6786 return -E1000_ERR_PHY;
6155 max_agc = cur_agc;
6156 6787
6157 agc_value += e1000_igp_2_cable_length_table[cur_agc]; 6788 /* Remove min & max AGC values from calculation. */
6789 if (e1000_igp_2_cable_length_table[min_agc_index] >
6790 e1000_igp_2_cable_length_table[cur_agc_index])
6791 min_agc_index = cur_agc_index;
6792 if (e1000_igp_2_cable_length_table[max_agc_index] <
6793 e1000_igp_2_cable_length_table[cur_agc_index])
6794 max_agc_index = cur_agc_index;
6795
6796 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6158 } 6797 }
6159 6798
6160 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); 6799 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6800 e1000_igp_2_cable_length_table[max_agc_index]);
6161 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 6801 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6162 6802
6163 /* Calculate cable length with the error range of +/- 10 meters. */ 6803 /* Calculate cable length with the error range of +/- 10 meters. */
@@ -6203,7 +6843,8 @@ e1000_check_polarity(struct e1000_hw *hw,
6203 return ret_val; 6843 return ret_val;
6204 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6844 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6205 M88E1000_PSSR_REV_POLARITY_SHIFT; 6845 M88E1000_PSSR_REV_POLARITY_SHIFT;
6206 } else if(hw->phy_type == e1000_phy_igp || 6846 } else if (hw->phy_type == e1000_phy_igp ||
6847 hw->phy_type == e1000_phy_igp_3 ||
6207 hw->phy_type == e1000_phy_igp_2) { 6848 hw->phy_type == e1000_phy_igp_2) {
6208 /* Read the Status register to check the speed */ 6849 /* Read the Status register to check the speed */
6209 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6850 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
@@ -6229,6 +6870,13 @@ e1000_check_polarity(struct e1000_hw *hw,
6229 * 100 Mbps this bit is always 0) */ 6870 * 100 Mbps this bit is always 0) */
6230 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; 6871 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6231 } 6872 }
6873 } else if (hw->phy_type == e1000_phy_ife) {
6874 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6875 &phy_data);
6876 if (ret_val)
6877 return ret_val;
6878 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6879 IFE_PESC_POLARITY_REVERSED_SHIFT;
6232 } 6880 }
6233 return E1000_SUCCESS; 6881 return E1000_SUCCESS;
6234} 6882}
@@ -6256,7 +6904,8 @@ e1000_check_downshift(struct e1000_hw *hw)
6256 6904
6257 DEBUGFUNC("e1000_check_downshift"); 6905 DEBUGFUNC("e1000_check_downshift");
6258 6906
6259 if(hw->phy_type == e1000_phy_igp || 6907 if (hw->phy_type == e1000_phy_igp ||
6908 hw->phy_type == e1000_phy_igp_3 ||
6260 hw->phy_type == e1000_phy_igp_2) { 6909 hw->phy_type == e1000_phy_igp_2) {
6261 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6910 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6262 &phy_data); 6911 &phy_data);
@@ -6273,6 +6922,9 @@ e1000_check_downshift(struct e1000_hw *hw)
6273 6922
6274 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6923 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6275 M88E1000_PSSR_DOWNSHIFT_SHIFT; 6924 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6925 } else if (hw->phy_type == e1000_phy_ife) {
6926 /* e1000_phy_ife supports 10/100 speed only */
6927 hw->speed_downgraded = FALSE;
6276 } 6928 }
6277 6929
6278 return E1000_SUCCESS; 6930 return E1000_SUCCESS;
@@ -6317,7 +6969,9 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6317 6969
6318 if(speed == SPEED_1000) { 6970 if(speed == SPEED_1000) {
6319 6971
6320 e1000_get_cable_length(hw, &min_length, &max_length); 6972 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6973 if (ret_val)
6974 return ret_val;
6321 6975
6322 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 6976 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6323 min_length >= e1000_igp_cable_length_50) { 6977 min_length >= e1000_igp_cable_length_50) {
@@ -6525,20 +7179,27 @@ static int32_t
6525e1000_set_d3_lplu_state(struct e1000_hw *hw, 7179e1000_set_d3_lplu_state(struct e1000_hw *hw,
6526 boolean_t active) 7180 boolean_t active)
6527{ 7181{
7182 uint32_t phy_ctrl = 0;
6528 int32_t ret_val; 7183 int32_t ret_val;
6529 uint16_t phy_data; 7184 uint16_t phy_data;
6530 DEBUGFUNC("e1000_set_d3_lplu_state"); 7185 DEBUGFUNC("e1000_set_d3_lplu_state");
6531 7186
6532 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) 7187 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7188 && hw->phy_type != e1000_phy_igp_3)
6533 return E1000_SUCCESS; 7189 return E1000_SUCCESS;
6534 7190
6535 /* During driver activity LPLU should not be used or it will attain link 7191 /* During driver activity LPLU should not be used or it will attain link
6536 * from the lowest speeds starting from 10Mbps. The capability is used for 7192 * from the lowest speeds starting from 10Mbps. The capability is used for
6537 * Dx transitions and states */ 7193 * Dx transitions and states */
6538 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 7194 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
6539 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 7195 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
6540 if(ret_val) 7196 if (ret_val)
6541 return ret_val; 7197 return ret_val;
7198 } else if (hw->mac_type == e1000_ich8lan) {
7199 /* MAC writes into PHY register based on the state transition
7200 * and start auto-negotiation. SW driver can overwrite the settings
7201 * in CSR PHY power control E1000_PHY_CTRL register. */
7202 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
6542 } else { 7203 } else {
6543 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7204 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6544 if(ret_val) 7205 if(ret_val)
@@ -6553,11 +7214,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6553 if(ret_val) 7214 if(ret_val)
6554 return ret_val; 7215 return ret_val;
6555 } else { 7216 } else {
7217 if (hw->mac_type == e1000_ich8lan) {
7218 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7219 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7220 } else {
6556 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7221 phy_data &= ~IGP02E1000_PM_D3_LPLU;
6557 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7222 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6558 phy_data); 7223 phy_data);
6559 if (ret_val) 7224 if (ret_val)
6560 return ret_val; 7225 return ret_val;
7226 }
6561 } 7227 }
6562 7228
6563 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7229 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
@@ -6593,17 +7259,22 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6593 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7259 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
6594 7260
6595 if(hw->mac_type == e1000_82541_rev_2 || 7261 if(hw->mac_type == e1000_82541_rev_2 ||
6596 hw->mac_type == e1000_82547_rev_2) { 7262 hw->mac_type == e1000_82547_rev_2) {
6597 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7263 phy_data |= IGP01E1000_GMII_FLEX_SPD;
6598 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7264 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6599 if(ret_val) 7265 if(ret_val)
6600 return ret_val; 7266 return ret_val;
6601 } else { 7267 } else {
7268 if (hw->mac_type == e1000_ich8lan) {
7269 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7270 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7271 } else {
6602 phy_data |= IGP02E1000_PM_D3_LPLU; 7272 phy_data |= IGP02E1000_PM_D3_LPLU;
6603 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7273 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6604 phy_data); 7274 phy_data);
6605 if (ret_val) 7275 if (ret_val)
6606 return ret_val; 7276 return ret_val;
7277 }
6607 } 7278 }
6608 7279
6609 /* When LPLU is enabled we should disable SmartSpeed */ 7280 /* When LPLU is enabled we should disable SmartSpeed */
@@ -6638,6 +7309,7 @@ static int32_t
6638e1000_set_d0_lplu_state(struct e1000_hw *hw, 7309e1000_set_d0_lplu_state(struct e1000_hw *hw,
6639 boolean_t active) 7310 boolean_t active)
6640{ 7311{
7312 uint32_t phy_ctrl = 0;
6641 int32_t ret_val; 7313 int32_t ret_val;
6642 uint16_t phy_data; 7314 uint16_t phy_data;
6643 DEBUGFUNC("e1000_set_d0_lplu_state"); 7315 DEBUGFUNC("e1000_set_d0_lplu_state");
@@ -6645,15 +7317,24 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6645 if(hw->mac_type <= e1000_82547_rev_2) 7317 if(hw->mac_type <= e1000_82547_rev_2)
6646 return E1000_SUCCESS; 7318 return E1000_SUCCESS;
6647 7319
7320 if (hw->mac_type == e1000_ich8lan) {
7321 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7322 } else {
6648 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7323 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6649 if(ret_val) 7324 if(ret_val)
6650 return ret_val; 7325 return ret_val;
7326 }
6651 7327
6652 if (!active) { 7328 if (!active) {
7329 if (hw->mac_type == e1000_ich8lan) {
7330 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7331 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7332 } else {
6653 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7333 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6654 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7334 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6655 if (ret_val) 7335 if (ret_val)
6656 return ret_val; 7336 return ret_val;
7337 }
6657 7338
6658 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7339 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6659 * Dx states where the power conservation is most important. During 7340 * Dx states where the power conservation is most important. During
@@ -6686,10 +7367,15 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6686 7367
6687 } else { 7368 } else {
6688 7369
7370 if (hw->mac_type == e1000_ich8lan) {
7371 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7372 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7373 } else {
6689 phy_data |= IGP02E1000_PM_D0_LPLU; 7374 phy_data |= IGP02E1000_PM_D0_LPLU;
6690 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7375 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6691 if (ret_val) 7376 if (ret_val)
6692 return ret_val; 7377 return ret_val;
7378 }
6693 7379
6694 /* When LPLU is enabled we should disable SmartSpeed */ 7380 /* When LPLU is enabled we should disable SmartSpeed */
6695 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7381 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
@@ -6928,8 +7614,10 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
6928 7614
6929 length >>= 2; 7615 length >>= 2;
6930 /* The device driver writes the relevant command block into the ram area. */ 7616 /* The device driver writes the relevant command block into the ram area. */
6931 for (i = 0; i < length; i++) 7617 for (i = 0; i < length; i++) {
6932 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); 7618 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7619 E1000_WRITE_FLUSH(hw);
7620 }
6933 7621
6934 return E1000_SUCCESS; 7622 return E1000_SUCCESS;
6935} 7623}
@@ -6961,15 +7649,18 @@ e1000_mng_write_commit(
6961 * returns - TRUE when the mode is IAMT or FALSE. 7649 * returns - TRUE when the mode is IAMT or FALSE.
6962 ****************************************************************************/ 7650 ****************************************************************************/
6963boolean_t 7651boolean_t
6964e1000_check_mng_mode( 7652e1000_check_mng_mode(struct e1000_hw *hw)
6965 struct e1000_hw *hw)
6966{ 7653{
6967 uint32_t fwsm; 7654 uint32_t fwsm;
6968 7655
6969 fwsm = E1000_READ_REG(hw, FWSM); 7656 fwsm = E1000_READ_REG(hw, FWSM);
6970 7657
6971 if((fwsm & E1000_FWSM_MODE_MASK) == 7658 if (hw->mac_type == e1000_ich8lan) {
6972 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7659 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7660 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7661 return TRUE;
7662 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7663 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6973 return TRUE; 7664 return TRUE;
6974 7665
6975 return FALSE; 7666 return FALSE;
@@ -7209,7 +7900,6 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7209 E1000_WRITE_REG(hw, CTRL, ctrl); 7900 E1000_WRITE_REG(hw, CTRL, ctrl);
7210} 7901}
7211 7902
7212#if 0
7213/*************************************************************************** 7903/***************************************************************************
7214 * 7904 *
7215 * Enables PCI-Express master access. 7905 * Enables PCI-Express master access.
@@ -7233,7 +7923,6 @@ e1000_enable_pciex_master(struct e1000_hw *hw)
7233 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 7923 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7234 E1000_WRITE_REG(hw, CTRL, ctrl); 7924 E1000_WRITE_REG(hw, CTRL, ctrl);
7235} 7925}
7236#endif /* 0 */
7237 7926
7238/******************************************************************************* 7927/*******************************************************************************
7239 * 7928 *
@@ -7299,8 +7988,10 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
7299 case e1000_82572: 7988 case e1000_82572:
7300 case e1000_82573: 7989 case e1000_82573:
7301 case e1000_80003es2lan: 7990 case e1000_80003es2lan:
7302 while(timeout) { 7991 case e1000_ich8lan:
7303 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; 7992 while (timeout) {
7993 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
7994 break;
7304 else msec_delay(1); 7995 else msec_delay(1);
7305 timeout--; 7996 timeout--;
7306 } 7997 }
@@ -7340,7 +8031,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
7340 8031
7341 switch (hw->mac_type) { 8032 switch (hw->mac_type) {
7342 default: 8033 default:
7343 msec_delay(10); 8034 msec_delay_irq(10);
7344 break; 8035 break;
7345 case e1000_80003es2lan: 8036 case e1000_80003es2lan:
7346 /* Separate *_CFG_DONE_* bit for each port */ 8037 /* Separate *_CFG_DONE_* bit for each port */
@@ -7523,6 +8214,13 @@ int32_t
7523e1000_check_phy_reset_block(struct e1000_hw *hw) 8214e1000_check_phy_reset_block(struct e1000_hw *hw)
7524{ 8215{
7525 uint32_t manc = 0; 8216 uint32_t manc = 0;
8217 uint32_t fwsm = 0;
8218
8219 if (hw->mac_type == e1000_ich8lan) {
8220 fwsm = E1000_READ_REG(hw, FWSM);
8221 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8222 : E1000_BLK_PHY_RESET;
8223 }
7526 8224
7527 if (hw->mac_type > e1000_82547_rev_2) 8225 if (hw->mac_type > e1000_82547_rev_2)
7528 manc = E1000_READ_REG(hw, MANC); 8226 manc = E1000_READ_REG(hw, MANC);
@@ -7549,6 +8247,8 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7549 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8247 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
7550 return TRUE; 8248 return TRUE;
7551 break; 8249 break;
8250 case e1000_ich8lan:
8251 return TRUE;
7552 default: 8252 default:
7553 break; 8253 break;
7554 } 8254 }
@@ -7556,4 +8256,846 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7556} 8256}
7557 8257
7558 8258
8259/******************************************************************************
8260 * Configure PCI-Ex no-snoop
8261 *
8262 * hw - Struct containing variables accessed by shared code.
8263 * no_snoop - Bitmap of no-snoop events.
8264 *
8265 * returns: E1000_SUCCESS
8266 *
8267 *****************************************************************************/
8268int32_t
8269e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8270{
8271 uint32_t gcr_reg = 0;
8272
8273 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8274
8275 if (hw->bus_type == e1000_bus_type_unknown)
8276 e1000_get_bus_info(hw);
8277
8278 if (hw->bus_type != e1000_bus_type_pci_express)
8279 return E1000_SUCCESS;
8280
8281 if (no_snoop) {
8282 gcr_reg = E1000_READ_REG(hw, GCR);
8283 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8284 gcr_reg |= no_snoop;
8285 E1000_WRITE_REG(hw, GCR, gcr_reg);
8286 }
8287 if (hw->mac_type == e1000_ich8lan) {
8288 uint32_t ctrl_ext;
8289
8290 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8291
8292 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8293 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8294 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8295 }
8296
8297 return E1000_SUCCESS;
8298}
8299
8300/***************************************************************************
8301 *
8302 * Get software semaphore FLAG bit (SWFLAG).
8303 * SWFLAG is used to synchronize the access to all shared resource between
8304 * SW, FW and HW.
8305 *
8306 * hw: Struct containing variables accessed by shared code
8307 *
8308 ***************************************************************************/
8309int32_t
8310e1000_get_software_flag(struct e1000_hw *hw)
8311{
8312 int32_t timeout = PHY_CFG_TIMEOUT;
8313 uint32_t extcnf_ctrl;
8314
8315 DEBUGFUNC("e1000_get_software_flag");
8316
8317 if (hw->mac_type == e1000_ich8lan) {
8318 while (timeout) {
8319 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8320 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8321 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8322
8323 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8324 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8325 break;
8326 msec_delay_irq(1);
8327 timeout--;
8328 }
8329
8330 if (!timeout) {
8331 DEBUGOUT("FW or HW locks the resource too long.\n");
8332 return -E1000_ERR_CONFIG;
8333 }
8334 }
8335
8336 return E1000_SUCCESS;
8337}
8338
8339/***************************************************************************
8340 *
8341 * Release software semaphore FLAG bit (SWFLAG).
8342 * SWFLAG is used to synchronize the access to all shared resource between
8343 * SW, FW and HW.
8344 *
8345 * hw: Struct containing variables accessed by shared code
8346 *
8347 ***************************************************************************/
8348void
8349e1000_release_software_flag(struct e1000_hw *hw)
8350{
8351 uint32_t extcnf_ctrl;
8352
8353 DEBUGFUNC("e1000_release_software_flag");
8354
8355 if (hw->mac_type == e1000_ich8lan) {
8356 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8357 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8358 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8359 }
8360
8361 return;
8362}
8363
8364/***************************************************************************
8365 *
8366 * Disable dynamic power down mode in ife PHY.
8367 * It can be used to workaround band-gap problem.
8368 *
8369 * hw: Struct containing variables accessed by shared code
8370 *
8371 ***************************************************************************/
8372int32_t
8373e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8374{
8375 uint16_t phy_data;
8376 int32_t ret_val = E1000_SUCCESS;
8377
8378 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8379
8380 if (hw->phy_type == e1000_phy_ife) {
8381 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8382 if (ret_val)
8383 return ret_val;
8384
8385 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8386 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8387 }
8388
8389 return ret_val;
8390}
8391
8392/***************************************************************************
8393 *
8394 * Enable dynamic power down mode in ife PHY.
8395 * It can be used to workaround band-gap problem.
8396 *
8397 * hw: Struct containing variables accessed by shared code
8398 *
8399 ***************************************************************************/
8400int32_t
8401e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8402{
8403 uint16_t phy_data;
8404 int32_t ret_val = E1000_SUCCESS;
8405
8406 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8407
8408 if (hw->phy_type == e1000_phy_ife) {
8409 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8410 if (ret_val)
8411 return ret_val;
8412
8413 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8414 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8415 }
8416
8417 return ret_val;
8418}
8419
8420/******************************************************************************
8421 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8422 * register.
8423 *
8424 * hw - Struct containing variables accessed by shared code
8425 * offset - offset of word in the EEPROM to read
8426 * data - word read from the EEPROM
8427 * words - number of words to read
8428 *****************************************************************************/
8429int32_t
8430e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8431 uint16_t *data)
8432{
8433 int32_t error = E1000_SUCCESS;
8434 uint32_t flash_bank = 0;
8435 uint32_t act_offset = 0;
8436 uint32_t bank_offset = 0;
8437 uint16_t word = 0;
8438 uint16_t i = 0;
8439
8440 /* We need to know which is the valid flash bank. In the event
8441 * that we didn't allocate eeprom_shadow_ram, we may not be
8442 * managing flash_bank. So it cannot be trusted and needs
8443 * to be updated with each read.
8444 */
8445 /* Value of bit 22 corresponds to the flash bank we're on. */
8446 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8447
8448 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8449 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8450
8451 error = e1000_get_software_flag(hw);
8452 if (error != E1000_SUCCESS)
8453 return error;
8454
8455 for (i = 0; i < words; i++) {
8456 if (hw->eeprom_shadow_ram != NULL &&
8457 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8458 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8459 } else {
8460 /* The NVM part needs a byte offset, hence * 2 */
8461 act_offset = bank_offset + ((offset + i) * 2);
8462 error = e1000_read_ich8_word(hw, act_offset, &word);
8463 if (error != E1000_SUCCESS)
8464 break;
8465 data[i] = word;
8466 }
8467 }
8468
8469 e1000_release_software_flag(hw);
8470
8471 return error;
8472}
8473
8474/******************************************************************************
8475 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8476 * register. Actually, writes are written to the shadow ram cache in the hw
8477 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8478 * the NVM, which occurs when the NVM checksum is updated.
8479 *
8480 * hw - Struct containing variables accessed by shared code
8481 * offset - offset of word in the EEPROM to write
8482 * words - number of words to write
8483 * data - words to write to the EEPROM
8484 *****************************************************************************/
8485int32_t
8486e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8487 uint16_t *data)
8488{
8489 uint32_t i = 0;
8490 int32_t error = E1000_SUCCESS;
8491
8492 error = e1000_get_software_flag(hw);
8493 if (error != E1000_SUCCESS)
8494 return error;
8495
8496 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8497 * allocated. Subsequent reads to the modified words are read from
8498 * this cached structure as well. Writes will only go into this
8499 * cached structure unless it's followed by a call to
8500 * e1000_update_eeprom_checksum() where it will commit the changes
8501 * and clear the "modified" field.
8502 */
8503 if (hw->eeprom_shadow_ram != NULL) {
8504 for (i = 0; i < words; i++) {
8505 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8506 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8507 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8508 } else {
8509 error = -E1000_ERR_EEPROM;
8510 break;
8511 }
8512 }
8513 } else {
8514 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8515 * as they don't perform any NVM writes. An attempt in doing so
8516 * will result in this error.
8517 */
8518 error = -E1000_ERR_EEPROM;
8519 }
8520
8521 e1000_release_software_flag(hw);
8522
8523 return error;
8524}
8525
8526/******************************************************************************
8527 * This function does initial flash setup so that a new read/write/erase cycle
8528 * can be started.
8529 *
8530 * hw - The pointer to the hw structure
8531 ****************************************************************************/
8532int32_t
8533e1000_ich8_cycle_init(struct e1000_hw *hw)
8534{
8535 union ich8_hws_flash_status hsfsts;
8536 int32_t error = E1000_ERR_EEPROM;
8537 int32_t i = 0;
8538
8539 DEBUGFUNC("e1000_ich8_cycle_init");
8540
8541 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8542
8543 /* May be check the Flash Des Valid bit in Hw status */
8544 if (hsfsts.hsf_status.fldesvalid == 0) {
8545 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8546 return error;
8547 }
8548
8549 /* Clear FCERR in Hw status by writing 1 */
8550 /* Clear DAEL in Hw status by writing a 1 */
8551 hsfsts.hsf_status.flcerr = 1;
8552 hsfsts.hsf_status.dael = 1;
8553
8554 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8555
8556 /* Either we should have a hardware SPI cycle in progress bit to check
8557 * against, in order to start a new cycle or FDONE bit should be changed
8558 * in the hardware so that it is 1 after harware reset, which can then be
8559 * used as an indication whether a cycle is in progress or has been
8560 * completed .. we should also have some software semaphore mechanism to
8561 * guard FDONE or the cycle in progress bit so that two threads access to
8562 * those bits can be sequentiallized or a way so that 2 threads dont
8563 * start the cycle at the same time */
8564
8565 if (hsfsts.hsf_status.flcinprog == 0) {
8566 /* There is no cycle running at present, so we can start a cycle */
8567 /* Begin by setting Flash Cycle Done. */
8568 hsfsts.hsf_status.flcdone = 1;
8569 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8570 error = E1000_SUCCESS;
8571 } else {
8572 /* otherwise poll for sometime so the current cycle has a chance
8573 * to end before giving up. */
8574 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8575 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8576 if (hsfsts.hsf_status.flcinprog == 0) {
8577 error = E1000_SUCCESS;
8578 break;
8579 }
8580 udelay(1);
8581 }
8582 if (error == E1000_SUCCESS) {
8583 /* Successful in waiting for previous cycle to timeout,
8584 * now set the Flash Cycle Done. */
8585 hsfsts.hsf_status.flcdone = 1;
8586 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8587 } else {
8588 DEBUGOUT("Flash controller busy, cannot get access");
8589 }
8590 }
8591 return error;
8592}
8593
8594/******************************************************************************
8595 * This function starts a flash cycle and waits for its completion
8596 *
8597 * hw - The pointer to the hw structure
8598 ****************************************************************************/
8599int32_t
8600e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8601{
8602 union ich8_hws_flash_ctrl hsflctl;
8603 union ich8_hws_flash_status hsfsts;
8604 int32_t error = E1000_ERR_EEPROM;
8605 uint32_t i = 0;
8606
8607 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8608 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8609 hsflctl.hsf_ctrl.flcgo = 1;
8610 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8611
8612 /* wait till FDONE bit is set to 1 */
8613 do {
8614 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8615 if (hsfsts.hsf_status.flcdone == 1)
8616 break;
8617 udelay(1);
8618 i++;
8619 } while (i < timeout);
8620 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8621 error = E1000_SUCCESS;
8622 }
8623 return error;
8624}
8625
8626/******************************************************************************
8627 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8628 *
8629 * hw - The pointer to the hw structure
8630 * index - The index of the byte or word to read.
8631 * size - Size of data to read, 1=byte 2=word
8632 * data - Pointer to the word to store the value read.
8633 *****************************************************************************/
8634int32_t
8635e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8636 uint32_t size, uint16_t* data)
8637{
8638 union ich8_hws_flash_status hsfsts;
8639 union ich8_hws_flash_ctrl hsflctl;
8640 uint32_t flash_linear_address;
8641 uint32_t flash_data = 0;
8642 int32_t error = -E1000_ERR_EEPROM;
8643 int32_t count = 0;
8644
8645 DEBUGFUNC("e1000_read_ich8_data");
8646
8647 if (size < 1 || size > 2 || data == 0x0 ||
8648 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8649 return error;
8650
8651 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8652 hw->flash_base_addr;
8653
8654 do {
8655 udelay(1);
8656 /* Steps */
8657 error = e1000_ich8_cycle_init(hw);
8658 if (error != E1000_SUCCESS)
8659 break;
8660
8661 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8662 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8663 hsflctl.hsf_ctrl.fldbcount = size - 1;
8664 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8665 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8666
8667 /* Write the last 24 bits of index into Flash Linear address field in
8668 * Flash Address */
8669 /* TODO: TBD maybe check the index against the size of flash */
8670
8671 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8672
8673 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8674
8675 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8676 * sequence a few more times, else read in (shift in) the Flash Data0,
8677 * the order is least significant byte first msb to lsb */
8678 if (error == E1000_SUCCESS) {
8679 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8680 if (size == 1) {
8681 *data = (uint8_t)(flash_data & 0x000000FF);
8682 } else if (size == 2) {
8683 *data = (uint16_t)(flash_data & 0x0000FFFF);
8684 }
8685 break;
8686 } else {
8687 /* If we've gotten here, then things are probably completely hosed,
8688 * but if the error condition is detected, it won't hurt to give
8689 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8690 */
8691 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8692 if (hsfsts.hsf_status.flcerr == 1) {
8693 /* Repeat for some time before giving up. */
8694 continue;
8695 } else if (hsfsts.hsf_status.flcdone == 0) {
8696 DEBUGOUT("Timeout error - flash cycle did not complete.");
8697 break;
8698 }
8699 }
8700 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8701
8702 return error;
8703}
8704
8705/******************************************************************************
8706 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8707 *
8708 * hw - The pointer to the hw structure
8709 * index - The index of the byte/word to read.
8710 * size - Size of data to read, 1=byte 2=word
8711 * data - The byte(s) to write to the NVM.
8712 *****************************************************************************/
8713int32_t
8714e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8715 uint16_t data)
8716{
8717 union ich8_hws_flash_status hsfsts;
8718 union ich8_hws_flash_ctrl hsflctl;
8719 uint32_t flash_linear_address;
8720 uint32_t flash_data = 0;
8721 int32_t error = -E1000_ERR_EEPROM;
8722 int32_t count = 0;
8723
8724 DEBUGFUNC("e1000_write_ich8_data");
8725
8726 if (size < 1 || size > 2 || data > size * 0xff ||
8727 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8728 return error;
8729
8730 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8731 hw->flash_base_addr;
8732
8733 do {
8734 udelay(1);
8735 /* Steps */
8736 error = e1000_ich8_cycle_init(hw);
8737 if (error != E1000_SUCCESS)
8738 break;
8739
8740 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8741 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8742 hsflctl.hsf_ctrl.fldbcount = size -1;
8743 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8744 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8745
8746 /* Write the last 24 bits of index into Flash Linear address field in
8747 * Flash Address */
8748 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8749
8750 if (size == 1)
8751 flash_data = (uint32_t)data & 0x00FF;
8752 else
8753 flash_data = (uint32_t)data;
8754
8755 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8756
8757 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8758 * sequence a few more times else done */
8759 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8760 if (error == E1000_SUCCESS) {
8761 break;
8762 } else {
8763 /* If we're here, then things are most likely completely hosed,
8764 * but if the error condition is detected, it won't hurt to give
8765 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8766 */
8767 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8768 if (hsfsts.hsf_status.flcerr == 1) {
8769 /* Repeat for some time before giving up. */
8770 continue;
8771 } else if (hsfsts.hsf_status.flcdone == 0) {
8772 DEBUGOUT("Timeout error - flash cycle did not complete.");
8773 break;
8774 }
8775 }
8776 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8777
8778 return error;
8779}
8780
8781/******************************************************************************
8782 * Reads a single byte from the NVM using the ICH8 flash access registers.
8783 *
8784 * hw - pointer to e1000_hw structure
8785 * index - The index of the byte to read.
8786 * data - Pointer to a byte to store the value read.
8787 *****************************************************************************/
8788int32_t
8789e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8790{
8791 int32_t status = E1000_SUCCESS;
8792 uint16_t word = 0;
8793
8794 status = e1000_read_ich8_data(hw, index, 1, &word);
8795 if (status == E1000_SUCCESS) {
8796 *data = (uint8_t)word;
8797 }
8798
8799 return status;
8800}
8801
8802/******************************************************************************
8803 * Writes a single byte to the NVM using the ICH8 flash access registers.
8804 * Performs verification by reading back the value and then going through
8805 * a retry algorithm before giving up.
8806 *
8807 * hw - pointer to e1000_hw structure
8808 * index - The index of the byte to write.
8809 * byte - The byte to write to the NVM.
8810 *****************************************************************************/
8811int32_t
8812e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8813{
8814 int32_t error = E1000_SUCCESS;
8815 int32_t program_retries;
8816 uint8_t temp_byte;
8817
8818 e1000_write_ich8_byte(hw, index, byte);
8819 udelay(100);
8820
8821 for (program_retries = 0; program_retries < 100; program_retries++) {
8822 e1000_read_ich8_byte(hw, index, &temp_byte);
8823 if (temp_byte == byte)
8824 break;
8825 udelay(10);
8826 e1000_write_ich8_byte(hw, index, byte);
8827 udelay(100);
8828 }
8829 if (program_retries == 100)
8830 error = E1000_ERR_EEPROM;
8831
8832 return error;
8833}
8834
8835/******************************************************************************
8836 * Writes a single byte to the NVM using the ICH8 flash access registers.
8837 *
8838 * hw - pointer to e1000_hw structure
8839 * index - The index of the byte to read.
8840 * data - The byte to write to the NVM.
8841 *****************************************************************************/
8842int32_t
8843e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8844{
8845 int32_t status = E1000_SUCCESS;
8846 uint16_t word = (uint16_t)data;
8847
8848 status = e1000_write_ich8_data(hw, index, 1, word);
8849
8850 return status;
8851}
8852
8853/******************************************************************************
8854 * Reads a word from the NVM using the ICH8 flash access registers.
8855 *
8856 * hw - pointer to e1000_hw structure
8857 * index - The starting byte index of the word to read.
8858 * data - Pointer to a word to store the value read.
8859 *****************************************************************************/
8860int32_t
8861e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8862{
8863 int32_t status = E1000_SUCCESS;
8864 status = e1000_read_ich8_data(hw, index, 2, data);
8865 return status;
8866}
8867
8868/******************************************************************************
8869 * Writes a word to the NVM using the ICH8 flash access registers.
8870 *
8871 * hw - pointer to e1000_hw structure
8872 * index - The starting byte index of the word to read.
8873 * data - The word to write to the NVM.
8874 *****************************************************************************/
8875int32_t
8876e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8877{
8878 int32_t status = E1000_SUCCESS;
8879 status = e1000_write_ich8_data(hw, index, 2, data);
8880 return status;
8881}
8882
8883/******************************************************************************
8884 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8885 * segment N is 4096 * N + flash_reg_addr.
8886 *
8887 * hw - pointer to e1000_hw structure
8888 * segment - 0 for first segment, 1 for second segment, etc.
8889 *****************************************************************************/
8890int32_t
8891e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8892{
8893 union ich8_hws_flash_status hsfsts;
8894 union ich8_hws_flash_ctrl hsflctl;
8895 uint32_t flash_linear_address;
8896 int32_t count = 0;
8897 int32_t error = E1000_ERR_EEPROM;
8898 int32_t iteration, seg_size;
8899 int32_t sector_size;
8900 int32_t j = 0;
8901 int32_t error_flag = 0;
8902
8903 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8904
8905 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8906 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8907 * consecutive sectors. The start index for the nth Hw sector can be
8908 * calculated as = segment * 4096 + n * 256
8909 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8910 * The start index for the nth Hw sector can be calculated
8911 * as = segment * 4096
8912 * 10: Error condition
8913 * 11: The Hw sector size is much bigger than the size asked to
8914 * erase...error condition */
8915 if (hsfsts.hsf_status.berasesz == 0x0) {
8916 /* Hw sector size 256 */
8917 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8918 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8919 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8920 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8921 iteration = 1;
8922 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8923 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8924 iteration = 1;
8925 } else {
8926 return error;
8927 }
8928
8929 for (j = 0; j < iteration ; j++) {
8930 do {
8931 count++;
8932 /* Steps */
8933 error = e1000_ich8_cycle_init(hw);
8934 if (error != E1000_SUCCESS) {
8935 error_flag = 1;
8936 break;
8937 }
8938
8939 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8940 * Control */
8941 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8942 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8943 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8944
8945 /* Write the last 24 bits of an index within the block into Flash
8946 * Linear address field in Flash Address. This probably needs to
8947 * be calculated here based off the on-chip segment size and the
8948 * software segment size assumed (4K) */
8949 /* TBD */
8950 flash_linear_address = segment * sector_size + j * seg_size;
8951 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8952 flash_linear_address += hw->flash_base_addr;
8953
8954 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8955
8956 error = e1000_ich8_flash_cycle(hw, 1000000);
8957 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8958 * sequence a few more times else Done */
8959 if (error == E1000_SUCCESS) {
8960 break;
8961 } else {
8962 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8963 if (hsfsts.hsf_status.flcerr == 1) {
8964 /* repeat for some time before giving up */
8965 continue;
8966 } else if (hsfsts.hsf_status.flcdone == 0) {
8967 error_flag = 1;
8968 break;
8969 }
8970 }
8971 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8972 if (error_flag == 1)
8973 break;
8974 }
8975 if (error_flag != 1)
8976 error = E1000_SUCCESS;
8977 return error;
8978}
8979
8980/******************************************************************************
8981 *
8982 * Reverse duplex setting without breaking the link.
8983 *
8984 * hw: Struct containing variables accessed by shared code
8985 *
8986 *****************************************************************************/
8987int32_t
8988e1000_duplex_reversal(struct e1000_hw *hw)
8989{
8990 int32_t ret_val;
8991 uint16_t phy_data;
8992
8993 if (hw->phy_type != e1000_phy_igp_3)
8994 return E1000_SUCCESS;
8995
8996 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8997 if (ret_val)
8998 return ret_val;
8999
9000 phy_data ^= MII_CR_FULL_DUPLEX;
9001
9002 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9003 if (ret_val)
9004 return ret_val;
9005
9006 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9007 if (ret_val)
9008 return ret_val;
9009
9010 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9011 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9012
9013 return ret_val;
9014}
9015
9016int32_t
9017e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9018 uint32_t cnf_base_addr, uint32_t cnf_size)
9019{
9020 uint32_t ret_val = E1000_SUCCESS;
9021 uint16_t word_addr, reg_data, reg_addr;
9022 uint16_t i;
9023
9024 /* cnf_base_addr is in DWORD */
9025 word_addr = (uint16_t)(cnf_base_addr << 1);
9026
9027 /* cnf_size is returned in size of dwords */
9028 for (i = 0; i < cnf_size; i++) {
9029 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9030 if (ret_val)
9031 return ret_val;
9032
9033 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9034 if (ret_val)
9035 return ret_val;
9036
9037 ret_val = e1000_get_software_flag(hw);
9038 if (ret_val != E1000_SUCCESS)
9039 return ret_val;
9040
9041 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9042
9043 e1000_release_software_flag(hw);
9044 }
9045
9046 return ret_val;
9047}
9048
9049
9050int32_t
9051e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9052{
9053 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9054
9055 if (hw->phy_type != e1000_phy_igp_3)
9056 return E1000_SUCCESS;
9057
9058 /* Check if SW needs configure the PHY */
9059 reg_data = E1000_READ_REG(hw, FEXTNVM);
9060 if (!(reg_data & FEXTNVM_SW_CONFIG))
9061 return E1000_SUCCESS;
9062
9063 /* Wait for basic configuration completes before proceeding*/
9064 loop = 0;
9065 do {
9066 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9067 udelay(100);
9068 loop++;
9069 } while ((!reg_data) && (loop < 50));
9070
9071 /* Clear the Init Done bit for the next init event */
9072 reg_data = E1000_READ_REG(hw, STATUS);
9073 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9074 E1000_WRITE_REG(hw, STATUS, reg_data);
9075
9076 /* Make sure HW does not configure LCD from PHY extended configuration
9077 before SW configuration */
9078 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9079 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9080 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9081 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9082 cnf_size >>= 16;
9083 if (cnf_size) {
9084 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9085 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9086 /* cnf_base_addr is in DWORD */
9087 cnf_base_addr >>= 16;
9088
9089 /* Configure LCD from extended configuration region. */
9090 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9091 cnf_size);
9092 if (ret_val)
9093 return ret_val;
9094 }
9095 }
9096
9097 return E1000_SUCCESS;
9098}
9099
9100
7559 9101
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 09:33:22 -0500