diff options
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r-- | drivers/net/e1000/e1000_hw.c | 406 |
1 files changed, 81 insertions, 325 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 8a7d7da4cd61..6ec5cdddb5aa 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -33,6 +33,62 @@ | |||
33 | 33 | ||
34 | #include "e1000_hw.h" | 34 | #include "e1000_hw.h" |
35 | 35 | ||
36 | static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); | ||
37 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); | ||
38 | static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); | ||
39 | static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); | ||
40 | static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); | ||
41 | static void e1000_release_software_semaphore(struct e1000_hw *hw); | ||
42 | |||
43 | static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); | ||
44 | static int32_t e1000_check_downshift(struct e1000_hw *hw); | ||
45 | static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); | ||
46 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); | ||
47 | static void e1000_clear_vfta(struct e1000_hw *hw); | ||
48 | static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); | ||
49 | static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); | ||
50 | static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); | ||
51 | static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); | ||
52 | static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); | ||
53 | static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); | ||
54 | static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); | ||
55 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
56 | static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); | ||
57 | static int32_t e1000_get_software_flag(struct e1000_hw *hw); | ||
58 | static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); | ||
59 | static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); | ||
60 | static int32_t e1000_id_led_init(struct e1000_hw *hw); | ||
61 | static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); | ||
62 | static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); | ||
63 | static void e1000_init_rx_addrs(struct e1000_hw *hw); | ||
64 | static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); | ||
65 | static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); | ||
66 | static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); | ||
67 | static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); | ||
68 | static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); | ||
69 | static int32_t e1000_mng_write_commit(struct e1000_hw *hw); | ||
70 | static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | ||
71 | static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | ||
72 | static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | ||
73 | static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | ||
74 | static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); | ||
75 | static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | ||
76 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
77 | static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); | ||
78 | static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); | ||
79 | static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); | ||
80 | static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); | ||
81 | static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); | ||
82 | static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); | ||
83 | static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | ||
84 | static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | ||
85 | static void e1000_release_software_flag(struct e1000_hw *hw); | ||
86 | static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | ||
87 | static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); | ||
88 | static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); | ||
89 | static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); | ||
90 | static int32_t e1000_wait_autoneg(struct e1000_hw *hw); | ||
91 | static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); | ||
36 | static int32_t e1000_set_phy_type(struct e1000_hw *hw); | 92 | static int32_t e1000_set_phy_type(struct e1000_hw *hw); |
37 | static void e1000_phy_init_script(struct e1000_hw *hw); | 93 | static void e1000_phy_init_script(struct e1000_hw *hw); |
38 | static int32_t e1000_setup_copper_link(struct e1000_hw *hw); | 94 | static int32_t e1000_setup_copper_link(struct e1000_hw *hw); |
@@ -69,69 +125,10 @@ static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); | |||
69 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); | 125 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); |
70 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); | 126 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
71 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); | 127 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); |
72 | static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); | ||
73 | static int32_t e1000_check_downshift(struct e1000_hw *hw); | ||
74 | static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); | ||
75 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); | ||
76 | static void e1000_clear_vfta(struct e1000_hw *hw); | ||
77 | static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); | ||
78 | static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, | ||
79 | boolean_t link_up); | ||
80 | static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); | ||
81 | static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); | ||
82 | static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); | ||
83 | static int32_t e1000_get_cable_length(struct e1000_hw *hw, | ||
84 | uint16_t *min_length, | ||
85 | uint16_t *max_length); | ||
86 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
87 | static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); | ||
88 | static int32_t e1000_id_led_init(struct e1000_hw * hw); | ||
89 | static void e1000_init_rx_addrs(struct e1000_hw *hw); | ||
90 | static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); | ||
91 | static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); | ||
92 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
93 | static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, | ||
94 | uint16_t words, uint16_t *data); | ||
95 | static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); | ||
96 | static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | ||
97 | static int32_t e1000_wait_autoneg(struct e1000_hw *hw); | ||
98 | |||
99 | static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, | ||
100 | uint32_t value); | ||
101 | |||
102 | #define E1000_WRITE_REG_IO(a, reg, val) \ | ||
103 | e1000_write_reg_io((a), E1000_##reg, val) | ||
104 | static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, | 128 | static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, |
105 | uint16_t duplex); | 129 | uint16_t duplex); |
106 | static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); | 130 | static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); |
107 | 131 | ||
108 | static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, | ||
109 | uint32_t segment); | ||
110 | static int32_t e1000_get_software_flag(struct e1000_hw *hw); | ||
111 | static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); | ||
112 | static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); | ||
113 | static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); | ||
114 | static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, | ||
115 | uint16_t words, uint16_t *data); | ||
116 | static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, | ||
117 | uint8_t* data); | ||
118 | static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, | ||
119 | uint16_t *data); | ||
120 | static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, | ||
121 | uint16_t *data); | ||
122 | static void e1000_release_software_flag(struct e1000_hw *hw); | ||
123 | static void e1000_release_software_semaphore(struct e1000_hw *hw); | ||
124 | static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, | ||
125 | uint32_t no_snoop); | ||
126 | static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, | ||
127 | uint32_t index, uint8_t byte); | ||
128 | static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, | ||
129 | uint16_t words, uint16_t *data); | ||
130 | static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, | ||
131 | uint8_t data); | ||
132 | static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, | ||
133 | uint16_t data); | ||
134 | |||
135 | /* IGP cable length table */ | 132 | /* IGP cable length table */ |
136 | static const | 133 | static const |
137 | uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = | 134 | uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = |
@@ -155,13 +152,12 @@ uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = | |||
155 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | 152 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, |
156 | 104, 109, 114, 118, 121, 124}; | 153 | 104, 109, 114, 118, 121, 124}; |
157 | 154 | ||
158 | |||
159 | /****************************************************************************** | 155 | /****************************************************************************** |
160 | * Set the phy type member in the hw struct. | 156 | * Set the phy type member in the hw struct. |
161 | * | 157 | * |
162 | * hw - Struct containing variables accessed by shared code | 158 | * hw - Struct containing variables accessed by shared code |
163 | *****************************************************************************/ | 159 | *****************************************************************************/ |
164 | int32_t | 160 | static int32_t |
165 | e1000_set_phy_type(struct e1000_hw *hw) | 161 | e1000_set_phy_type(struct e1000_hw *hw) |
166 | { | 162 | { |
167 | DEBUGFUNC("e1000_set_phy_type"); | 163 | DEBUGFUNC("e1000_set_phy_type"); |
@@ -207,7 +203,6 @@ e1000_set_phy_type(struct e1000_hw *hw) | |||
207 | return E1000_SUCCESS; | 203 | return E1000_SUCCESS; |
208 | } | 204 | } |
209 | 205 | ||
210 | |||
211 | /****************************************************************************** | 206 | /****************************************************************************** |
212 | * IGP phy init script - initializes the GbE PHY | 207 | * IGP phy init script - initializes the GbE PHY |
213 | * | 208 | * |
@@ -3416,9 +3411,8 @@ e1000_read_phy_reg(struct e1000_hw *hw, | |||
3416 | return ret_val; | 3411 | return ret_val; |
3417 | } | 3412 | } |
3418 | 3413 | ||
3419 | int32_t | 3414 | static int32_t |
3420 | e1000_read_phy_reg_ex(struct e1000_hw *hw, | 3415 | e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
3421 | uint32_t reg_addr, | ||
3422 | uint16_t *phy_data) | 3416 | uint16_t *phy_data) |
3423 | { | 3417 | { |
3424 | uint32_t i; | 3418 | uint32_t i; |
@@ -3498,8 +3492,7 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, | |||
3498 | * data - data to write to the PHY | 3492 | * data - data to write to the PHY |
3499 | ******************************************************************************/ | 3493 | ******************************************************************************/ |
3500 | int32_t | 3494 | int32_t |
3501 | e1000_write_phy_reg(struct e1000_hw *hw, | 3495 | e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, |
3502 | uint32_t reg_addr, | ||
3503 | uint16_t phy_data) | 3496 | uint16_t phy_data) |
3504 | { | 3497 | { |
3505 | uint32_t ret_val; | 3498 | uint32_t ret_val; |
@@ -3556,10 +3549,9 @@ e1000_write_phy_reg(struct e1000_hw *hw, | |||
3556 | return ret_val; | 3549 | return ret_val; |
3557 | } | 3550 | } |
3558 | 3551 | ||
3559 | int32_t | 3552 | static int32_t |
3560 | e1000_write_phy_reg_ex(struct e1000_hw *hw, | 3553 | e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
3561 | uint32_t reg_addr, | 3554 | uint16_t phy_data) |
3562 | uint16_t phy_data) | ||
3563 | { | 3555 | { |
3564 | uint32_t i; | 3556 | uint32_t i; |
3565 | uint32_t mdic = 0; | 3557 | uint32_t mdic = 0; |
@@ -3733,6 +3725,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw) | |||
3733 | 3725 | ||
3734 | if (hw->mac_type >= e1000_82571) | 3726 | if (hw->mac_type >= e1000_82571) |
3735 | mdelay(10); | 3727 | mdelay(10); |
3728 | |||
3736 | e1000_swfw_sync_release(hw, swfw); | 3729 | e1000_swfw_sync_release(hw, swfw); |
3737 | } else { | 3730 | } else { |
3738 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | 3731 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
@@ -3799,7 +3792,6 @@ e1000_phy_reset(struct e1000_hw *hw) | |||
3799 | ret_val = e1000_phy_hw_reset(hw); | 3792 | ret_val = e1000_phy_hw_reset(hw); |
3800 | if (ret_val) | 3793 | if (ret_val) |
3801 | return ret_val; | 3794 | return ret_val; |
3802 | |||
3803 | break; | 3795 | break; |
3804 | default: | 3796 | default: |
3805 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | 3797 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
@@ -3935,7 +3927,7 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) | |||
3935 | * | 3927 | * |
3936 | * hw - Struct containing variables accessed by shared code | 3928 | * hw - Struct containing variables accessed by shared code |
3937 | ******************************************************************************/ | 3929 | ******************************************************************************/ |
3938 | int32_t | 3930 | static int32_t |
3939 | e1000_detect_gig_phy(struct e1000_hw *hw) | 3931 | e1000_detect_gig_phy(struct e1000_hw *hw) |
3940 | { | 3932 | { |
3941 | int32_t phy_init_status, ret_val; | 3933 | int32_t phy_init_status, ret_val; |
@@ -4452,7 +4444,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw) | |||
4452 | eeprom->use_eewr = FALSE; | 4444 | eeprom->use_eewr = FALSE; |
4453 | break; | 4445 | break; |
4454 | case e1000_ich8lan: | 4446 | case e1000_ich8lan: |
4455 | { | 4447 | { |
4456 | int32_t i = 0; | 4448 | int32_t i = 0; |
4457 | uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG); | 4449 | uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG); |
4458 | 4450 | ||
@@ -4479,7 +4471,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw) | |||
4479 | hw->flash_bank_size /= 2 * sizeof(uint16_t); | 4471 | hw->flash_bank_size /= 2 * sizeof(uint16_t); |
4480 | 4472 | ||
4481 | break; | 4473 | break; |
4482 | } | 4474 | } |
4483 | default: | 4475 | default: |
4484 | break; | 4476 | break; |
4485 | } | 4477 | } |
@@ -4811,7 +4803,7 @@ e1000_release_eeprom(struct e1000_hw *hw) | |||
4811 | * | 4803 | * |
4812 | * hw - Struct containing variables accessed by shared code | 4804 | * hw - Struct containing variables accessed by shared code |
4813 | *****************************************************************************/ | 4805 | *****************************************************************************/ |
4814 | int32_t | 4806 | static int32_t |
4815 | e1000_spi_eeprom_ready(struct e1000_hw *hw) | 4807 | e1000_spi_eeprom_ready(struct e1000_hw *hw) |
4816 | { | 4808 | { |
4817 | uint16_t retry_count = 0; | 4809 | uint16_t retry_count = 0; |
@@ -5259,7 +5251,7 @@ e1000_write_eeprom(struct e1000_hw *hw, | |||
5259 | * data - pointer to array of 8 bit words to be written to the EEPROM | 5251 | * data - pointer to array of 8 bit words to be written to the EEPROM |
5260 | * | 5252 | * |
5261 | *****************************************************************************/ | 5253 | *****************************************************************************/ |
5262 | int32_t | 5254 | static int32_t |
5263 | e1000_write_eeprom_spi(struct e1000_hw *hw, | 5255 | e1000_write_eeprom_spi(struct e1000_hw *hw, |
5264 | uint16_t offset, | 5256 | uint16_t offset, |
5265 | uint16_t words, | 5257 | uint16_t words, |
@@ -5325,7 +5317,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw, | |||
5325 | * data - pointer to array of 16 bit words to be written to the EEPROM | 5317 | * data - pointer to array of 16 bit words to be written to the EEPROM |
5326 | * | 5318 | * |
5327 | *****************************************************************************/ | 5319 | *****************************************************************************/ |
5328 | int32_t | 5320 | static int32_t |
5329 | e1000_write_eeprom_microwire(struct e1000_hw *hw, | 5321 | e1000_write_eeprom_microwire(struct e1000_hw *hw, |
5330 | uint16_t offset, | 5322 | uint16_t offset, |
5331 | uint16_t words, | 5323 | uint16_t words, |
@@ -5651,99 +5643,6 @@ e1000_init_rx_addrs(struct e1000_hw *hw) | |||
5651 | } | 5643 | } |
5652 | 5644 | ||
5653 | /****************************************************************************** | 5645 | /****************************************************************************** |
5654 | * Updates the MAC's list of multicast addresses. | ||
5655 | * | ||
5656 | * hw - Struct containing variables accessed by shared code | ||
5657 | * mc_addr_list - the list of new multicast addresses | ||
5658 | * mc_addr_count - number of addresses | ||
5659 | * pad - number of bytes between addresses in the list | ||
5660 | * rar_used_count - offset where to start adding mc addresses into the RAR's | ||
5661 | * | ||
5662 | * The given list replaces any existing list. Clears the last 15 receive | ||
5663 | * address registers and the multicast table. Uses receive address registers | ||
5664 | * for the first 15 multicast addresses, and hashes the rest into the | ||
5665 | * multicast table. | ||
5666 | *****************************************************************************/ | ||
5667 | #if 0 | ||
5668 | void | ||
5669 | e1000_mc_addr_list_update(struct e1000_hw *hw, | ||
5670 | uint8_t *mc_addr_list, | ||
5671 | uint32_t mc_addr_count, | ||
5672 | uint32_t pad, | ||
5673 | uint32_t rar_used_count) | ||
5674 | { | ||
5675 | uint32_t hash_value; | ||
5676 | uint32_t i; | ||
5677 | uint32_t num_rar_entry; | ||
5678 | uint32_t num_mta_entry; | ||
5679 | |||
5680 | DEBUGFUNC("e1000_mc_addr_list_update"); | ||
5681 | |||
5682 | /* Set the new number of MC addresses that we are being requested to use. */ | ||
5683 | hw->num_mc_addrs = mc_addr_count; | ||
5684 | |||
5685 | /* Clear RAR[1-15] */ | ||
5686 | DEBUGOUT(" Clearing RAR[1-15]\n"); | ||
5687 | num_rar_entry = E1000_RAR_ENTRIES; | ||
5688 | if (hw->mac_type == e1000_ich8lan) | ||
5689 | num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; | ||
5690 | /* Reserve a spot for the Locally Administered Address to work around | ||
5691 | * an 82571 issue in which a reset on one port will reload the MAC on | ||
5692 | * the other port. */ | ||
5693 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) | ||
5694 | num_rar_entry -= 1; | ||
5695 | |||
5696 | for (i = rar_used_count; i < num_rar_entry; i++) { | ||
5697 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); | ||
5698 | E1000_WRITE_FLUSH(hw); | ||
5699 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | ||
5700 | E1000_WRITE_FLUSH(hw); | ||
5701 | } | ||
5702 | |||
5703 | /* Clear the MTA */ | ||
5704 | DEBUGOUT(" Clearing MTA\n"); | ||
5705 | num_mta_entry = E1000_NUM_MTA_REGISTERS; | ||
5706 | if (hw->mac_type == e1000_ich8lan) | ||
5707 | num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; | ||
5708 | for (i = 0; i < num_mta_entry; i++) { | ||
5709 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); | ||
5710 | E1000_WRITE_FLUSH(hw); | ||
5711 | } | ||
5712 | |||
5713 | /* Add the new addresses */ | ||
5714 | for (i = 0; i < mc_addr_count; i++) { | ||
5715 | DEBUGOUT(" Adding the multicast addresses:\n"); | ||
5716 | DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, | ||
5717 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], | ||
5718 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], | ||
5719 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], | ||
5720 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], | ||
5721 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], | ||
5722 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); | ||
5723 | |||
5724 | hash_value = e1000_hash_mc_addr(hw, | ||
5725 | mc_addr_list + | ||
5726 | (i * (ETH_LENGTH_OF_ADDRESS + pad))); | ||
5727 | |||
5728 | DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); | ||
5729 | |||
5730 | /* Place this multicast address in the RAR if there is room, * | ||
5731 | * else put it in the MTA | ||
5732 | */ | ||
5733 | if (rar_used_count < num_rar_entry) { | ||
5734 | e1000_rar_set(hw, | ||
5735 | mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), | ||
5736 | rar_used_count); | ||
5737 | rar_used_count++; | ||
5738 | } else { | ||
5739 | e1000_mta_set(hw, hash_value); | ||
5740 | } | ||
5741 | } | ||
5742 | DEBUGOUT("MC Update Complete\n"); | ||
5743 | } | ||
5744 | #endif /* 0 */ | ||
5745 | |||
5746 | /****************************************************************************** | ||
5747 | * Hashes an address to determine its location in the multicast table | 5646 | * Hashes an address to determine its location in the multicast table |
5748 | * | 5647 | * |
5749 | * hw - Struct containing variables accessed by shared code | 5648 | * hw - Struct containing variables accessed by shared code |
@@ -6301,7 +6200,7 @@ e1000_led_off(struct e1000_hw *hw) | |||
6301 | * | 6200 | * |
6302 | * hw - Struct containing variables accessed by shared code | 6201 | * hw - Struct containing variables accessed by shared code |
6303 | *****************************************************************************/ | 6202 | *****************************************************************************/ |
6304 | void | 6203 | static void |
6305 | e1000_clear_hw_cntrs(struct e1000_hw *hw) | 6204 | e1000_clear_hw_cntrs(struct e1000_hw *hw) |
6306 | { | 6205 | { |
6307 | volatile uint32_t temp; | 6206 | volatile uint32_t temp; |
@@ -6604,25 +6503,6 @@ e1000_get_bus_info(struct e1000_hw *hw) | |||
6604 | break; | 6503 | break; |
6605 | } | 6504 | } |
6606 | } | 6505 | } |
6607 | /****************************************************************************** | ||
6608 | * Reads a value from one of the devices registers using port I/O (as opposed | ||
6609 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | ||
6610 | * | ||
6611 | * hw - Struct containing variables accessed by shared code | ||
6612 | * offset - offset to read from | ||
6613 | *****************************************************************************/ | ||
6614 | #if 0 | ||
6615 | uint32_t | ||
6616 | e1000_read_reg_io(struct e1000_hw *hw, | ||
6617 | uint32_t offset) | ||
6618 | { | ||
6619 | unsigned long io_addr = hw->io_base; | ||
6620 | unsigned long io_data = hw->io_base + 4; | ||
6621 | |||
6622 | e1000_io_write(hw, io_addr, offset); | ||
6623 | return e1000_io_read(hw, io_data); | ||
6624 | } | ||
6625 | #endif /* 0 */ | ||
6626 | 6506 | ||
6627 | /****************************************************************************** | 6507 | /****************************************************************************** |
6628 | * Writes a value to one of the devices registers using port I/O (as opposed to | 6508 | * Writes a value to one of the devices registers using port I/O (as opposed to |
@@ -6644,7 +6524,6 @@ e1000_write_reg_io(struct e1000_hw *hw, | |||
6644 | e1000_io_write(hw, io_data, value); | 6524 | e1000_io_write(hw, io_data, value); |
6645 | } | 6525 | } |
6646 | 6526 | ||
6647 | |||
6648 | /****************************************************************************** | 6527 | /****************************************************************************** |
6649 | * Estimates the cable length. | 6528 | * Estimates the cable length. |
6650 | * | 6529 | * |
@@ -7275,7 +7154,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw, | |||
7275 | } else if (hw->smart_speed == e1000_smart_speed_off) { | 7154 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
7276 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | 7155 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
7277 | &phy_data); | 7156 | &phy_data); |
7278 | if (ret_val) | 7157 | if (ret_val) |
7279 | return ret_val; | 7158 | return ret_val; |
7280 | 7159 | ||
7281 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | 7160 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
@@ -7385,7 +7264,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, | |||
7385 | } else if (hw->smart_speed == e1000_smart_speed_off) { | 7264 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
7386 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | 7265 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
7387 | &phy_data); | 7266 | &phy_data); |
7388 | if (ret_val) | 7267 | if (ret_val) |
7389 | return ret_val; | 7268 | return ret_val; |
7390 | 7269 | ||
7391 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | 7270 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
@@ -7491,7 +7370,7 @@ e1000_set_vco_speed(struct e1000_hw *hw) | |||
7491 | * | 7370 | * |
7492 | * returns: - E1000_SUCCESS . | 7371 | * returns: - E1000_SUCCESS . |
7493 | ****************************************************************************/ | 7372 | ****************************************************************************/ |
7494 | int32_t | 7373 | static int32_t |
7495 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) | 7374 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) |
7496 | { | 7375 | { |
7497 | uint8_t i; | 7376 | uint8_t i; |
@@ -7702,7 +7581,7 @@ e1000_check_mng_mode(struct e1000_hw *hw) | |||
7702 | ****************************************************************************/ | 7581 | ****************************************************************************/ |
7703 | int32_t | 7582 | int32_t |
7704 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, | 7583 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, |
7705 | uint16_t length) | 7584 | uint16_t length) |
7706 | { | 7585 | { |
7707 | int32_t ret_val; | 7586 | int32_t ret_val; |
7708 | struct e1000_host_mng_command_header hdr; | 7587 | struct e1000_host_mng_command_header hdr; |
@@ -7732,7 +7611,7 @@ e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, | |||
7732 | * | 7611 | * |
7733 | * returns - checksum of buffer contents. | 7612 | * returns - checksum of buffer contents. |
7734 | ****************************************************************************/ | 7613 | ****************************************************************************/ |
7735 | uint8_t | 7614 | static uint8_t |
7736 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) | 7615 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) |
7737 | { | 7616 | { |
7738 | uint8_t sum = 0; | 7617 | uint8_t sum = 0; |
@@ -7930,32 +7809,6 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw) | |||
7930 | E1000_WRITE_REG(hw, CTRL, ctrl); | 7809 | E1000_WRITE_REG(hw, CTRL, ctrl); |
7931 | } | 7810 | } |
7932 | 7811 | ||
7933 | /*************************************************************************** | ||
7934 | * | ||
7935 | * Enables PCI-Express master access. | ||
7936 | * | ||
7937 | * hw: Struct containing variables accessed by shared code | ||
7938 | * | ||
7939 | * returns: - none. | ||
7940 | * | ||
7941 | ***************************************************************************/ | ||
7942 | #if 0 | ||
7943 | void | ||
7944 | e1000_enable_pciex_master(struct e1000_hw *hw) | ||
7945 | { | ||
7946 | uint32_t ctrl; | ||
7947 | |||
7948 | DEBUGFUNC("e1000_enable_pciex_master"); | ||
7949 | |||
7950 | if (hw->bus_type != e1000_bus_type_pci_express) | ||
7951 | return; | ||
7952 | |||
7953 | ctrl = E1000_READ_REG(hw, CTRL); | ||
7954 | ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; | ||
7955 | E1000_WRITE_REG(hw, CTRL, ctrl); | ||
7956 | } | ||
7957 | #endif /* 0 */ | ||
7958 | |||
7959 | /******************************************************************************* | 7812 | /******************************************************************************* |
7960 | * | 7813 | * |
7961 | * Disables PCI-Express master access and verifies there are no pending requests | 7814 | * Disables PCI-Express master access and verifies there are no pending requests |
@@ -8079,7 +7932,6 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) | |||
8079 | msleep(1); | 7932 | msleep(1); |
8080 | timeout--; | 7933 | timeout--; |
8081 | } | 7934 | } |
8082 | |||
8083 | if (!timeout) { | 7935 | if (!timeout) { |
8084 | DEBUGOUT("MNG configuration cycle has not completed.\n"); | 7936 | DEBUGOUT("MNG configuration cycle has not completed.\n"); |
8085 | return -E1000_ERR_RESET; | 7937 | return -E1000_ERR_RESET; |
@@ -8188,8 +8040,9 @@ e1000_get_software_semaphore(struct e1000_hw *hw) | |||
8188 | 8040 | ||
8189 | DEBUGFUNC("e1000_get_software_semaphore"); | 8041 | DEBUGFUNC("e1000_get_software_semaphore"); |
8190 | 8042 | ||
8191 | if (hw->mac_type != e1000_80003es2lan) | 8043 | if (hw->mac_type != e1000_80003es2lan) { |
8192 | return E1000_SUCCESS; | 8044 | return E1000_SUCCESS; |
8045 | } | ||
8193 | 8046 | ||
8194 | while (timeout) { | 8047 | while (timeout) { |
8195 | swsm = E1000_READ_REG(hw, SWSM); | 8048 | swsm = E1000_READ_REG(hw, SWSM); |
@@ -8222,8 +8075,9 @@ e1000_release_software_semaphore(struct e1000_hw *hw) | |||
8222 | 8075 | ||
8223 | DEBUGFUNC("e1000_release_software_semaphore"); | 8076 | DEBUGFUNC("e1000_release_software_semaphore"); |
8224 | 8077 | ||
8225 | if (hw->mac_type != e1000_80003es2lan) | 8078 | if (hw->mac_type != e1000_80003es2lan) { |
8226 | return; | 8079 | return; |
8080 | } | ||
8227 | 8081 | ||
8228 | swsm = E1000_READ_REG(hw, SWSM); | 8082 | swsm = E1000_READ_REG(hw, SWSM); |
8229 | /* Release the SW semaphores.*/ | 8083 | /* Release the SW semaphores.*/ |
@@ -8257,7 +8111,7 @@ e1000_check_phy_reset_block(struct e1000_hw *hw) | |||
8257 | if (hw->mac_type > e1000_82547_rev_2) | 8111 | if (hw->mac_type > e1000_82547_rev_2) |
8258 | manc = E1000_READ_REG(hw, MANC); | 8112 | manc = E1000_READ_REG(hw, MANC); |
8259 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | 8113 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
8260 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | 8114 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |
8261 | } | 8115 | } |
8262 | 8116 | ||
8263 | static uint8_t | 8117 | static uint8_t |
@@ -8393,66 +8247,6 @@ e1000_release_software_flag(struct e1000_hw *hw) | |||
8393 | return; | 8247 | return; |
8394 | } | 8248 | } |
8395 | 8249 | ||
8396 | /*************************************************************************** | ||
8397 | * | ||
8398 | * Disable dynamic power down mode in ife PHY. | ||
8399 | * It can be used to workaround band-gap problem. | ||
8400 | * | ||
8401 | * hw: Struct containing variables accessed by shared code | ||
8402 | * | ||
8403 | ***************************************************************************/ | ||
8404 | #if 0 | ||
8405 | int32_t | ||
8406 | e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw) | ||
8407 | { | ||
8408 | uint16_t phy_data; | ||
8409 | int32_t ret_val = E1000_SUCCESS; | ||
8410 | |||
8411 | DEBUGFUNC("e1000_ife_disable_dynamic_power_down"); | ||
8412 | |||
8413 | if (hw->phy_type == e1000_phy_ife) { | ||
8414 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | ||
8415 | if (ret_val) | ||
8416 | return ret_val; | ||
8417 | |||
8418 | phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; | ||
8419 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); | ||
8420 | } | ||
8421 | |||
8422 | return ret_val; | ||
8423 | } | ||
8424 | #endif /* 0 */ | ||
8425 | |||
8426 | /*************************************************************************** | ||
8427 | * | ||
8428 | * Enable dynamic power down mode in ife PHY. | ||
8429 | * It can be used to workaround band-gap problem. | ||
8430 | * | ||
8431 | * hw: Struct containing variables accessed by shared code | ||
8432 | * | ||
8433 | ***************************************************************************/ | ||
8434 | #if 0 | ||
8435 | int32_t | ||
8436 | e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw) | ||
8437 | { | ||
8438 | uint16_t phy_data; | ||
8439 | int32_t ret_val = E1000_SUCCESS; | ||
8440 | |||
8441 | DEBUGFUNC("e1000_ife_enable_dynamic_power_down"); | ||
8442 | |||
8443 | if (hw->phy_type == e1000_phy_ife) { | ||
8444 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | ||
8445 | if (ret_val) | ||
8446 | return ret_val; | ||
8447 | |||
8448 | phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; | ||
8449 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); | ||
8450 | } | ||
8451 | |||
8452 | return ret_val; | ||
8453 | } | ||
8454 | #endif /* 0 */ | ||
8455 | |||
8456 | /****************************************************************************** | 8250 | /****************************************************************************** |
8457 | * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access | 8251 | * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access |
8458 | * register. | 8252 | * register. |
@@ -9015,44 +8809,6 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment) | |||
9015 | return error; | 8809 | return error; |
9016 | } | 8810 | } |
9017 | 8811 | ||
9018 | /****************************************************************************** | ||
9019 | * | ||
9020 | * Reverse duplex setting without breaking the link. | ||
9021 | * | ||
9022 | * hw: Struct containing variables accessed by shared code | ||
9023 | * | ||
9024 | *****************************************************************************/ | ||
9025 | #if 0 | ||
9026 | int32_t | ||
9027 | e1000_duplex_reversal(struct e1000_hw *hw) | ||
9028 | { | ||
9029 | int32_t ret_val; | ||
9030 | uint16_t phy_data; | ||
9031 | |||
9032 | if (hw->phy_type != e1000_phy_igp_3) | ||
9033 | return E1000_SUCCESS; | ||
9034 | |||
9035 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | ||
9036 | if (ret_val) | ||
9037 | return ret_val; | ||
9038 | |||
9039 | phy_data ^= MII_CR_FULL_DUPLEX; | ||
9040 | |||
9041 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | ||
9042 | if (ret_val) | ||
9043 | return ret_val; | ||
9044 | |||
9045 | ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data); | ||
9046 | if (ret_val) | ||
9047 | return ret_val; | ||
9048 | |||
9049 | phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET; | ||
9050 | ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data); | ||
9051 | |||
9052 | return ret_val; | ||
9053 | } | ||
9054 | #endif /* 0 */ | ||
9055 | |||
9056 | static int32_t | 8812 | static int32_t |
9057 | e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, | 8813 | e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, |
9058 | uint32_t cnf_base_addr, uint32_t cnf_size) | 8814 | uint32_t cnf_base_addr, uint32_t cnf_size) |