diff options
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r-- | drivers/net/e1000/e1000_hw.c | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index a6f8f4fce701..10b8c8c25325 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -223,7 +223,7 @@ e1000_phy_init_script(struct e1000_hw *hw) | |||
223 | DEBUGFUNC("e1000_phy_init_script"); | 223 | DEBUGFUNC("e1000_phy_init_script"); |
224 | 224 | ||
225 | if (hw->phy_init_script) { | 225 | if (hw->phy_init_script) { |
226 | msec_delay(20); | 226 | msleep(20); |
227 | 227 | ||
228 | /* Save off the current value of register 0x2F5B to be restored at | 228 | /* Save off the current value of register 0x2F5B to be restored at |
229 | * the end of this routine. */ | 229 | * the end of this routine. */ |
@@ -232,11 +232,11 @@ e1000_phy_init_script(struct e1000_hw *hw) | |||
232 | /* Disabled the PHY transmitter */ | 232 | /* Disabled the PHY transmitter */ |
233 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | 233 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
234 | 234 | ||
235 | msec_delay(20); | 235 | msleep(20); |
236 | 236 | ||
237 | e1000_write_phy_reg(hw,0x0000,0x0140); | 237 | e1000_write_phy_reg(hw,0x0000,0x0140); |
238 | 238 | ||
239 | msec_delay(5); | 239 | msleep(5); |
240 | 240 | ||
241 | switch (hw->mac_type) { | 241 | switch (hw->mac_type) { |
242 | case e1000_82541: | 242 | case e1000_82541: |
@@ -270,7 +270,7 @@ e1000_phy_init_script(struct e1000_hw *hw) | |||
270 | 270 | ||
271 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | 271 | e1000_write_phy_reg(hw, 0x0000, 0x3300); |
272 | 272 | ||
273 | msec_delay(20); | 273 | msleep(20); |
274 | 274 | ||
275 | /* Now enable the transmitter */ | 275 | /* Now enable the transmitter */ |
276 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | 276 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
@@ -551,14 +551,14 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
551 | /* Delay to allow any outstanding PCI transactions to complete before | 551 | /* Delay to allow any outstanding PCI transactions to complete before |
552 | * resetting the device | 552 | * resetting the device |
553 | */ | 553 | */ |
554 | msec_delay(10); | 554 | msleep(10); |
555 | 555 | ||
556 | ctrl = E1000_READ_REG(hw, CTRL); | 556 | ctrl = E1000_READ_REG(hw, CTRL); |
557 | 557 | ||
558 | /* Must reset the PHY before resetting the MAC */ | 558 | /* Must reset the PHY before resetting the MAC */ |
559 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | 559 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
560 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); | 560 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
561 | msec_delay(5); | 561 | msleep(5); |
562 | } | 562 | } |
563 | 563 | ||
564 | /* Must acquire the MDIO ownership before MAC reset. | 564 | /* Must acquire the MDIO ownership before MAC reset. |
@@ -578,7 +578,7 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
578 | else | 578 | else |
579 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | 579 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
580 | 580 | ||
581 | msec_delay(2); | 581 | msleep(2); |
582 | timeout--; | 582 | timeout--; |
583 | } while (timeout); | 583 | } while (timeout); |
584 | } | 584 | } |
@@ -626,7 +626,7 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
626 | 626 | ||
627 | e1000_get_software_flag(hw); | 627 | e1000_get_software_flag(hw); |
628 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); | 628 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
629 | msec_delay(5); | 629 | msleep(5); |
630 | break; | 630 | break; |
631 | default: | 631 | default: |
632 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); | 632 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
@@ -649,14 +649,14 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
649 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | 649 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
650 | E1000_WRITE_FLUSH(hw); | 650 | E1000_WRITE_FLUSH(hw); |
651 | /* Wait for EEPROM reload */ | 651 | /* Wait for EEPROM reload */ |
652 | msec_delay(2); | 652 | msleep(2); |
653 | break; | 653 | break; |
654 | case e1000_82541: | 654 | case e1000_82541: |
655 | case e1000_82541_rev_2: | 655 | case e1000_82541_rev_2: |
656 | case e1000_82547: | 656 | case e1000_82547: |
657 | case e1000_82547_rev_2: | 657 | case e1000_82547_rev_2: |
658 | /* Wait for EEPROM reload */ | 658 | /* Wait for EEPROM reload */ |
659 | msec_delay(20); | 659 | msleep(20); |
660 | break; | 660 | break; |
661 | case e1000_82573: | 661 | case e1000_82573: |
662 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { | 662 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
@@ -678,7 +678,7 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
678 | break; | 678 | break; |
679 | default: | 679 | default: |
680 | /* Wait for EEPROM reload (it happens automatically) */ | 680 | /* Wait for EEPROM reload (it happens automatically) */ |
681 | msec_delay(5); | 681 | msleep(5); |
682 | break; | 682 | break; |
683 | } | 683 | } |
684 | 684 | ||
@@ -708,7 +708,7 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
708 | 708 | ||
709 | /* If MWI was previously enabled, reenable it. */ | 709 | /* If MWI was previously enabled, reenable it. */ |
710 | if (hw->mac_type == e1000_82542_rev2_0) { | 710 | if (hw->mac_type == e1000_82542_rev2_0) { |
711 | if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | 711 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
712 | e1000_pci_set_mwi(hw); | 712 | e1000_pci_set_mwi(hw); |
713 | } | 713 | } |
714 | 714 | ||
@@ -784,7 +784,7 @@ e1000_init_hw(struct e1000_hw *hw) | |||
784 | e1000_pci_clear_mwi(hw); | 784 | e1000_pci_clear_mwi(hw); |
785 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); | 785 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
786 | E1000_WRITE_FLUSH(hw); | 786 | E1000_WRITE_FLUSH(hw); |
787 | msec_delay(5); | 787 | msleep(5); |
788 | } | 788 | } |
789 | 789 | ||
790 | /* Setup the receive address. This involves initializing all of the Receive | 790 | /* Setup the receive address. This involves initializing all of the Receive |
@@ -796,8 +796,8 @@ e1000_init_hw(struct e1000_hw *hw) | |||
796 | if (hw->mac_type == e1000_82542_rev2_0) { | 796 | if (hw->mac_type == e1000_82542_rev2_0) { |
797 | E1000_WRITE_REG(hw, RCTL, 0); | 797 | E1000_WRITE_REG(hw, RCTL, 0); |
798 | E1000_WRITE_FLUSH(hw); | 798 | E1000_WRITE_FLUSH(hw); |
799 | msec_delay(1); | 799 | msleep(1); |
800 | if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | 800 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
801 | e1000_pci_set_mwi(hw); | 801 | e1000_pci_set_mwi(hw); |
802 | } | 802 | } |
803 | 803 | ||
@@ -851,7 +851,7 @@ e1000_init_hw(struct e1000_hw *hw) | |||
851 | 851 | ||
852 | /* More time needed for PHY to initialize */ | 852 | /* More time needed for PHY to initialize */ |
853 | if (hw->mac_type == e1000_ich8lan) | 853 | if (hw->mac_type == e1000_ich8lan) |
854 | msec_delay(15); | 854 | msleep(15); |
855 | 855 | ||
856 | /* Call a subroutine to configure the link and setup flow control. */ | 856 | /* Call a subroutine to configure the link and setup flow control. */ |
857 | ret_val = e1000_setup_link(hw); | 857 | ret_val = e1000_setup_link(hw); |
@@ -1231,7 +1231,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw) | |||
1231 | E1000_WRITE_FLUSH(hw); | 1231 | E1000_WRITE_FLUSH(hw); |
1232 | 1232 | ||
1233 | hw->txcw = txcw; | 1233 | hw->txcw = txcw; |
1234 | msec_delay(1); | 1234 | msleep(1); |
1235 | 1235 | ||
1236 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | 1236 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
1237 | * indication in the Device Status Register. Time-out if a link isn't | 1237 | * indication in the Device Status Register. Time-out if a link isn't |
@@ -1243,7 +1243,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw) | |||
1243 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { | 1243 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
1244 | DEBUGOUT("Looking for Link\n"); | 1244 | DEBUGOUT("Looking for Link\n"); |
1245 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { | 1245 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
1246 | msec_delay(10); | 1246 | msleep(10); |
1247 | status = E1000_READ_REG(hw, STATUS); | 1247 | status = E1000_READ_REG(hw, STATUS); |
1248 | if (status & E1000_STATUS_LU) break; | 1248 | if (status & E1000_STATUS_LU) break; |
1249 | } | 1249 | } |
@@ -1355,7 +1355,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) | |||
1355 | } | 1355 | } |
1356 | 1356 | ||
1357 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ | 1357 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
1358 | msec_delay(15); | 1358 | msleep(15); |
1359 | if (hw->mac_type != e1000_ich8lan) { | 1359 | if (hw->mac_type != e1000_ich8lan) { |
1360 | /* Configure activity LED after PHY reset */ | 1360 | /* Configure activity LED after PHY reset */ |
1361 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | 1361 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
@@ -2334,7 +2334,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |||
2334 | return ret_val; | 2334 | return ret_val; |
2335 | 2335 | ||
2336 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | 2336 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
2337 | msec_delay(100); | 2337 | msleep(100); |
2338 | } | 2338 | } |
2339 | if ((i == 0) && | 2339 | if ((i == 0) && |
2340 | ((hw->phy_type == e1000_phy_m88) || | 2340 | ((hw->phy_type == e1000_phy_m88) || |
@@ -2349,7 +2349,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |||
2349 | /* This loop will early-out if the link condition has been met. */ | 2349 | /* This loop will early-out if the link condition has been met. */ |
2350 | for (i = PHY_FORCE_TIME; i > 0; i--) { | 2350 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
2351 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | 2351 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
2352 | msec_delay(100); | 2352 | msleep(100); |
2353 | /* Read the MII Status Register and wait for Auto-Neg Complete bit | 2353 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
2354 | * to be set. | 2354 | * to be set. |
2355 | */ | 2355 | */ |
@@ -3132,7 +3132,7 @@ e1000_wait_autoneg(struct e1000_hw *hw) | |||
3132 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { | 3132 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
3133 | return E1000_SUCCESS; | 3133 | return E1000_SUCCESS; |
3134 | } | 3134 | } |
3135 | msec_delay(100); | 3135 | msleep(100); |
3136 | } | 3136 | } |
3137 | return E1000_SUCCESS; | 3137 | return E1000_SUCCESS; |
3138 | } | 3138 | } |
@@ -3306,7 +3306,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) | |||
3306 | /* firmware currently using resource (fwmask) */ | 3306 | /* firmware currently using resource (fwmask) */ |
3307 | /* or other software thread currently using resource (swmask) */ | 3307 | /* or other software thread currently using resource (swmask) */ |
3308 | e1000_put_hw_eeprom_semaphore(hw); | 3308 | e1000_put_hw_eeprom_semaphore(hw); |
3309 | msec_delay_irq(5); | 3309 | mdelay(5); |
3310 | timeout--; | 3310 | timeout--; |
3311 | } | 3311 | } |
3312 | 3312 | ||
@@ -3725,7 +3725,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw) | |||
3725 | E1000_WRITE_FLUSH(hw); | 3725 | E1000_WRITE_FLUSH(hw); |
3726 | 3726 | ||
3727 | if (hw->mac_type < e1000_82571) | 3727 | if (hw->mac_type < e1000_82571) |
3728 | msec_delay(10); | 3728 | msleep(10); |
3729 | else | 3729 | else |
3730 | udelay(100); | 3730 | udelay(100); |
3731 | 3731 | ||
@@ -3733,7 +3733,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw) | |||
3733 | E1000_WRITE_FLUSH(hw); | 3733 | E1000_WRITE_FLUSH(hw); |
3734 | 3734 | ||
3735 | if (hw->mac_type >= e1000_82571) | 3735 | if (hw->mac_type >= e1000_82571) |
3736 | msec_delay_irq(10); | 3736 | mdelay(10); |
3737 | e1000_swfw_sync_release(hw, swfw); | 3737 | e1000_swfw_sync_release(hw, swfw); |
3738 | } else { | 3738 | } else { |
3739 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | 3739 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
@@ -3744,7 +3744,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw) | |||
3744 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | 3744 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
3745 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | 3745 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
3746 | E1000_WRITE_FLUSH(hw); | 3746 | E1000_WRITE_FLUSH(hw); |
3747 | msec_delay(10); | 3747 | msleep(10); |
3748 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; | 3748 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
3749 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | 3749 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
3750 | E1000_WRITE_FLUSH(hw); | 3750 | E1000_WRITE_FLUSH(hw); |
@@ -3917,7 +3917,7 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) | |||
3917 | 3917 | ||
3918 | /* Issue PHY reset */ | 3918 | /* Issue PHY reset */ |
3919 | e1000_phy_hw_reset(hw); | 3919 | e1000_phy_hw_reset(hw); |
3920 | msec_delay_irq(5); | 3920 | mdelay(5); |
3921 | } | 3921 | } |
3922 | /* Disable GigE link negotiation */ | 3922 | /* Disable GigE link negotiation */ |
3923 | reg = E1000_READ_REG(hw, PHY_CTRL); | 3923 | reg = E1000_READ_REG(hw, PHY_CTRL); |
@@ -5179,7 +5179,7 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw) | |||
5179 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | 5179 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
5180 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | 5180 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
5181 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | 5181 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
5182 | msec_delay(10); | 5182 | msleep(10); |
5183 | } | 5183 | } |
5184 | return E1000_SUCCESS; | 5184 | return E1000_SUCCESS; |
5185 | } | 5185 | } |
@@ -5230,7 +5230,7 @@ e1000_write_eeprom(struct e1000_hw *hw, | |||
5230 | status = e1000_write_eeprom_microwire(hw, offset, words, data); | 5230 | status = e1000_write_eeprom_microwire(hw, offset, words, data); |
5231 | } else { | 5231 | } else { |
5232 | status = e1000_write_eeprom_spi(hw, offset, words, data); | 5232 | status = e1000_write_eeprom_spi(hw, offset, words, data); |
5233 | msec_delay(10); | 5233 | msleep(10); |
5234 | } | 5234 | } |
5235 | 5235 | ||
5236 | /* Done with writing */ | 5236 | /* Done with writing */ |
@@ -7058,7 +7058,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
7058 | if (ret_val) | 7058 | if (ret_val) |
7059 | return ret_val; | 7059 | return ret_val; |
7060 | 7060 | ||
7061 | msec_delay_irq(20); | 7061 | mdelay(20); |
7062 | 7062 | ||
7063 | ret_val = e1000_write_phy_reg(hw, 0x0000, | 7063 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
7064 | IGP01E1000_IEEE_FORCE_GIGA); | 7064 | IGP01E1000_IEEE_FORCE_GIGA); |
@@ -7082,7 +7082,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
7082 | if (ret_val) | 7082 | if (ret_val) |
7083 | return ret_val; | 7083 | return ret_val; |
7084 | 7084 | ||
7085 | msec_delay_irq(20); | 7085 | mdelay(20); |
7086 | 7086 | ||
7087 | /* Now enable the transmitter */ | 7087 | /* Now enable the transmitter */ |
7088 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | 7088 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
@@ -7107,7 +7107,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
7107 | if (ret_val) | 7107 | if (ret_val) |
7108 | return ret_val; | 7108 | return ret_val; |
7109 | 7109 | ||
7110 | msec_delay_irq(20); | 7110 | mdelay(20); |
7111 | 7111 | ||
7112 | ret_val = e1000_write_phy_reg(hw, 0x0000, | 7112 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
7113 | IGP01E1000_IEEE_FORCE_GIGA); | 7113 | IGP01E1000_IEEE_FORCE_GIGA); |
@@ -7123,7 +7123,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
7123 | if (ret_val) | 7123 | if (ret_val) |
7124 | return ret_val; | 7124 | return ret_val; |
7125 | 7125 | ||
7126 | msec_delay_irq(20); | 7126 | mdelay(20); |
7127 | 7127 | ||
7128 | /* Now enable the transmitter */ | 7128 | /* Now enable the transmitter */ |
7129 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | 7129 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
@@ -7519,7 +7519,7 @@ e1000_mng_enable_host_if(struct e1000_hw * hw) | |||
7519 | hicr = E1000_READ_REG(hw, HICR); | 7519 | hicr = E1000_READ_REG(hw, HICR); |
7520 | if (!(hicr & E1000_HICR_C)) | 7520 | if (!(hicr & E1000_HICR_C)) |
7521 | break; | 7521 | break; |
7522 | msec_delay_irq(1); | 7522 | mdelay(1); |
7523 | } | 7523 | } |
7524 | 7524 | ||
7525 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { | 7525 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
@@ -7842,26 +7842,26 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw) | |||
7842 | return ret_val; | 7842 | return ret_val; |
7843 | 7843 | ||
7844 | if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; | 7844 | if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
7845 | msec_delay_irq(100); | 7845 | mdelay(100); |
7846 | } | 7846 | } |
7847 | 7847 | ||
7848 | /* Recommended delay time after link has been lost */ | 7848 | /* Recommended delay time after link has been lost */ |
7849 | msec_delay_irq(1000); | 7849 | mdelay(1000); |
7850 | 7850 | ||
7851 | /* Now we will re-enable th transmitter on the PHY */ | 7851 | /* Now we will re-enable th transmitter on the PHY */ |
7852 | 7852 | ||
7853 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | 7853 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
7854 | if (ret_val) | 7854 | if (ret_val) |
7855 | return ret_val; | 7855 | return ret_val; |
7856 | msec_delay_irq(50); | 7856 | mdelay(50); |
7857 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); | 7857 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
7858 | if (ret_val) | 7858 | if (ret_val) |
7859 | return ret_val; | 7859 | return ret_val; |
7860 | msec_delay_irq(50); | 7860 | mdelay(50); |
7861 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); | 7861 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
7862 | if (ret_val) | 7862 | if (ret_val) |
7863 | return ret_val; | 7863 | return ret_val; |
7864 | msec_delay_irq(50); | 7864 | mdelay(50); |
7865 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); | 7865 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
7866 | if (ret_val) | 7866 | if (ret_val) |
7867 | return ret_val; | 7867 | return ret_val; |
@@ -7885,7 +7885,7 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw) | |||
7885 | return ret_val; | 7885 | return ret_val; |
7886 | 7886 | ||
7887 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | 7887 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
7888 | msec_delay_irq(100); | 7888 | mdelay(100); |
7889 | } | 7889 | } |
7890 | return E1000_SUCCESS; | 7890 | return E1000_SUCCESS; |
7891 | } | 7891 | } |
@@ -7998,7 +7998,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw) | |||
7998 | 7998 | ||
7999 | switch (hw->mac_type) { | 7999 | switch (hw->mac_type) { |
8000 | default: | 8000 | default: |
8001 | msec_delay(5); | 8001 | msleep(5); |
8002 | break; | 8002 | break; |
8003 | case e1000_82571: | 8003 | case e1000_82571: |
8004 | case e1000_82572: | 8004 | case e1000_82572: |
@@ -8008,7 +8008,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw) | |||
8008 | while (timeout) { | 8008 | while (timeout) { |
8009 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) | 8009 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) |
8010 | break; | 8010 | break; |
8011 | else msec_delay(1); | 8011 | else msleep(1); |
8012 | timeout--; | 8012 | timeout--; |
8013 | } | 8013 | } |
8014 | 8014 | ||
@@ -8023,7 +8023,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw) | |||
8023 | * Need to wait for PHY configuration completion before accessing NVM | 8023 | * Need to wait for PHY configuration completion before accessing NVM |
8024 | * and PHY. */ | 8024 | * and PHY. */ |
8025 | if (hw->mac_type == e1000_82573) | 8025 | if (hw->mac_type == e1000_82573) |
8026 | msec_delay(25); | 8026 | msleep(25); |
8027 | 8027 | ||
8028 | return E1000_SUCCESS; | 8028 | return E1000_SUCCESS; |
8029 | } | 8029 | } |
@@ -8047,7 +8047,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) | |||
8047 | 8047 | ||
8048 | switch (hw->mac_type) { | 8048 | switch (hw->mac_type) { |
8049 | default: | 8049 | default: |
8050 | msec_delay_irq(10); | 8050 | mdelay(10); |
8051 | break; | 8051 | break; |
8052 | case e1000_80003es2lan: | 8052 | case e1000_80003es2lan: |
8053 | /* Separate *_CFG_DONE_* bit for each port */ | 8053 | /* Separate *_CFG_DONE_* bit for each port */ |
@@ -8060,7 +8060,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) | |||
8060 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) | 8060 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
8061 | break; | 8061 | break; |
8062 | else | 8062 | else |
8063 | msec_delay(1); | 8063 | msleep(1); |
8064 | timeout--; | 8064 | timeout--; |
8065 | } | 8065 | } |
8066 | 8066 | ||
@@ -8180,7 +8180,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw) | |||
8180 | /* If SMBI bit cleared, it is now set and we hold the semaphore */ | 8180 | /* If SMBI bit cleared, it is now set and we hold the semaphore */ |
8181 | if (!(swsm & E1000_SWSM_SMBI)) | 8181 | if (!(swsm & E1000_SWSM_SMBI)) |
8182 | break; | 8182 | break; |
8183 | msec_delay_irq(1); | 8183 | mdelay(1); |
8184 | timeout--; | 8184 | timeout--; |
8185 | } | 8185 | } |
8186 | 8186 | ||
@@ -8339,7 +8339,7 @@ e1000_get_software_flag(struct e1000_hw *hw) | |||
8339 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | 8339 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
8340 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | 8340 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
8341 | break; | 8341 | break; |
8342 | msec_delay_irq(1); | 8342 | mdelay(1); |
8343 | timeout--; | 8343 | timeout--; |
8344 | } | 8344 | } |
8345 | 8345 | ||