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-rw-r--r--drivers/net/e1000/e1000_hw.c1987
1 files changed, 1597 insertions, 390 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 786a9b935659..723589b28be5 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -63,10 +63,11 @@ static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64static void e1000_release_eeprom(struct e1000_hw *hw); 64static void e1000_release_eeprom(struct e1000_hw *hw);
65static void e1000_standby_eeprom(struct e1000_hw *hw); 65static void e1000_standby_eeprom(struct e1000_hw *hw);
66static int32_t e1000_id_led_init(struct e1000_hw * hw);
67static int32_t e1000_set_vco_speed(struct e1000_hw *hw); 66static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); 67static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 68static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
69static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
70static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
70 71
71/* IGP cable length table */ 72/* IGP cable length table */
72static const 73static const
@@ -80,6 +81,17 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
80 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 81 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 82 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82 83
84static const
85uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
86 { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,
87 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,
88 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,
89 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,
90 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,
91 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,
92 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,
93 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};
94
83 95
84/****************************************************************************** 96/******************************************************************************
85 * Set the phy type member in the hw struct. 97 * Set the phy type member in the hw struct.
@@ -91,10 +103,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
91{ 103{
92 DEBUGFUNC("e1000_set_phy_type"); 104 DEBUGFUNC("e1000_set_phy_type");
93 105
106 if(hw->mac_type == e1000_undefined)
107 return -E1000_ERR_PHY_TYPE;
108
94 switch(hw->phy_id) { 109 switch(hw->phy_id) {
95 case M88E1000_E_PHY_ID: 110 case M88E1000_E_PHY_ID:
96 case M88E1000_I_PHY_ID: 111 case M88E1000_I_PHY_ID:
97 case M88E1011_I_PHY_ID: 112 case M88E1011_I_PHY_ID:
113 case M88E1111_I_PHY_ID:
98 hw->phy_type = e1000_phy_m88; 114 hw->phy_type = e1000_phy_m88;
99 break; 115 break;
100 case IGP01E1000_I_PHY_ID: 116 case IGP01E1000_I_PHY_ID:
@@ -128,7 +144,6 @@ e1000_phy_init_script(struct e1000_hw *hw)
128 144
129 DEBUGFUNC("e1000_phy_init_script"); 145 DEBUGFUNC("e1000_phy_init_script");
130 146
131
132 if(hw->phy_init_script) { 147 if(hw->phy_init_script) {
133 msec_delay(20); 148 msec_delay(20);
134 149
@@ -271,6 +286,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
271 case E1000_DEV_ID_82546GB_FIBER: 286 case E1000_DEV_ID_82546GB_FIBER:
272 case E1000_DEV_ID_82546GB_SERDES: 287 case E1000_DEV_ID_82546GB_SERDES:
273 case E1000_DEV_ID_82546GB_PCIE: 288 case E1000_DEV_ID_82546GB_PCIE:
289 case E1000_DEV_ID_82546GB_QUAD_COPPER:
274 hw->mac_type = e1000_82546_rev_3; 290 hw->mac_type = e1000_82546_rev_3;
275 break; 291 break;
276 case E1000_DEV_ID_82541EI: 292 case E1000_DEV_ID_82541EI:
@@ -289,12 +305,19 @@ e1000_set_mac_type(struct e1000_hw *hw)
289 case E1000_DEV_ID_82547GI: 305 case E1000_DEV_ID_82547GI:
290 hw->mac_type = e1000_82547_rev_2; 306 hw->mac_type = e1000_82547_rev_2;
291 break; 307 break;
308 case E1000_DEV_ID_82573E:
309 case E1000_DEV_ID_82573E_IAMT:
310 hw->mac_type = e1000_82573;
311 break;
292 default: 312 default:
293 /* Should never have loaded on this device */ 313 /* Should never have loaded on this device */
294 return -E1000_ERR_MAC_TYPE; 314 return -E1000_ERR_MAC_TYPE;
295 } 315 }
296 316
297 switch(hw->mac_type) { 317 switch(hw->mac_type) {
318 case e1000_82573:
319 hw->eeprom_semaphore_present = TRUE;
320 /* fall through */
298 case e1000_82541: 321 case e1000_82541:
299 case e1000_82547: 322 case e1000_82547:
300 case e1000_82541_rev_2: 323 case e1000_82541_rev_2:
@@ -360,6 +383,9 @@ e1000_reset_hw(struct e1000_hw *hw)
360 uint32_t icr; 383 uint32_t icr;
361 uint32_t manc; 384 uint32_t manc;
362 uint32_t led_ctrl; 385 uint32_t led_ctrl;
386 uint32_t timeout;
387 uint32_t extcnf_ctrl;
388 int32_t ret_val;
363 389
364 DEBUGFUNC("e1000_reset_hw"); 390 DEBUGFUNC("e1000_reset_hw");
365 391
@@ -369,6 +395,15 @@ e1000_reset_hw(struct e1000_hw *hw)
369 e1000_pci_clear_mwi(hw); 395 e1000_pci_clear_mwi(hw);
370 } 396 }
371 397
398 if(hw->bus_type == e1000_bus_type_pci_express) {
399 /* Prevent the PCI-E bus from sticking if there is no TLP connection
400 * on the last TLP read/write transaction when MAC is reset.
401 */
402 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
403 DEBUGOUT("PCI-E Master disable polling has failed.\n");
404 }
405 }
406
372 /* Clear interrupt mask to stop board from generating interrupts */ 407 /* Clear interrupt mask to stop board from generating interrupts */
373 DEBUGOUT("Masking off all interrupts\n"); 408 DEBUGOUT("Masking off all interrupts\n");
374 E1000_WRITE_REG(hw, IMC, 0xffffffff); 409 E1000_WRITE_REG(hw, IMC, 0xffffffff);
@@ -393,10 +428,32 @@ e1000_reset_hw(struct e1000_hw *hw)
393 428
394 /* Must reset the PHY before resetting the MAC */ 429 /* Must reset the PHY before resetting the MAC */
395 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 430 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
396 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 431 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
397 msec_delay(5); 432 msec_delay(5);
398 } 433 }
399 434
435 /* Must acquire the MDIO ownership before MAC reset.
436 * Ownership defaults to firmware after a reset. */
437 if(hw->mac_type == e1000_82573) {
438 timeout = 10;
439
440 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
441 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
442
443 do {
444 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
445 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
446
447 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
448 break;
449 else
450 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
451
452 msec_delay(2);
453 timeout--;
454 } while(timeout);
455 }
456
400 /* Issue a global reset to the MAC. This will reset the chip's 457 /* Issue a global reset to the MAC. This will reset the chip's
401 * transmit, receive, DMA, and link units. It will not effect 458 * transmit, receive, DMA, and link units. It will not effect
402 * the current PCI configuration. The global reset bit is self- 459 * the current PCI configuration. The global reset bit is self-
@@ -450,6 +507,18 @@ e1000_reset_hw(struct e1000_hw *hw)
450 /* Wait for EEPROM reload */ 507 /* Wait for EEPROM reload */
451 msec_delay(20); 508 msec_delay(20);
452 break; 509 break;
510 case e1000_82573:
511 udelay(10);
512 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
513 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
514 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
515 E1000_WRITE_FLUSH(hw);
516 /* fall through */
517 ret_val = e1000_get_auto_rd_done(hw);
518 if(ret_val)
519 /* We don't want to continue accessing MAC registers. */
520 return ret_val;
521 break;
453 default: 522 default:
454 /* Wait for EEPROM reload (it happens automatically) */ 523 /* Wait for EEPROM reload (it happens automatically) */
455 msec_delay(5); 524 msec_delay(5);
@@ -457,7 +526,7 @@ e1000_reset_hw(struct e1000_hw *hw)
457 } 526 }
458 527
459 /* Disable HW ARPs on ASF enabled adapters */ 528 /* Disable HW ARPs on ASF enabled adapters */
460 if(hw->mac_type >= e1000_82540) { 529 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
461 manc = E1000_READ_REG(hw, MANC); 530 manc = E1000_READ_REG(hw, MANC);
462 manc &= ~(E1000_MANC_ARP_EN); 531 manc &= ~(E1000_MANC_ARP_EN);
463 E1000_WRITE_REG(hw, MANC, manc); 532 E1000_WRITE_REG(hw, MANC, manc);
@@ -510,6 +579,8 @@ e1000_init_hw(struct e1000_hw *hw)
510 uint16_t pcix_stat_hi_word; 579 uint16_t pcix_stat_hi_word;
511 uint16_t cmd_mmrbc; 580 uint16_t cmd_mmrbc;
512 uint16_t stat_mmrbc; 581 uint16_t stat_mmrbc;
582 uint32_t mta_size;
583
513 DEBUGFUNC("e1000_init_hw"); 584 DEBUGFUNC("e1000_init_hw");
514 585
515 /* Initialize Identification LED */ 586 /* Initialize Identification LED */
@@ -524,8 +595,8 @@ e1000_init_hw(struct e1000_hw *hw)
524 595
525 /* Disabling VLAN filtering. */ 596 /* Disabling VLAN filtering. */
526 DEBUGOUT("Initializing the IEEE VLAN\n"); 597 DEBUGOUT("Initializing the IEEE VLAN\n");
527 E1000_WRITE_REG(hw, VET, 0); 598 if (hw->mac_type < e1000_82545_rev_3)
528 599 E1000_WRITE_REG(hw, VET, 0);
529 e1000_clear_vfta(hw); 600 e1000_clear_vfta(hw);
530 601
531 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 602 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
@@ -553,14 +624,16 @@ e1000_init_hw(struct e1000_hw *hw)
553 624
554 /* Zero out the Multicast HASH table */ 625 /* Zero out the Multicast HASH table */
555 DEBUGOUT("Zeroing the MTA\n"); 626 DEBUGOUT("Zeroing the MTA\n");
556 for(i = 0; i < E1000_MC_TBL_SIZE; i++) 627 mta_size = E1000_MC_TBL_SIZE;
628 for(i = 0; i < mta_size; i++)
557 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 629 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
558 630
559 /* Set the PCI priority bit correctly in the CTRL register. This 631 /* Set the PCI priority bit correctly in the CTRL register. This
560 * determines if the adapter gives priority to receives, or if it 632 * determines if the adapter gives priority to receives, or if it
561 * gives equal priority to transmits and receives. 633 * gives equal priority to transmits and receives. Valid only on
634 * 82542 and 82543 silicon.
562 */ 635 */
563 if(hw->dma_fairness) { 636 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
564 ctrl = E1000_READ_REG(hw, CTRL); 637 ctrl = E1000_READ_REG(hw, CTRL);
565 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 638 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
566 } 639 }
@@ -598,9 +671,21 @@ e1000_init_hw(struct e1000_hw *hw)
598 if(hw->mac_type > e1000_82544) { 671 if(hw->mac_type > e1000_82544) {
599 ctrl = E1000_READ_REG(hw, TXDCTL); 672 ctrl = E1000_READ_REG(hw, TXDCTL);
600 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 673 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
674 switch (hw->mac_type) {
675 default:
676 break;
677 case e1000_82573:
678 ctrl |= E1000_TXDCTL_COUNT_DESC;
679 break;
680 }
601 E1000_WRITE_REG(hw, TXDCTL, ctrl); 681 E1000_WRITE_REG(hw, TXDCTL, ctrl);
602 } 682 }
603 683
684 if (hw->mac_type == e1000_82573) {
685 e1000_enable_tx_pkt_filtering(hw);
686 }
687
688
604 /* Clear all of the statistics registers (clear on read). It is 689 /* Clear all of the statistics registers (clear on read). It is
605 * important that we do this after we have tried to establish link 690 * important that we do this after we have tried to establish link
606 * because the symbol error count will increment wildly if there 691 * because the symbol error count will increment wildly if there
@@ -679,7 +764,7 @@ e1000_setup_link(struct e1000_hw *hw)
679 * control setting, then the variable hw->fc will 764 * control setting, then the variable hw->fc will
680 * be initialized based on a value in the EEPROM. 765 * be initialized based on a value in the EEPROM.
681 */ 766 */
682 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) { 767 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) {
683 DEBUGOUT("EEPROM Read Error\n"); 768 DEBUGOUT("EEPROM Read Error\n");
684 return -E1000_ERR_EEPROM; 769 return -E1000_ERR_EEPROM;
685 } 770 }
@@ -736,6 +821,7 @@ e1000_setup_link(struct e1000_hw *hw)
736 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 821 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 822 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 823 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
824
739 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 825 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
740 826
741 /* Set the flow control receive threshold registers. Normally, 827 /* Set the flow control receive threshold registers. Normally,
@@ -906,20 +992,18 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
906} 992}
907 993
908/****************************************************************************** 994/******************************************************************************
909* Detects which PHY is present and the speed and duplex 995* Make sure we have a valid PHY and change PHY mode before link setup.
910* 996*
911* hw - Struct containing variables accessed by shared code 997* hw - Struct containing variables accessed by shared code
912******************************************************************************/ 998******************************************************************************/
913static int32_t 999static int32_t
914e1000_setup_copper_link(struct e1000_hw *hw) 1000e1000_copper_link_preconfig(struct e1000_hw *hw)
915{ 1001{
916 uint32_t ctrl; 1002 uint32_t ctrl;
917 uint32_t led_ctrl;
918 int32_t ret_val; 1003 int32_t ret_val;
919 uint16_t i;
920 uint16_t phy_data; 1004 uint16_t phy_data;
921 1005
922 DEBUGFUNC("e1000_setup_copper_link"); 1006 DEBUGFUNC("e1000_copper_link_preconfig");
923 1007
924 ctrl = E1000_READ_REG(hw, CTRL); 1008 ctrl = E1000_READ_REG(hw, CTRL);
925 /* With 82543, we need to force speed and duplex on the MAC equal to what 1009 /* With 82543, we need to force speed and duplex on the MAC equal to what
@@ -933,7 +1017,9 @@ e1000_setup_copper_link(struct e1000_hw *hw)
933 } else { 1017 } else {
934 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1018 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
935 E1000_WRITE_REG(hw, CTRL, ctrl); 1019 E1000_WRITE_REG(hw, CTRL, ctrl);
936 e1000_phy_hw_reset(hw); 1020 ret_val = e1000_phy_hw_reset(hw);
1021 if(ret_val)
1022 return ret_val;
937 } 1023 }
938 1024
939 /* Make sure we have a valid PHY */ 1025 /* Make sure we have a valid PHY */
@@ -961,274 +1047,398 @@ e1000_setup_copper_link(struct e1000_hw *hw)
961 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1047 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
962 hw->phy_reset_disable = FALSE; 1048 hw->phy_reset_disable = FALSE;
963 1049
964 if(!hw->phy_reset_disable) { 1050 return E1000_SUCCESS;
965 if (hw->phy_type == e1000_phy_igp) { 1051}
966 1052
967 ret_val = e1000_phy_reset(hw);
968 if(ret_val) {
969 DEBUGOUT("Error Resetting the PHY\n");
970 return ret_val;
971 }
972 1053
973 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1054/********************************************************************
974 msec_delay(15); 1055* Copper link setup for e1000_phy_igp series.
1056*
1057* hw - Struct containing variables accessed by shared code
1058*********************************************************************/
1059static int32_t
1060e1000_copper_link_igp_setup(struct e1000_hw *hw)
1061{
1062 uint32_t led_ctrl;
1063 int32_t ret_val;
1064 uint16_t phy_data;
975 1065
976 /* Configure activity LED after PHY reset */ 1066 DEBUGFUNC("e1000_copper_link_igp_setup");
977 led_ctrl = E1000_READ_REG(hw, LEDCTL);
978 led_ctrl &= IGP_ACTIVITY_LED_MASK;
979 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
980 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
981 1067
982 /* disable lplu d3 during driver init */ 1068 if (hw->phy_reset_disable)
983 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1069 return E1000_SUCCESS;
984 if(ret_val) { 1070
985 DEBUGOUT("Error Disabling LPLU D3\n"); 1071 ret_val = e1000_phy_reset(hw);
986 return ret_val; 1072 if (ret_val) {
987 } 1073 DEBUGOUT("Error Resetting the PHY\n");
1074 return ret_val;
1075 }
988 1076
989 /* Configure mdi-mdix settings */ 1077 /* Wait 10ms for MAC to configure PHY from eeprom settings */
990 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 1078 msec_delay(15);
991 &phy_data);
992 if(ret_val)
993 return ret_val;
994 1079
995 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1080 /* Configure activity LED after PHY reset */
996 hw->dsp_config_state = e1000_dsp_config_disabled; 1081 led_ctrl = E1000_READ_REG(hw, LEDCTL);
997 /* Force MDI for earlier revs of the IGP PHY */ 1082 led_ctrl &= IGP_ACTIVITY_LED_MASK;
998 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 1083 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
999 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1084 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1000 hw->mdix = 1;
1001 1085
1002 } else { 1086 /* disable lplu d3 during driver init */
1003 hw->dsp_config_state = e1000_dsp_config_enabled; 1087 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1004 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1088 if (ret_val) {
1005 1089 DEBUGOUT("Error Disabling LPLU D3\n");
1006 switch (hw->mdix) { 1090 return ret_val;
1007 case 1: 1091 }
1008 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009 break;
1010 case 2:
1011 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012 break;
1013 case 0:
1014 default:
1015 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1016 break;
1017 }
1018 }
1019 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020 phy_data);
1021 if(ret_val)
1022 return ret_val;
1023 1092
1024 /* set auto-master slave resolution settings */ 1093 /* disable lplu d0 during driver init */
1025 if(hw->autoneg) { 1094 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1026 e1000_ms_type phy_ms_setting = hw->master_slave; 1095 if (ret_val) {
1096 DEBUGOUT("Error Disabling LPLU D0\n");
1097 return ret_val;
1098 }
1099 /* Configure mdi-mdix settings */
1100 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1101 if (ret_val)
1102 return ret_val;
1027 1103
1028 if(hw->ffe_config_state == e1000_ffe_config_active) 1104 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1029 hw->ffe_config_state = e1000_ffe_config_enabled; 1105 hw->dsp_config_state = e1000_dsp_config_disabled;
1106 /* Force MDI for earlier revs of the IGP PHY */
1107 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1108 hw->mdix = 1;
1030 1109
1031 if(hw->dsp_config_state == e1000_dsp_config_activated) 1110 } else {
1032 hw->dsp_config_state = e1000_dsp_config_enabled; 1111 hw->dsp_config_state = e1000_dsp_config_enabled;
1112 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1033 1113
1034 /* when autonegotiation advertisment is only 1000Mbps then we 1114 switch (hw->mdix) {
1035 * should disable SmartSpeed and enable Auto MasterSlave 1115 case 1:
1036 * resolution as hardware default. */ 1116 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1037 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1117 break;
1038 /* Disable SmartSpeed */ 1118 case 2:
1039 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1119 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1040 &phy_data); 1120 break;
1041 if(ret_val) 1121 case 0:
1042 return ret_val; 1122 default:
1043 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1123 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1044 ret_val = e1000_write_phy_reg(hw, 1124 break;
1045 IGP01E1000_PHY_PORT_CONFIG, 1125 }
1046 phy_data); 1126 }
1047 if(ret_val) 1127 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1048 return ret_val; 1128 if(ret_val)
1049 /* Set auto Master/Slave resolution process */ 1129 return ret_val;
1050 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051 if(ret_val)
1052 return ret_val;
1053 phy_data &= ~CR_1000T_MS_ENABLE;
1054 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055 if(ret_val)
1056 return ret_val;
1057 }
1058 1130
1059 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1131 /* set auto-master slave resolution settings */
1060 if(ret_val) 1132 if(hw->autoneg) {
1061 return ret_val; 1133 e1000_ms_type phy_ms_setting = hw->master_slave;
1062 1134
1063 /* load defaults for future use */ 1135 if(hw->ffe_config_state == e1000_ffe_config_active)
1064 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1136 hw->ffe_config_state = e1000_ffe_config_enabled;
1065 ((phy_data & CR_1000T_MS_VALUE) ? 1137
1066 e1000_ms_force_master : 1138 if(hw->dsp_config_state == e1000_dsp_config_activated)
1067 e1000_ms_force_slave) : 1139 hw->dsp_config_state = e1000_dsp_config_enabled;
1068 e1000_ms_auto; 1140
1069 1141 /* when autonegotiation advertisment is only 1000Mbps then we
1070 switch (phy_ms_setting) { 1142 * should disable SmartSpeed and enable Auto MasterSlave
1071 case e1000_ms_force_master: 1143 * resolution as hardware default. */
1072 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1144 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1073 break; 1145 /* Disable SmartSpeed */
1074 case e1000_ms_force_slave: 1146 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1075 phy_data |= CR_1000T_MS_ENABLE; 1147 if(ret_val)
1076 phy_data &= ~(CR_1000T_MS_VALUE); 1148 return ret_val;
1077 break; 1149 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1078 case e1000_ms_auto: 1150 ret_val = e1000_write_phy_reg(hw,
1079 phy_data &= ~CR_1000T_MS_ENABLE; 1151 IGP01E1000_PHY_PORT_CONFIG,
1080 default: 1152 phy_data);
1081 break; 1153 if(ret_val)
1082 } 1154 return ret_val;
1083 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1155 /* Set auto Master/Slave resolution process */
1084 if(ret_val) 1156 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1085 return ret_val; 1157 if(ret_val)
1086 } 1158 return ret_val;
1087 } else { 1159 phy_data &= ~CR_1000T_MS_ENABLE;
1088 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1160 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1089 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1090 &phy_data);
1091 if(ret_val) 1161 if(ret_val)
1092 return ret_val; 1162 return ret_val;
1163 }
1093 1164
1094 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1165 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1166 if(ret_val)
1167 return ret_val;
1095 1168
1096 /* Options: 1169 /* load defaults for future use */
1097 * MDI/MDI-X = 0 (default) 1170 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1098 * 0 - Auto for all speeds 1171 ((phy_data & CR_1000T_MS_VALUE) ?
1099 * 1 - MDI mode 1172 e1000_ms_force_master :
1100 * 2 - MDI-X mode 1173 e1000_ms_force_slave) :
1101 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1174 e1000_ms_auto;
1102 */
1103 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104 1175
1105 switch (hw->mdix) { 1176 switch (phy_ms_setting) {
1106 case 1: 1177 case e1000_ms_force_master:
1107 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1178 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1108 break; 1179 break;
1109 case 2: 1180 case e1000_ms_force_slave:
1110 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1181 phy_data |= CR_1000T_MS_ENABLE;
1111 break; 1182 phy_data &= ~(CR_1000T_MS_VALUE);
1112 case 3: 1183 break;
1113 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1184 case e1000_ms_auto:
1114 break; 1185 phy_data &= ~CR_1000T_MS_ENABLE;
1115 case 0:
1116 default: 1186 default:
1117 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1187 break;
1118 break; 1188 }
1119 } 1189 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1190 if(ret_val)
1191 return ret_val;
1192 }
1120 1193
1121 /* Options: 1194 return E1000_SUCCESS;
1122 * disable_polarity_correction = 0 (default) 1195}
1123 * Automatic Correction for Reversed Cable Polarity
1124 * 0 - Disabled
1125 * 1 - Enabled
1126 */
1127 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128 if(hw->disable_polarity_correction == 1)
1129 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1131 phy_data);
1132 if(ret_val)
1133 return ret_val;
1134 1196
1135 /* Force TX_CLK in the Extended PHY Specific Control Register
1136 * to 25MHz clock.
1137 */
1138 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139 &phy_data);
1140 if(ret_val)
1141 return ret_val;
1142 1197
1143 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1198/********************************************************************
1199* Copper link setup for e1000_phy_m88 series.
1200*
1201* hw - Struct containing variables accessed by shared code
1202*********************************************************************/
1203static int32_t
1204e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1205{
1206 int32_t ret_val;
1207 uint16_t phy_data;
1208
1209 DEBUGFUNC("e1000_copper_link_mgp_setup");
1210
1211 if(hw->phy_reset_disable)
1212 return E1000_SUCCESS;
1213
1214 /* Enable CRS on TX. This must be set for half-duplex operation. */
1215 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1216 if(ret_val)
1217 return ret_val;
1218
1219 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1220
1221 /* Options:
1222 * MDI/MDI-X = 0 (default)
1223 * 0 - Auto for all speeds
1224 * 1 - MDI mode
1225 * 2 - MDI-X mode
1226 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1227 */
1228 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1229
1230 switch (hw->mdix) {
1231 case 1:
1232 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1233 break;
1234 case 2:
1235 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1236 break;
1237 case 3:
1238 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1239 break;
1240 case 0:
1241 default:
1242 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1243 break;
1244 }
1245
1246 /* Options:
1247 * disable_polarity_correction = 0 (default)
1248 * Automatic Correction for Reversed Cable Polarity
1249 * 0 - Disabled
1250 * 1 - Enabled
1251 */
1252 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1253 if(hw->disable_polarity_correction == 1)
1254 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1255 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1256 if(ret_val)
1257 return ret_val;
1144 1258
1145 if (hw->phy_revision < M88E1011_I_REV_4) { 1259 /* Force TX_CLK in the Extended PHY Specific Control Register
1146 /* Configure Master and Slave downshift values */ 1260 * to 25MHz clock.
1147 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1261 */
1262 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1263 if(ret_val)
1264 return ret_val;
1265
1266 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1267
1268 if (hw->phy_revision < M88E1011_I_REV_4) {
1269 /* Configure Master and Slave downshift values */
1270 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1148 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1271 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1272 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1150 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1273 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1274 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1152 phy_data); 1275 if(ret_val)
1153 if(ret_val) 1276 return ret_val;
1154 return ret_val; 1277 }
1155 }
1156 1278
1157 /* SW Reset the PHY so all changes take effect */ 1279 /* SW Reset the PHY so all changes take effect */
1158 ret_val = e1000_phy_reset(hw); 1280 ret_val = e1000_phy_reset(hw);
1159 if(ret_val) { 1281 if(ret_val) {
1160 DEBUGOUT("Error Resetting the PHY\n"); 1282 DEBUGOUT("Error Resetting the PHY\n");
1161 return ret_val; 1283 return ret_val;
1162 } 1284 }
1285
1286 return E1000_SUCCESS;
1287}
1288
1289/********************************************************************
1290* Setup auto-negotiation and flow control advertisements,
1291* and then perform auto-negotiation.
1292*
1293* hw - Struct containing variables accessed by shared code
1294*********************************************************************/
1295static int32_t
1296e1000_copper_link_autoneg(struct e1000_hw *hw)
1297{
1298 int32_t ret_val;
1299 uint16_t phy_data;
1300
1301 DEBUGFUNC("e1000_copper_link_autoneg");
1302
1303 /* Perform some bounds checking on the hw->autoneg_advertised
1304 * parameter. If this variable is zero, then set it to the default.
1305 */
1306 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1307
1308 /* If autoneg_advertised is zero, we assume it was not defaulted
1309 * by the calling code so we set to advertise full capability.
1310 */
1311 if(hw->autoneg_advertised == 0)
1312 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1313
1314 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1315 ret_val = e1000_phy_setup_autoneg(hw);
1316 if(ret_val) {
1317 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1318 return ret_val;
1319 }
1320 DEBUGOUT("Restarting Auto-Neg\n");
1321
1322 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1323 * the Auto Neg Restart bit in the PHY control register.
1324 */
1325 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1326 if(ret_val)
1327 return ret_val;
1328
1329 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1330 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1331 if(ret_val)
1332 return ret_val;
1333
1334 /* Does the user want to wait for Auto-Neg to complete here, or
1335 * check at a later time (for example, callback routine).
1336 */
1337 if(hw->wait_autoneg_complete) {
1338 ret_val = e1000_wait_autoneg(hw);
1339 if(ret_val) {
1340 DEBUGOUT("Error while waiting for autoneg to complete\n");
1341 return ret_val;
1163 } 1342 }
1343 }
1164 1344
1165 /* Options: 1345 hw->get_link_status = TRUE;
1166 * autoneg = 1 (default)
1167 * PHY will advertise value(s) parsed from
1168 * autoneg_advertised and fc
1169 * autoneg = 0
1170 * PHY will be set to 10H, 10F, 100H, or 100F
1171 * depending on value parsed from forced_speed_duplex.
1172 */
1173 1346
1174 /* Is autoneg enabled? This is enabled by default or by software 1347 return E1000_SUCCESS;
1175 * override. If so, call e1000_phy_setup_autoneg routine to parse the 1348}
1176 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177 * the user should have provided a speed/duplex override. If so, then
1178 * call e1000_phy_force_speed_duplex to parse and set this up.
1179 */
1180 if(hw->autoneg) {
1181 /* Perform some bounds checking on the hw->autoneg_advertised
1182 * parameter. If this variable is zero, then set it to the default.
1183 */
1184 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1185 1349
1186 /* If autoneg_advertised is zero, we assume it was not defaulted
1187 * by the calling code so we set to advertise full capability.
1188 */
1189 if(hw->autoneg_advertised == 0)
1190 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1191 1350
1192 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1351/******************************************************************************
1193 ret_val = e1000_phy_setup_autoneg(hw); 1352* Config the MAC and the PHY after link is up.
1194 if(ret_val) { 1353* 1) Set up the MAC to the current PHY speed/duplex
1195 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1354* if we are on 82543. If we
1196 return ret_val; 1355* are on newer silicon, we only need to configure
1197 } 1356* collision distance in the Transmit Control Register.
1198 DEBUGOUT("Restarting Auto-Neg\n"); 1357* 2) Set up flow control on the MAC to that established with
1358* the link partner.
1359* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1360*
1361* hw - Struct containing variables accessed by shared code
1362******************************************************************************/
1363static int32_t
1364e1000_copper_link_postconfig(struct e1000_hw *hw)
1365{
1366 int32_t ret_val;
1367 DEBUGFUNC("e1000_copper_link_postconfig");
1368
1369 if(hw->mac_type >= e1000_82544) {
1370 e1000_config_collision_dist(hw);
1371 } else {
1372 ret_val = e1000_config_mac_to_phy(hw);
1373 if(ret_val) {
1374 DEBUGOUT("Error configuring MAC to PHY settings\n");
1375 return ret_val;
1376 }
1377 }
1378 ret_val = e1000_config_fc_after_link_up(hw);
1379 if(ret_val) {
1380 DEBUGOUT("Error Configuring Flow Control\n");
1381 return ret_val;
1382 }
1199 1383
1200 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1384 /* Config DSP to improve Giga link quality */
1201 * the Auto Neg Restart bit in the PHY control register. 1385 if(hw->phy_type == e1000_phy_igp) {
1202 */ 1386 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1203 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1387 if(ret_val) {
1204 if(ret_val) 1388 DEBUGOUT("Error Configuring DSP after link up\n");
1205 return ret_val; 1389 return ret_val;
1390 }
1391 }
1392
1393 return E1000_SUCCESS;
1394}
1206 1395
1207 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1396/******************************************************************************
1208 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1397* Detects which PHY is present and setup the speed and duplex
1209 if(ret_val) 1398*
1210 return ret_val; 1399* hw - Struct containing variables accessed by shared code
1400******************************************************************************/
1401static int32_t
1402e1000_setup_copper_link(struct e1000_hw *hw)
1403{
1404 int32_t ret_val;
1405 uint16_t i;
1406 uint16_t phy_data;
1211 1407
1212 /* Does the user want to wait for Auto-Neg to complete here, or 1408 DEBUGFUNC("e1000_setup_copper_link");
1213 * check at a later time (for example, callback routine). 1409
1214 */ 1410 /* Check if it is a valid PHY and set PHY mode if necessary. */
1215 if(hw->wait_autoneg_complete) { 1411 ret_val = e1000_copper_link_preconfig(hw);
1216 ret_val = e1000_wait_autoneg(hw); 1412 if(ret_val)
1217 if(ret_val) { 1413 return ret_val;
1218 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1414
1219 return ret_val; 1415 if (hw->phy_type == e1000_phy_igp ||
1220 } 1416 hw->phy_type == e1000_phy_igp_2) {
1221 } 1417 ret_val = e1000_copper_link_igp_setup(hw);
1222 hw->get_link_status = TRUE; 1418 if(ret_val)
1223 } else { 1419 return ret_val;
1224 DEBUGOUT("Forcing speed and duplex\n"); 1420 } else if (hw->phy_type == e1000_phy_m88) {
1225 ret_val = e1000_phy_force_speed_duplex(hw); 1421 ret_val = e1000_copper_link_mgp_setup(hw);
1226 if(ret_val) { 1422 if(ret_val)
1227 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1423 return ret_val;
1228 return ret_val; 1424 }
1229 } 1425
1426 if(hw->autoneg) {
1427 /* Setup autoneg and flow control advertisement
1428 * and perform autonegotiation */
1429 ret_val = e1000_copper_link_autoneg(hw);
1430 if(ret_val)
1431 return ret_val;
1432 } else {
1433 /* PHY will be set to 10H, 10F, 100H,or 100F
1434 * depending on value from forced_speed_duplex. */
1435 DEBUGOUT("Forcing speed and duplex\n");
1436 ret_val = e1000_phy_force_speed_duplex(hw);
1437 if(ret_val) {
1438 DEBUGOUT("Error Forcing Speed and Duplex\n");
1439 return ret_val;
1230 } 1440 }
1231 } /* !hw->phy_reset_disable */ 1441 }
1232 1442
1233 /* Check link status. Wait up to 100 microseconds for link to become 1443 /* Check link status. Wait up to 100 microseconds for link to become
1234 * valid. 1444 * valid.
@@ -1242,37 +1452,11 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1242 return ret_val; 1452 return ret_val;
1243 1453
1244 if(phy_data & MII_SR_LINK_STATUS) { 1454 if(phy_data & MII_SR_LINK_STATUS) {
1245 /* We have link, so we need to finish the config process: 1455 /* Config the MAC and PHY after link is up */
1246 * 1) Set up the MAC to the current PHY speed/duplex 1456 ret_val = e1000_copper_link_postconfig(hw);
1247 * if we are on 82543. If we 1457 if(ret_val)
1248 * are on newer silicon, we only need to configure
1249 * collision distance in the Transmit Control Register.
1250 * 2) Set up flow control on the MAC to that established with
1251 * the link partner.
1252 */
1253 if(hw->mac_type >= e1000_82544) {
1254 e1000_config_collision_dist(hw);
1255 } else {
1256 ret_val = e1000_config_mac_to_phy(hw);
1257 if(ret_val) {
1258 DEBUGOUT("Error configuring MAC to PHY settings\n");
1259 return ret_val;
1260 }
1261 }
1262 ret_val = e1000_config_fc_after_link_up(hw);
1263 if(ret_val) {
1264 DEBUGOUT("Error Configuring Flow Control\n");
1265 return ret_val; 1458 return ret_val;
1266 } 1459
1267 DEBUGOUT("Valid link established!!!\n");
1268
1269 if(hw->phy_type == e1000_phy_igp) {
1270 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271 if(ret_val) {
1272 DEBUGOUT("Error Configuring DSP after link up\n");
1273 return ret_val;
1274 }
1275 }
1276 DEBUGOUT("Valid link established!!!\n"); 1460 DEBUGOUT("Valid link established!!!\n");
1277 return E1000_SUCCESS; 1461 return E1000_SUCCESS;
1278 } 1462 }
@@ -1302,10 +1486,10 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1302 if(ret_val) 1486 if(ret_val)
1303 return ret_val; 1487 return ret_val;
1304 1488
1305 /* Read the MII 1000Base-T Control Register (Address 9). */ 1489 /* Read the MII 1000Base-T Control Register (Address 9). */
1306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1490 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307 if(ret_val) 1491 if(ret_val)
1308 return ret_val; 1492 return ret_val;
1309 1493
1310 /* Need to parse both autoneg_advertised and fc and set up 1494 /* Need to parse both autoneg_advertised and fc and set up
1311 * the appropriate PHY registers. First we will parse for 1495 * the appropriate PHY registers. First we will parse for
@@ -1417,7 +1601,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1417 1601
1418 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1602 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1419 1603
1420 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1604 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421 if(ret_val) 1605 if(ret_val)
1422 return ret_val; 1606 return ret_val;
1423 1607
@@ -1678,6 +1862,11 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1678 1862
1679 DEBUGFUNC("e1000_config_mac_to_phy"); 1863 DEBUGFUNC("e1000_config_mac_to_phy");
1680 1864
1865 /* 82544 or newer MAC, Auto Speed Detection takes care of
1866 * MAC speed/duplex configuration.*/
1867 if (hw->mac_type >= e1000_82544)
1868 return E1000_SUCCESS;
1869
1681 /* Read the Device Control Register and set the bits to Force Speed 1870 /* Read the Device Control Register and set the bits to Force Speed
1682 * and Duplex. 1871 * and Duplex.
1683 */ 1872 */
@@ -1688,45 +1877,25 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1688 /* Set up duplex in the Device Control and Transmit Control 1877 /* Set up duplex in the Device Control and Transmit Control
1689 * registers depending on negotiated values. 1878 * registers depending on negotiated values.
1690 */ 1879 */
1691 if (hw->phy_type == e1000_phy_igp) { 1880 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1692 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 1881 if(ret_val)
1693 &phy_data); 1882 return ret_val;
1694 if(ret_val)
1695 return ret_val;
1696
1697 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1698 else ctrl &= ~E1000_CTRL_FD;
1699
1700 e1000_config_collision_dist(hw);
1701 1883
1702 /* Set up speed in the Device Control register depending on 1884 if(phy_data & M88E1000_PSSR_DPLX)
1703 * negotiated values. 1885 ctrl |= E1000_CTRL_FD;
1704 */ 1886 else
1705 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 1887 ctrl &= ~E1000_CTRL_FD;
1706 IGP01E1000_PSSR_SPEED_1000MBPS)
1707 ctrl |= E1000_CTRL_SPD_1000;
1708 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1709 IGP01E1000_PSSR_SPEED_100MBPS)
1710 ctrl |= E1000_CTRL_SPD_100;
1711 } else {
1712 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1713 &phy_data);
1714 if(ret_val)
1715 return ret_val;
1716 1888
1717 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; 1889 e1000_config_collision_dist(hw);
1718 else ctrl &= ~E1000_CTRL_FD;
1719 1890
1720 e1000_config_collision_dist(hw); 1891 /* Set up speed in the Device Control register depending on
1892 * negotiated values.
1893 */
1894 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1895 ctrl |= E1000_CTRL_SPD_1000;
1896 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1897 ctrl |= E1000_CTRL_SPD_100;
1721 1898
1722 /* Set up speed in the Device Control register depending on
1723 * negotiated values.
1724 */
1725 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1726 ctrl |= E1000_CTRL_SPD_1000;
1727 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1728 ctrl |= E1000_CTRL_SPD_100;
1729 }
1730 /* Write the configured values back to the Device Control Reg. */ 1899 /* Write the configured values back to the Device Control Reg. */
1731 E1000_WRITE_REG(hw, CTRL, ctrl); 1900 E1000_WRITE_REG(hw, CTRL, ctrl);
1732 return E1000_SUCCESS; 1901 return E1000_SUCCESS;
@@ -2494,8 +2663,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
2494 2663
2495 DEBUGFUNC("e1000_read_phy_reg"); 2664 DEBUGFUNC("e1000_read_phy_reg");
2496 2665
2497 2666 if((hw->phy_type == e1000_phy_igp ||
2498 if(hw->phy_type == e1000_phy_igp && 2667 hw->phy_type == e1000_phy_igp_2) &&
2499 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2668 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2500 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2669 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2501 (uint16_t)reg_addr); 2670 (uint16_t)reg_addr);
@@ -2600,8 +2769,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
2600 2769
2601 DEBUGFUNC("e1000_write_phy_reg"); 2770 DEBUGFUNC("e1000_write_phy_reg");
2602 2771
2603 2772 if((hw->phy_type == e1000_phy_igp ||
2604 if(hw->phy_type == e1000_phy_igp && 2773 hw->phy_type == e1000_phy_igp_2) &&
2605 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2774 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2606 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2775 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2607 (uint16_t)reg_addr); 2776 (uint16_t)reg_addr);
@@ -2679,19 +2848,27 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
2679 return E1000_SUCCESS; 2848 return E1000_SUCCESS;
2680} 2849}
2681 2850
2851
2682/****************************************************************************** 2852/******************************************************************************
2683* Returns the PHY to the power-on reset state 2853* Returns the PHY to the power-on reset state
2684* 2854*
2685* hw - Struct containing variables accessed by shared code 2855* hw - Struct containing variables accessed by shared code
2686******************************************************************************/ 2856******************************************************************************/
2687void 2857int32_t
2688e1000_phy_hw_reset(struct e1000_hw *hw) 2858e1000_phy_hw_reset(struct e1000_hw *hw)
2689{ 2859{
2690 uint32_t ctrl, ctrl_ext; 2860 uint32_t ctrl, ctrl_ext;
2691 uint32_t led_ctrl; 2861 uint32_t led_ctrl;
2862 int32_t ret_val;
2692 2863
2693 DEBUGFUNC("e1000_phy_hw_reset"); 2864 DEBUGFUNC("e1000_phy_hw_reset");
2694 2865
2866 /* In the case of the phy reset being blocked, it's not an error, we
2867 * simply return success without performing the reset. */
2868 ret_val = e1000_check_phy_reset_block(hw);
2869 if (ret_val)
2870 return E1000_SUCCESS;
2871
2695 DEBUGOUT("Resetting Phy...\n"); 2872 DEBUGOUT("Resetting Phy...\n");
2696 2873
2697 if(hw->mac_type > e1000_82543) { 2874 if(hw->mac_type > e1000_82543) {
@@ -2727,6 +2904,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
2727 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2904 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2728 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2905 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2729 } 2906 }
2907
2908 /* Wait for FW to finish PHY configuration. */
2909 ret_val = e1000_get_phy_cfg_done(hw);
2910
2911 return ret_val;
2730} 2912}
2731 2913
2732/****************************************************************************** 2914/******************************************************************************
@@ -2744,7 +2926,19 @@ e1000_phy_reset(struct e1000_hw *hw)
2744 2926
2745 DEBUGFUNC("e1000_phy_reset"); 2927 DEBUGFUNC("e1000_phy_reset");
2746 2928
2747 if(hw->mac_type != e1000_82541_rev_2) { 2929 /* In the case of the phy reset being blocked, it's not an error, we
2930 * simply return success without performing the reset. */
2931 ret_val = e1000_check_phy_reset_block(hw);
2932 if (ret_val)
2933 return E1000_SUCCESS;
2934
2935 switch (hw->mac_type) {
2936 case e1000_82541_rev_2:
2937 ret_val = e1000_phy_hw_reset(hw);
2938 if(ret_val)
2939 return ret_val;
2940 break;
2941 default:
2748 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2942 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2749 if(ret_val) 2943 if(ret_val)
2750 return ret_val; 2944 return ret_val;
@@ -2755,9 +2949,10 @@ e1000_phy_reset(struct e1000_hw *hw)
2755 return ret_val; 2949 return ret_val;
2756 2950
2757 udelay(1); 2951 udelay(1);
2758 } else e1000_phy_hw_reset(hw); 2952 break;
2953 }
2759 2954
2760 if(hw->phy_type == e1000_phy_igp) 2955 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
2761 e1000_phy_init_script(hw); 2956 e1000_phy_init_script(hw);
2762 2957
2763 return E1000_SUCCESS; 2958 return E1000_SUCCESS;
@@ -2811,6 +3006,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
2811 case e1000_82547_rev_2: 3006 case e1000_82547_rev_2:
2812 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3007 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2813 break; 3008 break;
3009 case e1000_82573:
3010 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3011 break;
2814 default: 3012 default:
2815 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3013 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2816 return -E1000_ERR_CONFIG; 3014 return -E1000_ERR_CONFIG;
@@ -2866,7 +3064,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2866 3064
2867 /* The downshift status is checked only once, after link is established, 3065 /* The downshift status is checked only once, after link is established,
2868 * and it stored in the hw->speed_downgraded parameter. */ 3066 * and it stored in the hw->speed_downgraded parameter. */
2869 phy_info->downshift = hw->speed_downgraded; 3067 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2870 3068
2871 /* IGP01E1000 does not need to support it. */ 3069 /* IGP01E1000 does not need to support it. */
2872 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3070 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
@@ -2905,7 +3103,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2905 if(ret_val) 3103 if(ret_val)
2906 return ret_val; 3104 return ret_val;
2907 3105
2908 /* transalte to old method */ 3106 /* Translate to old method */
2909 average = (max_length + min_length) / 2; 3107 average = (max_length + min_length) / 2;
2910 3108
2911 if(average <= e1000_igp_cable_length_50) 3109 if(average <= e1000_igp_cable_length_50)
@@ -2940,7 +3138,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
2940 3138
2941 /* The downshift status is checked only once, after link is established, 3139 /* The downshift status is checked only once, after link is established,
2942 * and it stored in the hw->speed_downgraded parameter. */ 3140 * and it stored in the hw->speed_downgraded parameter. */
2943 phy_info->downshift = hw->speed_downgraded; 3141 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2944 3142
2945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3143 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2946 if(ret_val) 3144 if(ret_val)
@@ -3029,7 +3227,8 @@ e1000_phy_get_info(struct e1000_hw *hw,
3029 return -E1000_ERR_CONFIG; 3227 return -E1000_ERR_CONFIG;
3030 } 3228 }
3031 3229
3032 if(hw->phy_type == e1000_phy_igp) 3230 if(hw->phy_type == e1000_phy_igp ||
3231 hw->phy_type == e1000_phy_igp_2)
3033 return e1000_phy_igp_get_info(hw, phy_info); 3232 return e1000_phy_igp_get_info(hw, phy_info);
3034 else 3233 else
3035 return e1000_phy_m88_get_info(hw, phy_info); 3234 return e1000_phy_m88_get_info(hw, phy_info);
@@ -3055,11 +3254,12 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
3055 * 3254 *
3056 * hw - Struct containing variables accessed by shared code 3255 * hw - Struct containing variables accessed by shared code
3057 *****************************************************************************/ 3256 *****************************************************************************/
3058void 3257int32_t
3059e1000_init_eeprom_params(struct e1000_hw *hw) 3258e1000_init_eeprom_params(struct e1000_hw *hw)
3060{ 3259{
3061 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3260 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3062 uint32_t eecd = E1000_READ_REG(hw, EECD); 3261 uint32_t eecd = E1000_READ_REG(hw, EECD);
3262 int32_t ret_val = E1000_SUCCESS;
3063 uint16_t eeprom_size; 3263 uint16_t eeprom_size;
3064 3264
3065 DEBUGFUNC("e1000_init_eeprom_params"); 3265 DEBUGFUNC("e1000_init_eeprom_params");
@@ -3074,6 +3274,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3074 eeprom->opcode_bits = 3; 3274 eeprom->opcode_bits = 3;
3075 eeprom->address_bits = 6; 3275 eeprom->address_bits = 6;
3076 eeprom->delay_usec = 50; 3276 eeprom->delay_usec = 50;
3277 eeprom->use_eerd = FALSE;
3278 eeprom->use_eewr = FALSE;
3077 break; 3279 break;
3078 case e1000_82540: 3280 case e1000_82540:
3079 case e1000_82545: 3281 case e1000_82545:
@@ -3090,6 +3292,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3090 eeprom->word_size = 64; 3292 eeprom->word_size = 64;
3091 eeprom->address_bits = 6; 3293 eeprom->address_bits = 6;
3092 } 3294 }
3295 eeprom->use_eerd = FALSE;
3296 eeprom->use_eewr = FALSE;
3093 break; 3297 break;
3094 case e1000_82541: 3298 case e1000_82541:
3095 case e1000_82541_rev_2: 3299 case e1000_82541_rev_2:
@@ -3118,42 +3322,60 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3118 eeprom->address_bits = 6; 3322 eeprom->address_bits = 6;
3119 } 3323 }
3120 } 3324 }
3325 eeprom->use_eerd = FALSE;
3326 eeprom->use_eewr = FALSE;
3327 break;
3328 case e1000_82573:
3329 eeprom->type = e1000_eeprom_spi;
3330 eeprom->opcode_bits = 8;
3331 eeprom->delay_usec = 1;
3332 if (eecd & E1000_EECD_ADDR_BITS) {
3333 eeprom->page_size = 32;
3334 eeprom->address_bits = 16;
3335 } else {
3336 eeprom->page_size = 8;
3337 eeprom->address_bits = 8;
3338 }
3339 eeprom->use_eerd = TRUE;
3340 eeprom->use_eewr = TRUE;
3341 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
3342 eeprom->type = e1000_eeprom_flash;
3343 eeprom->word_size = 2048;
3344
3345 /* Ensure that the Autonomous FLASH update bit is cleared due to
3346 * Flash update issue on parts which use a FLASH for NVM. */
3347 eecd &= ~E1000_EECD_AUPDEN;
3348 E1000_WRITE_REG(hw, EECD, eecd);
3349 }
3121 break; 3350 break;
3122 default: 3351 default:
3123 break; 3352 break;
3124 } 3353 }
3125 3354
3126 if (eeprom->type == e1000_eeprom_spi) { 3355 if (eeprom->type == e1000_eeprom_spi) {
3127 eeprom->word_size = 64; 3356 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3128 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) { 3357 * 32KB (incremented by powers of 2).
3129 eeprom_size &= EEPROM_SIZE_MASK; 3358 */
3130 3359 if(hw->mac_type <= e1000_82547_rev_2) {
3131 switch (eeprom_size) { 3360 /* Set to default value for initial eeprom read. */
3132 case EEPROM_SIZE_16KB: 3361 eeprom->word_size = 64;
3133 eeprom->word_size = 8192; 3362 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3134 break; 3363 if(ret_val)
3135 case EEPROM_SIZE_8KB: 3364 return ret_val;
3136 eeprom->word_size = 4096; 3365 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3137 break; 3366 /* 256B eeprom size was not supported in earlier hardware, so we
3138 case EEPROM_SIZE_4KB: 3367 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3139 eeprom->word_size = 2048; 3368 * is never the result used in the shifting logic below. */
3140 break; 3369 if(eeprom_size)
3141 case EEPROM_SIZE_2KB: 3370 eeprom_size++;
3142 eeprom->word_size = 1024; 3371 } else {
3143 break; 3372 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
3144 case EEPROM_SIZE_1KB: 3373 E1000_EECD_SIZE_EX_SHIFT);
3145 eeprom->word_size = 512;
3146 break;
3147 case EEPROM_SIZE_512B:
3148 eeprom->word_size = 256;
3149 break;
3150 case EEPROM_SIZE_128B:
3151 default:
3152 eeprom->word_size = 64;
3153 break;
3154 }
3155 } 3374 }
3375
3376 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3156 } 3377 }
3378 return ret_val;
3157} 3379}
3158 3380
3159/****************************************************************************** 3381/******************************************************************************
@@ -3306,8 +3528,12 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3306 3528
3307 DEBUGFUNC("e1000_acquire_eeprom"); 3529 DEBUGFUNC("e1000_acquire_eeprom");
3308 3530
3531 if(e1000_get_hw_eeprom_semaphore(hw))
3532 return -E1000_ERR_EEPROM;
3533
3309 eecd = E1000_READ_REG(hw, EECD); 3534 eecd = E1000_READ_REG(hw, EECD);
3310 3535
3536 if (hw->mac_type != e1000_82573) {
3311 /* Request EEPROM Access */ 3537 /* Request EEPROM Access */
3312 if(hw->mac_type > e1000_82544) { 3538 if(hw->mac_type > e1000_82544) {
3313 eecd |= E1000_EECD_REQ; 3539 eecd |= E1000_EECD_REQ;
@@ -3326,6 +3552,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3326 return -E1000_ERR_EEPROM; 3552 return -E1000_ERR_EEPROM;
3327 } 3553 }
3328 } 3554 }
3555 }
3329 3556
3330 /* Setup EEPROM for Read/Write */ 3557 /* Setup EEPROM for Read/Write */
3331 3558
@@ -3443,6 +3670,8 @@ e1000_release_eeprom(struct e1000_hw *hw)
3443 eecd &= ~E1000_EECD_REQ; 3670 eecd &= ~E1000_EECD_REQ;
3444 E1000_WRITE_REG(hw, EECD, eecd); 3671 E1000_WRITE_REG(hw, EECD, eecd);
3445 } 3672 }
3673
3674 e1000_put_hw_eeprom_semaphore(hw);
3446} 3675}
3447 3676
3448/****************************************************************************** 3677/******************************************************************************
@@ -3504,8 +3733,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
3504{ 3733{
3505 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3734 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3506 uint32_t i = 0; 3735 uint32_t i = 0;
3736 int32_t ret_val;
3507 3737
3508 DEBUGFUNC("e1000_read_eeprom"); 3738 DEBUGFUNC("e1000_read_eeprom");
3739
3509 /* A check for invalid values: offset too large, too many words, and not 3740 /* A check for invalid values: offset too large, too many words, and not
3510 * enough words. 3741 * enough words.
3511 */ 3742 */
@@ -3515,9 +3746,23 @@ e1000_read_eeprom(struct e1000_hw *hw,
3515 return -E1000_ERR_EEPROM; 3746 return -E1000_ERR_EEPROM;
3516 } 3747 }
3517 3748
3518 /* Prepare the EEPROM for reading */ 3749 /* FLASH reads without acquiring the semaphore are safe in 82573-based
3519 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3750 * controllers.
3520 return -E1000_ERR_EEPROM; 3751 */
3752 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3753 (hw->mac_type != e1000_82573)) {
3754 /* Prepare the EEPROM for reading */
3755 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3756 return -E1000_ERR_EEPROM;
3757 }
3758
3759 if(eeprom->use_eerd == TRUE) {
3760 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
3761 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3762 (hw->mac_type != e1000_82573))
3763 e1000_release_eeprom(hw);
3764 return ret_val;
3765 }
3521 3766
3522 if(eeprom->type == e1000_eeprom_spi) { 3767 if(eeprom->type == e1000_eeprom_spi) {
3523 uint16_t word_in; 3768 uint16_t word_in;
@@ -3569,6 +3814,132 @@ e1000_read_eeprom(struct e1000_hw *hw,
3569} 3814}
3570 3815
3571/****************************************************************************** 3816/******************************************************************************
3817 * Reads a 16 bit word from the EEPROM using the EERD register.
3818 *
3819 * hw - Struct containing variables accessed by shared code
3820 * offset - offset of word in the EEPROM to read
3821 * data - word read from the EEPROM
3822 * words - number of words to read
3823 *****************************************************************************/
3824int32_t
3825e1000_read_eeprom_eerd(struct e1000_hw *hw,
3826 uint16_t offset,
3827 uint16_t words,
3828 uint16_t *data)
3829{
3830 uint32_t i, eerd = 0;
3831 int32_t error = 0;
3832
3833 for (i = 0; i < words; i++) {
3834 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
3835 E1000_EEPROM_RW_REG_START;
3836
3837 E1000_WRITE_REG(hw, EERD, eerd);
3838 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
3839
3840 if(error) {
3841 break;
3842 }
3843 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
3844
3845 }
3846
3847 return error;
3848}
3849
3850/******************************************************************************
3851 * Writes a 16 bit word from the EEPROM using the EEWR register.
3852 *
3853 * hw - Struct containing variables accessed by shared code
3854 * offset - offset of word in the EEPROM to read
3855 * data - word read from the EEPROM
3856 * words - number of words to read
3857 *****************************************************************************/
3858int32_t
3859e1000_write_eeprom_eewr(struct e1000_hw *hw,
3860 uint16_t offset,
3861 uint16_t words,
3862 uint16_t *data)
3863{
3864 uint32_t register_value = 0;
3865 uint32_t i = 0;
3866 int32_t error = 0;
3867
3868 for (i = 0; i < words; i++) {
3869 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
3870 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
3871 E1000_EEPROM_RW_REG_START;
3872
3873 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3874 if(error) {
3875 break;
3876 }
3877
3878 E1000_WRITE_REG(hw, EEWR, register_value);
3879
3880 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3881
3882 if(error) {
3883 break;
3884 }
3885 }
3886
3887 return error;
3888}
3889
3890/******************************************************************************
3891 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
3892 *
3893 * hw - Struct containing variables accessed by shared code
3894 *****************************************************************************/
3895int32_t
3896e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
3897{
3898 uint32_t attempts = 100000;
3899 uint32_t i, reg = 0;
3900 int32_t done = E1000_ERR_EEPROM;
3901
3902 for(i = 0; i < attempts; i++) {
3903 if(eerd == E1000_EEPROM_POLL_READ)
3904 reg = E1000_READ_REG(hw, EERD);
3905 else
3906 reg = E1000_READ_REG(hw, EEWR);
3907
3908 if(reg & E1000_EEPROM_RW_REG_DONE) {
3909 done = E1000_SUCCESS;
3910 break;
3911 }
3912 udelay(5);
3913 }
3914
3915 return done;
3916}
3917
3918/***************************************************************************
3919* Description: Determines if the onboard NVM is FLASH or EEPROM.
3920*
3921* hw - Struct containing variables accessed by shared code
3922****************************************************************************/
3923boolean_t
3924e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
3925{
3926 uint32_t eecd = 0;
3927
3928 if(hw->mac_type == e1000_82573) {
3929 eecd = E1000_READ_REG(hw, EECD);
3930
3931 /* Isolate bits 15 & 16 */
3932 eecd = ((eecd >> 15) & 0x03);
3933
3934 /* If both bits are set, device is Flash type */
3935 if(eecd == 0x03) {
3936 return FALSE;
3937 }
3938 }
3939 return TRUE;
3940}
3941
3942/******************************************************************************
3572 * Verifies that the EEPROM has a valid checksum 3943 * Verifies that the EEPROM has a valid checksum
3573 * 3944 *
3574 * hw - Struct containing variables accessed by shared code 3945 * hw - Struct containing variables accessed by shared code
@@ -3585,6 +3956,25 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3585 3956
3586 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3957 DEBUGFUNC("e1000_validate_eeprom_checksum");
3587 3958
3959 if ((hw->mac_type == e1000_82573) &&
3960 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
3961 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
3962 * 10h-12h. Checksum may need to be fixed. */
3963 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
3964 if ((eeprom_data & 0x10) == 0) {
3965 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
3966 * has already been fixed. If the checksum is still wrong and this
3967 * bit is a 1, we need to return bad checksum. Otherwise, we need
3968 * to set this bit to a 1 and update the checksum. */
3969 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
3970 if ((eeprom_data & 0x8000) == 0) {
3971 eeprom_data |= 0x8000;
3972 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
3973 e1000_update_eeprom_checksum(hw);
3974 }
3975 }
3976 }
3977
3588 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3978 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3589 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3979 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3590 DEBUGOUT("EEPROM Read Error\n"); 3980 DEBUGOUT("EEPROM Read Error\n");
@@ -3628,6 +4018,8 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
3628 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4018 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3629 DEBUGOUT("EEPROM Write Error\n"); 4019 DEBUGOUT("EEPROM Write Error\n");
3630 return -E1000_ERR_EEPROM; 4020 return -E1000_ERR_EEPROM;
4021 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4022 e1000_commit_shadow_ram(hw);
3631 } 4023 }
3632 return E1000_SUCCESS; 4024 return E1000_SUCCESS;
3633} 4025}
@@ -3663,6 +4055,10 @@ e1000_write_eeprom(struct e1000_hw *hw,
3663 return -E1000_ERR_EEPROM; 4055 return -E1000_ERR_EEPROM;
3664 } 4056 }
3665 4057
4058 /* 82573 reads only through eerd */
4059 if(eeprom->use_eewr == TRUE)
4060 return e1000_write_eeprom_eewr(hw, offset, words, data);
4061
3666 /* Prepare the EEPROM for writing */ 4062 /* Prepare the EEPROM for writing */
3667 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4063 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3668 return -E1000_ERR_EEPROM; 4064 return -E1000_ERR_EEPROM;
@@ -3833,6 +4229,65 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
3833} 4229}
3834 4230
3835/****************************************************************************** 4231/******************************************************************************
4232 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4233 * in the eeprom cache and the non modified values in the currently active bank
4234 * to the new bank.
4235 *
4236 * hw - Struct containing variables accessed by shared code
4237 * offset - offset of word in the EEPROM to read
4238 * data - word read from the EEPROM
4239 * words - number of words to read
4240 *****************************************************************************/
4241int32_t
4242e1000_commit_shadow_ram(struct e1000_hw *hw)
4243{
4244 uint32_t attempts = 100000;
4245 uint32_t eecd = 0;
4246 uint32_t flop = 0;
4247 uint32_t i = 0;
4248 int32_t error = E1000_SUCCESS;
4249
4250 /* The flop register will be used to determine if flash type is STM */
4251 flop = E1000_READ_REG(hw, FLOP);
4252
4253 if (hw->mac_type == e1000_82573) {
4254 for (i=0; i < attempts; i++) {
4255 eecd = E1000_READ_REG(hw, EECD);
4256 if ((eecd & E1000_EECD_FLUPD) == 0) {
4257 break;
4258 }
4259 udelay(5);
4260 }
4261
4262 if (i == attempts) {
4263 return -E1000_ERR_EEPROM;
4264 }
4265
4266 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4267 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4268 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4269 }
4270
4271 /* Perform the flash update */
4272 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4273
4274 for (i=0; i < attempts; i++) {
4275 eecd = E1000_READ_REG(hw, EECD);
4276 if ((eecd & E1000_EECD_FLUPD) == 0) {
4277 break;
4278 }
4279 udelay(5);
4280 }
4281
4282 if (i == attempts) {
4283 return -E1000_ERR_EEPROM;
4284 }
4285 }
4286
4287 return error;
4288}
4289
4290/******************************************************************************
3836 * Reads the adapter's part number from the EEPROM 4291 * Reads the adapter's part number from the EEPROM
3837 * 4292 *
3838 * hw - Struct containing variables accessed by shared code 4293 * hw - Struct containing variables accessed by shared code
@@ -3911,6 +4366,7 @@ void
3911e1000_init_rx_addrs(struct e1000_hw *hw) 4366e1000_init_rx_addrs(struct e1000_hw *hw)
3912{ 4367{
3913 uint32_t i; 4368 uint32_t i;
4369 uint32_t rar_num;
3914 4370
3915 DEBUGFUNC("e1000_init_rx_addrs"); 4371 DEBUGFUNC("e1000_init_rx_addrs");
3916 4372
@@ -3919,9 +4375,10 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
3919 4375
3920 e1000_rar_set(hw, hw->mac_addr, 0); 4376 e1000_rar_set(hw, hw->mac_addr, 0);
3921 4377
4378 rar_num = E1000_RAR_ENTRIES;
3922 /* Zero out the other 15 receive addresses. */ 4379 /* Zero out the other 15 receive addresses. */
3923 DEBUGOUT("Clearing RAR[1-15]\n"); 4380 DEBUGOUT("Clearing RAR[1-15]\n");
3924 for(i = 1; i < E1000_RAR_ENTRIES; i++) { 4381 for(i = 1; i < rar_num; i++) {
3925 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4382 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3926 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4383 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3927 } 4384 }
@@ -3950,7 +4407,9 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3950{ 4407{
3951 uint32_t hash_value; 4408 uint32_t hash_value;
3952 uint32_t i; 4409 uint32_t i;
3953 4410 uint32_t num_rar_entry;
4411 uint32_t num_mta_entry;
4412
3954 DEBUGFUNC("e1000_mc_addr_list_update"); 4413 DEBUGFUNC("e1000_mc_addr_list_update");
3955 4414
3956 /* Set the new number of MC addresses that we are being requested to use. */ 4415 /* Set the new number of MC addresses that we are being requested to use. */
@@ -3958,14 +4417,16 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3958 4417
3959 /* Clear RAR[1-15] */ 4418 /* Clear RAR[1-15] */
3960 DEBUGOUT(" Clearing RAR[1-15]\n"); 4419 DEBUGOUT(" Clearing RAR[1-15]\n");
3961 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) { 4420 num_rar_entry = E1000_RAR_ENTRIES;
4421 for(i = rar_used_count; i < num_rar_entry; i++) {
3962 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4422 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3963 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4423 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3964 } 4424 }
3965 4425
3966 /* Clear the MTA */ 4426 /* Clear the MTA */
3967 DEBUGOUT(" Clearing MTA\n"); 4427 DEBUGOUT(" Clearing MTA\n");
3968 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) { 4428 num_mta_entry = E1000_NUM_MTA_REGISTERS;
4429 for(i = 0; i < num_mta_entry; i++) {
3969 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 4430 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3970 } 4431 }
3971 4432
@@ -3989,7 +4450,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3989 /* Place this multicast address in the RAR if there is room, * 4450 /* Place this multicast address in the RAR if there is room, *
3990 * else put it in the MTA 4451 * else put it in the MTA
3991 */ 4452 */
3992 if(rar_used_count < E1000_RAR_ENTRIES) { 4453 if (rar_used_count < num_rar_entry) {
3993 e1000_rar_set(hw, 4454 e1000_rar_set(hw,
3994 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), 4455 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3995 rar_used_count); 4456 rar_used_count);
@@ -4040,6 +4501,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
4040 } 4501 }
4041 4502
4042 hash_value &= 0xFFF; 4503 hash_value &= 0xFFF;
4504
4043 return hash_value; 4505 return hash_value;
4044} 4506}
4045 4507
@@ -4144,12 +4606,33 @@ void
4144e1000_clear_vfta(struct e1000_hw *hw) 4606e1000_clear_vfta(struct e1000_hw *hw)
4145{ 4607{
4146 uint32_t offset; 4608 uint32_t offset;
4147 4609 uint32_t vfta_value = 0;
4148 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 4610 uint32_t vfta_offset = 0;
4149 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 4611 uint32_t vfta_bit_in_reg = 0;
4612
4613 if (hw->mac_type == e1000_82573) {
4614 if (hw->mng_cookie.vlan_id != 0) {
4615 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4616 * ID. The following operations determine which 32b entry
4617 * (i.e. offset) into the array we want to set the VLAN ID
4618 * (i.e. bit) of the manageability unit. */
4619 vfta_offset = (hw->mng_cookie.vlan_id >>
4620 E1000_VFTA_ENTRY_SHIFT) &
4621 E1000_VFTA_ENTRY_MASK;
4622 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
4623 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
4624 }
4625 }
4626 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4627 /* If the offset we want to clear is the same offset of the
4628 * manageability VLAN ID, then clear all bits except that of the
4629 * manageability unit */
4630 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4631 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4632 }
4150} 4633}
4151 4634
4152static int32_t 4635int32_t
4153e1000_id_led_init(struct e1000_hw * hw) 4636e1000_id_led_init(struct e1000_hw * hw)
4154{ 4637{
4155 uint32_t ledctl; 4638 uint32_t ledctl;
@@ -4480,6 +4963,19 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
4480 temp = E1000_READ_REG(hw, MGTPRC); 4963 temp = E1000_READ_REG(hw, MGTPRC);
4481 temp = E1000_READ_REG(hw, MGTPDC); 4964 temp = E1000_READ_REG(hw, MGTPDC);
4482 temp = E1000_READ_REG(hw, MGTPTC); 4965 temp = E1000_READ_REG(hw, MGTPTC);
4966
4967 if(hw->mac_type <= e1000_82547_rev_2) return;
4968
4969 temp = E1000_READ_REG(hw, IAC);
4970 temp = E1000_READ_REG(hw, ICRXOC);
4971 temp = E1000_READ_REG(hw, ICRXPTC);
4972 temp = E1000_READ_REG(hw, ICRXATC);
4973 temp = E1000_READ_REG(hw, ICTXPTC);
4974 temp = E1000_READ_REG(hw, ICTXATC);
4975 temp = E1000_READ_REG(hw, ICTXQEC);
4976 temp = E1000_READ_REG(hw, ICTXQMTC);
4977 temp = E1000_READ_REG(hw, ICRXDMTC);
4978
4483} 4979}
4484 4980
4485/****************************************************************************** 4981/******************************************************************************
@@ -4646,6 +5142,11 @@ e1000_get_bus_info(struct e1000_hw *hw)
4646 hw->bus_speed = e1000_bus_speed_unknown; 5142 hw->bus_speed = e1000_bus_speed_unknown;
4647 hw->bus_width = e1000_bus_width_unknown; 5143 hw->bus_width = e1000_bus_width_unknown;
4648 break; 5144 break;
5145 case e1000_82573:
5146 hw->bus_type = e1000_bus_type_pci_express;
5147 hw->bus_speed = e1000_bus_speed_2500;
5148 hw->bus_width = e1000_bus_width_pciex_4;
5149 break;
4649 default: 5150 default:
4650 status = E1000_READ_REG(hw, STATUS); 5151 status = E1000_READ_REG(hw, STATUS);
4651 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5152 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
@@ -4749,6 +5250,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
4749 5250
4750 /* Use old method for Phy older than IGP */ 5251 /* Use old method for Phy older than IGP */
4751 if(hw->phy_type == e1000_phy_m88) { 5252 if(hw->phy_type == e1000_phy_m88) {
5253
4752 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5254 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4753 &phy_data); 5255 &phy_data);
4754 if(ret_val) 5256 if(ret_val)
@@ -4865,7 +5367,8 @@ e1000_check_polarity(struct e1000_hw *hw,
4865 return ret_val; 5367 return ret_val;
4866 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 5368 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4867 M88E1000_PSSR_REV_POLARITY_SHIFT; 5369 M88E1000_PSSR_REV_POLARITY_SHIFT;
4868 } else if(hw->phy_type == e1000_phy_igp) { 5370 } else if(hw->phy_type == e1000_phy_igp ||
5371 hw->phy_type == e1000_phy_igp_2) {
4869 /* Read the Status register to check the speed */ 5372 /* Read the Status register to check the speed */
4870 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5373 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4871 &phy_data); 5374 &phy_data);
@@ -4917,7 +5420,8 @@ e1000_check_downshift(struct e1000_hw *hw)
4917 5420
4918 DEBUGFUNC("e1000_check_downshift"); 5421 DEBUGFUNC("e1000_check_downshift");
4919 5422
4920 if(hw->phy_type == e1000_phy_igp) { 5423 if(hw->phy_type == e1000_phy_igp ||
5424 hw->phy_type == e1000_phy_igp_2) {
4921 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5425 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4922 &phy_data); 5426 &phy_data);
4923 if(ret_val) 5427 if(ret_val)
@@ -4933,6 +5437,7 @@ e1000_check_downshift(struct e1000_hw *hw)
4933 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5437 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4934 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5438 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4935 } 5439 }
5440
4936 return E1000_SUCCESS; 5441 return E1000_SUCCESS;
4937} 5442}
4938 5443
@@ -5047,7 +5552,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5047 if(ret_val) 5552 if(ret_val)
5048 return ret_val; 5553 return ret_val;
5049 5554
5050 msec_delay(20); 5555 msec_delay_irq(20);
5051 5556
5052 ret_val = e1000_write_phy_reg(hw, 0x0000, 5557 ret_val = e1000_write_phy_reg(hw, 0x0000,
5053 IGP01E1000_IEEE_FORCE_GIGA); 5558 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5071,7 +5576,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5071 if(ret_val) 5576 if(ret_val)
5072 return ret_val; 5577 return ret_val;
5073 5578
5074 msec_delay(20); 5579 msec_delay_irq(20);
5075 5580
5076 /* Now enable the transmitter */ 5581 /* Now enable the transmitter */
5077 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5582 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5096,7 +5601,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5096 if(ret_val) 5601 if(ret_val)
5097 return ret_val; 5602 return ret_val;
5098 5603
5099 msec_delay(20); 5604 msec_delay_irq(20);
5100 5605
5101 ret_val = e1000_write_phy_reg(hw, 0x0000, 5606 ret_val = e1000_write_phy_reg(hw, 0x0000,
5102 IGP01E1000_IEEE_FORCE_GIGA); 5607 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5112,7 +5617,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5112 if(ret_val) 5617 if(ret_val)
5113 return ret_val; 5618 return ret_val;
5114 5619
5115 msec_delay(20); 5620 msec_delay_irq(20);
5116 5621
5117 /* Now enable the transmitter */ 5622 /* Now enable the transmitter */
5118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5623 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5187,22 +5692,36 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5187 uint16_t phy_data; 5692 uint16_t phy_data;
5188 DEBUGFUNC("e1000_set_d3_lplu_state"); 5693 DEBUGFUNC("e1000_set_d3_lplu_state");
5189 5694
5190 if(!((hw->mac_type == e1000_82541_rev_2) || 5695 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
5191 (hw->mac_type == e1000_82547_rev_2)))
5192 return E1000_SUCCESS; 5696 return E1000_SUCCESS;
5193 5697
5194 /* During driver activity LPLU should not be used or it will attain link 5698 /* During driver activity LPLU should not be used or it will attain link
5195 * from the lowest speeds starting from 10Mbps. The capability is used for 5699 * from the lowest speeds starting from 10Mbps. The capability is used for
5196 * Dx transitions and states */ 5700 * Dx transitions and states */
5197 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5701 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
5198 if(ret_val) 5702 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5199 return ret_val;
5200
5201 if(!active) {
5202 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5204 if(ret_val) 5703 if(ret_val)
5205 return ret_val; 5704 return ret_val;
5705 } else {
5706 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5707 if(ret_val)
5708 return ret_val;
5709 }
5710
5711 if(!active) {
5712 if(hw->mac_type == e1000_82541_rev_2 ||
5713 hw->mac_type == e1000_82547_rev_2) {
5714 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5715 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5716 if(ret_val)
5717 return ret_val;
5718 } else {
5719 phy_data &= ~IGP02E1000_PM_D3_LPLU;
5720 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5721 phy_data);
5722 if (ret_val)
5723 return ret_val;
5724 }
5206 5725
5207 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5726 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5208 * Dx states where the power conservation is most important. During 5727 * Dx states where the power conservation is most important. During
@@ -5236,11 +5755,105 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5236 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 5755 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5237 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 5756 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5238 5757
5239 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5758 if(hw->mac_type == e1000_82541_rev_2 ||
5240 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 5759 hw->mac_type == e1000_82547_rev_2) {
5760 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5761 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5762 if(ret_val)
5763 return ret_val;
5764 } else {
5765 phy_data |= IGP02E1000_PM_D3_LPLU;
5766 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5767 phy_data);
5768 if (ret_val)
5769 return ret_val;
5770 }
5771
5772 /* When LPLU is enabled we should disable SmartSpeed */
5773 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5774 if(ret_val)
5775 return ret_val;
5776
5777 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5778 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5241 if(ret_val) 5779 if(ret_val)
5242 return ret_val; 5780 return ret_val;
5243 5781
5782 }
5783 return E1000_SUCCESS;
5784}
5785
5786/*****************************************************************************
5787 *
5788 * This function sets the lplu d0 state according to the active flag. When
5789 * activating lplu this function also disables smart speed and vise versa.
5790 * lplu will not be activated unless the device autonegotiation advertisment
5791 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5792 * hw: Struct containing variables accessed by shared code
5793 * active - true to enable lplu false to disable lplu.
5794 *
5795 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5796 * E1000_SUCCESS at any other case.
5797 *
5798 ****************************************************************************/
5799
5800int32_t
5801e1000_set_d0_lplu_state(struct e1000_hw *hw,
5802 boolean_t active)
5803{
5804 int32_t ret_val;
5805 uint16_t phy_data;
5806 DEBUGFUNC("e1000_set_d0_lplu_state");
5807
5808 if(hw->mac_type <= e1000_82547_rev_2)
5809 return E1000_SUCCESS;
5810
5811 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5812 if(ret_val)
5813 return ret_val;
5814
5815 if (!active) {
5816 phy_data &= ~IGP02E1000_PM_D0_LPLU;
5817 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5818 if (ret_val)
5819 return ret_val;
5820
5821 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5822 * Dx states where the power conservation is most important. During
5823 * driver activity we should enable SmartSpeed, so performance is
5824 * maintained. */
5825 if (hw->smart_speed == e1000_smart_speed_on) {
5826 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5827 &phy_data);
5828 if(ret_val)
5829 return ret_val;
5830
5831 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5832 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5833 phy_data);
5834 if(ret_val)
5835 return ret_val;
5836 } else if (hw->smart_speed == e1000_smart_speed_off) {
5837 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5838 &phy_data);
5839 if (ret_val)
5840 return ret_val;
5841
5842 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5843 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5844 phy_data);
5845 if(ret_val)
5846 return ret_val;
5847 }
5848
5849
5850 } else {
5851
5852 phy_data |= IGP02E1000_PM_D0_LPLU;
5853 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5854 if (ret_val)
5855 return ret_val;
5856
5244 /* When LPLU is enabled we should disable SmartSpeed */ 5857 /* When LPLU is enabled we should disable SmartSpeed */
5245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 5858 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5246 if(ret_val) 5859 if(ret_val)
@@ -5318,6 +5931,338 @@ e1000_set_vco_speed(struct e1000_hw *hw)
5318 return E1000_SUCCESS; 5931 return E1000_SUCCESS;
5319} 5932}
5320 5933
5934
5935/*****************************************************************************
5936 * This function reads the cookie from ARC ram.
5937 *
5938 * returns: - E1000_SUCCESS .
5939 ****************************************************************************/
5940int32_t
5941e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
5942{
5943 uint8_t i;
5944 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
5945 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
5946
5947 length = (length >> 2);
5948 offset = (offset >> 2);
5949
5950 for (i = 0; i < length; i++) {
5951 *((uint32_t *) buffer + i) =
5952 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
5953 }
5954 return E1000_SUCCESS;
5955}
5956
5957
5958/*****************************************************************************
5959 * This function checks whether the HOST IF is enabled for command operaton
5960 * and also checks whether the previous command is completed.
5961 * It busy waits in case of previous command is not completed.
5962 *
5963 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
5964 * timeout
5965 * - E1000_SUCCESS for success.
5966 ****************************************************************************/
5967int32_t
5968e1000_mng_enable_host_if(struct e1000_hw * hw)
5969{
5970 uint32_t hicr;
5971 uint8_t i;
5972
5973 /* Check that the host interface is enabled. */
5974 hicr = E1000_READ_REG(hw, HICR);
5975 if ((hicr & E1000_HICR_EN) == 0) {
5976 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
5977 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5978 }
5979 /* check the previous command is completed */
5980 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
5981 hicr = E1000_READ_REG(hw, HICR);
5982 if (!(hicr & E1000_HICR_C))
5983 break;
5984 msec_delay_irq(1);
5985 }
5986
5987 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
5988 DEBUGOUT("Previous command timeout failed .\n");
5989 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5990 }
5991 return E1000_SUCCESS;
5992}
5993
5994/*****************************************************************************
5995 * This function writes the buffer content at the offset given on the host if.
5996 * It also does alignment considerations to do the writes in most efficient way.
5997 * Also fills up the sum of the buffer in *buffer parameter.
5998 *
5999 * returns - E1000_SUCCESS for success.
6000 ****************************************************************************/
6001int32_t
6002e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6003 uint16_t length, uint16_t offset, uint8_t *sum)
6004{
6005 uint8_t *tmp;
6006 uint8_t *bufptr = buffer;
6007 uint32_t data;
6008 uint16_t remaining, i, j, prev_bytes;
6009
6010 /* sum = only sum of the data and it is not checksum */
6011
6012 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6013 return -E1000_ERR_PARAM;
6014 }
6015
6016 tmp = (uint8_t *)&data;
6017 prev_bytes = offset & 0x3;
6018 offset &= 0xFFFC;
6019 offset >>= 2;
6020
6021 if (prev_bytes) {
6022 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6023 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6024 *(tmp + j) = *bufptr++;
6025 *sum += *(tmp + j);
6026 }
6027 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6028 length -= j - prev_bytes;
6029 offset++;
6030 }
6031
6032 remaining = length & 0x3;
6033 length -= remaining;
6034
6035 /* Calculate length in DWORDs */
6036 length >>= 2;
6037
6038 /* The device driver writes the relevant command block into the
6039 * ram area. */
6040 for (i = 0; i < length; i++) {
6041 for (j = 0; j < sizeof(uint32_t); j++) {
6042 *(tmp + j) = *bufptr++;
6043 *sum += *(tmp + j);
6044 }
6045
6046 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6047 }
6048 if (remaining) {
6049 for (j = 0; j < sizeof(uint32_t); j++) {
6050 if (j < remaining)
6051 *(tmp + j) = *bufptr++;
6052 else
6053 *(tmp + j) = 0;
6054
6055 *sum += *(tmp + j);
6056 }
6057 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6058 }
6059
6060 return E1000_SUCCESS;
6061}
6062
6063
6064/*****************************************************************************
6065 * This function writes the command header after does the checksum calculation.
6066 *
6067 * returns - E1000_SUCCESS for success.
6068 ****************************************************************************/
6069int32_t
6070e1000_mng_write_cmd_header(struct e1000_hw * hw,
6071 struct e1000_host_mng_command_header * hdr)
6072{
6073 uint16_t i;
6074 uint8_t sum;
6075 uint8_t *buffer;
6076
6077 /* Write the whole command header structure which includes sum of
6078 * the buffer */
6079
6080 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6081
6082 sum = hdr->checksum;
6083 hdr->checksum = 0;
6084
6085 buffer = (uint8_t *) hdr;
6086 i = length;
6087 while(i--)
6088 sum += buffer[i];
6089
6090 hdr->checksum = 0 - sum;
6091
6092 length >>= 2;
6093 /* The device driver writes the relevant command block into the ram area. */
6094 for (i = 0; i < length; i++)
6095 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6096
6097 return E1000_SUCCESS;
6098}
6099
6100
6101/*****************************************************************************
6102 * This function indicates to ARC that a new command is pending which completes
6103 * one write operation by the driver.
6104 *
6105 * returns - E1000_SUCCESS for success.
6106 ****************************************************************************/
6107int32_t
6108e1000_mng_write_commit(
6109 struct e1000_hw * hw)
6110{
6111 uint32_t hicr;
6112
6113 hicr = E1000_READ_REG(hw, HICR);
6114 /* Setting this bit tells the ARC that a new command is pending. */
6115 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6116
6117 return E1000_SUCCESS;
6118}
6119
6120
6121/*****************************************************************************
6122 * This function checks the mode of the firmware.
6123 *
6124 * returns - TRUE when the mode is IAMT or FALSE.
6125 ****************************************************************************/
6126boolean_t
6127e1000_check_mng_mode(
6128 struct e1000_hw *hw)
6129{
6130 uint32_t fwsm;
6131
6132 fwsm = E1000_READ_REG(hw, FWSM);
6133
6134 if((fwsm & E1000_FWSM_MODE_MASK) ==
6135 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6136 return TRUE;
6137
6138 return FALSE;
6139}
6140
6141
6142/*****************************************************************************
6143 * This function writes the dhcp info .
6144 ****************************************************************************/
6145int32_t
6146e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
6147 uint16_t length)
6148{
6149 int32_t ret_val;
6150 struct e1000_host_mng_command_header hdr;
6151
6152 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6153 hdr.command_length = length;
6154 hdr.reserved1 = 0;
6155 hdr.reserved2 = 0;
6156 hdr.checksum = 0;
6157
6158 ret_val = e1000_mng_enable_host_if(hw);
6159 if (ret_val == E1000_SUCCESS) {
6160 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6161 &(hdr.checksum));
6162 if (ret_val == E1000_SUCCESS) {
6163 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
6164 if (ret_val == E1000_SUCCESS)
6165 ret_val = e1000_mng_write_commit(hw);
6166 }
6167 }
6168 return ret_val;
6169}
6170
6171
6172/*****************************************************************************
6173 * This function calculates the checksum.
6174 *
6175 * returns - checksum of buffer contents.
6176 ****************************************************************************/
6177uint8_t
6178e1000_calculate_mng_checksum(char *buffer, uint32_t length)
6179{
6180 uint8_t sum = 0;
6181 uint32_t i;
6182
6183 if (!buffer)
6184 return 0;
6185
6186 for (i=0; i < length; i++)
6187 sum += buffer[i];
6188
6189 return (uint8_t) (0 - sum);
6190}
6191
6192/*****************************************************************************
6193 * This function checks whether tx pkt filtering needs to be enabled or not.
6194 *
6195 * returns - TRUE for packet filtering or FALSE.
6196 ****************************************************************************/
6197boolean_t
6198e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
6199{
6200 /* called in init as well as watchdog timer functions */
6201
6202 int32_t ret_val, checksum;
6203 boolean_t tx_filter = FALSE;
6204 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
6205 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
6206
6207 if (e1000_check_mng_mode(hw)) {
6208 ret_val = e1000_mng_enable_host_if(hw);
6209 if (ret_val == E1000_SUCCESS) {
6210 ret_val = e1000_host_if_read_cookie(hw, buffer);
6211 if (ret_val == E1000_SUCCESS) {
6212 checksum = hdr->checksum;
6213 hdr->checksum = 0;
6214 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
6215 checksum == e1000_calculate_mng_checksum((char *)buffer,
6216 E1000_MNG_DHCP_COOKIE_LENGTH)) {
6217 if (hdr->status &
6218 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
6219 tx_filter = TRUE;
6220 } else
6221 tx_filter = TRUE;
6222 } else
6223 tx_filter = TRUE;
6224 }
6225 }
6226
6227 hw->tx_pkt_filtering = tx_filter;
6228 return tx_filter;
6229}
6230
6231/******************************************************************************
6232 * Verifies the hardware needs to allow ARPs to be processed by the host
6233 *
6234 * hw - Struct containing variables accessed by shared code
6235 *
6236 * returns: - TRUE/FALSE
6237 *
6238 *****************************************************************************/
6239uint32_t
6240e1000_enable_mng_pass_thru(struct e1000_hw *hw)
6241{
6242 uint32_t manc;
6243 uint32_t fwsm, factps;
6244
6245 if (hw->asf_firmware_present) {
6246 manc = E1000_READ_REG(hw, MANC);
6247
6248 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
6249 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
6250 return FALSE;
6251 if (e1000_arc_subsystem_valid(hw) == TRUE) {
6252 fwsm = E1000_READ_REG(hw, FWSM);
6253 factps = E1000_READ_REG(hw, FACTPS);
6254
6255 if (((fwsm & E1000_FWSM_MODE_MASK) ==
6256 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
6257 (factps & E1000_FACTPS_MNGCG))
6258 return TRUE;
6259 } else
6260 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
6261 return TRUE;
6262 }
6263 return FALSE;
6264}
6265
5321static int32_t 6266static int32_t
5322e1000_polarity_reversal_workaround(struct e1000_hw *hw) 6267e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5323{ 6268{
@@ -5403,3 +6348,265 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5403 return E1000_SUCCESS; 6348 return E1000_SUCCESS;
5404} 6349}
5405 6350
6351/***************************************************************************
6352 *
6353 * Disables PCI-Express master access.
6354 *
6355 * hw: Struct containing variables accessed by shared code
6356 *
6357 * returns: - none.
6358 *
6359 ***************************************************************************/
6360void
6361e1000_set_pci_express_master_disable(struct e1000_hw *hw)
6362{
6363 uint32_t ctrl;
6364
6365 DEBUGFUNC("e1000_set_pci_express_master_disable");
6366
6367 if (hw->bus_type != e1000_bus_type_pci_express)
6368 return;
6369
6370 ctrl = E1000_READ_REG(hw, CTRL);
6371 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
6372 E1000_WRITE_REG(hw, CTRL, ctrl);
6373}
6374
6375/***************************************************************************
6376 *
6377 * Enables PCI-Express master access.
6378 *
6379 * hw: Struct containing variables accessed by shared code
6380 *
6381 * returns: - none.
6382 *
6383 ***************************************************************************/
6384void
6385e1000_enable_pciex_master(struct e1000_hw *hw)
6386{
6387 uint32_t ctrl;
6388
6389 DEBUGFUNC("e1000_enable_pciex_master");
6390
6391 if (hw->bus_type != e1000_bus_type_pci_express)
6392 return;
6393
6394 ctrl = E1000_READ_REG(hw, CTRL);
6395 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
6396 E1000_WRITE_REG(hw, CTRL, ctrl);
6397}
6398
6399/*******************************************************************************
6400 *
6401 * Disables PCI-Express master access and verifies there are no pending requests
6402 *
6403 * hw: Struct containing variables accessed by shared code
6404 *
6405 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6406 * caused the master requests to be disabled.
6407 * E1000_SUCCESS master requests disabled.
6408 *
6409 ******************************************************************************/
6410int32_t
6411e1000_disable_pciex_master(struct e1000_hw *hw)
6412{
6413 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
6414
6415 DEBUGFUNC("e1000_disable_pciex_master");
6416
6417 if (hw->bus_type != e1000_bus_type_pci_express)
6418 return E1000_SUCCESS;
6419
6420 e1000_set_pci_express_master_disable(hw);
6421
6422 while(timeout) {
6423 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
6424 break;
6425 else
6426 udelay(100);
6427 timeout--;
6428 }
6429
6430 if(!timeout) {
6431 DEBUGOUT("Master requests are pending.\n");
6432 return -E1000_ERR_MASTER_REQUESTS_PENDING;
6433 }
6434
6435 return E1000_SUCCESS;
6436}
6437
6438/*******************************************************************************
6439 *
6440 * Check for EEPROM Auto Read bit done.
6441 *
6442 * hw: Struct containing variables accessed by shared code
6443 *
6444 * returns: - E1000_ERR_RESET if fail to reset MAC
6445 * E1000_SUCCESS at any other case.
6446 *
6447 ******************************************************************************/
6448int32_t
6449e1000_get_auto_rd_done(struct e1000_hw *hw)
6450{
6451 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
6452
6453 DEBUGFUNC("e1000_get_auto_rd_done");
6454
6455 switch (hw->mac_type) {
6456 default:
6457 msec_delay(5);
6458 break;
6459 case e1000_82573:
6460 while(timeout) {
6461 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
6462 else msec_delay(1);
6463 timeout--;
6464 }
6465
6466 if(!timeout) {
6467 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6468 return -E1000_ERR_RESET;
6469 }
6470 break;
6471 }
6472
6473 return E1000_SUCCESS;
6474}
6475
6476/***************************************************************************
6477 * Checks if the PHY configuration is done
6478 *
6479 * hw: Struct containing variables accessed by shared code
6480 *
6481 * returns: - E1000_ERR_RESET if fail to reset MAC
6482 * E1000_SUCCESS at any other case.
6483 *
6484 ***************************************************************************/
6485int32_t
6486e1000_get_phy_cfg_done(struct e1000_hw *hw)
6487{
6488 DEBUGFUNC("e1000_get_phy_cfg_done");
6489
6490 /* Simply wait for 10ms */
6491 msec_delay(10);
6492
6493 return E1000_SUCCESS;
6494}
6495
6496/***************************************************************************
6497 *
6498 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6499 * adapter or Eeprom access.
6500 *
6501 * hw: Struct containing variables accessed by shared code
6502 *
6503 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6504 * E1000_SUCCESS at any other case.
6505 *
6506 ***************************************************************************/
6507int32_t
6508e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
6509{
6510 int32_t timeout;
6511 uint32_t swsm;
6512
6513 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6514
6515 if(!hw->eeprom_semaphore_present)
6516 return E1000_SUCCESS;
6517
6518
6519 /* Get the FW semaphore. */
6520 timeout = hw->eeprom.word_size + 1;
6521 while(timeout) {
6522 swsm = E1000_READ_REG(hw, SWSM);
6523 swsm |= E1000_SWSM_SWESMBI;
6524 E1000_WRITE_REG(hw, SWSM, swsm);
6525 /* if we managed to set the bit we got the semaphore. */
6526 swsm = E1000_READ_REG(hw, SWSM);
6527 if(swsm & E1000_SWSM_SWESMBI)
6528 break;
6529
6530 udelay(50);
6531 timeout--;
6532 }
6533
6534 if(!timeout) {
6535 /* Release semaphores */
6536 e1000_put_hw_eeprom_semaphore(hw);
6537 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6538 return -E1000_ERR_EEPROM;
6539 }
6540
6541 return E1000_SUCCESS;
6542}
6543
6544/***************************************************************************
6545 * This function clears HW semaphore bits.
6546 *
6547 * hw: Struct containing variables accessed by shared code
6548 *
6549 * returns: - None.
6550 *
6551 ***************************************************************************/
6552void
6553e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
6554{
6555 uint32_t swsm;
6556
6557 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6558
6559 if(!hw->eeprom_semaphore_present)
6560 return;
6561
6562 swsm = E1000_READ_REG(hw, SWSM);
6563 /* Release both semaphores. */
6564 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
6565 E1000_WRITE_REG(hw, SWSM, swsm);
6566}
6567
6568/******************************************************************************
6569 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6570 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6571 * the caller to figure out how to deal with it.
6572 *
6573 * hw - Struct containing variables accessed by shared code
6574 *
6575 * returns: - E1000_BLK_PHY_RESET
6576 * E1000_SUCCESS
6577 *
6578 *****************************************************************************/
6579int32_t
6580e1000_check_phy_reset_block(struct e1000_hw *hw)
6581{
6582 uint32_t manc = 0;
6583 if(hw->mac_type > e1000_82547_rev_2)
6584 manc = E1000_READ_REG(hw, MANC);
6585 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
6586 E1000_BLK_PHY_RESET : E1000_SUCCESS;
6587}
6588
6589uint8_t
6590e1000_arc_subsystem_valid(struct e1000_hw *hw)
6591{
6592 uint32_t fwsm;
6593
6594 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6595 * may not be provided a DMA clock when no manageability features are
6596 * enabled. We do not want to perform any reads/writes to these registers
6597 * if this is the case. We read FWSM to determine the manageability mode.
6598 */
6599 switch (hw->mac_type) {
6600 case e1000_82573:
6601 fwsm = E1000_READ_REG(hw, FWSM);
6602 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
6603 return TRUE;
6604 break;
6605 default:
6606 break;
6607 }
6608 return FALSE;
6609}
6610
6611
6612
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 09:14:05 -0500