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path: root/drivers/net/e1000/e1000_hw.c
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c3281
1 files changed, 100 insertions, 3181 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 45ac225a7aaa..74aa59973316 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -35,49 +35,23 @@
35 35
36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask); 36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask); 37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
38static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
39static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
40static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42 38
43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static s32 e1000_check_downshift(struct e1000_hw *hw); 39static s32 e1000_check_downshift(struct e1000_hw *hw);
45static s32 e1000_check_polarity(struct e1000_hw *hw, 40static s32 e1000_check_polarity(struct e1000_hw *hw,
46 e1000_rev_polarity *polarity); 41 e1000_rev_polarity *polarity);
47static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 42static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
48static void e1000_clear_vfta(struct e1000_hw *hw); 43static void e1000_clear_vfta(struct e1000_hw *hw);
49static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
50static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 44static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
51 bool link_up); 45 bool link_up);
52static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 46static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
53static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 47static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
54static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
55static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 48static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
56static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 49static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
57 u16 *max_length); 50 u16 *max_length);
58static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); 51static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
59static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 52static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
60static s32 e1000_get_software_flag(struct e1000_hw *hw);
61static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
62static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
63static s32 e1000_id_led_init(struct e1000_hw *hw); 53static s32 e1000_id_led_init(struct e1000_hw *hw);
64static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
65 u32 cnf_base_addr,
66 u32 cnf_size);
67static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
68static void e1000_init_rx_addrs(struct e1000_hw *hw); 54static void e1000_init_rx_addrs(struct e1000_hw *hw);
69static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
70static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
71static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
72static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
73static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
74 u16 offset, u8 *sum);
75static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
76 struct e1000_host_mng_command_header
77 *hdr);
78static s32 e1000_mng_write_commit(struct e1000_hw *hw);
79static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
80 struct e1000_phy_info *phy_info);
81static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 55static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
82 struct e1000_phy_info *phy_info); 56 struct e1000_phy_info *phy_info);
83static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, 57static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
@@ -88,24 +62,7 @@ static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
88static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 62static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
89 struct e1000_phy_info *phy_info); 63 struct e1000_phy_info *phy_info);
90static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 64static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
91static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
92static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
93 u8 byte);
94static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
95static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
96static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
97 u16 *data);
98static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
99 u16 data);
100static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
101 u16 *data);
102static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
103 u16 *data);
104static void e1000_release_software_flag(struct e1000_hw *hw);
105static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 65static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
106static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
107static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
108static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
109static s32 e1000_wait_autoneg(struct e1000_hw *hw); 66static s32 e1000_wait_autoneg(struct e1000_hw *hw);
110static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); 67static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
111static s32 e1000_set_phy_type(struct e1000_hw *hw); 68static s32 e1000_set_phy_type(struct e1000_hw *hw);
@@ -140,10 +97,6 @@ static void e1000_standby_eeprom(struct e1000_hw *hw);
140static s32 e1000_set_vco_speed(struct e1000_hw *hw); 97static s32 e1000_set_vco_speed(struct e1000_hw *hw);
141static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 98static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
142static s32 e1000_set_phy_mode(struct e1000_hw *hw); 99static s32 e1000_set_phy_mode(struct e1000_hw *hw);
143static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
144static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
145static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);
146static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
147static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 100static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
148static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 101static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
149 102
@@ -159,17 +112,6 @@ u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
159 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 112 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
160 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 113 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
161 114
162static const
163u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
164 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
165 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
166 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
167 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
168 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
169 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
170 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
171 104, 109, 114, 118, 121, 124};
172
173static DEFINE_SPINLOCK(e1000_eeprom_lock); 115static DEFINE_SPINLOCK(e1000_eeprom_lock);
174 116
175/****************************************************************************** 117/******************************************************************************
@@ -199,20 +141,6 @@ static s32 e1000_set_phy_type(struct e1000_hw *hw)
199 hw->phy_type = e1000_phy_igp; 141 hw->phy_type = e1000_phy_igp;
200 break; 142 break;
201 } 143 }
202 case IGP03E1000_E_PHY_ID:
203 hw->phy_type = e1000_phy_igp_3;
204 break;
205 case IFE_E_PHY_ID:
206 case IFE_PLUS_E_PHY_ID:
207 case IFE_C_E_PHY_ID:
208 hw->phy_type = e1000_phy_ife;
209 break;
210 case GG82563_E_PHY_ID:
211 if (hw->mac_type == e1000_80003es2lan) {
212 hw->phy_type = e1000_phy_gg82563;
213 break;
214 }
215 /* Fall Through */
216 default: 144 default:
217 /* Should never have loaded on this device */ 145 /* Should never have loaded on this device */
218 hw->phy_type = e1000_phy_undefined; 146 hw->phy_type = e1000_phy_undefined;
@@ -397,61 +325,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
397 case E1000_DEV_ID_82547GI: 325 case E1000_DEV_ID_82547GI:
398 hw->mac_type = e1000_82547_rev_2; 326 hw->mac_type = e1000_82547_rev_2;
399 break; 327 break;
400 case E1000_DEV_ID_82571EB_COPPER:
401 case E1000_DEV_ID_82571EB_FIBER:
402 case E1000_DEV_ID_82571EB_SERDES:
403 case E1000_DEV_ID_82571EB_SERDES_DUAL:
404 case E1000_DEV_ID_82571EB_SERDES_QUAD:
405 case E1000_DEV_ID_82571EB_QUAD_COPPER:
406 case E1000_DEV_ID_82571PT_QUAD_COPPER:
407 case E1000_DEV_ID_82571EB_QUAD_FIBER:
408 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
409 hw->mac_type = e1000_82571;
410 break;
411 case E1000_DEV_ID_82572EI_COPPER:
412 case E1000_DEV_ID_82572EI_FIBER:
413 case E1000_DEV_ID_82572EI_SERDES:
414 case E1000_DEV_ID_82572EI:
415 hw->mac_type = e1000_82572;
416 break;
417 case E1000_DEV_ID_82573E:
418 case E1000_DEV_ID_82573E_IAMT:
419 case E1000_DEV_ID_82573L:
420 hw->mac_type = e1000_82573;
421 break;
422 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
423 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
424 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
425 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
426 hw->mac_type = e1000_80003es2lan;
427 break;
428 case E1000_DEV_ID_ICH8_IGP_M_AMT:
429 case E1000_DEV_ID_ICH8_IGP_AMT:
430 case E1000_DEV_ID_ICH8_IGP_C:
431 case E1000_DEV_ID_ICH8_IFE:
432 case E1000_DEV_ID_ICH8_IFE_GT:
433 case E1000_DEV_ID_ICH8_IFE_G:
434 case E1000_DEV_ID_ICH8_IGP_M:
435 hw->mac_type = e1000_ich8lan;
436 break;
437 default: 328 default:
438 /* Should never have loaded on this device */ 329 /* Should never have loaded on this device */
439 return -E1000_ERR_MAC_TYPE; 330 return -E1000_ERR_MAC_TYPE;
440 } 331 }
441 332
442 switch (hw->mac_type) { 333 switch (hw->mac_type) {
443 case e1000_ich8lan:
444 hw->swfwhw_semaphore_present = true;
445 hw->asf_firmware_present = true;
446 break;
447 case e1000_80003es2lan:
448 hw->swfw_sync_present = true;
449 /* fall through */
450 case e1000_82571:
451 case e1000_82572:
452 case e1000_82573:
453 hw->eeprom_semaphore_present = true;
454 /* fall through */
455 case e1000_82541: 334 case e1000_82541:
456 case e1000_82547: 335 case e1000_82547:
457 case e1000_82541_rev_2: 336 case e1000_82541_rev_2:
@@ -468,16 +347,6 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
468 if (hw->mac_type == e1000_82543) 347 if (hw->mac_type == e1000_82543)
469 hw->bad_tx_carr_stats_fd = true; 348 hw->bad_tx_carr_stats_fd = true;
470 349
471 /* capable of receiving management packets to the host */
472 if (hw->mac_type >= e1000_82571)
473 hw->has_manc2h = true;
474
475 /* In rare occasions, ESB2 systems would end up started without
476 * the RX unit being turned on.
477 */
478 if (hw->mac_type == e1000_80003es2lan)
479 hw->rx_needs_kicking = true;
480
481 if (hw->mac_type > e1000_82544) 350 if (hw->mac_type > e1000_82544)
482 hw->has_smbus = true; 351 hw->has_smbus = true;
483 352
@@ -503,11 +372,6 @@ void e1000_set_media_type(struct e1000_hw *hw)
503 switch (hw->device_id) { 372 switch (hw->device_id) {
504 case E1000_DEV_ID_82545GM_SERDES: 373 case E1000_DEV_ID_82545GM_SERDES:
505 case E1000_DEV_ID_82546GB_SERDES: 374 case E1000_DEV_ID_82546GB_SERDES:
506 case E1000_DEV_ID_82571EB_SERDES:
507 case E1000_DEV_ID_82571EB_SERDES_DUAL:
508 case E1000_DEV_ID_82571EB_SERDES_QUAD:
509 case E1000_DEV_ID_82572EI_SERDES:
510 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
511 hw->media_type = e1000_media_type_internal_serdes; 375 hw->media_type = e1000_media_type_internal_serdes;
512 break; 376 break;
513 default: 377 default:
@@ -516,13 +380,6 @@ void e1000_set_media_type(struct e1000_hw *hw)
516 case e1000_82542_rev2_1: 380 case e1000_82542_rev2_1:
517 hw->media_type = e1000_media_type_fiber; 381 hw->media_type = e1000_media_type_fiber;
518 break; 382 break;
519 case e1000_ich8lan:
520 case e1000_82573:
521 /* The STATUS_TBIMODE bit is reserved or reused for the this
522 * device.
523 */
524 hw->media_type = e1000_media_type_copper;
525 break;
526 default: 383 default:
527 status = er32(STATUS); 384 status = er32(STATUS);
528 if (status & E1000_STATUS_TBIMODE) { 385 if (status & E1000_STATUS_TBIMODE) {
@@ -549,8 +406,6 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
549 u32 icr; 406 u32 icr;
550 u32 manc; 407 u32 manc;
551 u32 led_ctrl; 408 u32 led_ctrl;
552 u32 timeout;
553 u32 extcnf_ctrl;
554 s32 ret_val; 409 s32 ret_val;
555 410
556 DEBUGFUNC("e1000_reset_hw"); 411 DEBUGFUNC("e1000_reset_hw");
@@ -561,15 +416,6 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
561 e1000_pci_clear_mwi(hw); 416 e1000_pci_clear_mwi(hw);
562 } 417 }
563 418
564 if (hw->bus_type == e1000_bus_type_pci_express) {
565 /* Prevent the PCI-E bus from sticking if there is no TLP connection
566 * on the last TLP read/write transaction when MAC is reset.
567 */
568 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
569 DEBUGOUT("PCI-E Master disable polling has failed.\n");
570 }
571 }
572
573 /* Clear interrupt mask to stop board from generating interrupts */ 419 /* Clear interrupt mask to stop board from generating interrupts */
574 DEBUGOUT("Masking off all interrupts\n"); 420 DEBUGOUT("Masking off all interrupts\n");
575 ew32(IMC, 0xffffffff); 421 ew32(IMC, 0xffffffff);
@@ -598,36 +444,6 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
598 msleep(5); 444 msleep(5);
599 } 445 }
600 446
601 /* Must acquire the MDIO ownership before MAC reset.
602 * Ownership defaults to firmware after a reset. */
603 if (hw->mac_type == e1000_82573) {
604 timeout = 10;
605
606 extcnf_ctrl = er32(EXTCNF_CTRL);
607 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
608
609 do {
610 ew32(EXTCNF_CTRL, extcnf_ctrl);
611 extcnf_ctrl = er32(EXTCNF_CTRL);
612
613 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
614 break;
615 else
616 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
617
618 msleep(2);
619 timeout--;
620 } while (timeout);
621 }
622
623 /* Workaround for ICH8 bit corruption issue in FIFO memory */
624 if (hw->mac_type == e1000_ich8lan) {
625 /* Set Tx and Rx buffer allocation to 8k apiece. */
626 ew32(PBA, E1000_PBA_8K);
627 /* Set Packet Buffer Size to 16k. */
628 ew32(PBS, E1000_PBS_16K);
629 }
630
631 /* Issue a global reset to the MAC. This will reset the chip's 447 /* Issue a global reset to the MAC. This will reset the chip's
632 * transmit, receive, DMA, and link units. It will not effect 448 * transmit, receive, DMA, and link units. It will not effect
633 * the current PCI configuration. The global reset bit is self- 449 * the current PCI configuration. The global reset bit is self-
@@ -651,20 +467,6 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
651 /* Reset is performed on a shadow of the control register */ 467 /* Reset is performed on a shadow of the control register */
652 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); 468 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
653 break; 469 break;
654 case e1000_ich8lan:
655 if (!hw->phy_reset_disable &&
656 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
657 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
658 * at the same time to make sure the interface between
659 * MAC and the external PHY is reset.
660 */
661 ctrl |= E1000_CTRL_PHY_RST;
662 }
663
664 e1000_get_software_flag(hw);
665 ew32(CTRL, (ctrl | E1000_CTRL_RST));
666 msleep(5);
667 break;
668 default: 470 default:
669 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 471 ew32(CTRL, (ctrl | E1000_CTRL_RST));
670 break; 472 break;
@@ -695,15 +497,6 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
695 /* Wait for EEPROM reload */ 497 /* Wait for EEPROM reload */
696 msleep(20); 498 msleep(20);
697 break; 499 break;
698 case e1000_82573:
699 if (!e1000_is_onboard_nvm_eeprom(hw)) {
700 udelay(10);
701 ctrl_ext = er32(CTRL_EXT);
702 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
703 ew32(CTRL_EXT, ctrl_ext);
704 E1000_WRITE_FLUSH();
705 }
706 /* fall through */
707 default: 500 default:
708 /* Auto read done will delay 5ms or poll based on mac type */ 501 /* Auto read done will delay 5ms or poll based on mac type */
709 ret_val = e1000_get_auto_rd_done(hw); 502 ret_val = e1000_get_auto_rd_done(hw);
@@ -713,7 +506,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
713 } 506 }
714 507
715 /* Disable HW ARPs on ASF enabled adapters */ 508 /* Disable HW ARPs on ASF enabled adapters */
716 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { 509 if (hw->mac_type >= e1000_82540) {
717 manc = er32(MANC); 510 manc = er32(MANC);
718 manc &= ~(E1000_MANC_ARP_EN); 511 manc &= ~(E1000_MANC_ARP_EN);
719 ew32(MANC, manc); 512 ew32(MANC, manc);
@@ -742,132 +535,10 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
742 e1000_pci_set_mwi(hw); 535 e1000_pci_set_mwi(hw);
743 } 536 }
744 537
745 if (hw->mac_type == e1000_ich8lan) {
746 u32 kab = er32(KABGTXD);
747 kab |= E1000_KABGTXD_BGSQLBIAS;
748 ew32(KABGTXD, kab);
749 }
750
751 return E1000_SUCCESS; 538 return E1000_SUCCESS;
752} 539}
753 540
754/****************************************************************************** 541/******************************************************************************
755 *
756 * Initialize a number of hardware-dependent bits
757 *
758 * hw: Struct containing variables accessed by shared code
759 *
760 * This function contains hardware limitation workarounds for PCI-E adapters
761 *
762 *****************************************************************************/
763static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
764{
765 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
766 /* Settings common to all PCI-express silicon */
767 u32 reg_ctrl, reg_ctrl_ext;
768 u32 reg_tarc0, reg_tarc1;
769 u32 reg_tctl;
770 u32 reg_txdctl, reg_txdctl1;
771
772 /* link autonegotiation/sync workarounds */
773 reg_tarc0 = er32(TARC0);
774 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
775
776 /* Enable not-done TX descriptor counting */
777 reg_txdctl = er32(TXDCTL);
778 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
779 ew32(TXDCTL, reg_txdctl);
780 reg_txdctl1 = er32(TXDCTL1);
781 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
782 ew32(TXDCTL1, reg_txdctl1);
783
784 switch (hw->mac_type) {
785 case e1000_82571:
786 case e1000_82572:
787 /* Clear PHY TX compatible mode bits */
788 reg_tarc1 = er32(TARC1);
789 reg_tarc1 &= ~((1 << 30)|(1 << 29));
790
791 /* link autonegotiation/sync workarounds */
792 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
793
794 /* TX ring control fixes */
795 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
796
797 /* Multiple read bit is reversed polarity */
798 reg_tctl = er32(TCTL);
799 if (reg_tctl & E1000_TCTL_MULR)
800 reg_tarc1 &= ~(1 << 28);
801 else
802 reg_tarc1 |= (1 << 28);
803
804 ew32(TARC1, reg_tarc1);
805 break;
806 case e1000_82573:
807 reg_ctrl_ext = er32(CTRL_EXT);
808 reg_ctrl_ext &= ~(1 << 23);
809 reg_ctrl_ext |= (1 << 22);
810
811 /* TX byte count fix */
812 reg_ctrl = er32(CTRL);
813 reg_ctrl &= ~(1 << 29);
814
815 ew32(CTRL_EXT, reg_ctrl_ext);
816 ew32(CTRL, reg_ctrl);
817 break;
818 case e1000_80003es2lan:
819 /* improve small packet performace for fiber/serdes */
820 if ((hw->media_type == e1000_media_type_fiber) ||
821 (hw->media_type == e1000_media_type_internal_serdes)) {
822 reg_tarc0 &= ~(1 << 20);
823 }
824
825 /* Multiple read bit is reversed polarity */
826 reg_tctl = er32(TCTL);
827 reg_tarc1 = er32(TARC1);
828 if (reg_tctl & E1000_TCTL_MULR)
829 reg_tarc1 &= ~(1 << 28);
830 else
831 reg_tarc1 |= (1 << 28);
832
833 ew32(TARC1, reg_tarc1);
834 break;
835 case e1000_ich8lan:
836 /* Reduce concurrent DMA requests to 3 from 4 */
837 if ((hw->revision_id < 3) ||
838 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
839 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
840 reg_tarc0 |= ((1 << 29)|(1 << 28));
841
842 reg_ctrl_ext = er32(CTRL_EXT);
843 reg_ctrl_ext |= (1 << 22);
844 ew32(CTRL_EXT, reg_ctrl_ext);
845
846 /* workaround TX hang with TSO=on */
847 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
848
849 /* Multiple read bit is reversed polarity */
850 reg_tctl = er32(TCTL);
851 reg_tarc1 = er32(TARC1);
852 if (reg_tctl & E1000_TCTL_MULR)
853 reg_tarc1 &= ~(1 << 28);
854 else
855 reg_tarc1 |= (1 << 28);
856
857 /* workaround TX hang with TSO=on */
858 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
859
860 ew32(TARC1, reg_tarc1);
861 break;
862 default:
863 break;
864 }
865
866 ew32(TARC0, reg_tarc0);
867 }
868}
869
870/******************************************************************************
871 * Performs basic configuration of the adapter. 542 * Performs basic configuration of the adapter.
872 * 543 *
873 * hw - Struct containing variables accessed by shared code 544 * hw - Struct containing variables accessed by shared code
@@ -884,21 +555,10 @@ s32 e1000_init_hw(struct e1000_hw *hw)
884 u32 i; 555 u32 i;
885 s32 ret_val; 556 s32 ret_val;
886 u32 mta_size; 557 u32 mta_size;
887 u32 reg_data;
888 u32 ctrl_ext; 558 u32 ctrl_ext;
889 559
890 DEBUGFUNC("e1000_init_hw"); 560 DEBUGFUNC("e1000_init_hw");
891 561
892 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
893 if ((hw->mac_type == e1000_ich8lan) &&
894 ((hw->revision_id < 3) ||
895 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
896 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
897 reg_data = er32(STATUS);
898 reg_data &= ~0x80000000;
899 ew32(STATUS, reg_data);
900 }
901
902 /* Initialize Identification LED */ 562 /* Initialize Identification LED */
903 ret_val = e1000_id_led_init(hw); 563 ret_val = e1000_id_led_init(hw);
904 if (ret_val) { 564 if (ret_val) {
@@ -909,17 +569,11 @@ s32 e1000_init_hw(struct e1000_hw *hw)
909 /* Set the media type and TBI compatibility */ 569 /* Set the media type and TBI compatibility */
910 e1000_set_media_type(hw); 570 e1000_set_media_type(hw);
911 571
912 /* Must be called after e1000_set_media_type because media_type is used */
913 e1000_initialize_hardware_bits(hw);
914
915 /* Disabling VLAN filtering. */ 572 /* Disabling VLAN filtering. */
916 DEBUGOUT("Initializing the IEEE VLAN\n"); 573 DEBUGOUT("Initializing the IEEE VLAN\n");
917 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 574 if (hw->mac_type < e1000_82545_rev_3)
918 if (hw->mac_type != e1000_ich8lan) { 575 ew32(VET, 0);
919 if (hw->mac_type < e1000_82545_rev_3) 576 e1000_clear_vfta(hw);
920 ew32(VET, 0);
921 e1000_clear_vfta(hw);
922 }
923 577
924 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 578 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
925 if (hw->mac_type == e1000_82542_rev2_0) { 579 if (hw->mac_type == e1000_82542_rev2_0) {
@@ -947,8 +601,6 @@ s32 e1000_init_hw(struct e1000_hw *hw)
947 /* Zero out the Multicast HASH table */ 601 /* Zero out the Multicast HASH table */
948 DEBUGOUT("Zeroing the MTA\n"); 602 DEBUGOUT("Zeroing the MTA\n");
949 mta_size = E1000_MC_TBL_SIZE; 603 mta_size = E1000_MC_TBL_SIZE;
950 if (hw->mac_type == e1000_ich8lan)
951 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
952 for (i = 0; i < mta_size; i++) { 604 for (i = 0; i < mta_size; i++) {
953 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 605 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
954 /* use write flush to prevent Memory Write Block (MWB) from 606 /* use write flush to prevent Memory Write Block (MWB) from
@@ -977,10 +629,6 @@ s32 e1000_init_hw(struct e1000_hw *hw)
977 break; 629 break;
978 } 630 }
979 631
980 /* More time needed for PHY to initialize */
981 if (hw->mac_type == e1000_ich8lan)
982 msleep(15);
983
984 /* Call a subroutine to configure the link and setup flow control. */ 632 /* Call a subroutine to configure the link and setup flow control. */
985 ret_val = e1000_setup_link(hw); 633 ret_val = e1000_setup_link(hw);
986 634
@@ -991,51 +639,6 @@ s32 e1000_init_hw(struct e1000_hw *hw)
991 ew32(TXDCTL, ctrl); 639 ew32(TXDCTL, ctrl);
992 } 640 }
993 641
994 if (hw->mac_type == e1000_82573) {
995 e1000_enable_tx_pkt_filtering(hw);
996 }
997
998 switch (hw->mac_type) {
999 default:
1000 break;
1001 case e1000_80003es2lan:
1002 /* Enable retransmit on late collisions */
1003 reg_data = er32(TCTL);
1004 reg_data |= E1000_TCTL_RTLC;
1005 ew32(TCTL, reg_data);
1006
1007 /* Configure Gigabit Carry Extend Padding */
1008 reg_data = er32(TCTL_EXT);
1009 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1010 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1011 ew32(TCTL_EXT, reg_data);
1012
1013 /* Configure Transmit Inter-Packet Gap */
1014 reg_data = er32(TIPG);
1015 reg_data &= ~E1000_TIPG_IPGT_MASK;
1016 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1017 ew32(TIPG, reg_data);
1018
1019 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1020 reg_data &= ~0x00100000;
1021 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1022 /* Fall through */
1023 case e1000_82571:
1024 case e1000_82572:
1025 case e1000_ich8lan:
1026 ctrl = er32(TXDCTL1);
1027 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1028 ew32(TXDCTL1, ctrl);
1029 break;
1030 }
1031
1032
1033 if (hw->mac_type == e1000_82573) {
1034 u32 gcr = er32(GCR);
1035 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1036 ew32(GCR, gcr);
1037 }
1038
1039 /* Clear all of the statistics registers (clear on read). It is 642 /* Clear all of the statistics registers (clear on read). It is
1040 * important that we do this after we have tried to establish link 643 * important that we do this after we have tried to establish link
1041 * because the symbol error count will increment wildly if there 644 * because the symbol error count will increment wildly if there
@@ -1043,11 +646,6 @@ s32 e1000_init_hw(struct e1000_hw *hw)
1043 */ 646 */
1044 e1000_clear_hw_cntrs(hw); 647 e1000_clear_hw_cntrs(hw);
1045 648
1046 /* ICH8 No-snoop bits are opposite polarity.
1047 * Set to snoop by default after reset. */
1048 if (hw->mac_type == e1000_ich8lan)
1049 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1050
1051 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 649 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1052 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 650 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1053 ctrl_ext = er32(CTRL_EXT); 651 ctrl_ext = er32(CTRL_EXT);
@@ -1118,11 +716,6 @@ s32 e1000_setup_link(struct e1000_hw *hw)
1118 716
1119 DEBUGFUNC("e1000_setup_link"); 717 DEBUGFUNC("e1000_setup_link");
1120 718
1121 /* In the case of the phy reset being blocked, we already have a link.
1122 * We do not have to set it up again. */
1123 if (e1000_check_phy_reset_block(hw))
1124 return E1000_SUCCESS;
1125
1126 /* Read and store word 0x0F of the EEPROM. This word contains bits 719 /* Read and store word 0x0F of the EEPROM. This word contains bits
1127 * that determine the hardware's default PAUSE (flow control) mode, 720 * that determine the hardware's default PAUSE (flow control) mode,
1128 * a bit that determines whether the HW defaults to enabling or 721 * a bit that determines whether the HW defaults to enabling or
@@ -1132,27 +725,19 @@ s32 e1000_setup_link(struct e1000_hw *hw)
1132 * be initialized based on a value in the EEPROM. 725 * be initialized based on a value in the EEPROM.
1133 */ 726 */
1134 if (hw->fc == E1000_FC_DEFAULT) { 727 if (hw->fc == E1000_FC_DEFAULT) {
1135 switch (hw->mac_type) { 728 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1136 case e1000_ich8lan: 729 1, &eeprom_data);
1137 case e1000_82573: 730 if (ret_val) {
1138 hw->fc = E1000_FC_FULL; 731 DEBUGOUT("EEPROM Read Error\n");
1139 break; 732 return -E1000_ERR_EEPROM;
1140 default:
1141 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1142 1, &eeprom_data);
1143 if (ret_val) {
1144 DEBUGOUT("EEPROM Read Error\n");
1145 return -E1000_ERR_EEPROM;
1146 }
1147 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1148 hw->fc = E1000_FC_NONE;
1149 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1150 EEPROM_WORD0F_ASM_DIR)
1151 hw->fc = E1000_FC_TX_PAUSE;
1152 else
1153 hw->fc = E1000_FC_FULL;
1154 break;
1155 } 733 }
734 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
735 hw->fc = E1000_FC_NONE;
736 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
737 EEPROM_WORD0F_ASM_DIR)
738 hw->fc = E1000_FC_TX_PAUSE;
739 else
740 hw->fc = E1000_FC_FULL;
1156 } 741 }
1157 742
1158 /* We want to save off the original Flow Control configuration just 743 /* We want to save off the original Flow Control configuration just
@@ -1200,12 +785,9 @@ s32 e1000_setup_link(struct e1000_hw *hw)
1200 */ 785 */
1201 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 786 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1202 787
1203 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 788 ew32(FCT, FLOW_CONTROL_TYPE);
1204 if (hw->mac_type != e1000_ich8lan) { 789 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1205 ew32(FCT, FLOW_CONTROL_TYPE); 790 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
1206 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1207 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
1208 }
1209 791
1210 ew32(FCTTV, hw->fc_pause_time); 792 ew32(FCTTV, hw->fc_pause_time);
1211 793
@@ -1253,14 +835,6 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1253 835
1254 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 836 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1255 837
1256 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1257 * until explicitly turned off or a power cycle is performed. A read to
1258 * the register does not indicate its status. Therefore, we ensure
1259 * loopback mode is disabled during initialization.
1260 */
1261 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1262 ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1263
1264 /* On adapters with a MAC newer than 82544, SWDP 1 will be 838 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1265 * set when the optics detect a signal. On older adapters, it will be 839 * set when the optics detect a signal. On older adapters, it will be
1266 * cleared when there is a signal. This applies to fiber media only. 840 * cleared when there is a signal. This applies to fiber media only.
@@ -1466,13 +1040,11 @@ static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1466 1040
1467 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1041 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1468 msleep(15); 1042 msleep(15);
1469 if (hw->mac_type != e1000_ich8lan) {
1470 /* Configure activity LED after PHY reset */ 1043 /* Configure activity LED after PHY reset */
1471 led_ctrl = er32(LEDCTL); 1044 led_ctrl = er32(LEDCTL);
1472 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1045 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1473 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1046 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1474 ew32(LEDCTL, led_ctrl); 1047 ew32(LEDCTL, led_ctrl);
1475 }
1476 1048
1477 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1049 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1478 if (hw->phy_type == e1000_phy_igp) { 1050 if (hw->phy_type == e1000_phy_igp) {
@@ -1484,12 +1056,6 @@ static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1484 } 1056 }
1485 } 1057 }
1486 1058
1487 /* disable lplu d0 during driver init */
1488 ret_val = e1000_set_d0_lplu_state(hw, false);
1489 if (ret_val) {
1490 DEBUGOUT("Error Disabling LPLU D0\n");
1491 return ret_val;
1492 }
1493 /* Configure mdi-mdix settings */ 1059 /* Configure mdi-mdix settings */
1494 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1060 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1495 if (ret_val) 1061 if (ret_val)
@@ -1589,153 +1155,6 @@ static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1589} 1155}
1590 1156
1591/******************************************************************** 1157/********************************************************************
1592* Copper link setup for e1000_phy_gg82563 series.
1593*
1594* hw - Struct containing variables accessed by shared code
1595*********************************************************************/
1596static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1597{
1598 s32 ret_val;
1599 u16 phy_data;
1600 u32 reg_data;
1601
1602 DEBUGFUNC("e1000_copper_link_ggp_setup");
1603
1604 if (!hw->phy_reset_disable) {
1605
1606 /* Enable CRS on TX for half-duplex operation. */
1607 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1608 &phy_data);
1609 if (ret_val)
1610 return ret_val;
1611
1612 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1613 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1614 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1615
1616 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1617 phy_data);
1618 if (ret_val)
1619 return ret_val;
1620
1621 /* Options:
1622 * MDI/MDI-X = 0 (default)
1623 * 0 - Auto for all speeds
1624 * 1 - MDI mode
1625 * 2 - MDI-X mode
1626 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1627 */
1628 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1629 if (ret_val)
1630 return ret_val;
1631
1632 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1633
1634 switch (hw->mdix) {
1635 case 1:
1636 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1637 break;
1638 case 2:
1639 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1640 break;
1641 case 0:
1642 default:
1643 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1644 break;
1645 }
1646
1647 /* Options:
1648 * disable_polarity_correction = 0 (default)
1649 * Automatic Correction for Reversed Cable Polarity
1650 * 0 - Disabled
1651 * 1 - Enabled
1652 */
1653 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1654 if (hw->disable_polarity_correction == 1)
1655 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1656 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1657
1658 if (ret_val)
1659 return ret_val;
1660
1661 /* SW Reset the PHY so all changes take effect */
1662 ret_val = e1000_phy_reset(hw);
1663 if (ret_val) {
1664 DEBUGOUT("Error Resetting the PHY\n");
1665 return ret_val;
1666 }
1667 } /* phy_reset_disable */
1668
1669 if (hw->mac_type == e1000_80003es2lan) {
1670 /* Bypass RX and TX FIFO's */
1671 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1672 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1673 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1674 if (ret_val)
1675 return ret_val;
1676
1677 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1678 if (ret_val)
1679 return ret_val;
1680
1681 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1682 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1683
1684 if (ret_val)
1685 return ret_val;
1686
1687 reg_data = er32(CTRL_EXT);
1688 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1689 ew32(CTRL_EXT, reg_data);
1690
1691 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1692 &phy_data);
1693 if (ret_val)
1694 return ret_val;
1695
1696 /* Do not init these registers when the HW is in IAMT mode, since the
1697 * firmware will have already initialized them. We only initialize
1698 * them if the HW is not in IAMT mode.
1699 */
1700 if (!e1000_check_mng_mode(hw)) {
1701 /* Enable Electrical Idle on the PHY */
1702 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1703 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1704 phy_data);
1705 if (ret_val)
1706 return ret_val;
1707
1708 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1709 &phy_data);
1710 if (ret_val)
1711 return ret_val;
1712
1713 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1714 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1715 phy_data);
1716
1717 if (ret_val)
1718 return ret_val;
1719 }
1720
1721 /* Workaround: Disable padding in Kumeran interface in the MAC
1722 * and in the PHY to avoid CRC errors.
1723 */
1724 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1725 &phy_data);
1726 if (ret_val)
1727 return ret_val;
1728 phy_data |= GG82563_ICR_DIS_PADDING;
1729 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1730 phy_data);
1731 if (ret_val)
1732 return ret_val;
1733 }
1734
1735 return E1000_SUCCESS;
1736}
1737
1738/********************************************************************
1739* Copper link setup for e1000_phy_m88 series. 1158* Copper link setup for e1000_phy_m88 series.
1740* 1159*
1741* hw - Struct containing variables accessed by shared code 1160* hw - Struct containing variables accessed by shared code
@@ -1861,10 +1280,6 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1861 if (hw->autoneg_advertised == 0) 1280 if (hw->autoneg_advertised == 0)
1862 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1281 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1863 1282
1864 /* IFE phy only supports 10/100 */
1865 if (hw->phy_type == e1000_phy_ife)
1866 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1867
1868 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1283 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1869 ret_val = e1000_phy_setup_autoneg(hw); 1284 ret_val = e1000_phy_setup_autoneg(hw);
1870 if (ret_val) { 1285 if (ret_val) {
@@ -1955,52 +1370,15 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1955 s32 ret_val; 1370 s32 ret_val;
1956 u16 i; 1371 u16 i;
1957 u16 phy_data; 1372 u16 phy_data;
1958 u16 reg_data = 0;
1959 1373
1960 DEBUGFUNC("e1000_setup_copper_link"); 1374 DEBUGFUNC("e1000_setup_copper_link");
1961 1375
1962 switch (hw->mac_type) {
1963 case e1000_80003es2lan:
1964 case e1000_ich8lan:
1965 /* Set the mac to wait the maximum time between each
1966 * iteration and increase the max iterations when
1967 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1968 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1969 if (ret_val)
1970 return ret_val;
1971 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1972 if (ret_val)
1973 return ret_val;
1974 reg_data |= 0x3F;
1975 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1976 if (ret_val)
1977 return ret_val;
1978 default:
1979 break;
1980 }
1981
1982 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1376 /* Check if it is a valid PHY and set PHY mode if necessary. */
1983 ret_val = e1000_copper_link_preconfig(hw); 1377 ret_val = e1000_copper_link_preconfig(hw);
1984 if (ret_val) 1378 if (ret_val)
1985 return ret_val; 1379 return ret_val;
1986 1380
1987 switch (hw->mac_type) { 1381 if (hw->phy_type == e1000_phy_igp) {
1988 case e1000_80003es2lan:
1989 /* Kumeran registers are written-only */
1990 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1991 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1992 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1993 reg_data);
1994 if (ret_val)
1995 return ret_val;
1996 break;
1997 default:
1998 break;
1999 }
2000
2001 if (hw->phy_type == e1000_phy_igp ||
2002 hw->phy_type == e1000_phy_igp_3 ||
2003 hw->phy_type == e1000_phy_igp_2) {
2004 ret_val = e1000_copper_link_igp_setup(hw); 1382 ret_val = e1000_copper_link_igp_setup(hw);
2005 if (ret_val) 1383 if (ret_val)
2006 return ret_val; 1384 return ret_val;
@@ -2008,10 +1386,6 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
2008 ret_val = e1000_copper_link_mgp_setup(hw); 1386 ret_val = e1000_copper_link_mgp_setup(hw);
2009 if (ret_val) 1387 if (ret_val)
2010 return ret_val; 1388 return ret_val;
2011 } else if (hw->phy_type == e1000_phy_gg82563) {
2012 ret_val = e1000_copper_link_ggp_setup(hw);
2013 if (ret_val)
2014 return ret_val;
2015 } 1389 }
2016 1390
2017 if (hw->autoneg) { 1391 if (hw->autoneg) {
@@ -2059,77 +1433,6 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
2059} 1433}
2060 1434
2061/****************************************************************************** 1435/******************************************************************************
2062* Configure the MAC-to-PHY interface for 10/100Mbps
2063*
2064* hw - Struct containing variables accessed by shared code
2065******************************************************************************/
2066static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2067{
2068 s32 ret_val = E1000_SUCCESS;
2069 u32 tipg;
2070 u16 reg_data;
2071
2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2073
2074 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2075 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2076 reg_data);
2077 if (ret_val)
2078 return ret_val;
2079
2080 /* Configure Transmit Inter-Packet Gap */
2081 tipg = er32(TIPG);
2082 tipg &= ~E1000_TIPG_IPGT_MASK;
2083 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2084 ew32(TIPG, tipg);
2085
2086 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2087
2088 if (ret_val)
2089 return ret_val;
2090
2091 if (duplex == HALF_DUPLEX)
2092 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2093 else
2094 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2095
2096 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2097
2098 return ret_val;
2099}
2100
2101static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2102{
2103 s32 ret_val = E1000_SUCCESS;
2104 u16 reg_data;
2105 u32 tipg;
2106
2107 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2108
2109 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2110 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2111 reg_data);
2112 if (ret_val)
2113 return ret_val;
2114
2115 /* Configure Transmit Inter-Packet Gap */
2116 tipg = er32(TIPG);
2117 tipg &= ~E1000_TIPG_IPGT_MASK;
2118 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2119 ew32(TIPG, tipg);
2120
2121 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2122
2123 if (ret_val)
2124 return ret_val;
2125
2126 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2127 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2128
2129 return ret_val;
2130}
2131
2132/******************************************************************************
2133* Configures PHY autoneg and flow control advertisement settings 1436* Configures PHY autoneg and flow control advertisement settings
2134* 1437*
2135* hw - Struct containing variables accessed by shared code 1438* hw - Struct containing variables accessed by shared code
@@ -2147,13 +1450,10 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2147 if (ret_val) 1450 if (ret_val)
2148 return ret_val; 1451 return ret_val;
2149 1452
2150 if (hw->phy_type != e1000_phy_ife) { 1453 /* Read the MII 1000Base-T Control Register (Address 9). */
2151 /* Read the MII 1000Base-T Control Register (Address 9). */ 1454 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2152 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1455 if (ret_val)
2153 if (ret_val) 1456 return ret_val;
2154 return ret_val;
2155 } else
2156 mii_1000t_ctrl_reg=0;
2157 1457
2158 /* Need to parse both autoneg_advertised and fc and set up 1458 /* Need to parse both autoneg_advertised and fc and set up
2159 * the appropriate PHY registers. First we will parse for 1459 * the appropriate PHY registers. First we will parse for
@@ -2204,9 +1504,6 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2204 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1504 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2205 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1505 DEBUGOUT("Advertise 1000mb Full duplex\n");
2206 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1506 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2207 if (hw->phy_type == e1000_phy_ife) {
2208 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2209 }
2210 } 1507 }
2211 1508
2212 /* Check for a software override of the flow control settings, and 1509 /* Check for a software override of the flow control settings, and
@@ -2268,11 +1565,9 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2268 1565
2269 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1566 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2270 1567
2271 if (hw->phy_type != e1000_phy_ife) { 1568 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2272 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1569 if (ret_val)
2273 if (ret_val) 1570 return ret_val;
2274 return ret_val;
2275 }
2276 1571
2277 return E1000_SUCCESS; 1572 return E1000_SUCCESS;
2278} 1573}
@@ -2356,8 +1651,7 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2356 /* Write the configured values back to the Device Control Reg. */ 1651 /* Write the configured values back to the Device Control Reg. */
2357 ew32(CTRL, ctrl); 1652 ew32(CTRL, ctrl);
2358 1653
2359 if ((hw->phy_type == e1000_phy_m88) || 1654 if (hw->phy_type == e1000_phy_m88) {
2360 (hw->phy_type == e1000_phy_gg82563)) {
2361 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1655 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2362 if (ret_val) 1656 if (ret_val)
2363 return ret_val; 1657 return ret_val;
@@ -2375,19 +1669,6 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2375 /* Need to reset the PHY or these changes will be ignored */ 1669 /* Need to reset the PHY or these changes will be ignored */
2376 mii_ctrl_reg |= MII_CR_RESET; 1670 mii_ctrl_reg |= MII_CR_RESET;
2377 1671
2378 /* Disable MDI-X support for 10/100 */
2379 } else if (hw->phy_type == e1000_phy_ife) {
2380 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2381 if (ret_val)
2382 return ret_val;
2383
2384 phy_data &= ~IFE_PMC_AUTO_MDIX;
2385 phy_data &= ~IFE_PMC_FORCE_MDIX;
2386
2387 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2388 if (ret_val)
2389 return ret_val;
2390
2391 } else { 1672 } else {
2392 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1673 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2393 * forced whenever speed or duplex are forced. 1674 * forced whenever speed or duplex are forced.
@@ -2440,8 +1721,7 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2440 msleep(100); 1721 msleep(100);
2441 } 1722 }
2442 if ((i == 0) && 1723 if ((i == 0) &&
2443 ((hw->phy_type == e1000_phy_m88) || 1724 (hw->phy_type == e1000_phy_m88)) {
2444 (hw->phy_type == e1000_phy_gg82563))) {
2445 /* We didn't get link. Reset the DSP and wait again for link. */ 1725 /* We didn't get link. Reset the DSP and wait again for link. */
2446 ret_val = e1000_phy_reset_dsp(hw); 1726 ret_val = e1000_phy_reset_dsp(hw);
2447 if (ret_val) { 1727 if (ret_val) {
@@ -2499,27 +1779,6 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2499 if (ret_val) 1779 if (ret_val)
2500 return ret_val; 1780 return ret_val;
2501 } 1781 }
2502 } else if (hw->phy_type == e1000_phy_gg82563) {
2503 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2504 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2505 * we're not in a forced 10/duplex configuration. */
2506 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2507 if (ret_val)
2508 return ret_val;
2509
2510 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2511 if ((hw->forced_speed_duplex == e1000_10_full) ||
2512 (hw->forced_speed_duplex == e1000_10_half))
2513 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2514 else
2515 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2516
2517 /* Also due to the reset, we need to enable CRS on Tx. */
2518 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2519
2520 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2521 if (ret_val)
2522 return ret_val;
2523 } 1782 }
2524 return E1000_SUCCESS; 1783 return E1000_SUCCESS;
2525} 1784}
@@ -3179,22 +2438,6 @@ s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
3179 } 2438 }
3180 } 2439 }
3181 2440
3182 if ((hw->mac_type == e1000_80003es2lan) &&
3183 (hw->media_type == e1000_media_type_copper)) {
3184 if (*speed == SPEED_1000)
3185 ret_val = e1000_configure_kmrn_for_1000(hw);
3186 else
3187 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3188 if (ret_val)
3189 return ret_val;
3190 }
3191
3192 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3193 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3194 if (ret_val)
3195 return ret_val;
3196 }
3197
3198 return E1000_SUCCESS; 2441 return E1000_SUCCESS;
3199} 2442}
3200 2443
@@ -3373,9 +2616,6 @@ static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3373 2616
3374 DEBUGFUNC("e1000_swfw_sync_acquire"); 2617 DEBUGFUNC("e1000_swfw_sync_acquire");
3375 2618
3376 if (hw->swfwhw_semaphore_present)
3377 return e1000_get_software_flag(hw);
3378
3379 if (!hw->swfw_sync_present) 2619 if (!hw->swfw_sync_present)
3380 return e1000_get_hw_eeprom_semaphore(hw); 2620 return e1000_get_hw_eeprom_semaphore(hw);
3381 2621
@@ -3414,11 +2654,6 @@ static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3414 2654
3415 DEBUGFUNC("e1000_swfw_sync_release"); 2655 DEBUGFUNC("e1000_swfw_sync_release");
3416 2656
3417 if (hw->swfwhw_semaphore_present) {
3418 e1000_release_software_flag(hw);
3419 return;
3420 }
3421
3422 if (!hw->swfw_sync_present) { 2657 if (!hw->swfw_sync_present) {
3423 e1000_put_hw_eeprom_semaphore(hw); 2658 e1000_put_hw_eeprom_semaphore(hw);
3424 return; 2659 return;
@@ -3449,46 +2684,18 @@ s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
3449 2684
3450 DEBUGFUNC("e1000_read_phy_reg"); 2685 DEBUGFUNC("e1000_read_phy_reg");
3451 2686
3452 if ((hw->mac_type == e1000_80003es2lan) && 2687 swfw = E1000_SWFW_PHY0_SM;
3453 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3454 swfw = E1000_SWFW_PHY1_SM;
3455 } else {
3456 swfw = E1000_SWFW_PHY0_SM;
3457 }
3458 if (e1000_swfw_sync_acquire(hw, swfw)) 2688 if (e1000_swfw_sync_acquire(hw, swfw))
3459 return -E1000_ERR_SWFW_SYNC; 2689 return -E1000_ERR_SWFW_SYNC;
3460 2690
3461 if ((hw->phy_type == e1000_phy_igp || 2691 if ((hw->phy_type == e1000_phy_igp) &&
3462 hw->phy_type == e1000_phy_igp_3 || 2692 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3463 hw->phy_type == e1000_phy_igp_2) &&
3464 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3465 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2693 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3466 (u16)reg_addr); 2694 (u16)reg_addr);
3467 if (ret_val) { 2695 if (ret_val) {
3468 e1000_swfw_sync_release(hw, swfw); 2696 e1000_swfw_sync_release(hw, swfw);
3469 return ret_val; 2697 return ret_val;
3470 } 2698 }
3471 } else if (hw->phy_type == e1000_phy_gg82563) {
3472 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3473 (hw->mac_type == e1000_80003es2lan)) {
3474 /* Select Configuration Page */
3475 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3476 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3477 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3478 } else {
3479 /* Use Alternative Page Select register to access
3480 * registers 30 and 31
3481 */
3482 ret_val = e1000_write_phy_reg_ex(hw,
3483 GG82563_PHY_PAGE_SELECT_ALT,
3484 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3485 }
3486
3487 if (ret_val) {
3488 e1000_swfw_sync_release(hw, swfw);
3489 return ret_val;
3490 }
3491 }
3492 } 2699 }
3493 2700
3494 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2701 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
@@ -3584,46 +2791,18 @@ s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
3584 2791
3585 DEBUGFUNC("e1000_write_phy_reg"); 2792 DEBUGFUNC("e1000_write_phy_reg");
3586 2793
3587 if ((hw->mac_type == e1000_80003es2lan) && 2794 swfw = E1000_SWFW_PHY0_SM;
3588 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3589 swfw = E1000_SWFW_PHY1_SM;
3590 } else {
3591 swfw = E1000_SWFW_PHY0_SM;
3592 }
3593 if (e1000_swfw_sync_acquire(hw, swfw)) 2795 if (e1000_swfw_sync_acquire(hw, swfw))
3594 return -E1000_ERR_SWFW_SYNC; 2796 return -E1000_ERR_SWFW_SYNC;
3595 2797
3596 if ((hw->phy_type == e1000_phy_igp || 2798 if ((hw->phy_type == e1000_phy_igp) &&
3597 hw->phy_type == e1000_phy_igp_3 || 2799 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3598 hw->phy_type == e1000_phy_igp_2) &&
3599 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3600 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2800 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3601 (u16)reg_addr); 2801 (u16)reg_addr);
3602 if (ret_val) { 2802 if (ret_val) {
3603 e1000_swfw_sync_release(hw, swfw); 2803 e1000_swfw_sync_release(hw, swfw);
3604 return ret_val; 2804 return ret_val;
3605 } 2805 }
3606 } else if (hw->phy_type == e1000_phy_gg82563) {
3607 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3608 (hw->mac_type == e1000_80003es2lan)) {
3609 /* Select Configuration Page */
3610 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3611 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3612 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3613 } else {
3614 /* Use Alternative Page Select register to access
3615 * registers 30 and 31
3616 */
3617 ret_val = e1000_write_phy_reg_ex(hw,
3618 GG82563_PHY_PAGE_SELECT_ALT,
3619 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3620 }
3621
3622 if (ret_val) {
3623 e1000_swfw_sync_release(hw, swfw);
3624 return ret_val;
3625 }
3626 }
3627 } 2806 }
3628 2807
3629 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2808 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
@@ -3694,60 +2873,6 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3694 return E1000_SUCCESS; 2873 return E1000_SUCCESS;
3695} 2874}
3696 2875
3697static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
3698{
3699 u32 reg_val;
3700 u16 swfw;
3701 DEBUGFUNC("e1000_read_kmrn_reg");
3702
3703 if ((hw->mac_type == e1000_80003es2lan) &&
3704 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3705 swfw = E1000_SWFW_PHY1_SM;
3706 } else {
3707 swfw = E1000_SWFW_PHY0_SM;
3708 }
3709 if (e1000_swfw_sync_acquire(hw, swfw))
3710 return -E1000_ERR_SWFW_SYNC;
3711
3712 /* Write register address */
3713 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3714 E1000_KUMCTRLSTA_OFFSET) |
3715 E1000_KUMCTRLSTA_REN;
3716 ew32(KUMCTRLSTA, reg_val);
3717 udelay(2);
3718
3719 /* Read the data returned */
3720 reg_val = er32(KUMCTRLSTA);
3721 *data = (u16)reg_val;
3722
3723 e1000_swfw_sync_release(hw, swfw);
3724 return E1000_SUCCESS;
3725}
3726
3727static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
3728{
3729 u32 reg_val;
3730 u16 swfw;
3731 DEBUGFUNC("e1000_write_kmrn_reg");
3732
3733 if ((hw->mac_type == e1000_80003es2lan) &&
3734 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3735 swfw = E1000_SWFW_PHY1_SM;
3736 } else {
3737 swfw = E1000_SWFW_PHY0_SM;
3738 }
3739 if (e1000_swfw_sync_acquire(hw, swfw))
3740 return -E1000_ERR_SWFW_SYNC;
3741
3742 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3743 E1000_KUMCTRLSTA_OFFSET) | data;
3744 ew32(KUMCTRLSTA, reg_val);
3745 udelay(2);
3746
3747 e1000_swfw_sync_release(hw, swfw);
3748 return E1000_SUCCESS;
3749}
3750
3751/****************************************************************************** 2876/******************************************************************************
3752* Returns the PHY to the power-on reset state 2877* Returns the PHY to the power-on reset state
3753* 2878*
@@ -3762,46 +2887,28 @@ s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3762 2887
3763 DEBUGFUNC("e1000_phy_hw_reset"); 2888 DEBUGFUNC("e1000_phy_hw_reset");
3764 2889
3765 /* In the case of the phy reset being blocked, it's not an error, we
3766 * simply return success without performing the reset. */
3767 ret_val = e1000_check_phy_reset_block(hw);
3768 if (ret_val)
3769 return E1000_SUCCESS;
3770
3771 DEBUGOUT("Resetting Phy...\n"); 2890 DEBUGOUT("Resetting Phy...\n");
3772 2891
3773 if (hw->mac_type > e1000_82543) { 2892 if (hw->mac_type > e1000_82543) {
3774 if ((hw->mac_type == e1000_80003es2lan) && 2893 swfw = E1000_SWFW_PHY0_SM;
3775 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3776 swfw = E1000_SWFW_PHY1_SM;
3777 } else {
3778 swfw = E1000_SWFW_PHY0_SM;
3779 }
3780 if (e1000_swfw_sync_acquire(hw, swfw)) { 2894 if (e1000_swfw_sync_acquire(hw, swfw)) {
3781 DEBUGOUT("Unable to acquire swfw sync\n"); 2895 DEBUGOUT("Unable to acquire swfw sync\n");
3782 return -E1000_ERR_SWFW_SYNC; 2896 return -E1000_ERR_SWFW_SYNC;
3783 } 2897 }
3784 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2898 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3785 * bit. Then, take it out of reset. 2899 * bit. Then, take it out of reset.
3786 * For pre-e1000_82571 hardware, we delay for 10ms between the assert 2900 * For e1000 hardware, we delay for 10ms between the assert
3787 * and deassert. For e1000_82571 hardware and later, we instead delay 2901 * and deassert.
3788 * for 50us between and 10ms after the deassertion.
3789 */ 2902 */
3790 ctrl = er32(CTRL); 2903 ctrl = er32(CTRL);
3791 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2904 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3792 E1000_WRITE_FLUSH(); 2905 E1000_WRITE_FLUSH();
3793 2906
3794 if (hw->mac_type < e1000_82571) 2907 msleep(10);
3795 msleep(10);
3796 else
3797 udelay(100);
3798 2908
3799 ew32(CTRL, ctrl); 2909 ew32(CTRL, ctrl);
3800 E1000_WRITE_FLUSH(); 2910 E1000_WRITE_FLUSH();
3801 2911
3802 if (hw->mac_type >= e1000_82571)
3803 mdelay(10);
3804
3805 e1000_swfw_sync_release(hw, swfw); 2912 e1000_swfw_sync_release(hw, swfw);
3806 } else { 2913 } else {
3807 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2914 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3831,10 +2938,6 @@ s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3831 ret_val = e1000_get_phy_cfg_done(hw); 2938 ret_val = e1000_get_phy_cfg_done(hw);
3832 if (ret_val != E1000_SUCCESS) 2939 if (ret_val != E1000_SUCCESS)
3833 return ret_val; 2940 return ret_val;
3834 e1000_release_software_semaphore(hw);
3835
3836 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3837 ret_val = e1000_init_lcd_from_nvm(hw);
3838 2941
3839 return ret_val; 2942 return ret_val;
3840} 2943}
@@ -3853,17 +2956,8 @@ s32 e1000_phy_reset(struct e1000_hw *hw)
3853 2956
3854 DEBUGFUNC("e1000_phy_reset"); 2957 DEBUGFUNC("e1000_phy_reset");
3855 2958
3856 /* In the case of the phy reset being blocked, it's not an error, we
3857 * simply return success without performing the reset. */
3858 ret_val = e1000_check_phy_reset_block(hw);
3859 if (ret_val)
3860 return E1000_SUCCESS;
3861
3862 switch (hw->phy_type) { 2959 switch (hw->phy_type) {
3863 case e1000_phy_igp: 2960 case e1000_phy_igp:
3864 case e1000_phy_igp_2:
3865 case e1000_phy_igp_3:
3866 case e1000_phy_ife:
3867 ret_val = e1000_phy_hw_reset(hw); 2961 ret_val = e1000_phy_hw_reset(hw);
3868 if (ret_val) 2962 if (ret_val)
3869 return ret_val; 2963 return ret_val;
@@ -3882,121 +2976,13 @@ s32 e1000_phy_reset(struct e1000_hw *hw)
3882 break; 2976 break;
3883 } 2977 }
3884 2978
3885 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 2979 if (hw->phy_type == e1000_phy_igp)
3886 e1000_phy_init_script(hw); 2980 e1000_phy_init_script(hw);
3887 2981
3888 return E1000_SUCCESS; 2982 return E1000_SUCCESS;
3889} 2983}
3890 2984
3891/****************************************************************************** 2985/******************************************************************************
3892* Work-around for 82566 power-down: on D3 entry-
3893* 1) disable gigabit link
3894* 2) write VR power-down enable
3895* 3) read it back
3896* if successful continue, else issue LCD reset and repeat
3897*
3898* hw - struct containing variables accessed by shared code
3899******************************************************************************/
3900void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3901{
3902 s32 reg;
3903 u16 phy_data;
3904 s32 retry = 0;
3905
3906 DEBUGFUNC("e1000_phy_powerdown_workaround");
3907
3908 if (hw->phy_type != e1000_phy_igp_3)
3909 return;
3910
3911 do {
3912 /* Disable link */
3913 reg = er32(PHY_CTRL);
3914 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3915 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3916
3917 /* Write VR power-down enable - bits 9:8 should be 10b */
3918 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3919 phy_data |= (1 << 9);
3920 phy_data &= ~(1 << 8);
3921 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3922
3923 /* Read it back and test */
3924 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3925 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3926 break;
3927
3928 /* Issue PHY reset and repeat at most one more time */
3929 reg = er32(CTRL);
3930 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3931 retry++;
3932 } while (retry);
3933
3934 return;
3935
3936}
3937
3938/******************************************************************************
3939* Work-around for 82566 Kumeran PCS lock loss:
3940* On link status change (i.e. PCI reset, speed change) and link is up and
3941* speed is gigabit-
3942* 0) if workaround is optionally disabled do nothing
3943* 1) wait 1ms for Kumeran link to come up
3944* 2) check Kumeran Diagnostic register PCS lock loss bit
3945* 3) if not set the link is locked (all is good), otherwise...
3946* 4) reset the PHY
3947* 5) repeat up to 10 times
3948* Note: this is only called for IGP3 copper when speed is 1gb.
3949*
3950* hw - struct containing variables accessed by shared code
3951******************************************************************************/
3952static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3953{
3954 s32 ret_val;
3955 s32 reg;
3956 s32 cnt;
3957 u16 phy_data;
3958
3959 if (hw->kmrn_lock_loss_workaround_disabled)
3960 return E1000_SUCCESS;
3961
3962 /* Make sure link is up before proceeding. If not just return.
3963 * Attempting this while link is negotiating fouled up link
3964 * stability */
3965 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3966 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3967
3968 if (phy_data & MII_SR_LINK_STATUS) {
3969 for (cnt = 0; cnt < 10; cnt++) {
3970 /* read once to clear */
3971 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3972 if (ret_val)
3973 return ret_val;
3974 /* and again to get new status */
3975 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3976 if (ret_val)
3977 return ret_val;
3978
3979 /* check for PCS lock */
3980 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3981 return E1000_SUCCESS;
3982
3983 /* Issue PHY reset */
3984 e1000_phy_hw_reset(hw);
3985 mdelay(5);
3986 }
3987 /* Disable GigE link negotiation */
3988 reg = er32(PHY_CTRL);
3989 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3990 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3991
3992 /* unable to acquire PCS lock */
3993 return E1000_ERR_PHY;
3994 }
3995
3996 return E1000_SUCCESS;
3997}
3998
3999/******************************************************************************
4000* Probes the expected PHY address for known PHY IDs 2986* Probes the expected PHY address for known PHY IDs
4001* 2987*
4002* hw - Struct containing variables accessed by shared code 2988* hw - Struct containing variables accessed by shared code
@@ -4012,25 +2998,6 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
4012 if (hw->phy_id != 0) 2998 if (hw->phy_id != 0)
4013 return E1000_SUCCESS; 2999 return E1000_SUCCESS;
4014 3000
4015 /* The 82571 firmware may still be configuring the PHY. In this
4016 * case, we cannot access the PHY until the configuration is done. So
4017 * we explicitly set the PHY values. */
4018 if (hw->mac_type == e1000_82571 ||
4019 hw->mac_type == e1000_82572) {
4020 hw->phy_id = IGP01E1000_I_PHY_ID;
4021 hw->phy_type = e1000_phy_igp_2;
4022 return E1000_SUCCESS;
4023 }
4024
4025 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4026 * around that forces PHY page 0 to be set or the reads fail. The rest of
4027 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4028 * So for ESB-2 we need to have this set so our reads won't fail. If the
4029 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4030 * this out as well. */
4031 if (hw->mac_type == e1000_80003es2lan)
4032 hw->phy_type = e1000_phy_gg82563;
4033
4034 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3001 /* Read the PHY ID Registers to identify which PHY is onboard. */
4035 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3002 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4036 if (ret_val) 3003 if (ret_val)
@@ -4065,18 +3032,6 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
4065 case e1000_82547_rev_2: 3032 case e1000_82547_rev_2:
4066 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true; 3033 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
4067 break; 3034 break;
4068 case e1000_82573:
4069 if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
4070 break;
4071 case e1000_80003es2lan:
4072 if (hw->phy_id == GG82563_E_PHY_ID) match = true;
4073 break;
4074 case e1000_ich8lan:
4075 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
4076 if (hw->phy_id == IFE_E_PHY_ID) match = true;
4077 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
4078 if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
4079 break;
4080 default: 3035 default:
4081 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3036 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4082 return -E1000_ERR_CONFIG; 3037 return -E1000_ERR_CONFIG;
@@ -4102,10 +3057,8 @@ static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
4102 DEBUGFUNC("e1000_phy_reset_dsp"); 3057 DEBUGFUNC("e1000_phy_reset_dsp");
4103 3058
4104 do { 3059 do {
4105 if (hw->phy_type != e1000_phy_gg82563) { 3060 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4106 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3061 if (ret_val) break;
4107 if (ret_val) break;
4108 }
4109 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3062 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4110 if (ret_val) break; 3063 if (ret_val) break;
4111 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3064 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
@@ -4192,54 +3145,6 @@ static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
4192 return E1000_SUCCESS; 3145 return E1000_SUCCESS;
4193} 3146}
4194 3147
4195/******************************************************************************
4196* Get PHY information from various PHY registers for ife PHY only.
4197*
4198* hw - Struct containing variables accessed by shared code
4199* phy_info - PHY information structure
4200******************************************************************************/
4201static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
4202 struct e1000_phy_info *phy_info)
4203{
4204 s32 ret_val;
4205 u16 phy_data;
4206 e1000_rev_polarity polarity;
4207
4208 DEBUGFUNC("e1000_phy_ife_get_info");
4209
4210 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4211 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4212
4213 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4214 if (ret_val)
4215 return ret_val;
4216 phy_info->polarity_correction =
4217 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4218 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4219 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4220
4221 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4222 ret_val = e1000_check_polarity(hw, &polarity);
4223 if (ret_val)
4224 return ret_val;
4225 } else {
4226 /* Polarity is forced. */
4227 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4228 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4229 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4230 }
4231 phy_info->cable_polarity = polarity;
4232
4233 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4234 if (ret_val)
4235 return ret_val;
4236
4237 phy_info->mdix_mode = (e1000_auto_x_mode)
4238 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4239 IFE_PMC_MDIX_MODE_SHIFT);
4240
4241 return E1000_SUCCESS;
4242}
4243 3148
4244/****************************************************************************** 3149/******************************************************************************
4245* Get PHY information from various PHY registers fot m88 PHY only. 3150* Get PHY information from various PHY registers fot m88 PHY only.
@@ -4291,17 +3196,8 @@ static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
4291 /* Cable Length Estimation and Local/Remote Receiver Information 3196 /* Cable Length Estimation and Local/Remote Receiver Information
4292 * are only valid at 1000 Mbps. 3197 * are only valid at 1000 Mbps.
4293 */ 3198 */
4294 if (hw->phy_type != e1000_phy_gg82563) { 3199 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4295 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 3200 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4296 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4297 } else {
4298 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4299 &phy_data);
4300 if (ret_val)
4301 return ret_val;
4302
4303 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4304 }
4305 3201
4306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3202 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4307 if (ret_val) 3203 if (ret_val)
@@ -4359,12 +3255,8 @@ s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
4359 return -E1000_ERR_CONFIG; 3255 return -E1000_ERR_CONFIG;
4360 } 3256 }
4361 3257
4362 if (hw->phy_type == e1000_phy_igp || 3258 if (hw->phy_type == e1000_phy_igp)
4363 hw->phy_type == e1000_phy_igp_3 ||
4364 hw->phy_type == e1000_phy_igp_2)
4365 return e1000_phy_igp_get_info(hw, phy_info); 3259 return e1000_phy_igp_get_info(hw, phy_info);
4366 else if (hw->phy_type == e1000_phy_ife)
4367 return e1000_phy_ife_get_info(hw, phy_info);
4368 else 3260 else
4369 return e1000_phy_m88_get_info(hw, phy_info); 3261 return e1000_phy_m88_get_info(hw, phy_info);
4370} 3262}
@@ -4384,8 +3276,7 @@ s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
4384 3276
4385/****************************************************************************** 3277/******************************************************************************
4386 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3278 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4387 * is configured. Additionally, if this is ICH8, the flash controller GbE 3279 * is configured.
4388 * registers must be mapped, or this will crash.
4389 * 3280 *
4390 * hw - Struct containing variables accessed by shared code 3281 * hw - Struct containing variables accessed by shared code
4391 *****************************************************************************/ 3282 *****************************************************************************/
@@ -4459,89 +3350,6 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4459 eeprom->use_eerd = false; 3350 eeprom->use_eerd = false;
4460 eeprom->use_eewr = false; 3351 eeprom->use_eewr = false;
4461 break; 3352 break;
4462 case e1000_82571:
4463 case e1000_82572:
4464 eeprom->type = e1000_eeprom_spi;
4465 eeprom->opcode_bits = 8;
4466 eeprom->delay_usec = 1;
4467 if (eecd & E1000_EECD_ADDR_BITS) {
4468 eeprom->page_size = 32;
4469 eeprom->address_bits = 16;
4470 } else {
4471 eeprom->page_size = 8;
4472 eeprom->address_bits = 8;
4473 }
4474 eeprom->use_eerd = false;
4475 eeprom->use_eewr = false;
4476 break;
4477 case e1000_82573:
4478 eeprom->type = e1000_eeprom_spi;
4479 eeprom->opcode_bits = 8;
4480 eeprom->delay_usec = 1;
4481 if (eecd & E1000_EECD_ADDR_BITS) {
4482 eeprom->page_size = 32;
4483 eeprom->address_bits = 16;
4484 } else {
4485 eeprom->page_size = 8;
4486 eeprom->address_bits = 8;
4487 }
4488 eeprom->use_eerd = true;
4489 eeprom->use_eewr = true;
4490 if (!e1000_is_onboard_nvm_eeprom(hw)) {
4491 eeprom->type = e1000_eeprom_flash;
4492 eeprom->word_size = 2048;
4493
4494 /* Ensure that the Autonomous FLASH update bit is cleared due to
4495 * Flash update issue on parts which use a FLASH for NVM. */
4496 eecd &= ~E1000_EECD_AUPDEN;
4497 ew32(EECD, eecd);
4498 }
4499 break;
4500 case e1000_80003es2lan:
4501 eeprom->type = e1000_eeprom_spi;
4502 eeprom->opcode_bits = 8;
4503 eeprom->delay_usec = 1;
4504 if (eecd & E1000_EECD_ADDR_BITS) {
4505 eeprom->page_size = 32;
4506 eeprom->address_bits = 16;
4507 } else {
4508 eeprom->page_size = 8;
4509 eeprom->address_bits = 8;
4510 }
4511 eeprom->use_eerd = true;
4512 eeprom->use_eewr = false;
4513 break;
4514 case e1000_ich8lan:
4515 {
4516 s32 i = 0;
4517 u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4518
4519 eeprom->type = e1000_eeprom_ich8;
4520 eeprom->use_eerd = false;
4521 eeprom->use_eewr = false;
4522 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4523
4524 /* Zero the shadow RAM structure. But don't load it from NVM
4525 * so as to save time for driver init */
4526 if (hw->eeprom_shadow_ram != NULL) {
4527 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4528 hw->eeprom_shadow_ram[i].modified = false;
4529 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4530 }
4531 }
4532
4533 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4534 ICH_FLASH_SECTOR_SIZE;
4535
4536 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4537 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4538
4539 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4540
4541 hw->flash_bank_size /= 2 * sizeof(u16);
4542
4543 break;
4544 }
4545 default: 3353 default:
4546 break; 3354 break;
4547 } 3355 }
@@ -4550,22 +3358,17 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4550 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 3358 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4551 * 32KB (incremented by powers of 2). 3359 * 32KB (incremented by powers of 2).
4552 */ 3360 */
4553 if (hw->mac_type <= e1000_82547_rev_2) { 3361 /* Set to default value for initial eeprom read. */
4554 /* Set to default value for initial eeprom read. */ 3362 eeprom->word_size = 64;
4555 eeprom->word_size = 64; 3363 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4556 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 3364 if (ret_val)
4557 if (ret_val) 3365 return ret_val;
4558 return ret_val; 3366 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4559 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3367 /* 256B eeprom size was not supported in earlier hardware, so we
4560 /* 256B eeprom size was not supported in earlier hardware, so we 3368 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4561 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 3369 * is never the result used in the shifting logic below. */
4562 * is never the result used in the shifting logic below. */ 3370 if (eeprom_size)
4563 if (eeprom_size) 3371 eeprom_size++;
4564 eeprom_size++;
4565 } else {
4566 eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4567 E1000_EECD_SIZE_EX_SHIFT);
4568 }
4569 3372
4570 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 3373 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4571 } 3374 }
@@ -4716,25 +3519,23 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
4716 return -E1000_ERR_SWFW_SYNC; 3519 return -E1000_ERR_SWFW_SYNC;
4717 eecd = er32(EECD); 3520 eecd = er32(EECD);
4718 3521
4719 if (hw->mac_type != e1000_82573) { 3522 /* Request EEPROM Access */
4720 /* Request EEPROM Access */ 3523 if (hw->mac_type > e1000_82544) {
4721 if (hw->mac_type > e1000_82544) { 3524 eecd |= E1000_EECD_REQ;
4722 eecd |= E1000_EECD_REQ; 3525 ew32(EECD, eecd);
4723 ew32(EECD, eecd); 3526 eecd = er32(EECD);
3527 while ((!(eecd & E1000_EECD_GNT)) &&
3528 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3529 i++;
3530 udelay(5);
4724 eecd = er32(EECD); 3531 eecd = er32(EECD);
4725 while ((!(eecd & E1000_EECD_GNT)) && 3532 }
4726 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3533 if (!(eecd & E1000_EECD_GNT)) {
4727 i++; 3534 eecd &= ~E1000_EECD_REQ;
4728 udelay(5); 3535 ew32(EECD, eecd);
4729 eecd = er32(EECD); 3536 DEBUGOUT("Could not acquire EEPROM grant\n");
4730 } 3537 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4731 if (!(eecd & E1000_EECD_GNT)) { 3538 return -E1000_ERR_EEPROM;
4732 eecd &= ~E1000_EECD_REQ;
4733 ew32(EECD, eecd);
4734 DEBUGOUT("Could not acquire EEPROM grant\n");
4735 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4736 return -E1000_ERR_EEPROM;
4737 }
4738 } 3539 }
4739 } 3540 }
4740 3541
@@ -4939,7 +3740,7 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16
4939 * directly. In this case, we need to acquire the EEPROM so that 3740 * directly. In this case, we need to acquire the EEPROM so that
4940 * FW or other port software does not interrupt. 3741 * FW or other port software does not interrupt.
4941 */ 3742 */
4942 if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) { 3743 if (!hw->eeprom.use_eerd) {
4943 /* Prepare the EEPROM for bit-bang reading */ 3744 /* Prepare the EEPROM for bit-bang reading */
4944 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3745 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4945 return -E1000_ERR_EEPROM; 3746 return -E1000_ERR_EEPROM;
@@ -4949,10 +3750,6 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16
4949 if (eeprom->use_eerd) 3750 if (eeprom->use_eerd)
4950 return e1000_read_eeprom_eerd(hw, offset, words, data); 3751 return e1000_read_eeprom_eerd(hw, offset, words, data);
4951 3752
4952 /* ICH EEPROM access is done via the ICH flash controller */
4953 if (eeprom->type == e1000_eeprom_ich8)
4954 return e1000_read_eeprom_ich8(hw, offset, words, data);
4955
4956 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 3753 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
4957 * acquired the EEPROM at this point, so any returns should relase it */ 3754 * acquired the EEPROM at this point, so any returns should relase it */
4958 if (eeprom->type == e1000_eeprom_spi) { 3755 if (eeprom->type == e1000_eeprom_spi) {
@@ -5103,34 +3900,6 @@ static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5103 return done; 3900 return done;
5104} 3901}
5105 3902
5106/***************************************************************************
5107* Description: Determines if the onboard NVM is FLASH or EEPROM.
5108*
5109* hw - Struct containing variables accessed by shared code
5110****************************************************************************/
5111static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5112{
5113 u32 eecd = 0;
5114
5115 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5116
5117 if (hw->mac_type == e1000_ich8lan)
5118 return false;
5119
5120 if (hw->mac_type == e1000_82573) {
5121 eecd = er32(EECD);
5122
5123 /* Isolate bits 15 & 16 */
5124 eecd = ((eecd >> 15) & 0x03);
5125
5126 /* If both bits are set, device is Flash type */
5127 if (eecd == 0x03) {
5128 return false;
5129 }
5130 }
5131 return true;
5132}
5133
5134/****************************************************************************** 3903/******************************************************************************
5135 * Verifies that the EEPROM has a valid checksum 3904 * Verifies that the EEPROM has a valid checksum
5136 * 3905 *
@@ -5147,38 +3916,6 @@ s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5147 3916
5148 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3917 DEBUGFUNC("e1000_validate_eeprom_checksum");
5149 3918
5150 if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
5151 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5152 * 10h-12h. Checksum may need to be fixed. */
5153 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5154 if ((eeprom_data & 0x10) == 0) {
5155 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5156 * has already been fixed. If the checksum is still wrong and this
5157 * bit is a 1, we need to return bad checksum. Otherwise, we need
5158 * to set this bit to a 1 and update the checksum. */
5159 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5160 if ((eeprom_data & 0x8000) == 0) {
5161 eeprom_data |= 0x8000;
5162 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5163 e1000_update_eeprom_checksum(hw);
5164 }
5165 }
5166 }
5167
5168 if (hw->mac_type == e1000_ich8lan) {
5169 /* Drivers must allocate the shadow ram structure for the
5170 * EEPROM checksum to be updated. Otherwise, this bit as well
5171 * as the checksum must both be set correctly for this
5172 * validation to pass.
5173 */
5174 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5175 if ((eeprom_data & 0x40) == 0) {
5176 eeprom_data |= 0x40;
5177 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5178 e1000_update_eeprom_checksum(hw);
5179 }
5180 }
5181
5182 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3919 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5183 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3920 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5184 DEBUGOUT("EEPROM Read Error\n"); 3921 DEBUGOUT("EEPROM Read Error\n");
@@ -5205,7 +3942,6 @@ s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5205 *****************************************************************************/ 3942 *****************************************************************************/
5206s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 3943s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5207{ 3944{
5208 u32 ctrl_ext;
5209 u16 checksum = 0; 3945 u16 checksum = 0;
5210 u16 i, eeprom_data; 3946 u16 i, eeprom_data;
5211 3947
@@ -5222,16 +3958,6 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5222 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 3958 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5223 DEBUGOUT("EEPROM Write Error\n"); 3959 DEBUGOUT("EEPROM Write Error\n");
5224 return -E1000_ERR_EEPROM; 3960 return -E1000_ERR_EEPROM;
5225 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5226 e1000_commit_shadow_ram(hw);
5227 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5228 e1000_commit_shadow_ram(hw);
5229 /* Reload the EEPROM, or else modifications will not appear
5230 * until after next adapter reset. */
5231 ctrl_ext = er32(CTRL_EXT);
5232 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5233 ew32(CTRL_EXT, ctrl_ext);
5234 msleep(10);
5235 } 3961 }
5236 return E1000_SUCCESS; 3962 return E1000_SUCCESS;
5237} 3963}
@@ -5277,13 +4003,9 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16
5277 return -E1000_ERR_EEPROM; 4003 return -E1000_ERR_EEPROM;
5278 } 4004 }
5279 4005
5280 /* 82573 writes only through eewr */
5281 if (eeprom->use_eewr) 4006 if (eeprom->use_eewr)
5282 return e1000_write_eeprom_eewr(hw, offset, words, data); 4007 return e1000_write_eeprom_eewr(hw, offset, words, data);
5283 4008
5284 if (eeprom->type == e1000_eeprom_ich8)
5285 return e1000_write_eeprom_ich8(hw, offset, words, data);
5286
5287 /* Prepare the EEPROM for writing */ 4009 /* Prepare the EEPROM for writing */
5288 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4010 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5289 return -E1000_ERR_EEPROM; 4011 return -E1000_ERR_EEPROM;
@@ -5448,173 +4170,6 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
5448} 4170}
5449 4171
5450/****************************************************************************** 4172/******************************************************************************
5451 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5452 * in the eeprom cache and the non modified values in the currently active bank
5453 * to the new bank.
5454 *
5455 * hw - Struct containing variables accessed by shared code
5456 * offset - offset of word in the EEPROM to read
5457 * data - word read from the EEPROM
5458 * words - number of words to read
5459 *****************************************************************************/
5460static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
5461{
5462 u32 attempts = 100000;
5463 u32 eecd = 0;
5464 u32 flop = 0;
5465 u32 i = 0;
5466 s32 error = E1000_SUCCESS;
5467 u32 old_bank_offset = 0;
5468 u32 new_bank_offset = 0;
5469 u8 low_byte = 0;
5470 u8 high_byte = 0;
5471 bool sector_write_failed = false;
5472
5473 if (hw->mac_type == e1000_82573) {
5474 /* The flop register will be used to determine if flash type is STM */
5475 flop = er32(FLOP);
5476 for (i=0; i < attempts; i++) {
5477 eecd = er32(EECD);
5478 if ((eecd & E1000_EECD_FLUPD) == 0) {
5479 break;
5480 }
5481 udelay(5);
5482 }
5483
5484 if (i == attempts) {
5485 return -E1000_ERR_EEPROM;
5486 }
5487
5488 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5489 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5490 ew32(HICR, E1000_HICR_FW_RESET);
5491 }
5492
5493 /* Perform the flash update */
5494 ew32(EECD, eecd | E1000_EECD_FLUPD);
5495
5496 for (i=0; i < attempts; i++) {
5497 eecd = er32(EECD);
5498 if ((eecd & E1000_EECD_FLUPD) == 0) {
5499 break;
5500 }
5501 udelay(5);
5502 }
5503
5504 if (i == attempts) {
5505 return -E1000_ERR_EEPROM;
5506 }
5507 }
5508
5509 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5510 /* We're writing to the opposite bank so if we're on bank 1,
5511 * write to bank 0 etc. We also need to erase the segment that
5512 * is going to be written */
5513 if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
5514 new_bank_offset = hw->flash_bank_size * 2;
5515 old_bank_offset = 0;
5516 e1000_erase_ich8_4k_segment(hw, 1);
5517 } else {
5518 old_bank_offset = hw->flash_bank_size * 2;
5519 new_bank_offset = 0;
5520 e1000_erase_ich8_4k_segment(hw, 0);
5521 }
5522
5523 sector_write_failed = false;
5524 /* Loop for every byte in the shadow RAM,
5525 * which is in units of words. */
5526 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5527 /* Determine whether to write the value stored
5528 * in the other NVM bank or a modified value stored
5529 * in the shadow RAM */
5530 if (hw->eeprom_shadow_ram[i].modified) {
5531 low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
5532 udelay(100);
5533 error = e1000_verify_write_ich8_byte(hw,
5534 (i << 1) + new_bank_offset, low_byte);
5535
5536 if (error != E1000_SUCCESS)
5537 sector_write_failed = true;
5538 else {
5539 high_byte =
5540 (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5541 udelay(100);
5542 }
5543 } else {
5544 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5545 &low_byte);
5546 udelay(100);
5547 error = e1000_verify_write_ich8_byte(hw,
5548 (i << 1) + new_bank_offset, low_byte);
5549
5550 if (error != E1000_SUCCESS)
5551 sector_write_failed = true;
5552 else {
5553 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5554 &high_byte);
5555 udelay(100);
5556 }
5557 }
5558
5559 /* If the write of the low byte was successful, go ahead and
5560 * write the high byte while checking to make sure that if it
5561 * is the signature byte, then it is handled properly */
5562 if (!sector_write_failed) {
5563 /* If the word is 0x13, then make sure the signature bits
5564 * (15:14) are 11b until the commit has completed.
5565 * This will allow us to write 10b which indicates the
5566 * signature is valid. We want to do this after the write
5567 * has completed so that we don't mark the segment valid
5568 * while the write is still in progress */
5569 if (i == E1000_ICH_NVM_SIG_WORD)
5570 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5571
5572 error = e1000_verify_write_ich8_byte(hw,
5573 (i << 1) + new_bank_offset + 1, high_byte);
5574 if (error != E1000_SUCCESS)
5575 sector_write_failed = true;
5576
5577 } else {
5578 /* If the write failed then break from the loop and
5579 * return an error */
5580 break;
5581 }
5582 }
5583
5584 /* Don't bother writing the segment valid bits if sector
5585 * programming failed. */
5586 if (!sector_write_failed) {
5587 /* Finally validate the new segment by setting bit 15:14
5588 * to 10b in word 0x13 , this can be done without an
5589 * erase as well since these bits are 11 to start with
5590 * and we need to change bit 14 to 0b */
5591 e1000_read_ich8_byte(hw,
5592 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5593 &high_byte);
5594 high_byte &= 0xBF;
5595 error = e1000_verify_write_ich8_byte(hw,
5596 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5597 /* And invalidate the previously valid segment by setting
5598 * its signature word (0x13) high_byte to 0b. This can be
5599 * done without an erase because flash erase sets all bits
5600 * to 1's. We can write 1's to 0's without an erase */
5601 if (error == E1000_SUCCESS) {
5602 error = e1000_verify_write_ich8_byte(hw,
5603 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5604 }
5605
5606 /* Clear the now not used entry in the cache */
5607 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5608 hw->eeprom_shadow_ram[i].modified = false;
5609 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5610 }
5611 }
5612 }
5613
5614 return error;
5615}
5616
5617/******************************************************************************
5618 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4173 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5619 * second function of dual function devices 4174 * second function of dual function devices
5620 * 4175 *
@@ -5642,8 +4197,6 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw)
5642 break; 4197 break;
5643 case e1000_82546: 4198 case e1000_82546:
5644 case e1000_82546_rev_3: 4199 case e1000_82546_rev_3:
5645 case e1000_82571:
5646 case e1000_80003es2lan:
5647 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4200 if (er32(STATUS) & E1000_STATUS_FUNC_1)
5648 hw->perm_mac_addr[5] ^= 0x01; 4201 hw->perm_mac_addr[5] ^= 0x01;
5649 break; 4202 break;
@@ -5677,14 +4230,6 @@ static void e1000_init_rx_addrs(struct e1000_hw *hw)
5677 4230
5678 rar_num = E1000_RAR_ENTRIES; 4231 rar_num = E1000_RAR_ENTRIES;
5679 4232
5680 /* Reserve a spot for the Locally Administered Address to work around
5681 * an 82571 issue in which a reset on one port will reload the MAC on
5682 * the other port. */
5683 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
5684 rar_num -= 1;
5685 if (hw->mac_type == e1000_ich8lan)
5686 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5687
5688 /* Zero out the other 15 receive addresses. */ 4233 /* Zero out the other 15 receive addresses. */
5689 DEBUGOUT("Clearing RAR[1-15]\n"); 4234 DEBUGOUT("Clearing RAR[1-15]\n");
5690 for (i = 1; i < rar_num; i++) { 4235 for (i = 1; i < rar_num; i++) {
@@ -5714,47 +4259,24 @@ u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
5714 * LSB MSB 4259 * LSB MSB
5715 */ 4260 */
5716 case 0: 4261 case 0:
5717 if (hw->mac_type == e1000_ich8lan) { 4262 /* [47:36] i.e. 0x563 for above example address */
5718 /* [47:38] i.e. 0x158 for above example address */ 4263 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5719 hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2));
5720 } else {
5721 /* [47:36] i.e. 0x563 for above example address */
5722 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5723 }
5724 break; 4264 break;
5725 case 1: 4265 case 1:
5726 if (hw->mac_type == e1000_ich8lan) { 4266 /* [46:35] i.e. 0xAC6 for above example address */
5727 /* [46:37] i.e. 0x2B1 for above example address */ 4267 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
5728 hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3));
5729 } else {
5730 /* [46:35] i.e. 0xAC6 for above example address */
5731 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
5732 }
5733 break; 4268 break;
5734 case 2: 4269 case 2:
5735 if (hw->mac_type == e1000_ich8lan) { 4270 /* [45:34] i.e. 0x5D8 for above example address */
5736 /*[45:36] i.e. 0x163 for above example address */ 4271 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5737 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5738 } else {
5739 /* [45:34] i.e. 0x5D8 for above example address */
5740 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5741 }
5742 break; 4272 break;
5743 case 3: 4273 case 3:
5744 if (hw->mac_type == e1000_ich8lan) { 4274 /* [43:32] i.e. 0x634 for above example address */
5745 /* [43:34] i.e. 0x18D for above example address */ 4275 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
5746 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5747 } else {
5748 /* [43:32] i.e. 0x634 for above example address */
5749 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
5750 }
5751 break; 4276 break;
5752 } 4277 }
5753 4278
5754 hash_value &= 0xFFF; 4279 hash_value &= 0xFFF;
5755 if (hw->mac_type == e1000_ich8lan)
5756 hash_value &= 0x3FF;
5757
5758 return hash_value; 4280 return hash_value;
5759} 4281}
5760 4282
@@ -5795,11 +4317,6 @@ void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
5795 * on our merry way. 4317 * on our merry way.
5796 */ 4318 */
5797 switch (hw->mac_type) { 4319 switch (hw->mac_type) {
5798 case e1000_82571:
5799 case e1000_82572:
5800 case e1000_80003es2lan:
5801 if (hw->leave_av_bit_off)
5802 break;
5803 default: 4320 default:
5804 /* Indicate to hardware the Address is Valid. */ 4321 /* Indicate to hardware the Address is Valid. */
5805 rar_high |= E1000_RAH_AV; 4322 rar_high |= E1000_RAH_AV;
@@ -5823,9 +4340,6 @@ void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
5823{ 4340{
5824 u32 temp; 4341 u32 temp;
5825 4342
5826 if (hw->mac_type == e1000_ich8lan)
5827 return;
5828
5829 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4343 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5830 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4344 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5831 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4345 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
@@ -5850,22 +4364,6 @@ static void e1000_clear_vfta(struct e1000_hw *hw)
5850 u32 vfta_offset = 0; 4364 u32 vfta_offset = 0;
5851 u32 vfta_bit_in_reg = 0; 4365 u32 vfta_bit_in_reg = 0;
5852 4366
5853 if (hw->mac_type == e1000_ich8lan)
5854 return;
5855
5856 if (hw->mac_type == e1000_82573) {
5857 if (hw->mng_cookie.vlan_id != 0) {
5858 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5859 * ID. The following operations determine which 32b entry
5860 * (i.e. offset) into the array we want to set the VLAN ID
5861 * (i.e. bit) of the manageability unit. */
5862 vfta_offset = (hw->mng_cookie.vlan_id >>
5863 E1000_VFTA_ENTRY_SHIFT) &
5864 E1000_VFTA_ENTRY_MASK;
5865 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5866 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5867 }
5868 }
5869 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 4367 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5870 /* If the offset we want to clear is the same offset of the 4368 /* If the offset we want to clear is the same offset of the
5871 * manageability VLAN ID, then clear all bits except that of the 4369 * manageability VLAN ID, then clear all bits except that of the
@@ -5902,14 +4400,8 @@ static s32 e1000_id_led_init(struct e1000_hw *hw)
5902 return -E1000_ERR_EEPROM; 4400 return -E1000_ERR_EEPROM;
5903 } 4401 }
5904 4402
5905 if ((hw->mac_type == e1000_82573) && 4403 if ((eeprom_data == ID_LED_RESERVED_0000) ||
5906 (eeprom_data == ID_LED_RESERVED_82573))
5907 eeprom_data = ID_LED_DEFAULT_82573;
5908 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5909 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4404 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5910 if (hw->mac_type == e1000_ich8lan)
5911 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5912 else
5913 eeprom_data = ID_LED_DEFAULT; 4405 eeprom_data = ID_LED_DEFAULT;
5914 } 4406 }
5915 4407
@@ -6007,44 +4499,6 @@ s32 e1000_setup_led(struct e1000_hw *hw)
6007 return E1000_SUCCESS; 4499 return E1000_SUCCESS;
6008} 4500}
6009 4501
6010
6011/******************************************************************************
6012 * Used on 82571 and later Si that has LED blink bits.
6013 * Callers must use their own timer and should have already called
6014 * e1000_id_led_init()
6015 * Call e1000_cleanup led() to stop blinking
6016 *
6017 * hw - Struct containing variables accessed by shared code
6018 *****************************************************************************/
6019s32 e1000_blink_led_start(struct e1000_hw *hw)
6020{
6021 s16 i;
6022 u32 ledctl_blink = 0;
6023
6024 DEBUGFUNC("e1000_id_led_blink_on");
6025
6026 if (hw->mac_type < e1000_82571) {
6027 /* Nothing to do */
6028 return E1000_SUCCESS;
6029 }
6030 if (hw->media_type == e1000_media_type_fiber) {
6031 /* always blink LED0 for PCI-E fiber */
6032 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6033 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6034 } else {
6035 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6036 ledctl_blink = hw->ledctl_mode2;
6037 for (i=0; i < 4; i++)
6038 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6039 E1000_LEDCTL_MODE_LED_ON)
6040 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6041 }
6042
6043 ew32(LEDCTL, ledctl_blink);
6044
6045 return E1000_SUCCESS;
6046}
6047
6048/****************************************************************************** 4502/******************************************************************************
6049 * Restores the saved state of the SW controlable LED. 4503 * Restores the saved state of the SW controlable LED.
6050 * 4504 *
@@ -6074,10 +4528,6 @@ s32 e1000_cleanup_led(struct e1000_hw *hw)
6074 return ret_val; 4528 return ret_val;
6075 /* Fall Through */ 4529 /* Fall Through */
6076 default: 4530 default:
6077 if (hw->phy_type == e1000_phy_ife) {
6078 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6079 break;
6080 }
6081 /* Restore LEDCTL settings */ 4531 /* Restore LEDCTL settings */
6082 ew32(LEDCTL, hw->ledctl_default); 4532 ew32(LEDCTL, hw->ledctl_default);
6083 break; 4533 break;
@@ -6121,9 +4571,6 @@ s32 e1000_led_on(struct e1000_hw *hw)
6121 /* Clear SW Defineable Pin 0 to turn on the LED */ 4571 /* Clear SW Defineable Pin 0 to turn on the LED */
6122 ctrl &= ~E1000_CTRL_SWDPIN0; 4572 ctrl &= ~E1000_CTRL_SWDPIN0;
6123 ctrl |= E1000_CTRL_SWDPIO0; 4573 ctrl |= E1000_CTRL_SWDPIO0;
6124 } else if (hw->phy_type == e1000_phy_ife) {
6125 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6126 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6127 } else if (hw->media_type == e1000_media_type_copper) { 4574 } else if (hw->media_type == e1000_media_type_copper) {
6128 ew32(LEDCTL, hw->ledctl_mode2); 4575 ew32(LEDCTL, hw->ledctl_mode2);
6129 return E1000_SUCCESS; 4576 return E1000_SUCCESS;
@@ -6171,9 +4618,6 @@ s32 e1000_led_off(struct e1000_hw *hw)
6171 /* Set SW Defineable Pin 0 to turn off the LED */ 4618 /* Set SW Defineable Pin 0 to turn off the LED */
6172 ctrl |= E1000_CTRL_SWDPIN0; 4619 ctrl |= E1000_CTRL_SWDPIN0;
6173 ctrl |= E1000_CTRL_SWDPIO0; 4620 ctrl |= E1000_CTRL_SWDPIO0;
6174 } else if (hw->phy_type == e1000_phy_ife) {
6175 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6176 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6177 } else if (hw->media_type == e1000_media_type_copper) { 4621 } else if (hw->media_type == e1000_media_type_copper) {
6178 ew32(LEDCTL, hw->ledctl_mode1); 4622 ew32(LEDCTL, hw->ledctl_mode1);
6179 return E1000_SUCCESS; 4623 return E1000_SUCCESS;
@@ -6212,14 +4656,12 @@ static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6212 temp = er32(XOFFTXC); 4656 temp = er32(XOFFTXC);
6213 temp = er32(FCRUC); 4657 temp = er32(FCRUC);
6214 4658
6215 if (hw->mac_type != e1000_ich8lan) {
6216 temp = er32(PRC64); 4659 temp = er32(PRC64);
6217 temp = er32(PRC127); 4660 temp = er32(PRC127);
6218 temp = er32(PRC255); 4661 temp = er32(PRC255);
6219 temp = er32(PRC511); 4662 temp = er32(PRC511);
6220 temp = er32(PRC1023); 4663 temp = er32(PRC1023);
6221 temp = er32(PRC1522); 4664 temp = er32(PRC1522);
6222 }
6223 4665
6224 temp = er32(GPRC); 4666 temp = er32(GPRC);
6225 temp = er32(BPRC); 4667 temp = er32(BPRC);
@@ -6241,14 +4683,12 @@ static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6241 temp = er32(TPR); 4683 temp = er32(TPR);
6242 temp = er32(TPT); 4684 temp = er32(TPT);
6243 4685
6244 if (hw->mac_type != e1000_ich8lan) {
6245 temp = er32(PTC64); 4686 temp = er32(PTC64);
6246 temp = er32(PTC127); 4687 temp = er32(PTC127);
6247 temp = er32(PTC255); 4688 temp = er32(PTC255);
6248 temp = er32(PTC511); 4689 temp = er32(PTC511);
6249 temp = er32(PTC1023); 4690 temp = er32(PTC1023);
6250 temp = er32(PTC1522); 4691 temp = er32(PTC1522);
6251 }
6252 4692
6253 temp = er32(MPTC); 4693 temp = er32(MPTC);
6254 temp = er32(BPTC); 4694 temp = er32(BPTC);
@@ -6267,21 +4707,6 @@ static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6267 temp = er32(MGTPRC); 4707 temp = er32(MGTPRC);
6268 temp = er32(MGTPDC); 4708 temp = er32(MGTPDC);
6269 temp = er32(MGTPTC); 4709 temp = er32(MGTPTC);
6270
6271 if (hw->mac_type <= e1000_82547_rev_2) return;
6272
6273 temp = er32(IAC);
6274 temp = er32(ICRXOC);
6275
6276 if (hw->mac_type == e1000_ich8lan) return;
6277
6278 temp = er32(ICRXPTC);
6279 temp = er32(ICRXATC);
6280 temp = er32(ICTXPTC);
6281 temp = er32(ICTXATC);
6282 temp = er32(ICTXQEC);
6283 temp = er32(ICTXQMTC);
6284 temp = er32(ICRXDMTC);
6285} 4710}
6286 4711
6287/****************************************************************************** 4712/******************************************************************************
@@ -6433,8 +4858,6 @@ void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
6433 *****************************************************************************/ 4858 *****************************************************************************/
6434void e1000_get_bus_info(struct e1000_hw *hw) 4859void e1000_get_bus_info(struct e1000_hw *hw)
6435{ 4860{
6436 s32 ret_val;
6437 u16 pci_ex_link_status;
6438 u32 status; 4861 u32 status;
6439 4862
6440 switch (hw->mac_type) { 4863 switch (hw->mac_type) {
@@ -6444,26 +4867,6 @@ void e1000_get_bus_info(struct e1000_hw *hw)
6444 hw->bus_speed = e1000_bus_speed_unknown; 4867 hw->bus_speed = e1000_bus_speed_unknown;
6445 hw->bus_width = e1000_bus_width_unknown; 4868 hw->bus_width = e1000_bus_width_unknown;
6446 break; 4869 break;
6447 case e1000_82571:
6448 case e1000_82572:
6449 case e1000_82573:
6450 case e1000_80003es2lan:
6451 hw->bus_type = e1000_bus_type_pci_express;
6452 hw->bus_speed = e1000_bus_speed_2500;
6453 ret_val = e1000_read_pcie_cap_reg(hw,
6454 PCI_EX_LINK_STATUS,
6455 &pci_ex_link_status);
6456 if (ret_val)
6457 hw->bus_width = e1000_bus_width_unknown;
6458 else
6459 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6460 PCI_EX_LINK_WIDTH_SHIFT;
6461 break;
6462 case e1000_ich8lan:
6463 hw->bus_type = e1000_bus_type_pci_express;
6464 hw->bus_speed = e1000_bus_speed_2500;
6465 hw->bus_width = e1000_bus_width_pciex_1;
6466 break;
6467 default: 4870 default:
6468 status = er32(STATUS); 4871 status = er32(STATUS);
6469 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4872 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
@@ -6577,34 +4980,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
6577 return -E1000_ERR_PHY; 4980 return -E1000_ERR_PHY;
6578 break; 4981 break;
6579 } 4982 }
6580 } else if (hw->phy_type == e1000_phy_gg82563) {
6581 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6582 &phy_data);
6583 if (ret_val)
6584 return ret_val;
6585 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6586
6587 switch (cable_length) {
6588 case e1000_gg_cable_length_60:
6589 *min_length = 0;
6590 *max_length = e1000_igp_cable_length_60;
6591 break;
6592 case e1000_gg_cable_length_60_115:
6593 *min_length = e1000_igp_cable_length_60;
6594 *max_length = e1000_igp_cable_length_115;
6595 break;
6596 case e1000_gg_cable_length_115_150:
6597 *min_length = e1000_igp_cable_length_115;
6598 *max_length = e1000_igp_cable_length_150;
6599 break;
6600 case e1000_gg_cable_length_150:
6601 *min_length = e1000_igp_cable_length_150;
6602 *max_length = e1000_igp_cable_length_180;
6603 break;
6604 default:
6605 return -E1000_ERR_PHY;
6606 break;
6607 }
6608 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 4983 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6609 u16 cur_agc_value; 4984 u16 cur_agc_value;
6610 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 4985 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
@@ -6652,51 +5027,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
6652 IGP01E1000_AGC_RANGE) : 0; 5027 IGP01E1000_AGC_RANGE) : 0;
6653 *max_length = e1000_igp_cable_length_table[agc_value] + 5028 *max_length = e1000_igp_cable_length_table[agc_value] +
6654 IGP01E1000_AGC_RANGE; 5029 IGP01E1000_AGC_RANGE;
6655 } else if (hw->phy_type == e1000_phy_igp_2 ||
6656 hw->phy_type == e1000_phy_igp_3) {
6657 u16 cur_agc_index, max_agc_index = 0;
6658 u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6659 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6660 {IGP02E1000_PHY_AGC_A,
6661 IGP02E1000_PHY_AGC_B,
6662 IGP02E1000_PHY_AGC_C,
6663 IGP02E1000_PHY_AGC_D};
6664 /* Read the AGC registers for all channels */
6665 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6666 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6667 if (ret_val)
6668 return ret_val;
6669
6670 /* Getting bits 15:9, which represent the combination of course and
6671 * fine gain values. The result is a number that can be put into
6672 * the lookup table to obtain the approximate cable length. */
6673 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6674 IGP02E1000_AGC_LENGTH_MASK;
6675
6676 /* Array index bound check. */
6677 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6678 (cur_agc_index == 0))
6679 return -E1000_ERR_PHY;
6680
6681 /* Remove min & max AGC values from calculation. */
6682 if (e1000_igp_2_cable_length_table[min_agc_index] >
6683 e1000_igp_2_cable_length_table[cur_agc_index])
6684 min_agc_index = cur_agc_index;
6685 if (e1000_igp_2_cable_length_table[max_agc_index] <
6686 e1000_igp_2_cable_length_table[cur_agc_index])
6687 max_agc_index = cur_agc_index;
6688
6689 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6690 }
6691
6692 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6693 e1000_igp_2_cable_length_table[max_agc_index]);
6694 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6695
6696 /* Calculate cable length with the error range of +/- 10 meters. */
6697 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6698 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6699 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6700 } 5030 }
6701 5031
6702 return E1000_SUCCESS; 5032 return E1000_SUCCESS;
@@ -6726,8 +5056,7 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
6726 5056
6727 DEBUGFUNC("e1000_check_polarity"); 5057 DEBUGFUNC("e1000_check_polarity");
6728 5058
6729 if ((hw->phy_type == e1000_phy_m88) || 5059 if (hw->phy_type == e1000_phy_m88) {
6730 (hw->phy_type == e1000_phy_gg82563)) {
6731 /* return the Polarity bit in the Status register. */ 5060 /* return the Polarity bit in the Status register. */
6732 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5061 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6733 &phy_data); 5062 &phy_data);
@@ -6737,9 +5066,7 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
6737 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 5066 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6738 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5067 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6739 5068
6740 } else if (hw->phy_type == e1000_phy_igp || 5069 } else if (hw->phy_type == e1000_phy_igp) {
6741 hw->phy_type == e1000_phy_igp_3 ||
6742 hw->phy_type == e1000_phy_igp_2) {
6743 /* Read the Status register to check the speed */ 5070 /* Read the Status register to check the speed */
6744 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5071 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6745 &phy_data); 5072 &phy_data);
@@ -6766,14 +5093,6 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
6766 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 5093 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6767 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5094 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6768 } 5095 }
6769 } else if (hw->phy_type == e1000_phy_ife) {
6770 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6771 &phy_data);
6772 if (ret_val)
6773 return ret_val;
6774 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6775 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6776 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6777 } 5096 }
6778 return E1000_SUCCESS; 5097 return E1000_SUCCESS;
6779} 5098}
@@ -6800,17 +5119,14 @@ static s32 e1000_check_downshift(struct e1000_hw *hw)
6800 5119
6801 DEBUGFUNC("e1000_check_downshift"); 5120 DEBUGFUNC("e1000_check_downshift");
6802 5121
6803 if (hw->phy_type == e1000_phy_igp || 5122 if (hw->phy_type == e1000_phy_igp) {
6804 hw->phy_type == e1000_phy_igp_3 ||
6805 hw->phy_type == e1000_phy_igp_2) {
6806 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5123 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6807 &phy_data); 5124 &phy_data);
6808 if (ret_val) 5125 if (ret_val)
6809 return ret_val; 5126 return ret_val;
6810 5127
6811 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 5128 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6812 } else if ((hw->phy_type == e1000_phy_m88) || 5129 } else if (hw->phy_type == e1000_phy_m88) {
6813 (hw->phy_type == e1000_phy_gg82563)) {
6814 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5130 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6815 &phy_data); 5131 &phy_data);
6816 if (ret_val) 5132 if (ret_val)
@@ -6818,9 +5134,6 @@ static s32 e1000_check_downshift(struct e1000_hw *hw)
6818 5134
6819 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5135 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6820 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5136 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6821 } else if (hw->phy_type == e1000_phy_ife) {
6822 /* e1000_phy_ife supports 10/100 speed only */
6823 hw->speed_downgraded = false;
6824 } 5137 }
6825 5138
6826 return E1000_SUCCESS; 5139 return E1000_SUCCESS;
@@ -7070,13 +5383,11 @@ static s32 e1000_set_phy_mode(struct e1000_hw *hw)
7070 5383
7071static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5384static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7072{ 5385{
7073 u32 phy_ctrl = 0;
7074 s32 ret_val; 5386 s32 ret_val;
7075 u16 phy_data; 5387 u16 phy_data;
7076 DEBUGFUNC("e1000_set_d3_lplu_state"); 5388 DEBUGFUNC("e1000_set_d3_lplu_state");
7077 5389
7078 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 5390 if (hw->phy_type != e1000_phy_igp)
7079 && hw->phy_type != e1000_phy_igp_3)
7080 return E1000_SUCCESS; 5391 return E1000_SUCCESS;
7081 5392
7082 /* During driver activity LPLU should not be used or it will attain link 5393 /* During driver activity LPLU should not be used or it will attain link
@@ -7086,11 +5397,6 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7086 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5397 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7087 if (ret_val) 5398 if (ret_val)
7088 return ret_val; 5399 return ret_val;
7089 } else if (hw->mac_type == e1000_ich8lan) {
7090 /* MAC writes into PHY register based on the state transition
7091 * and start auto-negotiation. SW driver can overwrite the settings
7092 * in CSR PHY power control E1000_PHY_CTRL register. */
7093 phy_ctrl = er32(PHY_CTRL);
7094 } else { 5400 } else {
7095 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 5401 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7096 if (ret_val) 5402 if (ret_val)
@@ -7105,16 +5411,11 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7105 if (ret_val) 5411 if (ret_val)
7106 return ret_val; 5412 return ret_val;
7107 } else { 5413 } else {
7108 if (hw->mac_type == e1000_ich8lan) { 5414 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7109 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 5415 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7110 ew32(PHY_CTRL, phy_ctrl); 5416 phy_data);
7111 } else { 5417 if (ret_val)
7112 phy_data &= ~IGP02E1000_PM_D3_LPLU; 5418 return ret_val;
7113 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7114 phy_data);
7115 if (ret_val)
7116 return ret_val;
7117 }
7118 } 5419 }
7119 5420
7120 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5421 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
@@ -7156,114 +5457,11 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7156 if (ret_val) 5457 if (ret_val)
7157 return ret_val; 5458 return ret_val;
7158 } else { 5459 } else {
7159 if (hw->mac_type == e1000_ich8lan) { 5460 phy_data |= IGP02E1000_PM_D3_LPLU;
7160 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 5461 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7161 ew32(PHY_CTRL, phy_ctrl);
7162 } else {
7163 phy_data |= IGP02E1000_PM_D3_LPLU;
7164 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7165 phy_data);
7166 if (ret_val)
7167 return ret_val;
7168 }
7169 }
7170
7171 /* When LPLU is enabled we should disable SmartSpeed */
7172 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7173 if (ret_val)
7174 return ret_val;
7175
7176 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7177 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7178 if (ret_val)
7179 return ret_val;
7180
7181 }
7182 return E1000_SUCCESS;
7183}
7184
7185/*****************************************************************************
7186 *
7187 * This function sets the lplu d0 state according to the active flag. When
7188 * activating lplu this function also disables smart speed and vise versa.
7189 * lplu will not be activated unless the device autonegotiation advertisment
7190 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7191 * hw: Struct containing variables accessed by shared code
7192 * active - true to enable lplu false to disable lplu.
7193 *
7194 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7195 * E1000_SUCCESS at any other case.
7196 *
7197 ****************************************************************************/
7198
7199static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7200{
7201 u32 phy_ctrl = 0;
7202 s32 ret_val;
7203 u16 phy_data;
7204 DEBUGFUNC("e1000_set_d0_lplu_state");
7205
7206 if (hw->mac_type <= e1000_82547_rev_2)
7207 return E1000_SUCCESS;
7208
7209 if (hw->mac_type == e1000_ich8lan) {
7210 phy_ctrl = er32(PHY_CTRL);
7211 } else {
7212 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7213 if (ret_val)
7214 return ret_val;
7215 }
7216
7217 if (!active) {
7218 if (hw->mac_type == e1000_ich8lan) {
7219 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7220 ew32(PHY_CTRL, phy_ctrl);
7221 } else {
7222 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7223 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7224 if (ret_val)
7225 return ret_val;
7226 }
7227
7228 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7229 * Dx states where the power conservation is most important. During
7230 * driver activity we should enable SmartSpeed, so performance is
7231 * maintained. */
7232 if (hw->smart_speed == e1000_smart_speed_on) {
7233 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7234 &phy_data);
7235 if (ret_val)
7236 return ret_val;
7237
7238 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7239 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7240 phy_data); 5462 phy_data);
7241 if (ret_val) 5463 if (ret_val)
7242 return ret_val; 5464 return ret_val;
7243 } else if (hw->smart_speed == e1000_smart_speed_off) {
7244 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7245 &phy_data);
7246 if (ret_val)
7247 return ret_val;
7248
7249 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7250 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7251 phy_data);
7252 if (ret_val)
7253 return ret_val;
7254 }
7255
7256
7257 } else {
7258
7259 if (hw->mac_type == e1000_ich8lan) {
7260 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7261 ew32(PHY_CTRL, phy_ctrl);
7262 } else {
7263 phy_data |= IGP02E1000_PM_D0_LPLU;
7264 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7265 if (ret_val)
7266 return ret_val;
7267 } 5465 }
7268 5466
7269 /* When LPLU is enabled we should disable SmartSpeed */ 5467 /* When LPLU is enabled we should disable SmartSpeed */
@@ -7343,296 +5541,6 @@ static s32 e1000_set_vco_speed(struct e1000_hw *hw)
7343} 5541}
7344 5542
7345 5543
7346/*****************************************************************************
7347 * This function reads the cookie from ARC ram.
7348 *
7349 * returns: - E1000_SUCCESS .
7350 ****************************************************************************/
7351static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer)
7352{
7353 u8 i;
7354 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7355 u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
7356
7357 length = (length >> 2);
7358 offset = (offset >> 2);
7359
7360 for (i = 0; i < length; i++) {
7361 *((u32 *)buffer + i) =
7362 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7363 }
7364 return E1000_SUCCESS;
7365}
7366
7367
7368/*****************************************************************************
7369 * This function checks whether the HOST IF is enabled for command operaton
7370 * and also checks whether the previous command is completed.
7371 * It busy waits in case of previous command is not completed.
7372 *
7373 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7374 * timeout
7375 * - E1000_SUCCESS for success.
7376 ****************************************************************************/
7377static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
7378{
7379 u32 hicr;
7380 u8 i;
7381
7382 /* Check that the host interface is enabled. */
7383 hicr = er32(HICR);
7384 if ((hicr & E1000_HICR_EN) == 0) {
7385 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7386 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7387 }
7388 /* check the previous command is completed */
7389 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7390 hicr = er32(HICR);
7391 if (!(hicr & E1000_HICR_C))
7392 break;
7393 mdelay(1);
7394 }
7395
7396 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7397 DEBUGOUT("Previous command timeout failed .\n");
7398 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7399 }
7400 return E1000_SUCCESS;
7401}
7402
7403/*****************************************************************************
7404 * This function writes the buffer content at the offset given on the host if.
7405 * It also does alignment considerations to do the writes in most efficient way.
7406 * Also fills up the sum of the buffer in *buffer parameter.
7407 *
7408 * returns - E1000_SUCCESS for success.
7409 ****************************************************************************/
7410static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
7411 u16 offset, u8 *sum)
7412{
7413 u8 *tmp;
7414 u8 *bufptr = buffer;
7415 u32 data = 0;
7416 u16 remaining, i, j, prev_bytes;
7417
7418 /* sum = only sum of the data and it is not checksum */
7419
7420 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7421 return -E1000_ERR_PARAM;
7422 }
7423
7424 tmp = (u8 *)&data;
7425 prev_bytes = offset & 0x3;
7426 offset &= 0xFFFC;
7427 offset >>= 2;
7428
7429 if (prev_bytes) {
7430 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7431 for (j = prev_bytes; j < sizeof(u32); j++) {
7432 *(tmp + j) = *bufptr++;
7433 *sum += *(tmp + j);
7434 }
7435 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7436 length -= j - prev_bytes;
7437 offset++;
7438 }
7439
7440 remaining = length & 0x3;
7441 length -= remaining;
7442
7443 /* Calculate length in DWORDs */
7444 length >>= 2;
7445
7446 /* The device driver writes the relevant command block into the
7447 * ram area. */
7448 for (i = 0; i < length; i++) {
7449 for (j = 0; j < sizeof(u32); j++) {
7450 *(tmp + j) = *bufptr++;
7451 *sum += *(tmp + j);
7452 }
7453
7454 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7455 }
7456 if (remaining) {
7457 for (j = 0; j < sizeof(u32); j++) {
7458 if (j < remaining)
7459 *(tmp + j) = *bufptr++;
7460 else
7461 *(tmp + j) = 0;
7462
7463 *sum += *(tmp + j);
7464 }
7465 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7466 }
7467
7468 return E1000_SUCCESS;
7469}
7470
7471
7472/*****************************************************************************
7473 * This function writes the command header after does the checksum calculation.
7474 *
7475 * returns - E1000_SUCCESS for success.
7476 ****************************************************************************/
7477static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
7478 struct e1000_host_mng_command_header *hdr)
7479{
7480 u16 i;
7481 u8 sum;
7482 u8 *buffer;
7483
7484 /* Write the whole command header structure which includes sum of
7485 * the buffer */
7486
7487 u16 length = sizeof(struct e1000_host_mng_command_header);
7488
7489 sum = hdr->checksum;
7490 hdr->checksum = 0;
7491
7492 buffer = (u8 *)hdr;
7493 i = length;
7494 while (i--)
7495 sum += buffer[i];
7496
7497 hdr->checksum = 0 - sum;
7498
7499 length >>= 2;
7500 /* The device driver writes the relevant command block into the ram area. */
7501 for (i = 0; i < length; i++) {
7502 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i));
7503 E1000_WRITE_FLUSH();
7504 }
7505
7506 return E1000_SUCCESS;
7507}
7508
7509
7510/*****************************************************************************
7511 * This function indicates to ARC that a new command is pending which completes
7512 * one write operation by the driver.
7513 *
7514 * returns - E1000_SUCCESS for success.
7515 ****************************************************************************/
7516static s32 e1000_mng_write_commit(struct e1000_hw *hw)
7517{
7518 u32 hicr;
7519
7520 hicr = er32(HICR);
7521 /* Setting this bit tells the ARC that a new command is pending. */
7522 ew32(HICR, hicr | E1000_HICR_C);
7523
7524 return E1000_SUCCESS;
7525}
7526
7527
7528/*****************************************************************************
7529 * This function checks the mode of the firmware.
7530 *
7531 * returns - true when the mode is IAMT or false.
7532 ****************************************************************************/
7533bool e1000_check_mng_mode(struct e1000_hw *hw)
7534{
7535 u32 fwsm;
7536
7537 fwsm = er32(FWSM);
7538
7539 if (hw->mac_type == e1000_ich8lan) {
7540 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7541 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7542 return true;
7543 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7544 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7545 return true;
7546
7547 return false;
7548}
7549
7550
7551/*****************************************************************************
7552 * This function writes the dhcp info .
7553 ****************************************************************************/
7554s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
7555{
7556 s32 ret_val;
7557 struct e1000_host_mng_command_header hdr;
7558
7559 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7560 hdr.command_length = length;
7561 hdr.reserved1 = 0;
7562 hdr.reserved2 = 0;
7563 hdr.checksum = 0;
7564
7565 ret_val = e1000_mng_enable_host_if(hw);
7566 if (ret_val == E1000_SUCCESS) {
7567 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7568 &(hdr.checksum));
7569 if (ret_val == E1000_SUCCESS) {
7570 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7571 if (ret_val == E1000_SUCCESS)
7572 ret_val = e1000_mng_write_commit(hw);
7573 }
7574 }
7575 return ret_val;
7576}
7577
7578
7579/*****************************************************************************
7580 * This function calculates the checksum.
7581 *
7582 * returns - checksum of buffer contents.
7583 ****************************************************************************/
7584static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
7585{
7586 u8 sum = 0;
7587 u32 i;
7588
7589 if (!buffer)
7590 return 0;
7591
7592 for (i=0; i < length; i++)
7593 sum += buffer[i];
7594
7595 return (u8)(0 - sum);
7596}
7597
7598/*****************************************************************************
7599 * This function checks whether tx pkt filtering needs to be enabled or not.
7600 *
7601 * returns - true for packet filtering or false.
7602 ****************************************************************************/
7603bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7604{
7605 /* called in init as well as watchdog timer functions */
7606
7607 s32 ret_val, checksum;
7608 bool tx_filter = false;
7609 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7610 u8 *buffer = (u8 *) &(hw->mng_cookie);
7611
7612 if (e1000_check_mng_mode(hw)) {
7613 ret_val = e1000_mng_enable_host_if(hw);
7614 if (ret_val == E1000_SUCCESS) {
7615 ret_val = e1000_host_if_read_cookie(hw, buffer);
7616 if (ret_val == E1000_SUCCESS) {
7617 checksum = hdr->checksum;
7618 hdr->checksum = 0;
7619 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7620 checksum == e1000_calculate_mng_checksum((char *)buffer,
7621 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7622 if (hdr->status &
7623 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7624 tx_filter = true;
7625 } else
7626 tx_filter = true;
7627 } else
7628 tx_filter = true;
7629 }
7630 }
7631
7632 hw->tx_pkt_filtering = tx_filter;
7633 return tx_filter;
7634}
7635
7636/****************************************************************************** 5544/******************************************************************************
7637 * Verifies the hardware needs to allow ARPs to be processed by the host 5545 * Verifies the hardware needs to allow ARPs to be processed by the host
7638 * 5546 *
@@ -7644,7 +5552,6 @@ bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7644u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5552u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7645{ 5553{
7646 u32 manc; 5554 u32 manc;
7647 u32 fwsm, factps;
7648 5555
7649 if (hw->asf_firmware_present) { 5556 if (hw->asf_firmware_present) {
7650 manc = er32(MANC); 5557 manc = er32(MANC);
@@ -7652,16 +5559,8 @@ u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7652 if (!(manc & E1000_MANC_RCV_TCO_EN) || 5559 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7653 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 5560 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7654 return false; 5561 return false;
7655 if (e1000_arc_subsystem_valid(hw)) { 5562 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7656 fwsm = er32(FWSM); 5563 return true;
7657 factps = er32(FACTPS);
7658
7659 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7660 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7661 return true;
7662 } else
7663 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7664 return true;
7665 } 5564 }
7666 return false; 5565 return false;
7667} 5566}
@@ -7750,67 +5649,6 @@ static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7750 return E1000_SUCCESS; 5649 return E1000_SUCCESS;
7751} 5650}
7752 5651
7753/***************************************************************************
7754 *
7755 * Disables PCI-Express master access.
7756 *
7757 * hw: Struct containing variables accessed by shared code
7758 *
7759 * returns: - none.
7760 *
7761 ***************************************************************************/
7762static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7763{
7764 u32 ctrl;
7765
7766 DEBUGFUNC("e1000_set_pci_express_master_disable");
7767
7768 if (hw->bus_type != e1000_bus_type_pci_express)
7769 return;
7770
7771 ctrl = er32(CTRL);
7772 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7773 ew32(CTRL, ctrl);
7774}
7775
7776/*******************************************************************************
7777 *
7778 * Disables PCI-Express master access and verifies there are no pending requests
7779 *
7780 * hw: Struct containing variables accessed by shared code
7781 *
7782 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7783 * caused the master requests to be disabled.
7784 * E1000_SUCCESS master requests disabled.
7785 *
7786 ******************************************************************************/
7787s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7788{
7789 s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7790
7791 DEBUGFUNC("e1000_disable_pciex_master");
7792
7793 if (hw->bus_type != e1000_bus_type_pci_express)
7794 return E1000_SUCCESS;
7795
7796 e1000_set_pci_express_master_disable(hw);
7797
7798 while (timeout) {
7799 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7800 break;
7801 else
7802 udelay(100);
7803 timeout--;
7804 }
7805
7806 if (!timeout) {
7807 DEBUGOUT("Master requests are pending.\n");
7808 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7809 }
7810
7811 return E1000_SUCCESS;
7812}
7813
7814/******************************************************************************* 5652/*******************************************************************************
7815 * 5653 *
7816 * Check for EEPROM Auto Read bit done. 5654 * Check for EEPROM Auto Read bit done.
@@ -7823,39 +5661,8 @@ s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7823 ******************************************************************************/ 5661 ******************************************************************************/
7824static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5662static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7825{ 5663{
7826 s32 timeout = AUTO_READ_DONE_TIMEOUT;
7827
7828 DEBUGFUNC("e1000_get_auto_rd_done"); 5664 DEBUGFUNC("e1000_get_auto_rd_done");
7829 5665 msleep(5);
7830 switch (hw->mac_type) {
7831 default:
7832 msleep(5);
7833 break;
7834 case e1000_82571:
7835 case e1000_82572:
7836 case e1000_82573:
7837 case e1000_80003es2lan:
7838 case e1000_ich8lan:
7839 while (timeout) {
7840 if (er32(EECD) & E1000_EECD_AUTO_RD)
7841 break;
7842 else msleep(1);
7843 timeout--;
7844 }
7845
7846 if (!timeout) {
7847 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7848 return -E1000_ERR_RESET;
7849 }
7850 break;
7851 }
7852
7853 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
7854 * Need to wait for PHY configuration completion before accessing NVM
7855 * and PHY. */
7856 if (hw->mac_type == e1000_82573)
7857 msleep(25);
7858
7859 return E1000_SUCCESS; 5666 return E1000_SUCCESS;
7860} 5667}
7861 5668
@@ -7870,36 +5677,8 @@ static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7870 ***************************************************************************/ 5677 ***************************************************************************/
7871static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5678static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7872{ 5679{
7873 s32 timeout = PHY_CFG_TIMEOUT;
7874 u32 cfg_mask = E1000_EEPROM_CFG_DONE;
7875
7876 DEBUGFUNC("e1000_get_phy_cfg_done"); 5680 DEBUGFUNC("e1000_get_phy_cfg_done");
7877 5681 mdelay(10);
7878 switch (hw->mac_type) {
7879 default:
7880 mdelay(10);
7881 break;
7882 case e1000_80003es2lan:
7883 /* Separate *_CFG_DONE_* bit for each port */
7884 if (er32(STATUS) & E1000_STATUS_FUNC_1)
7885 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7886 /* Fall Through */
7887 case e1000_82571:
7888 case e1000_82572:
7889 while (timeout) {
7890 if (er32(EEMNGCTL) & cfg_mask)
7891 break;
7892 else
7893 msleep(1);
7894 timeout--;
7895 }
7896 if (!timeout) {
7897 DEBUGOUT("MNG configuration cycle has not completed.\n");
7898 return -E1000_ERR_RESET;
7899 }
7900 break;
7901 }
7902
7903 return E1000_SUCCESS; 5682 return E1000_SUCCESS;
7904} 5683}
7905 5684
@@ -7924,12 +5703,6 @@ static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7924 if (!hw->eeprom_semaphore_present) 5703 if (!hw->eeprom_semaphore_present)
7925 return E1000_SUCCESS; 5704 return E1000_SUCCESS;
7926 5705
7927 if (hw->mac_type == e1000_80003es2lan) {
7928 /* Get the SW semaphore. */
7929 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
7930 return -E1000_ERR_EEPROM;
7931 }
7932
7933 /* Get the FW semaphore. */ 5706 /* Get the FW semaphore. */
7934 timeout = hw->eeprom.word_size + 1; 5707 timeout = hw->eeprom.word_size + 1;
7935 while (timeout) { 5708 while (timeout) {
@@ -7973,860 +5746,6 @@ static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7973 return; 5746 return;
7974 5747
7975 swsm = er32(SWSM); 5748 swsm = er32(SWSM);
7976 if (hw->mac_type == e1000_80003es2lan) { 5749 swsm &= ~(E1000_SWSM_SWESMBI);
7977 /* Release both semaphores. */
7978 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
7979 } else
7980 swsm &= ~(E1000_SWSM_SWESMBI);
7981 ew32(SWSM, swsm);
7982}
7983
7984/***************************************************************************
7985 *
7986 * Obtaining software semaphore bit (SMBI) before resetting PHY.
7987 *
7988 * hw: Struct containing variables accessed by shared code
7989 *
7990 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
7991 * E1000_SUCCESS at any other case.
7992 *
7993 ***************************************************************************/
7994static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
7995{
7996 s32 timeout = hw->eeprom.word_size + 1;
7997 u32 swsm;
7998
7999 DEBUGFUNC("e1000_get_software_semaphore");
8000
8001 if (hw->mac_type != e1000_80003es2lan) {
8002 return E1000_SUCCESS;
8003 }
8004
8005 while (timeout) {
8006 swsm = er32(SWSM);
8007 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8008 if (!(swsm & E1000_SWSM_SMBI))
8009 break;
8010 mdelay(1);
8011 timeout--;
8012 }
8013
8014 if (!timeout) {
8015 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8016 return -E1000_ERR_RESET;
8017 }
8018
8019 return E1000_SUCCESS;
8020}
8021
8022/***************************************************************************
8023 *
8024 * Release semaphore bit (SMBI).
8025 *
8026 * hw: Struct containing variables accessed by shared code
8027 *
8028 ***************************************************************************/
8029static void e1000_release_software_semaphore(struct e1000_hw *hw)
8030{
8031 u32 swsm;
8032
8033 DEBUGFUNC("e1000_release_software_semaphore");
8034
8035 if (hw->mac_type != e1000_80003es2lan) {
8036 return;
8037 }
8038
8039 swsm = er32(SWSM);
8040 /* Release the SW semaphores.*/
8041 swsm &= ~E1000_SWSM_SMBI;
8042 ew32(SWSM, swsm); 5750 ew32(SWSM, swsm);
8043} 5751}
8044
8045/******************************************************************************
8046 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8047 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8048 * the caller to figure out how to deal with it.
8049 *
8050 * hw - Struct containing variables accessed by shared code
8051 *
8052 * returns: - E1000_BLK_PHY_RESET
8053 * E1000_SUCCESS
8054 *
8055 *****************************************************************************/
8056s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
8057{
8058 u32 manc = 0;
8059 u32 fwsm = 0;
8060
8061 if (hw->mac_type == e1000_ich8lan) {
8062 fwsm = er32(FWSM);
8063 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8064 : E1000_BLK_PHY_RESET;
8065 }
8066
8067 if (hw->mac_type > e1000_82547_rev_2)
8068 manc = er32(MANC);
8069 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8070 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8071}
8072
8073static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8074{
8075 u32 fwsm;
8076
8077 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8078 * may not be provided a DMA clock when no manageability features are
8079 * enabled. We do not want to perform any reads/writes to these registers
8080 * if this is the case. We read FWSM to determine the manageability mode.
8081 */
8082 switch (hw->mac_type) {
8083 case e1000_82571:
8084 case e1000_82572:
8085 case e1000_82573:
8086 case e1000_80003es2lan:
8087 fwsm = er32(FWSM);
8088 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8089 return true;
8090 break;
8091 case e1000_ich8lan:
8092 return true;
8093 default:
8094 break;
8095 }
8096 return false;
8097}
8098
8099
8100/******************************************************************************
8101 * Configure PCI-Ex no-snoop
8102 *
8103 * hw - Struct containing variables accessed by shared code.
8104 * no_snoop - Bitmap of no-snoop events.
8105 *
8106 * returns: E1000_SUCCESS
8107 *
8108 *****************************************************************************/
8109static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8110{
8111 u32 gcr_reg = 0;
8112
8113 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8114
8115 if (hw->bus_type == e1000_bus_type_unknown)
8116 e1000_get_bus_info(hw);
8117
8118 if (hw->bus_type != e1000_bus_type_pci_express)
8119 return E1000_SUCCESS;
8120
8121 if (no_snoop) {
8122 gcr_reg = er32(GCR);
8123 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8124 gcr_reg |= no_snoop;
8125 ew32(GCR, gcr_reg);
8126 }
8127 if (hw->mac_type == e1000_ich8lan) {
8128 u32 ctrl_ext;
8129
8130 ew32(GCR, PCI_EX_82566_SNOOP_ALL);
8131
8132 ctrl_ext = er32(CTRL_EXT);
8133 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8134 ew32(CTRL_EXT, ctrl_ext);
8135 }
8136
8137 return E1000_SUCCESS;
8138}
8139
8140/***************************************************************************
8141 *
8142 * Get software semaphore FLAG bit (SWFLAG).
8143 * SWFLAG is used to synchronize the access to all shared resource between
8144 * SW, FW and HW.
8145 *
8146 * hw: Struct containing variables accessed by shared code
8147 *
8148 ***************************************************************************/
8149static s32 e1000_get_software_flag(struct e1000_hw *hw)
8150{
8151 s32 timeout = PHY_CFG_TIMEOUT;
8152 u32 extcnf_ctrl;
8153
8154 DEBUGFUNC("e1000_get_software_flag");
8155
8156 if (hw->mac_type == e1000_ich8lan) {
8157 while (timeout) {
8158 extcnf_ctrl = er32(EXTCNF_CTRL);
8159 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8160 ew32(EXTCNF_CTRL, extcnf_ctrl);
8161
8162 extcnf_ctrl = er32(EXTCNF_CTRL);
8163 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8164 break;
8165 mdelay(1);
8166 timeout--;
8167 }
8168
8169 if (!timeout) {
8170 DEBUGOUT("FW or HW locks the resource too long.\n");
8171 return -E1000_ERR_CONFIG;
8172 }
8173 }
8174
8175 return E1000_SUCCESS;
8176}
8177
8178/***************************************************************************
8179 *
8180 * Release software semaphore FLAG bit (SWFLAG).
8181 * SWFLAG is used to synchronize the access to all shared resource between
8182 * SW, FW and HW.
8183 *
8184 * hw: Struct containing variables accessed by shared code
8185 *
8186 ***************************************************************************/
8187static void e1000_release_software_flag(struct e1000_hw *hw)
8188{
8189 u32 extcnf_ctrl;
8190
8191 DEBUGFUNC("e1000_release_software_flag");
8192
8193 if (hw->mac_type == e1000_ich8lan) {
8194 extcnf_ctrl= er32(EXTCNF_CTRL);
8195 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8196 ew32(EXTCNF_CTRL, extcnf_ctrl);
8197 }
8198
8199 return;
8200}
8201
8202/******************************************************************************
8203 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8204 * register.
8205 *
8206 * hw - Struct containing variables accessed by shared code
8207 * offset - offset of word in the EEPROM to read
8208 * data - word read from the EEPROM
8209 * words - number of words to read
8210 *****************************************************************************/
8211static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8212 u16 *data)
8213{
8214 s32 error = E1000_SUCCESS;
8215 u32 flash_bank = 0;
8216 u32 act_offset = 0;
8217 u32 bank_offset = 0;
8218 u16 word = 0;
8219 u16 i = 0;
8220
8221 /* We need to know which is the valid flash bank. In the event
8222 * that we didn't allocate eeprom_shadow_ram, we may not be
8223 * managing flash_bank. So it cannot be trusted and needs
8224 * to be updated with each read.
8225 */
8226 /* Value of bit 22 corresponds to the flash bank we're on. */
8227 flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8228
8229 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8230 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8231
8232 error = e1000_get_software_flag(hw);
8233 if (error != E1000_SUCCESS)
8234 return error;
8235
8236 for (i = 0; i < words; i++) {
8237 if (hw->eeprom_shadow_ram != NULL &&
8238 hw->eeprom_shadow_ram[offset+i].modified) {
8239 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8240 } else {
8241 /* The NVM part needs a byte offset, hence * 2 */
8242 act_offset = bank_offset + ((offset + i) * 2);
8243 error = e1000_read_ich8_word(hw, act_offset, &word);
8244 if (error != E1000_SUCCESS)
8245 break;
8246 data[i] = word;
8247 }
8248 }
8249
8250 e1000_release_software_flag(hw);
8251
8252 return error;
8253}
8254
8255/******************************************************************************
8256 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8257 * register. Actually, writes are written to the shadow ram cache in the hw
8258 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8259 * the NVM, which occurs when the NVM checksum is updated.
8260 *
8261 * hw - Struct containing variables accessed by shared code
8262 * offset - offset of word in the EEPROM to write
8263 * words - number of words to write
8264 * data - words to write to the EEPROM
8265 *****************************************************************************/
8266static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8267 u16 *data)
8268{
8269 u32 i = 0;
8270 s32 error = E1000_SUCCESS;
8271
8272 error = e1000_get_software_flag(hw);
8273 if (error != E1000_SUCCESS)
8274 return error;
8275
8276 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8277 * allocated. Subsequent reads to the modified words are read from
8278 * this cached structure as well. Writes will only go into this
8279 * cached structure unless it's followed by a call to
8280 * e1000_update_eeprom_checksum() where it will commit the changes
8281 * and clear the "modified" field.
8282 */
8283 if (hw->eeprom_shadow_ram != NULL) {
8284 for (i = 0; i < words; i++) {
8285 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8286 hw->eeprom_shadow_ram[offset+i].modified = true;
8287 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8288 } else {
8289 error = -E1000_ERR_EEPROM;
8290 break;
8291 }
8292 }
8293 } else {
8294 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8295 * as they don't perform any NVM writes. An attempt in doing so
8296 * will result in this error.
8297 */
8298 error = -E1000_ERR_EEPROM;
8299 }
8300
8301 e1000_release_software_flag(hw);
8302
8303 return error;
8304}
8305
8306/******************************************************************************
8307 * This function does initial flash setup so that a new read/write/erase cycle
8308 * can be started.
8309 *
8310 * hw - The pointer to the hw structure
8311 ****************************************************************************/
8312static s32 e1000_ich8_cycle_init(struct e1000_hw *hw)
8313{
8314 union ich8_hws_flash_status hsfsts;
8315 s32 error = E1000_ERR_EEPROM;
8316 s32 i = 0;
8317
8318 DEBUGFUNC("e1000_ich8_cycle_init");
8319
8320 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8321
8322 /* May be check the Flash Des Valid bit in Hw status */
8323 if (hsfsts.hsf_status.fldesvalid == 0) {
8324 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8325 return error;
8326 }
8327
8328 /* Clear FCERR in Hw status by writing 1 */
8329 /* Clear DAEL in Hw status by writing a 1 */
8330 hsfsts.hsf_status.flcerr = 1;
8331 hsfsts.hsf_status.dael = 1;
8332
8333 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8334
8335 /* Either we should have a hardware SPI cycle in progress bit to check
8336 * against, in order to start a new cycle or FDONE bit should be changed
8337 * in the hardware so that it is 1 after harware reset, which can then be
8338 * used as an indication whether a cycle is in progress or has been
8339 * completed .. we should also have some software semaphore mechanism to
8340 * guard FDONE or the cycle in progress bit so that two threads access to
8341 * those bits can be sequentiallized or a way so that 2 threads dont
8342 * start the cycle at the same time */
8343
8344 if (hsfsts.hsf_status.flcinprog == 0) {
8345 /* There is no cycle running at present, so we can start a cycle */
8346 /* Begin by setting Flash Cycle Done. */
8347 hsfsts.hsf_status.flcdone = 1;
8348 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8349 error = E1000_SUCCESS;
8350 } else {
8351 /* otherwise poll for sometime so the current cycle has a chance
8352 * to end before giving up. */
8353 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8354 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8355 if (hsfsts.hsf_status.flcinprog == 0) {
8356 error = E1000_SUCCESS;
8357 break;
8358 }
8359 udelay(1);
8360 }
8361 if (error == E1000_SUCCESS) {
8362 /* Successful in waiting for previous cycle to timeout,
8363 * now set the Flash Cycle Done. */
8364 hsfsts.hsf_status.flcdone = 1;
8365 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8366 } else {
8367 DEBUGOUT("Flash controller busy, cannot get access");
8368 }
8369 }
8370 return error;
8371}
8372
8373/******************************************************************************
8374 * This function starts a flash cycle and waits for its completion
8375 *
8376 * hw - The pointer to the hw structure
8377 ****************************************************************************/
8378static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8379{
8380 union ich8_hws_flash_ctrl hsflctl;
8381 union ich8_hws_flash_status hsfsts;
8382 s32 error = E1000_ERR_EEPROM;
8383 u32 i = 0;
8384
8385 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8386 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8387 hsflctl.hsf_ctrl.flcgo = 1;
8388 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8389
8390 /* wait till FDONE bit is set to 1 */
8391 do {
8392 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8393 if (hsfsts.hsf_status.flcdone == 1)
8394 break;
8395 udelay(1);
8396 i++;
8397 } while (i < timeout);
8398 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8399 error = E1000_SUCCESS;
8400 }
8401 return error;
8402}
8403
8404/******************************************************************************
8405 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8406 *
8407 * hw - The pointer to the hw structure
8408 * index - The index of the byte or word to read.
8409 * size - Size of data to read, 1=byte 2=word
8410 * data - Pointer to the word to store the value read.
8411 *****************************************************************************/
8412static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8413 u16 *data)
8414{
8415 union ich8_hws_flash_status hsfsts;
8416 union ich8_hws_flash_ctrl hsflctl;
8417 u32 flash_linear_address;
8418 u32 flash_data = 0;
8419 s32 error = -E1000_ERR_EEPROM;
8420 s32 count = 0;
8421
8422 DEBUGFUNC("e1000_read_ich8_data");
8423
8424 if (size < 1 || size > 2 || data == NULL ||
8425 index > ICH_FLASH_LINEAR_ADDR_MASK)
8426 return error;
8427
8428 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8429 hw->flash_base_addr;
8430
8431 do {
8432 udelay(1);
8433 /* Steps */
8434 error = e1000_ich8_cycle_init(hw);
8435 if (error != E1000_SUCCESS)
8436 break;
8437
8438 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8439 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8440 hsflctl.hsf_ctrl.fldbcount = size - 1;
8441 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8442 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8443
8444 /* Write the last 24 bits of index into Flash Linear address field in
8445 * Flash Address */
8446 /* TODO: TBD maybe check the index against the size of flash */
8447
8448 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8449
8450 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8451
8452 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8453 * sequence a few more times, else read in (shift in) the Flash Data0,
8454 * the order is least significant byte first msb to lsb */
8455 if (error == E1000_SUCCESS) {
8456 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8457 if (size == 1) {
8458 *data = (u8)(flash_data & 0x000000FF);
8459 } else if (size == 2) {
8460 *data = (u16)(flash_data & 0x0000FFFF);
8461 }
8462 break;
8463 } else {
8464 /* If we've gotten here, then things are probably completely hosed,
8465 * but if the error condition is detected, it won't hurt to give
8466 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8467 */
8468 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8469 if (hsfsts.hsf_status.flcerr == 1) {
8470 /* Repeat for some time before giving up. */
8471 continue;
8472 } else if (hsfsts.hsf_status.flcdone == 0) {
8473 DEBUGOUT("Timeout error - flash cycle did not complete.");
8474 break;
8475 }
8476 }
8477 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8478
8479 return error;
8480}
8481
8482/******************************************************************************
8483 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8484 *
8485 * hw - The pointer to the hw structure
8486 * index - The index of the byte/word to read.
8487 * size - Size of data to read, 1=byte 2=word
8488 * data - The byte(s) to write to the NVM.
8489 *****************************************************************************/
8490static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8491 u16 data)
8492{
8493 union ich8_hws_flash_status hsfsts;
8494 union ich8_hws_flash_ctrl hsflctl;
8495 u32 flash_linear_address;
8496 u32 flash_data = 0;
8497 s32 error = -E1000_ERR_EEPROM;
8498 s32 count = 0;
8499
8500 DEBUGFUNC("e1000_write_ich8_data");
8501
8502 if (size < 1 || size > 2 || data > size * 0xff ||
8503 index > ICH_FLASH_LINEAR_ADDR_MASK)
8504 return error;
8505
8506 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8507 hw->flash_base_addr;
8508
8509 do {
8510 udelay(1);
8511 /* Steps */
8512 error = e1000_ich8_cycle_init(hw);
8513 if (error != E1000_SUCCESS)
8514 break;
8515
8516 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8517 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8518 hsflctl.hsf_ctrl.fldbcount = size -1;
8519 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8520 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8521
8522 /* Write the last 24 bits of index into Flash Linear address field in
8523 * Flash Address */
8524 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8525
8526 if (size == 1)
8527 flash_data = (u32)data & 0x00FF;
8528 else
8529 flash_data = (u32)data;
8530
8531 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8532
8533 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8534 * sequence a few more times else done */
8535 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8536 if (error == E1000_SUCCESS) {
8537 break;
8538 } else {
8539 /* If we're here, then things are most likely completely hosed,
8540 * but if the error condition is detected, it won't hurt to give
8541 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8542 */
8543 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8544 if (hsfsts.hsf_status.flcerr == 1) {
8545 /* Repeat for some time before giving up. */
8546 continue;
8547 } else if (hsfsts.hsf_status.flcdone == 0) {
8548 DEBUGOUT("Timeout error - flash cycle did not complete.");
8549 break;
8550 }
8551 }
8552 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8553
8554 return error;
8555}
8556
8557/******************************************************************************
8558 * Reads a single byte from the NVM using the ICH8 flash access registers.
8559 *
8560 * hw - pointer to e1000_hw structure
8561 * index - The index of the byte to read.
8562 * data - Pointer to a byte to store the value read.
8563 *****************************************************************************/
8564static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data)
8565{
8566 s32 status = E1000_SUCCESS;
8567 u16 word = 0;
8568
8569 status = e1000_read_ich8_data(hw, index, 1, &word);
8570 if (status == E1000_SUCCESS) {
8571 *data = (u8)word;
8572 }
8573
8574 return status;
8575}
8576
8577/******************************************************************************
8578 * Writes a single byte to the NVM using the ICH8 flash access registers.
8579 * Performs verification by reading back the value and then going through
8580 * a retry algorithm before giving up.
8581 *
8582 * hw - pointer to e1000_hw structure
8583 * index - The index of the byte to write.
8584 * byte - The byte to write to the NVM.
8585 *****************************************************************************/
8586static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8587{
8588 s32 error = E1000_SUCCESS;
8589 s32 program_retries = 0;
8590
8591 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8592
8593 error = e1000_write_ich8_byte(hw, index, byte);
8594
8595 if (error != E1000_SUCCESS) {
8596 for (program_retries = 0; program_retries < 100; program_retries++) {
8597 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8598 error = e1000_write_ich8_byte(hw, index, byte);
8599 udelay(100);
8600 if (error == E1000_SUCCESS)
8601 break;
8602 }
8603 }
8604
8605 if (program_retries == 100)
8606 error = E1000_ERR_EEPROM;
8607
8608 return error;
8609}
8610
8611/******************************************************************************
8612 * Writes a single byte to the NVM using the ICH8 flash access registers.
8613 *
8614 * hw - pointer to e1000_hw structure
8615 * index - The index of the byte to read.
8616 * data - The byte to write to the NVM.
8617 *****************************************************************************/
8618static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8619{
8620 s32 status = E1000_SUCCESS;
8621 u16 word = (u16)data;
8622
8623 status = e1000_write_ich8_data(hw, index, 1, word);
8624
8625 return status;
8626}
8627
8628/******************************************************************************
8629 * Reads a word from the NVM using the ICH8 flash access registers.
8630 *
8631 * hw - pointer to e1000_hw structure
8632 * index - The starting byte index of the word to read.
8633 * data - Pointer to a word to store the value read.
8634 *****************************************************************************/
8635static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8636{
8637 s32 status = E1000_SUCCESS;
8638 status = e1000_read_ich8_data(hw, index, 2, data);
8639 return status;
8640}
8641
8642/******************************************************************************
8643 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8644 * based.
8645 *
8646 * hw - pointer to e1000_hw structure
8647 * bank - 0 for first bank, 1 for second bank
8648 *
8649 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8650 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8651 * bank size may be 4, 8 or 64 KBytes
8652 *****************************************************************************/
8653static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8654{
8655 union ich8_hws_flash_status hsfsts;
8656 union ich8_hws_flash_ctrl hsflctl;
8657 u32 flash_linear_address;
8658 s32 count = 0;
8659 s32 error = E1000_ERR_EEPROM;
8660 s32 iteration;
8661 s32 sub_sector_size = 0;
8662 s32 bank_size;
8663 s32 j = 0;
8664 s32 error_flag = 0;
8665
8666 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8667
8668 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8669 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8670 * consecutive sectors. The start index for the nth Hw sector can be
8671 * calculated as bank * 4096 + n * 256
8672 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8673 * The start index for the nth Hw sector can be calculated
8674 * as bank * 4096
8675 * 10: The HW sector is 8K bytes
8676 * 11: The Hw sector size is 64K bytes */
8677 if (hsfsts.hsf_status.berasesz == 0x0) {
8678 /* Hw sector size 256 */
8679 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8680 bank_size = ICH_FLASH_SECTOR_SIZE;
8681 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8682 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8683 bank_size = ICH_FLASH_SEG_SIZE_4K;
8684 iteration = 1;
8685 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8686 bank_size = ICH_FLASH_SEG_SIZE_64K;
8687 iteration = 1;
8688 } else {
8689 return error;
8690 }
8691
8692 for (j = 0; j < iteration ; j++) {
8693 do {
8694 count++;
8695 /* Steps */
8696 error = e1000_ich8_cycle_init(hw);
8697 if (error != E1000_SUCCESS) {
8698 error_flag = 1;
8699 break;
8700 }
8701
8702 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8703 * Control */
8704 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8705 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8706 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8707
8708 /* Write the last 24 bits of an index within the block into Flash
8709 * Linear address field in Flash Address. This probably needs to
8710 * be calculated here based off the on-chip erase sector size and
8711 * the software bank size (4, 8 or 64 KBytes) */
8712 flash_linear_address = bank * bank_size + j * sub_sector_size;
8713 flash_linear_address += hw->flash_base_addr;
8714 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8715
8716 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8717
8718 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8719 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8720 * sequence a few more times else Done */
8721 if (error == E1000_SUCCESS) {
8722 break;
8723 } else {
8724 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8725 if (hsfsts.hsf_status.flcerr == 1) {
8726 /* repeat for some time before giving up */
8727 continue;
8728 } else if (hsfsts.hsf_status.flcdone == 0) {
8729 error_flag = 1;
8730 break;
8731 }
8732 }
8733 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8734 if (error_flag == 1)
8735 break;
8736 }
8737 if (error_flag != 1)
8738 error = E1000_SUCCESS;
8739 return error;
8740}
8741
8742static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8743 u32 cnf_base_addr,
8744 u32 cnf_size)
8745{
8746 u32 ret_val = E1000_SUCCESS;
8747 u16 word_addr, reg_data, reg_addr;
8748 u16 i;
8749
8750 /* cnf_base_addr is in DWORD */
8751 word_addr = (u16)(cnf_base_addr << 1);
8752
8753 /* cnf_size is returned in size of dwords */
8754 for (i = 0; i < cnf_size; i++) {
8755 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8756 if (ret_val)
8757 return ret_val;
8758
8759 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8760 if (ret_val)
8761 return ret_val;
8762
8763 ret_val = e1000_get_software_flag(hw);
8764 if (ret_val != E1000_SUCCESS)
8765 return ret_val;
8766
8767 ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
8768
8769 e1000_release_software_flag(hw);
8770 }
8771
8772 return ret_val;
8773}
8774
8775
8776/******************************************************************************
8777 * This function initializes the PHY from the NVM on ICH8 platforms. This
8778 * is needed due to an issue where the NVM configuration is not properly
8779 * autoloaded after power transitions. Therefore, after each PHY reset, we
8780 * will load the configuration data out of the NVM manually.
8781 *
8782 * hw: Struct containing variables accessed by shared code
8783 *****************************************************************************/
8784static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8785{
8786 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8787
8788 if (hw->phy_type != e1000_phy_igp_3)
8789 return E1000_SUCCESS;
8790
8791 /* Check if SW needs configure the PHY */
8792 reg_data = er32(FEXTNVM);
8793 if (!(reg_data & FEXTNVM_SW_CONFIG))
8794 return E1000_SUCCESS;
8795
8796 /* Wait for basic configuration completes before proceeding*/
8797 loop = 0;
8798 do {
8799 reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
8800 udelay(100);
8801 loop++;
8802 } while ((!reg_data) && (loop < 50));
8803
8804 /* Clear the Init Done bit for the next init event */
8805 reg_data = er32(STATUS);
8806 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8807 ew32(STATUS, reg_data);
8808
8809 /* Make sure HW does not configure LCD from PHY extended configuration
8810 before SW configuration */
8811 reg_data = er32(EXTCNF_CTRL);
8812 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8813 reg_data = er32(EXTCNF_SIZE);
8814 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8815 cnf_size >>= 16;
8816 if (cnf_size) {
8817 reg_data = er32(EXTCNF_CTRL);
8818 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
8819 /* cnf_base_addr is in DWORD */
8820 cnf_base_addr >>= 16;
8821
8822 /* Configure LCD from extended configuration region. */
8823 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
8824 cnf_size);
8825 if (ret_val)
8826 return ret_val;
8827 }
8828 }
8829
8830 return E1000_SUCCESS;
8831}
8832
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 04:56:53 -0500