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path: root/drivers/net/e1000/e1000_hw.c
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Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c1373
1 files changed, 602 insertions, 771 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 9a4b6cbddf2c..9d6edf3e73f9 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -42,48 +42,65 @@ static void e1000_release_software_semaphore(struct e1000_hw *hw);
42 42
43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw); 43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static s32 e1000_check_downshift(struct e1000_hw *hw); 44static s32 e1000_check_downshift(struct e1000_hw *hw);
45static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); 45static s32 e1000_check_polarity(struct e1000_hw *hw,
46 e1000_rev_polarity *polarity);
46static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 47static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47static void e1000_clear_vfta(struct e1000_hw *hw); 48static void e1000_clear_vfta(struct e1000_hw *hw);
48static s32 e1000_commit_shadow_ram(struct e1000_hw *hw); 49static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
49static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 50static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
50 bool link_up); 51 bool link_up);
51static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 52static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
52static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 53static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
53static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank); 54static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
54static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 55static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
55static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, u16 *max_length); 56static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
57 u16 *max_length);
56static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); 58static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
57static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 59static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
58static s32 e1000_get_software_flag(struct e1000_hw *hw); 60static s32 e1000_get_software_flag(struct e1000_hw *hw);
59static s32 e1000_ich8_cycle_init(struct e1000_hw *hw); 61static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
60static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout); 62static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
61static s32 e1000_id_led_init(struct e1000_hw *hw); 63static s32 e1000_id_led_init(struct e1000_hw *hw);
62static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, u32 cnf_base_addr, u32 cnf_size); 64static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
65 u32 cnf_base_addr,
66 u32 cnf_size);
63static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw); 67static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
64static void e1000_init_rx_addrs(struct e1000_hw *hw); 68static void e1000_init_rx_addrs(struct e1000_hw *hw);
65static void e1000_initialize_hardware_bits(struct e1000_hw *hw); 69static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
66static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); 70static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
67static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); 71static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
68static s32 e1000_mng_enable_host_if(struct e1000_hw *hw); 72static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
69static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum); 73static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
70static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); 74 u16 offset, u8 *sum);
75static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
76 struct e1000_host_mng_command_header
77 *hdr);
71static s32 e1000_mng_write_commit(struct e1000_hw *hw); 78static s32 e1000_mng_write_commit(struct e1000_hw *hw);
72static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 79static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
73static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 80 struct e1000_phy_info *phy_info);
74static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 81static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
75static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 82 struct e1000_phy_info *phy_info);
83static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
84 u16 *data);
85static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
86 u16 *data);
76static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); 87static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
77static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 88static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
89 struct e1000_phy_info *phy_info);
78static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); 90static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
79static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data); 91static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
80static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte); 92static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
93 u8 byte);
81static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte); 94static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
82static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data); 95static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
83static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 *data); 96static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
84static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 data); 97 u16 *data);
85static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 98static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
86static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 99 u16 data);
100static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
101 u16 *data);
102static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
103 u16 *data);
87static void e1000_release_software_flag(struct e1000_hw *hw); 104static void e1000_release_software_flag(struct e1000_hw *hw);
88static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 105static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
89static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); 106static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
@@ -101,23 +118,21 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
101static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 118static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
102static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 119static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
103static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, 120static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
104 u16 count); 121 u16 count);
105static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 122static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
106static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 123static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
107static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 124static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
108 u16 words, u16 *data); 125 u16 words, u16 *data);
109static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, 126static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
110 u16 offset, u16 words, 127 u16 words, u16 *data);
111 u16 *data);
112static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 128static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
113static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); 129static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
114static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); 130static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
115static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, 131static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
116 u16 count);
117static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 132static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
118 u16 phy_data); 133 u16 phy_data);
119static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr, 134static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
120 u16 *phy_data); 135 u16 *phy_data);
121static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 136static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
122static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 137static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
123static void e1000_release_eeprom(struct e1000_hw *hw); 138static void e1000_release_eeprom(struct e1000_hw *hw);
@@ -127,8 +142,7 @@ static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
127static s32 e1000_set_phy_mode(struct e1000_hw *hw); 142static s32 e1000_set_phy_mode(struct e1000_hw *hw);
128static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer); 143static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
129static u8 e1000_calculate_mng_checksum(char *buffer, u32 length); 144static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
130static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, 145static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);
131 u16 duplex);
132static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 146static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
133 147
134/* IGP cable length table */ 148/* IGP cable length table */
@@ -159,8 +173,7 @@ u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
159 * 173 *
160 * hw - Struct containing variables accessed by shared code 174 * hw - Struct containing variables accessed by shared code
161 *****************************************************************************/ 175 *****************************************************************************/
162static s32 176static s32 e1000_set_phy_type(struct e1000_hw *hw)
163e1000_set_phy_type(struct e1000_hw *hw)
164{ 177{
165 DEBUGFUNC("e1000_set_phy_type"); 178 DEBUGFUNC("e1000_set_phy_type");
166 179
@@ -210,8 +223,7 @@ e1000_set_phy_type(struct e1000_hw *hw)
210 * 223 *
211 * hw - Struct containing variables accessed by shared code 224 * hw - Struct containing variables accessed by shared code
212 *****************************************************************************/ 225 *****************************************************************************/
213static void 226static void e1000_phy_init_script(struct e1000_hw *hw)
214e1000_phy_init_script(struct e1000_hw *hw)
215{ 227{
216 u32 ret_val; 228 u32 ret_val;
217 u16 phy_saved_data; 229 u16 phy_saved_data;
@@ -306,8 +318,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
306 * 318 *
307 * hw - Struct containing variables accessed by shared code 319 * hw - Struct containing variables accessed by shared code
308 *****************************************************************************/ 320 *****************************************************************************/
309s32 321s32 e1000_set_mac_type(struct e1000_hw *hw)
310e1000_set_mac_type(struct e1000_hw *hw)
311{ 322{
312 DEBUGFUNC("e1000_set_mac_type"); 323 DEBUGFUNC("e1000_set_mac_type");
313 324
@@ -474,8 +485,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
474 * 485 *
475 * hw - Struct containing variables accessed by shared code 486 * hw - Struct containing variables accessed by shared code
476 * **************************************************************************/ 487 * **************************************************************************/
477void 488void e1000_set_media_type(struct e1000_hw *hw)
478e1000_set_media_type(struct e1000_hw *hw)
479{ 489{
480 u32 status; 490 u32 status;
481 491
@@ -510,7 +520,7 @@ e1000_set_media_type(struct e1000_hw *hw)
510 hw->media_type = e1000_media_type_copper; 520 hw->media_type = e1000_media_type_copper;
511 break; 521 break;
512 default: 522 default:
513 status = E1000_READ_REG(hw, STATUS); 523 status = er32(STATUS);
514 if (status & E1000_STATUS_TBIMODE) { 524 if (status & E1000_STATUS_TBIMODE) {
515 hw->media_type = e1000_media_type_fiber; 525 hw->media_type = e1000_media_type_fiber;
516 /* tbi_compatibility not valid on fiber */ 526 /* tbi_compatibility not valid on fiber */
@@ -528,8 +538,7 @@ e1000_set_media_type(struct e1000_hw *hw)
528 * 538 *
529 * hw - Struct containing variables accessed by shared code 539 * hw - Struct containing variables accessed by shared code
530 *****************************************************************************/ 540 *****************************************************************************/
531s32 541s32 e1000_reset_hw(struct e1000_hw *hw)
532e1000_reset_hw(struct e1000_hw *hw)
533{ 542{
534 u32 ctrl; 543 u32 ctrl;
535 u32 ctrl_ext; 544 u32 ctrl_ext;
@@ -559,15 +568,15 @@ e1000_reset_hw(struct e1000_hw *hw)
559 568
560 /* Clear interrupt mask to stop board from generating interrupts */ 569 /* Clear interrupt mask to stop board from generating interrupts */
561 DEBUGOUT("Masking off all interrupts\n"); 570 DEBUGOUT("Masking off all interrupts\n");
562 E1000_WRITE_REG(hw, IMC, 0xffffffff); 571 ew32(IMC, 0xffffffff);
563 572
564 /* Disable the Transmit and Receive units. Then delay to allow 573 /* Disable the Transmit and Receive units. Then delay to allow
565 * any pending transactions to complete before we hit the MAC with 574 * any pending transactions to complete before we hit the MAC with
566 * the global reset. 575 * the global reset.
567 */ 576 */
568 E1000_WRITE_REG(hw, RCTL, 0); 577 ew32(RCTL, 0);
569 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 578 ew32(TCTL, E1000_TCTL_PSP);
570 E1000_WRITE_FLUSH(hw); 579 E1000_WRITE_FLUSH();
571 580
572 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 581 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
573 hw->tbi_compatibility_on = false; 582 hw->tbi_compatibility_on = false;
@@ -577,11 +586,11 @@ e1000_reset_hw(struct e1000_hw *hw)
577 */ 586 */
578 msleep(10); 587 msleep(10);
579 588
580 ctrl = E1000_READ_REG(hw, CTRL); 589 ctrl = er32(CTRL);
581 590
582 /* Must reset the PHY before resetting the MAC */ 591 /* Must reset the PHY before resetting the MAC */
583 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 592 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
584 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 593 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
585 msleep(5); 594 msleep(5);
586 } 595 }
587 596
@@ -590,12 +599,12 @@ e1000_reset_hw(struct e1000_hw *hw)
590 if (hw->mac_type == e1000_82573) { 599 if (hw->mac_type == e1000_82573) {
591 timeout = 10; 600 timeout = 10;
592 601
593 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 602 extcnf_ctrl = er32(EXTCNF_CTRL);
594 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 603 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
595 604
596 do { 605 do {
597 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 606 ew32(EXTCNF_CTRL, extcnf_ctrl);
598 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 607 extcnf_ctrl = er32(EXTCNF_CTRL);
599 608
600 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 609 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
601 break; 610 break;
@@ -610,9 +619,9 @@ e1000_reset_hw(struct e1000_hw *hw)
610 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 619 /* Workaround for ICH8 bit corruption issue in FIFO memory */
611 if (hw->mac_type == e1000_ich8lan) { 620 if (hw->mac_type == e1000_ich8lan) {
612 /* Set Tx and Rx buffer allocation to 8k apiece. */ 621 /* Set Tx and Rx buffer allocation to 8k apiece. */
613 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 622 ew32(PBA, E1000_PBA_8K);
614 /* Set Packet Buffer Size to 16k. */ 623 /* Set Packet Buffer Size to 16k. */
615 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 624 ew32(PBS, E1000_PBS_16K);
616 } 625 }
617 626
618 /* Issue a global reset to the MAC. This will reset the chip's 627 /* Issue a global reset to the MAC. This will reset the chip's
@@ -636,7 +645,7 @@ e1000_reset_hw(struct e1000_hw *hw)
636 case e1000_82545_rev_3: 645 case e1000_82545_rev_3:
637 case e1000_82546_rev_3: 646 case e1000_82546_rev_3:
638 /* Reset is performed on a shadow of the control register */ 647 /* Reset is performed on a shadow of the control register */
639 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 648 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
640 break; 649 break;
641 case e1000_ich8lan: 650 case e1000_ich8lan:
642 if (!hw->phy_reset_disable && 651 if (!hw->phy_reset_disable &&
@@ -649,11 +658,11 @@ e1000_reset_hw(struct e1000_hw *hw)
649 } 658 }
650 659
651 e1000_get_software_flag(hw); 660 e1000_get_software_flag(hw);
652 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 661 ew32(CTRL, (ctrl | E1000_CTRL_RST));
653 msleep(5); 662 msleep(5);
654 break; 663 break;
655 default: 664 default:
656 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 665 ew32(CTRL, (ctrl | E1000_CTRL_RST));
657 break; 666 break;
658 } 667 }
659 668
@@ -668,10 +677,10 @@ e1000_reset_hw(struct e1000_hw *hw)
668 case e1000_82544: 677 case e1000_82544:
669 /* Wait for reset to complete */ 678 /* Wait for reset to complete */
670 udelay(10); 679 udelay(10);
671 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 680 ctrl_ext = er32(CTRL_EXT);
672 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 681 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
673 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 682 ew32(CTRL_EXT, ctrl_ext);
674 E1000_WRITE_FLUSH(hw); 683 E1000_WRITE_FLUSH();
675 /* Wait for EEPROM reload */ 684 /* Wait for EEPROM reload */
676 msleep(2); 685 msleep(2);
677 break; 686 break;
@@ -685,10 +694,10 @@ e1000_reset_hw(struct e1000_hw *hw)
685 case e1000_82573: 694 case e1000_82573:
686 if (!e1000_is_onboard_nvm_eeprom(hw)) { 695 if (!e1000_is_onboard_nvm_eeprom(hw)) {
687 udelay(10); 696 udelay(10);
688 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 697 ctrl_ext = er32(CTRL_EXT);
689 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 698 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
690 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 699 ew32(CTRL_EXT, ctrl_ext);
691 E1000_WRITE_FLUSH(hw); 700 E1000_WRITE_FLUSH();
692 } 701 }
693 /* fall through */ 702 /* fall through */
694 default: 703 default:
@@ -701,27 +710,27 @@ e1000_reset_hw(struct e1000_hw *hw)
701 710
702 /* Disable HW ARPs on ASF enabled adapters */ 711 /* Disable HW ARPs on ASF enabled adapters */
703 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { 712 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
704 manc = E1000_READ_REG(hw, MANC); 713 manc = er32(MANC);
705 manc &= ~(E1000_MANC_ARP_EN); 714 manc &= ~(E1000_MANC_ARP_EN);
706 E1000_WRITE_REG(hw, MANC, manc); 715 ew32(MANC, manc);
707 } 716 }
708 717
709 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 718 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
710 e1000_phy_init_script(hw); 719 e1000_phy_init_script(hw);
711 720
712 /* Configure activity LED after PHY reset */ 721 /* Configure activity LED after PHY reset */
713 led_ctrl = E1000_READ_REG(hw, LEDCTL); 722 led_ctrl = er32(LEDCTL);
714 led_ctrl &= IGP_ACTIVITY_LED_MASK; 723 led_ctrl &= IGP_ACTIVITY_LED_MASK;
715 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 724 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
716 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 725 ew32(LEDCTL, led_ctrl);
717 } 726 }
718 727
719 /* Clear interrupt mask to stop board from generating interrupts */ 728 /* Clear interrupt mask to stop board from generating interrupts */
720 DEBUGOUT("Masking off all interrupts\n"); 729 DEBUGOUT("Masking off all interrupts\n");
721 E1000_WRITE_REG(hw, IMC, 0xffffffff); 730 ew32(IMC, 0xffffffff);
722 731
723 /* Clear any pending interrupt events. */ 732 /* Clear any pending interrupt events. */
724 icr = E1000_READ_REG(hw, ICR); 733 icr = er32(ICR);
725 734
726 /* If MWI was previously enabled, reenable it. */ 735 /* If MWI was previously enabled, reenable it. */
727 if (hw->mac_type == e1000_82542_rev2_0) { 736 if (hw->mac_type == e1000_82542_rev2_0) {
@@ -730,9 +739,9 @@ e1000_reset_hw(struct e1000_hw *hw)
730 } 739 }
731 740
732 if (hw->mac_type == e1000_ich8lan) { 741 if (hw->mac_type == e1000_ich8lan) {
733 u32 kab = E1000_READ_REG(hw, KABGTXD); 742 u32 kab = er32(KABGTXD);
734 kab |= E1000_KABGTXD_BGSQLBIAS; 743 kab |= E1000_KABGTXD_BGSQLBIAS;
735 E1000_WRITE_REG(hw, KABGTXD, kab); 744 ew32(KABGTXD, kab);
736 } 745 }
737 746
738 return E1000_SUCCESS; 747 return E1000_SUCCESS;
@@ -747,8 +756,7 @@ e1000_reset_hw(struct e1000_hw *hw)
747 * This function contains hardware limitation workarounds for PCI-E adapters 756 * This function contains hardware limitation workarounds for PCI-E adapters
748 * 757 *
749 *****************************************************************************/ 758 *****************************************************************************/
750static void 759static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
751e1000_initialize_hardware_bits(struct e1000_hw *hw)
752{ 760{
753 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { 761 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
754 /* Settings common to all PCI-express silicon */ 762 /* Settings common to all PCI-express silicon */
@@ -758,22 +766,22 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
758 u32 reg_txdctl, reg_txdctl1; 766 u32 reg_txdctl, reg_txdctl1;
759 767
760 /* link autonegotiation/sync workarounds */ 768 /* link autonegotiation/sync workarounds */
761 reg_tarc0 = E1000_READ_REG(hw, TARC0); 769 reg_tarc0 = er32(TARC0);
762 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 770 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
763 771
764 /* Enable not-done TX descriptor counting */ 772 /* Enable not-done TX descriptor counting */
765 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 773 reg_txdctl = er32(TXDCTL);
766 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 774 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
767 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 775 ew32(TXDCTL, reg_txdctl);
768 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 776 reg_txdctl1 = er32(TXDCTL1);
769 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 777 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
770 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 778 ew32(TXDCTL1, reg_txdctl1);
771 779
772 switch (hw->mac_type) { 780 switch (hw->mac_type) {
773 case e1000_82571: 781 case e1000_82571:
774 case e1000_82572: 782 case e1000_82572:
775 /* Clear PHY TX compatible mode bits */ 783 /* Clear PHY TX compatible mode bits */
776 reg_tarc1 = E1000_READ_REG(hw, TARC1); 784 reg_tarc1 = er32(TARC1);
777 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 785 reg_tarc1 &= ~((1 << 30)|(1 << 29));
778 786
779 /* link autonegotiation/sync workarounds */ 787 /* link autonegotiation/sync workarounds */
@@ -783,25 +791,25 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
783 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 791 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
784 792
785 /* Multiple read bit is reversed polarity */ 793 /* Multiple read bit is reversed polarity */
786 reg_tctl = E1000_READ_REG(hw, TCTL); 794 reg_tctl = er32(TCTL);
787 if (reg_tctl & E1000_TCTL_MULR) 795 if (reg_tctl & E1000_TCTL_MULR)
788 reg_tarc1 &= ~(1 << 28); 796 reg_tarc1 &= ~(1 << 28);
789 else 797 else
790 reg_tarc1 |= (1 << 28); 798 reg_tarc1 |= (1 << 28);
791 799
792 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 800 ew32(TARC1, reg_tarc1);
793 break; 801 break;
794 case e1000_82573: 802 case e1000_82573:
795 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 803 reg_ctrl_ext = er32(CTRL_EXT);
796 reg_ctrl_ext &= ~(1 << 23); 804 reg_ctrl_ext &= ~(1 << 23);
797 reg_ctrl_ext |= (1 << 22); 805 reg_ctrl_ext |= (1 << 22);
798 806
799 /* TX byte count fix */ 807 /* TX byte count fix */
800 reg_ctrl = E1000_READ_REG(hw, CTRL); 808 reg_ctrl = er32(CTRL);
801 reg_ctrl &= ~(1 << 29); 809 reg_ctrl &= ~(1 << 29);
802 810
803 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 811 ew32(CTRL_EXT, reg_ctrl_ext);
804 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 812 ew32(CTRL, reg_ctrl);
805 break; 813 break;
806 case e1000_80003es2lan: 814 case e1000_80003es2lan:
807 /* improve small packet performace for fiber/serdes */ 815 /* improve small packet performace for fiber/serdes */
@@ -811,14 +819,14 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
811 } 819 }
812 820
813 /* Multiple read bit is reversed polarity */ 821 /* Multiple read bit is reversed polarity */
814 reg_tctl = E1000_READ_REG(hw, TCTL); 822 reg_tctl = er32(TCTL);
815 reg_tarc1 = E1000_READ_REG(hw, TARC1); 823 reg_tarc1 = er32(TARC1);
816 if (reg_tctl & E1000_TCTL_MULR) 824 if (reg_tctl & E1000_TCTL_MULR)
817 reg_tarc1 &= ~(1 << 28); 825 reg_tarc1 &= ~(1 << 28);
818 else 826 else
819 reg_tarc1 |= (1 << 28); 827 reg_tarc1 |= (1 << 28);
820 828
821 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 829 ew32(TARC1, reg_tarc1);
822 break; 830 break;
823 case e1000_ich8lan: 831 case e1000_ich8lan:
824 /* Reduce concurrent DMA requests to 3 from 4 */ 832 /* Reduce concurrent DMA requests to 3 from 4 */
@@ -827,16 +835,16 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
827 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 835 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
828 reg_tarc0 |= ((1 << 29)|(1 << 28)); 836 reg_tarc0 |= ((1 << 29)|(1 << 28));
829 837
830 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 838 reg_ctrl_ext = er32(CTRL_EXT);
831 reg_ctrl_ext |= (1 << 22); 839 reg_ctrl_ext |= (1 << 22);
832 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 840 ew32(CTRL_EXT, reg_ctrl_ext);
833 841
834 /* workaround TX hang with TSO=on */ 842 /* workaround TX hang with TSO=on */
835 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 843 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
836 844
837 /* Multiple read bit is reversed polarity */ 845 /* Multiple read bit is reversed polarity */
838 reg_tctl = E1000_READ_REG(hw, TCTL); 846 reg_tctl = er32(TCTL);
839 reg_tarc1 = E1000_READ_REG(hw, TARC1); 847 reg_tarc1 = er32(TARC1);
840 if (reg_tctl & E1000_TCTL_MULR) 848 if (reg_tctl & E1000_TCTL_MULR)
841 reg_tarc1 &= ~(1 << 28); 849 reg_tarc1 &= ~(1 << 28);
842 else 850 else
@@ -845,13 +853,13 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
845 /* workaround TX hang with TSO=on */ 853 /* workaround TX hang with TSO=on */
846 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 854 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
847 855
848 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 856 ew32(TARC1, reg_tarc1);
849 break; 857 break;
850 default: 858 default:
851 break; 859 break;
852 } 860 }
853 861
854 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 862 ew32(TARC0, reg_tarc0);
855 } 863 }
856} 864}
857 865
@@ -866,8 +874,7 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw)
866 * configuration and flow control settings. Clears all on-chip counters. Leaves 874 * configuration and flow control settings. Clears all on-chip counters. Leaves
867 * the transmit and receive units disabled and uninitialized. 875 * the transmit and receive units disabled and uninitialized.
868 *****************************************************************************/ 876 *****************************************************************************/
869s32 877s32 e1000_init_hw(struct e1000_hw *hw)
870e1000_init_hw(struct e1000_hw *hw)
871{ 878{
872 u32 ctrl; 879 u32 ctrl;
873 u32 i; 880 u32 i;
@@ -883,9 +890,9 @@ e1000_init_hw(struct e1000_hw *hw)
883 ((hw->revision_id < 3) || 890 ((hw->revision_id < 3) ||
884 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 891 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
885 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 892 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
886 reg_data = E1000_READ_REG(hw, STATUS); 893 reg_data = er32(STATUS);
887 reg_data &= ~0x80000000; 894 reg_data &= ~0x80000000;
888 E1000_WRITE_REG(hw, STATUS, reg_data); 895 ew32(STATUS, reg_data);
889 } 896 }
890 897
891 /* Initialize Identification LED */ 898 /* Initialize Identification LED */
@@ -906,7 +913,7 @@ e1000_init_hw(struct e1000_hw *hw)
906 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 913 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
907 if (hw->mac_type != e1000_ich8lan) { 914 if (hw->mac_type != e1000_ich8lan) {
908 if (hw->mac_type < e1000_82545_rev_3) 915 if (hw->mac_type < e1000_82545_rev_3)
909 E1000_WRITE_REG(hw, VET, 0); 916 ew32(VET, 0);
910 e1000_clear_vfta(hw); 917 e1000_clear_vfta(hw);
911 } 918 }
912 919
@@ -914,8 +921,8 @@ e1000_init_hw(struct e1000_hw *hw)
914 if (hw->mac_type == e1000_82542_rev2_0) { 921 if (hw->mac_type == e1000_82542_rev2_0) {
915 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 922 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
916 e1000_pci_clear_mwi(hw); 923 e1000_pci_clear_mwi(hw);
917 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 924 ew32(RCTL, E1000_RCTL_RST);
918 E1000_WRITE_FLUSH(hw); 925 E1000_WRITE_FLUSH();
919 msleep(5); 926 msleep(5);
920 } 927 }
921 928
@@ -926,8 +933,8 @@ e1000_init_hw(struct e1000_hw *hw)
926 933
927 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 934 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
928 if (hw->mac_type == e1000_82542_rev2_0) { 935 if (hw->mac_type == e1000_82542_rev2_0) {
929 E1000_WRITE_REG(hw, RCTL, 0); 936 ew32(RCTL, 0);
930 E1000_WRITE_FLUSH(hw); 937 E1000_WRITE_FLUSH();
931 msleep(1); 938 msleep(1);
932 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 939 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
933 e1000_pci_set_mwi(hw); 940 e1000_pci_set_mwi(hw);
@@ -942,7 +949,7 @@ e1000_init_hw(struct e1000_hw *hw)
942 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 949 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
943 /* use write flush to prevent Memory Write Block (MWB) from 950 /* use write flush to prevent Memory Write Block (MWB) from
944 * occuring when accessing our register space */ 951 * occuring when accessing our register space */
945 E1000_WRITE_FLUSH(hw); 952 E1000_WRITE_FLUSH();
946 } 953 }
947 954
948 /* Set the PCI priority bit correctly in the CTRL register. This 955 /* Set the PCI priority bit correctly in the CTRL register. This
@@ -951,8 +958,8 @@ e1000_init_hw(struct e1000_hw *hw)
951 * 82542 and 82543 silicon. 958 * 82542 and 82543 silicon.
952 */ 959 */
953 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 960 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
954 ctrl = E1000_READ_REG(hw, CTRL); 961 ctrl = er32(CTRL);
955 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 962 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
956 } 963 }
957 964
958 switch (hw->mac_type) { 965 switch (hw->mac_type) {
@@ -975,9 +982,9 @@ e1000_init_hw(struct e1000_hw *hw)
975 982
976 /* Set the transmit descriptor write-back policy */ 983 /* Set the transmit descriptor write-back policy */
977 if (hw->mac_type > e1000_82544) { 984 if (hw->mac_type > e1000_82544) {
978 ctrl = E1000_READ_REG(hw, TXDCTL); 985 ctrl = er32(TXDCTL);
979 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 986 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
980 E1000_WRITE_REG(hw, TXDCTL, ctrl); 987 ew32(TXDCTL, ctrl);
981 } 988 }
982 989
983 if (hw->mac_type == e1000_82573) { 990 if (hw->mac_type == e1000_82573) {
@@ -989,21 +996,21 @@ e1000_init_hw(struct e1000_hw *hw)
989 break; 996 break;
990 case e1000_80003es2lan: 997 case e1000_80003es2lan:
991 /* Enable retransmit on late collisions */ 998 /* Enable retransmit on late collisions */
992 reg_data = E1000_READ_REG(hw, TCTL); 999 reg_data = er32(TCTL);
993 reg_data |= E1000_TCTL_RTLC; 1000 reg_data |= E1000_TCTL_RTLC;
994 E1000_WRITE_REG(hw, TCTL, reg_data); 1001 ew32(TCTL, reg_data);
995 1002
996 /* Configure Gigabit Carry Extend Padding */ 1003 /* Configure Gigabit Carry Extend Padding */
997 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1004 reg_data = er32(TCTL_EXT);
998 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1005 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
999 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1006 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1000 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1007 ew32(TCTL_EXT, reg_data);
1001 1008
1002 /* Configure Transmit Inter-Packet Gap */ 1009 /* Configure Transmit Inter-Packet Gap */
1003 reg_data = E1000_READ_REG(hw, TIPG); 1010 reg_data = er32(TIPG);
1004 reg_data &= ~E1000_TIPG_IPGT_MASK; 1011 reg_data &= ~E1000_TIPG_IPGT_MASK;
1005 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1012 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1006 E1000_WRITE_REG(hw, TIPG, reg_data); 1013 ew32(TIPG, reg_data);
1007 1014
1008 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1015 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1009 reg_data &= ~0x00100000; 1016 reg_data &= ~0x00100000;
@@ -1012,17 +1019,17 @@ e1000_init_hw(struct e1000_hw *hw)
1012 case e1000_82571: 1019 case e1000_82571:
1013 case e1000_82572: 1020 case e1000_82572:
1014 case e1000_ich8lan: 1021 case e1000_ich8lan:
1015 ctrl = E1000_READ_REG(hw, TXDCTL1); 1022 ctrl = er32(TXDCTL1);
1016 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 1023 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1017 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1024 ew32(TXDCTL1, ctrl);
1018 break; 1025 break;
1019 } 1026 }
1020 1027
1021 1028
1022 if (hw->mac_type == e1000_82573) { 1029 if (hw->mac_type == e1000_82573) {
1023 u32 gcr = E1000_READ_REG(hw, GCR); 1030 u32 gcr = er32(GCR);
1024 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1031 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1025 E1000_WRITE_REG(hw, GCR, gcr); 1032 ew32(GCR, gcr);
1026 } 1033 }
1027 1034
1028 /* Clear all of the statistics registers (clear on read). It is 1035 /* Clear all of the statistics registers (clear on read). It is
@@ -1039,11 +1046,11 @@ e1000_init_hw(struct e1000_hw *hw)
1039 1046
1040 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1047 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1041 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1048 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1042 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1049 ctrl_ext = er32(CTRL_EXT);
1043 /* Relaxed ordering must be disabled to avoid a parity 1050 /* Relaxed ordering must be disabled to avoid a parity
1044 * error crash in a PCI slot. */ 1051 * error crash in a PCI slot. */
1045 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1052 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1046 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1053 ew32(CTRL_EXT, ctrl_ext);
1047 } 1054 }
1048 1055
1049 return ret_val; 1056 return ret_val;
@@ -1054,8 +1061,7 @@ e1000_init_hw(struct e1000_hw *hw)
1054 * 1061 *
1055 * hw - Struct containing variables accessed by shared code. 1062 * hw - Struct containing variables accessed by shared code.
1056 *****************************************************************************/ 1063 *****************************************************************************/
1057static s32 1064static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1058e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1059{ 1065{
1060 u16 eeprom_data; 1066 u16 eeprom_data;
1061 s32 ret_val; 1067 s32 ret_val;
@@ -1100,8 +1106,7 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1100 * established. Assumes the hardware has previously been reset and the 1106 * established. Assumes the hardware has previously been reset and the
1101 * transmitter and receiver are not enabled. 1107 * transmitter and receiver are not enabled.
1102 *****************************************************************************/ 1108 *****************************************************************************/
1103s32 1109s32 e1000_setup_link(struct e1000_hw *hw)
1104e1000_setup_link(struct e1000_hw *hw)
1105{ 1110{
1106 u32 ctrl_ext; 1111 u32 ctrl_ext;
1107 s32 ret_val; 1112 s32 ret_val;
@@ -1176,7 +1181,7 @@ e1000_setup_link(struct e1000_hw *hw)
1176 } 1181 }
1177 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1182 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1178 SWDPIO__EXT_SHIFT); 1183 SWDPIO__EXT_SHIFT);
1179 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1184 ew32(CTRL_EXT, ctrl_ext);
1180 } 1185 }
1181 1186
1182 /* Call the necessary subroutine to configure the link. */ 1187 /* Call the necessary subroutine to configure the link. */
@@ -1193,12 +1198,12 @@ e1000_setup_link(struct e1000_hw *hw)
1193 1198
1194 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1199 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1195 if (hw->mac_type != e1000_ich8lan) { 1200 if (hw->mac_type != e1000_ich8lan) {
1196 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1201 ew32(FCT, FLOW_CONTROL_TYPE);
1197 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1202 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1198 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1203 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
1199 } 1204 }
1200 1205
1201 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1206 ew32(FCTTV, hw->fc_pause_time);
1202 1207
1203 /* Set the flow control receive threshold registers. Normally, 1208 /* Set the flow control receive threshold registers. Normally,
1204 * these registers will be set to a default threshold that may be 1209 * these registers will be set to a default threshold that may be
@@ -1207,18 +1212,18 @@ e1000_setup_link(struct e1000_hw *hw)
1207 * registers will be set to 0. 1212 * registers will be set to 0.
1208 */ 1213 */
1209 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1214 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1210 E1000_WRITE_REG(hw, FCRTL, 0); 1215 ew32(FCRTL, 0);
1211 E1000_WRITE_REG(hw, FCRTH, 0); 1216 ew32(FCRTH, 0);
1212 } else { 1217 } else {
1213 /* We need to set up the Receive Threshold high and low water marks 1218 /* We need to set up the Receive Threshold high and low water marks
1214 * as well as (optionally) enabling the transmission of XON frames. 1219 * as well as (optionally) enabling the transmission of XON frames.
1215 */ 1220 */
1216 if (hw->fc_send_xon) { 1221 if (hw->fc_send_xon) {
1217 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1222 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1218 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1223 ew32(FCRTH, hw->fc_high_water);
1219 } else { 1224 } else {
1220 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1225 ew32(FCRTL, hw->fc_low_water);
1221 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1226 ew32(FCRTH, hw->fc_high_water);
1222 } 1227 }
1223 } 1228 }
1224 return ret_val; 1229 return ret_val;
@@ -1233,8 +1238,7 @@ e1000_setup_link(struct e1000_hw *hw)
1233 * link. Assumes the hardware has been previously reset and the transmitter 1238 * link. Assumes the hardware has been previously reset and the transmitter
1234 * and receiver are not enabled. 1239 * and receiver are not enabled.
1235 *****************************************************************************/ 1240 *****************************************************************************/
1236static s32 1241static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1237e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1238{ 1242{
1239 u32 ctrl; 1243 u32 ctrl;
1240 u32 status; 1244 u32 status;
@@ -1251,7 +1255,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1251 * loopback mode is disabled during initialization. 1255 * loopback mode is disabled during initialization.
1252 */ 1256 */
1253 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) 1257 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1254 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1258 ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1255 1259
1256 /* On adapters with a MAC newer than 82544, SWDP 1 will be 1260 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1257 * set when the optics detect a signal. On older adapters, it will be 1261 * set when the optics detect a signal. On older adapters, it will be
@@ -1259,7 +1263,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1259 * If we're on serdes media, adjust the output amplitude to value 1263 * If we're on serdes media, adjust the output amplitude to value
1260 * set in the EEPROM. 1264 * set in the EEPROM.
1261 */ 1265 */
1262 ctrl = E1000_READ_REG(hw, CTRL); 1266 ctrl = er32(CTRL);
1263 if (hw->media_type == e1000_media_type_fiber) 1267 if (hw->media_type == e1000_media_type_fiber)
1264 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 1268 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1265 1269
@@ -1330,9 +1334,9 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1330 */ 1334 */
1331 DEBUGOUT("Auto-negotiation enabled\n"); 1335 DEBUGOUT("Auto-negotiation enabled\n");
1332 1336
1333 E1000_WRITE_REG(hw, TXCW, txcw); 1337 ew32(TXCW, txcw);
1334 E1000_WRITE_REG(hw, CTRL, ctrl); 1338 ew32(CTRL, ctrl);
1335 E1000_WRITE_FLUSH(hw); 1339 E1000_WRITE_FLUSH();
1336 1340
1337 hw->txcw = txcw; 1341 hw->txcw = txcw;
1338 msleep(1); 1342 msleep(1);
@@ -1344,11 +1348,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1344 * For internal serdes, we just assume a signal is present, then poll. 1348 * For internal serdes, we just assume a signal is present, then poll.
1345 */ 1349 */
1346 if (hw->media_type == e1000_media_type_internal_serdes || 1350 if (hw->media_type == e1000_media_type_internal_serdes ||
1347 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1351 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1348 DEBUGOUT("Looking for Link\n"); 1352 DEBUGOUT("Looking for Link\n");
1349 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1353 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1350 msleep(10); 1354 msleep(10);
1351 status = E1000_READ_REG(hw, STATUS); 1355 status = er32(STATUS);
1352 if (status & E1000_STATUS_LU) break; 1356 if (status & E1000_STATUS_LU) break;
1353 } 1357 }
1354 if (i == (LINK_UP_TIMEOUT / 10)) { 1358 if (i == (LINK_UP_TIMEOUT / 10)) {
@@ -1380,8 +1384,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1380* 1384*
1381* hw - Struct containing variables accessed by shared code 1385* hw - Struct containing variables accessed by shared code
1382******************************************************************************/ 1386******************************************************************************/
1383static s32 1387static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1384e1000_copper_link_preconfig(struct e1000_hw *hw)
1385{ 1388{
1386 u32 ctrl; 1389 u32 ctrl;
1387 s32 ret_val; 1390 s32 ret_val;
@@ -1389,7 +1392,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1389 1392
1390 DEBUGFUNC("e1000_copper_link_preconfig"); 1393 DEBUGFUNC("e1000_copper_link_preconfig");
1391 1394
1392 ctrl = E1000_READ_REG(hw, CTRL); 1395 ctrl = er32(CTRL);
1393 /* With 82543, we need to force speed and duplex on the MAC equal to what 1396 /* With 82543, we need to force speed and duplex on the MAC equal to what
1394 * the PHY speed and duplex configuration is. In addition, we need to 1397 * the PHY speed and duplex configuration is. In addition, we need to
1395 * perform a hardware reset on the PHY to take it out of reset. 1398 * perform a hardware reset on the PHY to take it out of reset.
@@ -1397,10 +1400,10 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1397 if (hw->mac_type > e1000_82543) { 1400 if (hw->mac_type > e1000_82543) {
1398 ctrl |= E1000_CTRL_SLU; 1401 ctrl |= E1000_CTRL_SLU;
1399 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1402 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1400 E1000_WRITE_REG(hw, CTRL, ctrl); 1403 ew32(CTRL, ctrl);
1401 } else { 1404 } else {
1402 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1405 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1403 E1000_WRITE_REG(hw, CTRL, ctrl); 1406 ew32(CTRL, ctrl);
1404 ret_val = e1000_phy_hw_reset(hw); 1407 ret_val = e1000_phy_hw_reset(hw);
1405 if (ret_val) 1408 if (ret_val)
1406 return ret_val; 1409 return ret_val;
@@ -1440,8 +1443,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1440* 1443*
1441* hw - Struct containing variables accessed by shared code 1444* hw - Struct containing variables accessed by shared code
1442*********************************************************************/ 1445*********************************************************************/
1443static s32 1446static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1444e1000_copper_link_igp_setup(struct e1000_hw *hw)
1445{ 1447{
1446 u32 led_ctrl; 1448 u32 led_ctrl;
1447 s32 ret_val; 1449 s32 ret_val;
@@ -1462,10 +1464,10 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1462 msleep(15); 1464 msleep(15);
1463 if (hw->mac_type != e1000_ich8lan) { 1465 if (hw->mac_type != e1000_ich8lan) {
1464 /* Configure activity LED after PHY reset */ 1466 /* Configure activity LED after PHY reset */
1465 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1467 led_ctrl = er32(LEDCTL);
1466 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1468 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1467 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1469 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1468 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1470 ew32(LEDCTL, led_ctrl);
1469 } 1471 }
1470 1472
1471 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1473 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
@@ -1587,8 +1589,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1587* 1589*
1588* hw - Struct containing variables accessed by shared code 1590* hw - Struct containing variables accessed by shared code
1589*********************************************************************/ 1591*********************************************************************/
1590static s32 1592static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1591e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1592{ 1593{
1593 s32 ret_val; 1594 s32 ret_val;
1594 u16 phy_data; 1595 u16 phy_data;
@@ -1679,9 +1680,9 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1679 if (ret_val) 1680 if (ret_val)
1680 return ret_val; 1681 return ret_val;
1681 1682
1682 reg_data = E1000_READ_REG(hw, CTRL_EXT); 1683 reg_data = er32(CTRL_EXT);
1683 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1684 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1684 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 1685 ew32(CTRL_EXT, reg_data);
1685 1686
1686 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1687 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1687 &phy_data); 1688 &phy_data);
@@ -1735,8 +1736,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1735* 1736*
1736* hw - Struct containing variables accessed by shared code 1737* hw - Struct containing variables accessed by shared code
1737*********************************************************************/ 1738*********************************************************************/
1738static s32 1739static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1739e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1740{ 1740{
1741 s32 ret_val; 1741 s32 ret_val;
1742 u16 phy_data; 1742 u16 phy_data;
@@ -1839,8 +1839,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1839* 1839*
1840* hw - Struct containing variables accessed by shared code 1840* hw - Struct containing variables accessed by shared code
1841*********************************************************************/ 1841*********************************************************************/
1842static s32 1842static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1843e1000_copper_link_autoneg(struct e1000_hw *hw)
1844{ 1843{
1845 s32 ret_val; 1844 s32 ret_val;
1846 u16 phy_data; 1845 u16 phy_data;
@@ -1910,8 +1909,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1910* 1909*
1911* hw - Struct containing variables accessed by shared code 1910* hw - Struct containing variables accessed by shared code
1912******************************************************************************/ 1911******************************************************************************/
1913static s32 1912static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1914e1000_copper_link_postconfig(struct e1000_hw *hw)
1915{ 1913{
1916 s32 ret_val; 1914 s32 ret_val;
1917 DEBUGFUNC("e1000_copper_link_postconfig"); 1915 DEBUGFUNC("e1000_copper_link_postconfig");
@@ -1948,8 +1946,7 @@ e1000_copper_link_postconfig(struct e1000_hw *hw)
1948* 1946*
1949* hw - Struct containing variables accessed by shared code 1947* hw - Struct containing variables accessed by shared code
1950******************************************************************************/ 1948******************************************************************************/
1951static s32 1949static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1952e1000_setup_copper_link(struct e1000_hw *hw)
1953{ 1950{
1954 s32 ret_val; 1951 s32 ret_val;
1955 u16 i; 1952 u16 i;
@@ -2062,8 +2059,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
2062* 2059*
2063* hw - Struct containing variables accessed by shared code 2060* hw - Struct containing variables accessed by shared code
2064******************************************************************************/ 2061******************************************************************************/
2065static s32 2062static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2066e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2067{ 2063{
2068 s32 ret_val = E1000_SUCCESS; 2064 s32 ret_val = E1000_SUCCESS;
2069 u32 tipg; 2065 u32 tipg;
@@ -2078,10 +2074,10 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2078 return ret_val; 2074 return ret_val;
2079 2075
2080 /* Configure Transmit Inter-Packet Gap */ 2076 /* Configure Transmit Inter-Packet Gap */
2081 tipg = E1000_READ_REG(hw, TIPG); 2077 tipg = er32(TIPG);
2082 tipg &= ~E1000_TIPG_IPGT_MASK; 2078 tipg &= ~E1000_TIPG_IPGT_MASK;
2083 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2079 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2084 E1000_WRITE_REG(hw, TIPG, tipg); 2080 ew32(TIPG, tipg);
2085 2081
2086 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); 2082 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2087 2083
@@ -2098,8 +2094,7 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2098 return ret_val; 2094 return ret_val;
2099} 2095}
2100 2096
2101static s32 2097static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2102e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2103{ 2098{
2104 s32 ret_val = E1000_SUCCESS; 2099 s32 ret_val = E1000_SUCCESS;
2105 u16 reg_data; 2100 u16 reg_data;
@@ -2114,10 +2109,10 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2114 return ret_val; 2109 return ret_val;
2115 2110
2116 /* Configure Transmit Inter-Packet Gap */ 2111 /* Configure Transmit Inter-Packet Gap */
2117 tipg = E1000_READ_REG(hw, TIPG); 2112 tipg = er32(TIPG);
2118 tipg &= ~E1000_TIPG_IPGT_MASK; 2113 tipg &= ~E1000_TIPG_IPGT_MASK;
2119 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2114 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2120 E1000_WRITE_REG(hw, TIPG, tipg); 2115 ew32(TIPG, tipg);
2121 2116
2122 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); 2117 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2123 2118
@@ -2135,8 +2130,7 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2135* 2130*
2136* hw - Struct containing variables accessed by shared code 2131* hw - Struct containing variables accessed by shared code
2137******************************************************************************/ 2132******************************************************************************/
2138s32 2133s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2139e1000_phy_setup_autoneg(struct e1000_hw *hw)
2140{ 2134{
2141 s32 ret_val; 2135 s32 ret_val;
2142 u16 mii_autoneg_adv_reg; 2136 u16 mii_autoneg_adv_reg;
@@ -2284,8 +2278,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2284* 2278*
2285* hw - Struct containing variables accessed by shared code 2279* hw - Struct containing variables accessed by shared code
2286******************************************************************************/ 2280******************************************************************************/
2287static s32 2281static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2288e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2289{ 2282{
2290 u32 ctrl; 2283 u32 ctrl;
2291 s32 ret_val; 2284 s32 ret_val;
@@ -2302,7 +2295,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2302 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2295 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2303 2296
2304 /* Read the Device Control Register. */ 2297 /* Read the Device Control Register. */
2305 ctrl = E1000_READ_REG(hw, CTRL); 2298 ctrl = er32(CTRL);
2306 2299
2307 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2300 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2308 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2301 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
@@ -2357,7 +2350,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2357 e1000_config_collision_dist(hw); 2350 e1000_config_collision_dist(hw);
2358 2351
2359 /* Write the configured values back to the Device Control Reg. */ 2352 /* Write the configured values back to the Device Control Reg. */
2360 E1000_WRITE_REG(hw, CTRL, ctrl); 2353 ew32(CTRL, ctrl);
2361 2354
2362 if ((hw->phy_type == e1000_phy_m88) || 2355 if ((hw->phy_type == e1000_phy_m88) ||
2363 (hw->phy_type == e1000_phy_gg82563)) { 2356 (hw->phy_type == e1000_phy_gg82563)) {
@@ -2535,8 +2528,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2535* Link should have been established previously. Reads the speed and duplex 2528* Link should have been established previously. Reads the speed and duplex
2536* information from the Device Status register. 2529* information from the Device Status register.
2537******************************************************************************/ 2530******************************************************************************/
2538void 2531void e1000_config_collision_dist(struct e1000_hw *hw)
2539e1000_config_collision_dist(struct e1000_hw *hw)
2540{ 2532{
2541 u32 tctl, coll_dist; 2533 u32 tctl, coll_dist;
2542 2534
@@ -2547,13 +2539,13 @@ e1000_config_collision_dist(struct e1000_hw *hw)
2547 else 2539 else
2548 coll_dist = E1000_COLLISION_DISTANCE; 2540 coll_dist = E1000_COLLISION_DISTANCE;
2549 2541
2550 tctl = E1000_READ_REG(hw, TCTL); 2542 tctl = er32(TCTL);
2551 2543
2552 tctl &= ~E1000_TCTL_COLD; 2544 tctl &= ~E1000_TCTL_COLD;
2553 tctl |= coll_dist << E1000_COLD_SHIFT; 2545 tctl |= coll_dist << E1000_COLD_SHIFT;
2554 2546
2555 E1000_WRITE_REG(hw, TCTL, tctl); 2547 ew32(TCTL, tctl);
2556 E1000_WRITE_FLUSH(hw); 2548 E1000_WRITE_FLUSH();
2557} 2549}
2558 2550
2559/****************************************************************************** 2551/******************************************************************************
@@ -2565,8 +2557,7 @@ e1000_config_collision_dist(struct e1000_hw *hw)
2565* The contents of the PHY register containing the needed information need to 2557* The contents of the PHY register containing the needed information need to
2566* be passed in. 2558* be passed in.
2567******************************************************************************/ 2559******************************************************************************/
2568static s32 2560static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
2569e1000_config_mac_to_phy(struct e1000_hw *hw)
2570{ 2561{
2571 u32 ctrl; 2562 u32 ctrl;
2572 s32 ret_val; 2563 s32 ret_val;
@@ -2582,7 +2573,7 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2582 /* Read the Device Control Register and set the bits to Force Speed 2573 /* Read the Device Control Register and set the bits to Force Speed
2583 * and Duplex. 2574 * and Duplex.
2584 */ 2575 */
2585 ctrl = E1000_READ_REG(hw, CTRL); 2576 ctrl = er32(CTRL);
2586 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2577 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2587 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 2578 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2588 2579
@@ -2609,7 +2600,7 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2609 ctrl |= E1000_CTRL_SPD_100; 2600 ctrl |= E1000_CTRL_SPD_100;
2610 2601
2611 /* Write the configured values back to the Device Control Reg. */ 2602 /* Write the configured values back to the Device Control Reg. */
2612 E1000_WRITE_REG(hw, CTRL, ctrl); 2603 ew32(CTRL, ctrl);
2613 return E1000_SUCCESS; 2604 return E1000_SUCCESS;
2614} 2605}
2615 2606
@@ -2624,15 +2615,14 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2624 * by the PHY rather than the MAC. Software must also configure these 2615 * by the PHY rather than the MAC. Software must also configure these
2625 * bits when link is forced on a fiber connection. 2616 * bits when link is forced on a fiber connection.
2626 *****************************************************************************/ 2617 *****************************************************************************/
2627s32 2618s32 e1000_force_mac_fc(struct e1000_hw *hw)
2628e1000_force_mac_fc(struct e1000_hw *hw)
2629{ 2619{
2630 u32 ctrl; 2620 u32 ctrl;
2631 2621
2632 DEBUGFUNC("e1000_force_mac_fc"); 2622 DEBUGFUNC("e1000_force_mac_fc");
2633 2623
2634 /* Get the current configuration of the Device Control Register */ 2624 /* Get the current configuration of the Device Control Register */
2635 ctrl = E1000_READ_REG(hw, CTRL); 2625 ctrl = er32(CTRL);
2636 2626
2637 /* Because we didn't get link via the internal auto-negotiation 2627 /* Because we didn't get link via the internal auto-negotiation
2638 * mechanism (we either forced link or we got link via PHY 2628 * mechanism (we either forced link or we got link via PHY
@@ -2676,7 +2666,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2676 if (hw->mac_type == e1000_82542_rev2_0) 2666 if (hw->mac_type == e1000_82542_rev2_0)
2677 ctrl &= (~E1000_CTRL_TFCE); 2667 ctrl &= (~E1000_CTRL_TFCE);
2678 2668
2679 E1000_WRITE_REG(hw, CTRL, ctrl); 2669 ew32(CTRL, ctrl);
2680 return E1000_SUCCESS; 2670 return E1000_SUCCESS;
2681} 2671}
2682 2672
@@ -2691,8 +2681,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2691 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2681 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2692 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 2682 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2693 *****************************************************************************/ 2683 *****************************************************************************/
2694static s32 2684static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2695e1000_config_fc_after_link_up(struct e1000_hw *hw)
2696{ 2685{
2697 s32 ret_val; 2686 s32 ret_val;
2698 u16 mii_status_reg; 2687 u16 mii_status_reg;
@@ -2896,8 +2885,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2896 * 2885 *
2897 * Called by any function that needs to check the link status of the adapter. 2886 * Called by any function that needs to check the link status of the adapter.
2898 *****************************************************************************/ 2887 *****************************************************************************/
2899s32 2888s32 e1000_check_for_link(struct e1000_hw *hw)
2900e1000_check_for_link(struct e1000_hw *hw)
2901{ 2889{
2902 u32 rxcw = 0; 2890 u32 rxcw = 0;
2903 u32 ctrl; 2891 u32 ctrl;
@@ -2910,8 +2898,8 @@ e1000_check_for_link(struct e1000_hw *hw)
2910 2898
2911 DEBUGFUNC("e1000_check_for_link"); 2899 DEBUGFUNC("e1000_check_for_link");
2912 2900
2913 ctrl = E1000_READ_REG(hw, CTRL); 2901 ctrl = er32(CTRL);
2914 status = E1000_READ_REG(hw, STATUS); 2902 status = er32(STATUS);
2915 2903
2916 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 2904 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2917 * set when the optics detect a signal. On older adapters, it will be 2905 * set when the optics detect a signal. On older adapters, it will be
@@ -2919,7 +2907,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2919 */ 2907 */
2920 if ((hw->media_type == e1000_media_type_fiber) || 2908 if ((hw->media_type == e1000_media_type_fiber) ||
2921 (hw->media_type == e1000_media_type_internal_serdes)) { 2909 (hw->media_type == e1000_media_type_internal_serdes)) {
2922 rxcw = E1000_READ_REG(hw, RXCW); 2910 rxcw = er32(RXCW);
2923 2911
2924 if (hw->media_type == e1000_media_type_fiber) { 2912 if (hw->media_type == e1000_media_type_fiber) {
2925 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2913 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
@@ -2965,11 +2953,11 @@ e1000_check_for_link(struct e1000_hw *hw)
2965 (!hw->autoneg) && 2953 (!hw->autoneg) &&
2966 (hw->forced_speed_duplex == e1000_10_full || 2954 (hw->forced_speed_duplex == e1000_10_full ||
2967 hw->forced_speed_duplex == e1000_10_half)) { 2955 hw->forced_speed_duplex == e1000_10_half)) {
2968 E1000_WRITE_REG(hw, IMC, 0xffffffff); 2956 ew32(IMC, 0xffffffff);
2969 ret_val = e1000_polarity_reversal_workaround(hw); 2957 ret_val = e1000_polarity_reversal_workaround(hw);
2970 icr = E1000_READ_REG(hw, ICR); 2958 icr = er32(ICR);
2971 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); 2959 ew32(ICS, (icr & ~E1000_ICS_LSC));
2972 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 2960 ew32(IMS, IMS_ENABLE_MASK);
2973 } 2961 }
2974 2962
2975 } else { 2963 } else {
@@ -3034,9 +3022,9 @@ e1000_check_for_link(struct e1000_hw *hw)
3034 */ 3022 */
3035 if (hw->tbi_compatibility_on) { 3023 if (hw->tbi_compatibility_on) {
3036 /* If we previously were in the mode, turn it off. */ 3024 /* If we previously were in the mode, turn it off. */
3037 rctl = E1000_READ_REG(hw, RCTL); 3025 rctl = er32(RCTL);
3038 rctl &= ~E1000_RCTL_SBP; 3026 rctl &= ~E1000_RCTL_SBP;
3039 E1000_WRITE_REG(hw, RCTL, rctl); 3027 ew32(RCTL, rctl);
3040 hw->tbi_compatibility_on = false; 3028 hw->tbi_compatibility_on = false;
3041 } 3029 }
3042 } else { 3030 } else {
@@ -3047,9 +3035,9 @@ e1000_check_for_link(struct e1000_hw *hw)
3047 */ 3035 */
3048 if (!hw->tbi_compatibility_on) { 3036 if (!hw->tbi_compatibility_on) {
3049 hw->tbi_compatibility_on = true; 3037 hw->tbi_compatibility_on = true;
3050 rctl = E1000_READ_REG(hw, RCTL); 3038 rctl = er32(RCTL);
3051 rctl |= E1000_RCTL_SBP; 3039 rctl |= E1000_RCTL_SBP;
3052 E1000_WRITE_REG(hw, RCTL, rctl); 3040 ew32(RCTL, rctl);
3053 } 3041 }
3054 } 3042 }
3055 } 3043 }
@@ -3073,12 +3061,12 @@ e1000_check_for_link(struct e1000_hw *hw)
3073 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3061 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3074 3062
3075 /* Disable auto-negotiation in the TXCW register */ 3063 /* Disable auto-negotiation in the TXCW register */
3076 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3064 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3077 3065
3078 /* Force link-up and also force full-duplex. */ 3066 /* Force link-up and also force full-duplex. */
3079 ctrl = E1000_READ_REG(hw, CTRL); 3067 ctrl = er32(CTRL);
3080 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3068 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3081 E1000_WRITE_REG(hw, CTRL, ctrl); 3069 ew32(CTRL, ctrl);
3082 3070
3083 /* Configure Flow Control after forcing link up. */ 3071 /* Configure Flow Control after forcing link up. */
3084 ret_val = e1000_config_fc_after_link_up(hw); 3072 ret_val = e1000_config_fc_after_link_up(hw);
@@ -3096,8 +3084,8 @@ e1000_check_for_link(struct e1000_hw *hw)
3096 (hw->media_type == e1000_media_type_internal_serdes)) && 3084 (hw->media_type == e1000_media_type_internal_serdes)) &&
3097 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3085 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3098 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3086 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3099 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3087 ew32(TXCW, hw->txcw);
3100 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3088 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
3101 3089
3102 hw->serdes_link_down = false; 3090 hw->serdes_link_down = false;
3103 } 3091 }
@@ -3105,10 +3093,10 @@ e1000_check_for_link(struct e1000_hw *hw)
3105 * based on MAC synchronization for internal serdes media type. 3093 * based on MAC synchronization for internal serdes media type.
3106 */ 3094 */
3107 else if ((hw->media_type == e1000_media_type_internal_serdes) && 3095 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3108 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3096 !(E1000_TXCW_ANE & er32(TXCW))) {
3109 /* SYNCH bit and IV bit are sticky. */ 3097 /* SYNCH bit and IV bit are sticky. */
3110 udelay(10); 3098 udelay(10);
3111 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3099 if (E1000_RXCW_SYNCH & er32(RXCW)) {
3112 if (!(rxcw & E1000_RXCW_IV)) { 3100 if (!(rxcw & E1000_RXCW_IV)) {
3113 hw->serdes_link_down = false; 3101 hw->serdes_link_down = false;
3114 DEBUGOUT("SERDES: Link is up.\n"); 3102 DEBUGOUT("SERDES: Link is up.\n");
@@ -3119,8 +3107,8 @@ e1000_check_for_link(struct e1000_hw *hw)
3119 } 3107 }
3120 } 3108 }
3121 if ((hw->media_type == e1000_media_type_internal_serdes) && 3109 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3122 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3110 (E1000_TXCW_ANE & er32(TXCW))) {
3123 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); 3111 hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
3124 } 3112 }
3125 return E1000_SUCCESS; 3113 return E1000_SUCCESS;
3126} 3114}
@@ -3132,10 +3120,7 @@ e1000_check_for_link(struct e1000_hw *hw)
3132 * speed - Speed of the connection 3120 * speed - Speed of the connection
3133 * duplex - Duplex setting of the connection 3121 * duplex - Duplex setting of the connection
3134 *****************************************************************************/ 3122 *****************************************************************************/
3135s32 3123s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
3136e1000_get_speed_and_duplex(struct e1000_hw *hw,
3137 u16 *speed,
3138 u16 *duplex)
3139{ 3124{
3140 u32 status; 3125 u32 status;
3141 s32 ret_val; 3126 s32 ret_val;
@@ -3144,7 +3129,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3144 DEBUGFUNC("e1000_get_speed_and_duplex"); 3129 DEBUGFUNC("e1000_get_speed_and_duplex");
3145 3130
3146 if (hw->mac_type >= e1000_82543) { 3131 if (hw->mac_type >= e1000_82543) {
3147 status = E1000_READ_REG(hw, STATUS); 3132 status = er32(STATUS);
3148 if (status & E1000_STATUS_SPEED_1000) { 3133 if (status & E1000_STATUS_SPEED_1000) {
3149 *speed = SPEED_1000; 3134 *speed = SPEED_1000;
3150 DEBUGOUT("1000 Mbs, "); 3135 DEBUGOUT("1000 Mbs, ");
@@ -3214,8 +3199,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3214* 3199*
3215* hw - Struct containing variables accessed by shared code 3200* hw - Struct containing variables accessed by shared code
3216******************************************************************************/ 3201******************************************************************************/
3217static s32 3202static s32 e1000_wait_autoneg(struct e1000_hw *hw)
3218e1000_wait_autoneg(struct e1000_hw *hw)
3219{ 3203{
3220 s32 ret_val; 3204 s32 ret_val;
3221 u16 i; 3205 u16 i;
@@ -3249,15 +3233,13 @@ e1000_wait_autoneg(struct e1000_hw *hw)
3249* hw - Struct containing variables accessed by shared code 3233* hw - Struct containing variables accessed by shared code
3250* ctrl - Device control register's current value 3234* ctrl - Device control register's current value
3251******************************************************************************/ 3235******************************************************************************/
3252static void 3236static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3253e1000_raise_mdi_clk(struct e1000_hw *hw,
3254 u32 *ctrl)
3255{ 3237{
3256 /* Raise the clock input to the Management Data Clock (by setting the MDC 3238 /* Raise the clock input to the Management Data Clock (by setting the MDC
3257 * bit), and then delay 10 microseconds. 3239 * bit), and then delay 10 microseconds.
3258 */ 3240 */
3259 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3241 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
3260 E1000_WRITE_FLUSH(hw); 3242 E1000_WRITE_FLUSH();
3261 udelay(10); 3243 udelay(10);
3262} 3244}
3263 3245
@@ -3267,15 +3249,13 @@ e1000_raise_mdi_clk(struct e1000_hw *hw,
3267* hw - Struct containing variables accessed by shared code 3249* hw - Struct containing variables accessed by shared code
3268* ctrl - Device control register's current value 3250* ctrl - Device control register's current value
3269******************************************************************************/ 3251******************************************************************************/
3270static void 3252static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3271e1000_lower_mdi_clk(struct e1000_hw *hw,
3272 u32 *ctrl)
3273{ 3253{
3274 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3254 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3275 * bit), and then delay 10 microseconds. 3255 * bit), and then delay 10 microseconds.
3276 */ 3256 */
3277 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3257 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
3278 E1000_WRITE_FLUSH(hw); 3258 E1000_WRITE_FLUSH();
3279 udelay(10); 3259 udelay(10);
3280} 3260}
3281 3261
@@ -3288,10 +3268,7 @@ e1000_lower_mdi_clk(struct e1000_hw *hw,
3288* 3268*
3289* Bits are shifted out in MSB to LSB order. 3269* Bits are shifted out in MSB to LSB order.
3290******************************************************************************/ 3270******************************************************************************/
3291static void 3271static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
3292e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3293 u32 data,
3294 u16 count)
3295{ 3272{
3296 u32 ctrl; 3273 u32 ctrl;
3297 u32 mask; 3274 u32 mask;
@@ -3303,7 +3280,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3303 mask = 0x01; 3280 mask = 0x01;
3304 mask <<= (count - 1); 3281 mask <<= (count - 1);
3305 3282
3306 ctrl = E1000_READ_REG(hw, CTRL); 3283 ctrl = er32(CTRL);
3307 3284
3308 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3285 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3309 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3286 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
@@ -3319,8 +3296,8 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3319 else 3296 else
3320 ctrl &= ~E1000_CTRL_MDIO; 3297 ctrl &= ~E1000_CTRL_MDIO;
3321 3298
3322 E1000_WRITE_REG(hw, CTRL, ctrl); 3299 ew32(CTRL, ctrl);
3323 E1000_WRITE_FLUSH(hw); 3300 E1000_WRITE_FLUSH();
3324 3301
3325 udelay(10); 3302 udelay(10);
3326 3303
@@ -3338,8 +3315,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3338* 3315*
3339* Bits are shifted in in MSB to LSB order. 3316* Bits are shifted in in MSB to LSB order.
3340******************************************************************************/ 3317******************************************************************************/
3341static u16 3318static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3342e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3343{ 3319{
3344 u32 ctrl; 3320 u32 ctrl;
3345 u16 data = 0; 3321 u16 data = 0;
@@ -3352,14 +3328,14 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3352 * by raising the input to the Management Data Clock (setting the MDC bit), 3328 * by raising the input to the Management Data Clock (setting the MDC bit),
3353 * and then reading the value of the MDIO bit. 3329 * and then reading the value of the MDIO bit.
3354 */ 3330 */
3355 ctrl = E1000_READ_REG(hw, CTRL); 3331 ctrl = er32(CTRL);
3356 3332
3357 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 3333 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3358 ctrl &= ~E1000_CTRL_MDIO_DIR; 3334 ctrl &= ~E1000_CTRL_MDIO_DIR;
3359 ctrl &= ~E1000_CTRL_MDIO; 3335 ctrl &= ~E1000_CTRL_MDIO;
3360 3336
3361 E1000_WRITE_REG(hw, CTRL, ctrl); 3337 ew32(CTRL, ctrl);
3362 E1000_WRITE_FLUSH(hw); 3338 E1000_WRITE_FLUSH();
3363 3339
3364 /* Raise and Lower the clock before reading in the data. This accounts for 3340 /* Raise and Lower the clock before reading in the data. This accounts for
3365 * the turnaround bits. The first clock occurred when we clocked out the 3341 * the turnaround bits. The first clock occurred when we clocked out the
@@ -3371,7 +3347,7 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3371 for (data = 0, i = 0; i < 16; i++) { 3347 for (data = 0, i = 0; i < 16; i++) {
3372 data = data << 1; 3348 data = data << 1;
3373 e1000_raise_mdi_clk(hw, &ctrl); 3349 e1000_raise_mdi_clk(hw, &ctrl);
3374 ctrl = E1000_READ_REG(hw, CTRL); 3350 ctrl = er32(CTRL);
3375 /* Check to see if we shifted in a "1". */ 3351 /* Check to see if we shifted in a "1". */
3376 if (ctrl & E1000_CTRL_MDIO) 3352 if (ctrl & E1000_CTRL_MDIO)
3377 data |= 1; 3353 data |= 1;
@@ -3384,8 +3360,7 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3384 return data; 3360 return data;
3385} 3361}
3386 3362
3387static s32 3363static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3388e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3389{ 3364{
3390 u32 swfw_sync = 0; 3365 u32 swfw_sync = 0;
3391 u32 swmask = mask; 3366 u32 swmask = mask;
@@ -3404,7 +3379,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3404 if (e1000_get_hw_eeprom_semaphore(hw)) 3379 if (e1000_get_hw_eeprom_semaphore(hw))
3405 return -E1000_ERR_SWFW_SYNC; 3380 return -E1000_ERR_SWFW_SYNC;
3406 3381
3407 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3382 swfw_sync = er32(SW_FW_SYNC);
3408 if (!(swfw_sync & (fwmask | swmask))) { 3383 if (!(swfw_sync & (fwmask | swmask))) {
3409 break; 3384 break;
3410 } 3385 }
@@ -3422,14 +3397,13 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3422 } 3397 }
3423 3398
3424 swfw_sync |= swmask; 3399 swfw_sync |= swmask;
3425 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3400 ew32(SW_FW_SYNC, swfw_sync);
3426 3401
3427 e1000_put_hw_eeprom_semaphore(hw); 3402 e1000_put_hw_eeprom_semaphore(hw);
3428 return E1000_SUCCESS; 3403 return E1000_SUCCESS;
3429} 3404}
3430 3405
3431static void 3406static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3432e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3433{ 3407{
3434 u32 swfw_sync; 3408 u32 swfw_sync;
3435 u32 swmask = mask; 3409 u32 swmask = mask;
@@ -3451,9 +3425,9 @@ e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3451 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 3425 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3452 /* empty */ 3426 /* empty */
3453 3427
3454 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3428 swfw_sync = er32(SW_FW_SYNC);
3455 swfw_sync &= ~swmask; 3429 swfw_sync &= ~swmask;
3456 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3430 ew32(SW_FW_SYNC, swfw_sync);
3457 3431
3458 e1000_put_hw_eeprom_semaphore(hw); 3432 e1000_put_hw_eeprom_semaphore(hw);
3459} 3433}
@@ -3464,10 +3438,7 @@ e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3464* hw - Struct containing variables accessed by shared code 3438* hw - Struct containing variables accessed by shared code
3465* reg_addr - address of the PHY register to read 3439* reg_addr - address of the PHY register to read
3466******************************************************************************/ 3440******************************************************************************/
3467s32 3441s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
3468e1000_read_phy_reg(struct e1000_hw *hw,
3469 u32 reg_addr,
3470 u16 *phy_data)
3471{ 3442{
3472 u32 ret_val; 3443 u32 ret_val;
3473 u16 swfw; 3444 u16 swfw;
@@ -3475,7 +3446,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3475 DEBUGFUNC("e1000_read_phy_reg"); 3446 DEBUGFUNC("e1000_read_phy_reg");
3476 3447
3477 if ((hw->mac_type == e1000_80003es2lan) && 3448 if ((hw->mac_type == e1000_80003es2lan) &&
3478 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3449 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3479 swfw = E1000_SWFW_PHY1_SM; 3450 swfw = E1000_SWFW_PHY1_SM;
3480 } else { 3451 } else {
3481 swfw = E1000_SWFW_PHY0_SM; 3452 swfw = E1000_SWFW_PHY0_SM;
@@ -3523,9 +3494,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3523 return ret_val; 3494 return ret_val;
3524} 3495}
3525 3496
3526static s32 3497static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3527e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 3498 u16 *phy_data)
3528 u16 *phy_data)
3529{ 3499{
3530 u32 i; 3500 u32 i;
3531 u32 mdic = 0; 3501 u32 mdic = 0;
@@ -3547,12 +3517,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3547 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3517 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3548 (E1000_MDIC_OP_READ)); 3518 (E1000_MDIC_OP_READ));
3549 3519
3550 E1000_WRITE_REG(hw, MDIC, mdic); 3520 ew32(MDIC, mdic);
3551 3521
3552 /* Poll the ready bit to see if the MDI read completed */ 3522 /* Poll the ready bit to see if the MDI read completed */
3553 for (i = 0; i < 64; i++) { 3523 for (i = 0; i < 64; i++) {
3554 udelay(50); 3524 udelay(50);
3555 mdic = E1000_READ_REG(hw, MDIC); 3525 mdic = er32(MDIC);
3556 if (mdic & E1000_MDIC_READY) break; 3526 if (mdic & E1000_MDIC_READY) break;
3557 } 3527 }
3558 if (!(mdic & E1000_MDIC_READY)) { 3528 if (!(mdic & E1000_MDIC_READY)) {
@@ -3563,7 +3533,7 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3563 DEBUGOUT("MDI Error\n"); 3533 DEBUGOUT("MDI Error\n");
3564 return -E1000_ERR_PHY; 3534 return -E1000_ERR_PHY;
3565 } 3535 }
3566 *phy_data = (u16) mdic; 3536 *phy_data = (u16)mdic;
3567 } else { 3537 } else {
3568 /* We must first send a preamble through the MDIO pin to signal the 3538 /* We must first send a preamble through the MDIO pin to signal the
3569 * beginning of an MII instruction. This is done by sending 32 3539 * beginning of an MII instruction. This is done by sending 32
@@ -3603,9 +3573,7 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3603* reg_addr - address of the PHY register to write 3573* reg_addr - address of the PHY register to write
3604* data - data to write to the PHY 3574* data - data to write to the PHY
3605******************************************************************************/ 3575******************************************************************************/
3606s32 3576s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
3607e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr,
3608 u16 phy_data)
3609{ 3577{
3610 u32 ret_val; 3578 u32 ret_val;
3611 u16 swfw; 3579 u16 swfw;
@@ -3613,7 +3581,7 @@ e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr,
3613 DEBUGFUNC("e1000_write_phy_reg"); 3581 DEBUGFUNC("e1000_write_phy_reg");
3614 3582
3615 if ((hw->mac_type == e1000_80003es2lan) && 3583 if ((hw->mac_type == e1000_80003es2lan) &&
3616 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3584 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3617 swfw = E1000_SWFW_PHY1_SM; 3585 swfw = E1000_SWFW_PHY1_SM;
3618 } else { 3586 } else {
3619 swfw = E1000_SWFW_PHY0_SM; 3587 swfw = E1000_SWFW_PHY0_SM;
@@ -3661,9 +3629,8 @@ e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr,
3661 return ret_val; 3629 return ret_val;
3662} 3630}
3663 3631
3664static s32 3632static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3665e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 3633 u16 phy_data)
3666 u16 phy_data)
3667{ 3634{
3668 u32 i; 3635 u32 i;
3669 u32 mdic = 0; 3636 u32 mdic = 0;
@@ -3681,17 +3648,17 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3681 * for the PHY register in the MDI Control register. The MAC will take 3648 * for the PHY register in the MDI Control register. The MAC will take
3682 * care of interfacing with the PHY to send the desired data. 3649 * care of interfacing with the PHY to send the desired data.
3683 */ 3650 */
3684 mdic = (((u32) phy_data) | 3651 mdic = (((u32)phy_data) |
3685 (reg_addr << E1000_MDIC_REG_SHIFT) | 3652 (reg_addr << E1000_MDIC_REG_SHIFT) |
3686 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3653 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3687 (E1000_MDIC_OP_WRITE)); 3654 (E1000_MDIC_OP_WRITE));
3688 3655
3689 E1000_WRITE_REG(hw, MDIC, mdic); 3656 ew32(MDIC, mdic);
3690 3657
3691 /* Poll the ready bit to see if the MDI read completed */ 3658 /* Poll the ready bit to see if the MDI read completed */
3692 for (i = 0; i < 641; i++) { 3659 for (i = 0; i < 641; i++) {
3693 udelay(5); 3660 udelay(5);
3694 mdic = E1000_READ_REG(hw, MDIC); 3661 mdic = er32(MDIC);
3695 if (mdic & E1000_MDIC_READY) break; 3662 if (mdic & E1000_MDIC_READY) break;
3696 } 3663 }
3697 if (!(mdic & E1000_MDIC_READY)) { 3664 if (!(mdic & E1000_MDIC_READY)) {
@@ -3715,7 +3682,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3715 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3682 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3716 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3683 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3717 mdic <<= 16; 3684 mdic <<= 16;
3718 mdic |= (u32) phy_data; 3685 mdic |= (u32)phy_data;
3719 3686
3720 e1000_shift_out_mdi_bits(hw, mdic, 32); 3687 e1000_shift_out_mdi_bits(hw, mdic, 32);
3721 } 3688 }
@@ -3723,17 +3690,14 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3723 return E1000_SUCCESS; 3690 return E1000_SUCCESS;
3724} 3691}
3725 3692
3726static s32 3693static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
3727e1000_read_kmrn_reg(struct e1000_hw *hw,
3728 u32 reg_addr,
3729 u16 *data)
3730{ 3694{
3731 u32 reg_val; 3695 u32 reg_val;
3732 u16 swfw; 3696 u16 swfw;
3733 DEBUGFUNC("e1000_read_kmrn_reg"); 3697 DEBUGFUNC("e1000_read_kmrn_reg");
3734 3698
3735 if ((hw->mac_type == e1000_80003es2lan) && 3699 if ((hw->mac_type == e1000_80003es2lan) &&
3736 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3700 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3737 swfw = E1000_SWFW_PHY1_SM; 3701 swfw = E1000_SWFW_PHY1_SM;
3738 } else { 3702 } else {
3739 swfw = E1000_SWFW_PHY0_SM; 3703 swfw = E1000_SWFW_PHY0_SM;
@@ -3745,28 +3709,25 @@ e1000_read_kmrn_reg(struct e1000_hw *hw,
3745 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3709 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3746 E1000_KUMCTRLSTA_OFFSET) | 3710 E1000_KUMCTRLSTA_OFFSET) |
3747 E1000_KUMCTRLSTA_REN; 3711 E1000_KUMCTRLSTA_REN;
3748 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3712 ew32(KUMCTRLSTA, reg_val);
3749 udelay(2); 3713 udelay(2);
3750 3714
3751 /* Read the data returned */ 3715 /* Read the data returned */
3752 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 3716 reg_val = er32(KUMCTRLSTA);
3753 *data = (u16)reg_val; 3717 *data = (u16)reg_val;
3754 3718
3755 e1000_swfw_sync_release(hw, swfw); 3719 e1000_swfw_sync_release(hw, swfw);
3756 return E1000_SUCCESS; 3720 return E1000_SUCCESS;
3757} 3721}
3758 3722
3759static s32 3723static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
3760e1000_write_kmrn_reg(struct e1000_hw *hw,
3761 u32 reg_addr,
3762 u16 data)
3763{ 3724{
3764 u32 reg_val; 3725 u32 reg_val;
3765 u16 swfw; 3726 u16 swfw;
3766 DEBUGFUNC("e1000_write_kmrn_reg"); 3727 DEBUGFUNC("e1000_write_kmrn_reg");
3767 3728
3768 if ((hw->mac_type == e1000_80003es2lan) && 3729 if ((hw->mac_type == e1000_80003es2lan) &&
3769 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3730 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3770 swfw = E1000_SWFW_PHY1_SM; 3731 swfw = E1000_SWFW_PHY1_SM;
3771 } else { 3732 } else {
3772 swfw = E1000_SWFW_PHY0_SM; 3733 swfw = E1000_SWFW_PHY0_SM;
@@ -3776,7 +3737,7 @@ e1000_write_kmrn_reg(struct e1000_hw *hw,
3776 3737
3777 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3738 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3778 E1000_KUMCTRLSTA_OFFSET) | data; 3739 E1000_KUMCTRLSTA_OFFSET) | data;
3779 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3740 ew32(KUMCTRLSTA, reg_val);
3780 udelay(2); 3741 udelay(2);
3781 3742
3782 e1000_swfw_sync_release(hw, swfw); 3743 e1000_swfw_sync_release(hw, swfw);
@@ -3788,8 +3749,7 @@ e1000_write_kmrn_reg(struct e1000_hw *hw,
3788* 3749*
3789* hw - Struct containing variables accessed by shared code 3750* hw - Struct containing variables accessed by shared code
3790******************************************************************************/ 3751******************************************************************************/
3791s32 3752s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3792e1000_phy_hw_reset(struct e1000_hw *hw)
3793{ 3753{
3794 u32 ctrl, ctrl_ext; 3754 u32 ctrl, ctrl_ext;
3795 u32 led_ctrl; 3755 u32 led_ctrl;
@@ -3808,7 +3768,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3808 3768
3809 if (hw->mac_type > e1000_82543) { 3769 if (hw->mac_type > e1000_82543) {
3810 if ((hw->mac_type == e1000_80003es2lan) && 3770 if ((hw->mac_type == e1000_80003es2lan) &&
3811 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3771 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3812 swfw = E1000_SWFW_PHY1_SM; 3772 swfw = E1000_SWFW_PHY1_SM;
3813 } else { 3773 } else {
3814 swfw = E1000_SWFW_PHY0_SM; 3774 swfw = E1000_SWFW_PHY0_SM;
@@ -3823,17 +3783,17 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3823 * and deassert. For e1000_82571 hardware and later, we instead delay 3783 * and deassert. For e1000_82571 hardware and later, we instead delay
3824 * for 50us between and 10ms after the deassertion. 3784 * for 50us between and 10ms after the deassertion.
3825 */ 3785 */
3826 ctrl = E1000_READ_REG(hw, CTRL); 3786 ctrl = er32(CTRL);
3827 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 3787 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3828 E1000_WRITE_FLUSH(hw); 3788 E1000_WRITE_FLUSH();
3829 3789
3830 if (hw->mac_type < e1000_82571) 3790 if (hw->mac_type < e1000_82571)
3831 msleep(10); 3791 msleep(10);
3832 else 3792 else
3833 udelay(100); 3793 udelay(100);
3834 3794
3835 E1000_WRITE_REG(hw, CTRL, ctrl); 3795 ew32(CTRL, ctrl);
3836 E1000_WRITE_FLUSH(hw); 3796 E1000_WRITE_FLUSH();
3837 3797
3838 if (hw->mac_type >= e1000_82571) 3798 if (hw->mac_type >= e1000_82571)
3839 mdelay(10); 3799 mdelay(10);
@@ -3843,24 +3803,24 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3843 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3803 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3844 * bit to put the PHY into reset. Then, take it out of reset. 3804 * bit to put the PHY into reset. Then, take it out of reset.
3845 */ 3805 */
3846 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3806 ctrl_ext = er32(CTRL_EXT);
3847 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3807 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3848 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3808 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3849 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3809 ew32(CTRL_EXT, ctrl_ext);
3850 E1000_WRITE_FLUSH(hw); 3810 E1000_WRITE_FLUSH();
3851 msleep(10); 3811 msleep(10);
3852 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3812 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3853 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3813 ew32(CTRL_EXT, ctrl_ext);
3854 E1000_WRITE_FLUSH(hw); 3814 E1000_WRITE_FLUSH();
3855 } 3815 }
3856 udelay(150); 3816 udelay(150);
3857 3817
3858 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3818 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3859 /* Configure activity LED after PHY reset */ 3819 /* Configure activity LED after PHY reset */
3860 led_ctrl = E1000_READ_REG(hw, LEDCTL); 3820 led_ctrl = er32(LEDCTL);
3861 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3821 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3862 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3822 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3863 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 3823 ew32(LEDCTL, led_ctrl);
3864 } 3824 }
3865 3825
3866 /* Wait for FW to finish PHY configuration. */ 3826 /* Wait for FW to finish PHY configuration. */
@@ -3882,8 +3842,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3882* 3842*
3883* Sets bit 15 of the MII Control register 3843* Sets bit 15 of the MII Control register
3884******************************************************************************/ 3844******************************************************************************/
3885s32 3845s32 e1000_phy_reset(struct e1000_hw *hw)
3886e1000_phy_reset(struct e1000_hw *hw)
3887{ 3846{
3888 s32 ret_val; 3847 s32 ret_val;
3889 u16 phy_data; 3848 u16 phy_data;
@@ -3934,8 +3893,7 @@ e1000_phy_reset(struct e1000_hw *hw)
3934* 3893*
3935* hw - struct containing variables accessed by shared code 3894* hw - struct containing variables accessed by shared code
3936******************************************************************************/ 3895******************************************************************************/
3937void 3896void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3938e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3939{ 3897{
3940 s32 reg; 3898 s32 reg;
3941 u16 phy_data; 3899 u16 phy_data;
@@ -3948,8 +3906,8 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3948 3906
3949 do { 3907 do {
3950 /* Disable link */ 3908 /* Disable link */
3951 reg = E1000_READ_REG(hw, PHY_CTRL); 3909 reg = er32(PHY_CTRL);
3952 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 3910 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3953 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3911 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3954 3912
3955 /* Write VR power-down enable - bits 9:8 should be 10b */ 3913 /* Write VR power-down enable - bits 9:8 should be 10b */
@@ -3964,8 +3922,8 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3964 break; 3922 break;
3965 3923
3966 /* Issue PHY reset and repeat at most one more time */ 3924 /* Issue PHY reset and repeat at most one more time */
3967 reg = E1000_READ_REG(hw, CTRL); 3925 reg = er32(CTRL);
3968 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); 3926 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3969 retry++; 3927 retry++;
3970 } while (retry); 3928 } while (retry);
3971 3929
@@ -3987,8 +3945,7 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3987* 3945*
3988* hw - struct containing variables accessed by shared code 3946* hw - struct containing variables accessed by shared code
3989******************************************************************************/ 3947******************************************************************************/
3990static s32 3948static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3991e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3992{ 3949{
3993 s32 ret_val; 3950 s32 ret_val;
3994 s32 reg; 3951 s32 reg;
@@ -4024,8 +3981,8 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4024 mdelay(5); 3981 mdelay(5);
4025 } 3982 }
4026 /* Disable GigE link negotiation */ 3983 /* Disable GigE link negotiation */
4027 reg = E1000_READ_REG(hw, PHY_CTRL); 3984 reg = er32(PHY_CTRL);
4028 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 3985 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4029 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3986 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4030 3987
4031 /* unable to acquire PCS lock */ 3988 /* unable to acquire PCS lock */
@@ -4040,8 +3997,7 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4040* 3997*
4041* hw - Struct containing variables accessed by shared code 3998* hw - Struct containing variables accessed by shared code
4042******************************************************************************/ 3999******************************************************************************/
4043static s32 4000static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
4044e1000_detect_gig_phy(struct e1000_hw *hw)
4045{ 4001{
4046 s32 phy_init_status, ret_val; 4002 s32 phy_init_status, ret_val;
4047 u16 phy_id_high, phy_id_low; 4003 u16 phy_id_high, phy_id_low;
@@ -4076,14 +4032,14 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
4076 if (ret_val) 4032 if (ret_val)
4077 return ret_val; 4033 return ret_val;
4078 4034
4079 hw->phy_id = (u32) (phy_id_high << 16); 4035 hw->phy_id = (u32)(phy_id_high << 16);
4080 udelay(20); 4036 udelay(20);
4081 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4037 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4082 if (ret_val) 4038 if (ret_val)
4083 return ret_val; 4039 return ret_val;
4084 4040
4085 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); 4041 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
4086 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; 4042 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
4087 4043
4088 switch (hw->mac_type) { 4044 switch (hw->mac_type) {
4089 case e1000_82543: 4045 case e1000_82543:
@@ -4136,8 +4092,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
4136* 4092*
4137* hw - Struct containing variables accessed by shared code 4093* hw - Struct containing variables accessed by shared code
4138******************************************************************************/ 4094******************************************************************************/
4139static s32 4095static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
4140e1000_phy_reset_dsp(struct e1000_hw *hw)
4141{ 4096{
4142 s32 ret_val; 4097 s32 ret_val;
4143 DEBUGFUNC("e1000_phy_reset_dsp"); 4098 DEBUGFUNC("e1000_phy_reset_dsp");
@@ -4163,9 +4118,8 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
4163* hw - Struct containing variables accessed by shared code 4118* hw - Struct containing variables accessed by shared code
4164* phy_info - PHY information structure 4119* phy_info - PHY information structure
4165******************************************************************************/ 4120******************************************************************************/
4166static s32 4121static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
4167e1000_phy_igp_get_info(struct e1000_hw *hw, 4122 struct e1000_phy_info *phy_info)
4168 struct e1000_phy_info *phy_info)
4169{ 4123{
4170 s32 ret_val; 4124 s32 ret_val;
4171 u16 phy_data, min_length, max_length, average; 4125 u16 phy_data, min_length, max_length, average;
@@ -4240,9 +4194,8 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4240* hw - Struct containing variables accessed by shared code 4194* hw - Struct containing variables accessed by shared code
4241* phy_info - PHY information structure 4195* phy_info - PHY information structure
4242******************************************************************************/ 4196******************************************************************************/
4243static s32 4197static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
4244e1000_phy_ife_get_info(struct e1000_hw *hw, 4198 struct e1000_phy_info *phy_info)
4245 struct e1000_phy_info *phy_info)
4246{ 4199{
4247 s32 ret_val; 4200 s32 ret_val;
4248 u16 phy_data; 4201 u16 phy_data;
@@ -4290,9 +4243,8 @@ e1000_phy_ife_get_info(struct e1000_hw *hw,
4290* hw - Struct containing variables accessed by shared code 4243* hw - Struct containing variables accessed by shared code
4291* phy_info - PHY information structure 4244* phy_info - PHY information structure
4292******************************************************************************/ 4245******************************************************************************/
4293static s32 4246static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
4294e1000_phy_m88_get_info(struct e1000_hw *hw, 4247 struct e1000_phy_info *phy_info)
4295 struct e1000_phy_info *phy_info)
4296{ 4248{
4297 s32 ret_val; 4249 s32 ret_val;
4298 u16 phy_data; 4250 u16 phy_data;
@@ -4369,9 +4321,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4369* hw - Struct containing variables accessed by shared code 4321* hw - Struct containing variables accessed by shared code
4370* phy_info - PHY information structure 4322* phy_info - PHY information structure
4371******************************************************************************/ 4323******************************************************************************/
4372s32 4324s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
4373e1000_phy_get_info(struct e1000_hw *hw,
4374 struct e1000_phy_info *phy_info)
4375{ 4325{
4376 s32 ret_val; 4326 s32 ret_val;
4377 u16 phy_data; 4327 u16 phy_data;
@@ -4415,8 +4365,7 @@ e1000_phy_get_info(struct e1000_hw *hw,
4415 return e1000_phy_m88_get_info(hw, phy_info); 4365 return e1000_phy_m88_get_info(hw, phy_info);
4416} 4366}
4417 4367
4418s32 4368s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
4419e1000_validate_mdi_setting(struct e1000_hw *hw)
4420{ 4369{
4421 DEBUGFUNC("e1000_validate_mdi_settings"); 4370 DEBUGFUNC("e1000_validate_mdi_settings");
4422 4371
@@ -4436,11 +4385,10 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
4436 * 4385 *
4437 * hw - Struct containing variables accessed by shared code 4386 * hw - Struct containing variables accessed by shared code
4438 *****************************************************************************/ 4387 *****************************************************************************/
4439s32 4388s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4440e1000_init_eeprom_params(struct e1000_hw *hw)
4441{ 4389{
4442 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4390 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4443 u32 eecd = E1000_READ_REG(hw, EECD); 4391 u32 eecd = er32(EECD);
4444 s32 ret_val = E1000_SUCCESS; 4392 s32 ret_val = E1000_SUCCESS;
4445 u16 eeprom_size; 4393 u16 eeprom_size;
4446 4394
@@ -4542,7 +4490,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4542 /* Ensure that the Autonomous FLASH update bit is cleared due to 4490 /* Ensure that the Autonomous FLASH update bit is cleared due to
4543 * Flash update issue on parts which use a FLASH for NVM. */ 4491 * Flash update issue on parts which use a FLASH for NVM. */
4544 eecd &= ~E1000_EECD_AUPDEN; 4492 eecd &= ~E1000_EECD_AUPDEN;
4545 E1000_WRITE_REG(hw, EECD, eecd); 4493 ew32(EECD, eecd);
4546 } 4494 }
4547 break; 4495 break;
4548 case e1000_80003es2lan: 4496 case e1000_80003es2lan:
@@ -4626,16 +4574,14 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4626 * hw - Struct containing variables accessed by shared code 4574 * hw - Struct containing variables accessed by shared code
4627 * eecd - EECD's current value 4575 * eecd - EECD's current value
4628 *****************************************************************************/ 4576 *****************************************************************************/
4629static void 4577static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
4630e1000_raise_ee_clk(struct e1000_hw *hw,
4631 u32 *eecd)
4632{ 4578{
4633 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 4579 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4634 * wait <delay> microseconds. 4580 * wait <delay> microseconds.
4635 */ 4581 */
4636 *eecd = *eecd | E1000_EECD_SK; 4582 *eecd = *eecd | E1000_EECD_SK;
4637 E1000_WRITE_REG(hw, EECD, *eecd); 4583 ew32(EECD, *eecd);
4638 E1000_WRITE_FLUSH(hw); 4584 E1000_WRITE_FLUSH();
4639 udelay(hw->eeprom.delay_usec); 4585 udelay(hw->eeprom.delay_usec);
4640} 4586}
4641 4587
@@ -4645,16 +4591,14 @@ e1000_raise_ee_clk(struct e1000_hw *hw,
4645 * hw - Struct containing variables accessed by shared code 4591 * hw - Struct containing variables accessed by shared code
4646 * eecd - EECD's current value 4592 * eecd - EECD's current value
4647 *****************************************************************************/ 4593 *****************************************************************************/
4648static void 4594static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
4649e1000_lower_ee_clk(struct e1000_hw *hw,
4650 u32 *eecd)
4651{ 4595{
4652 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 4596 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4653 * wait 50 microseconds. 4597 * wait 50 microseconds.
4654 */ 4598 */
4655 *eecd = *eecd & ~E1000_EECD_SK; 4599 *eecd = *eecd & ~E1000_EECD_SK;
4656 E1000_WRITE_REG(hw, EECD, *eecd); 4600 ew32(EECD, *eecd);
4657 E1000_WRITE_FLUSH(hw); 4601 E1000_WRITE_FLUSH();
4658 udelay(hw->eeprom.delay_usec); 4602 udelay(hw->eeprom.delay_usec);
4659} 4603}
4660 4604
@@ -4665,10 +4609,7 @@ e1000_lower_ee_clk(struct e1000_hw *hw,
4665 * data - data to send to the EEPROM 4609 * data - data to send to the EEPROM
4666 * count - number of bits to shift out 4610 * count - number of bits to shift out
4667 *****************************************************************************/ 4611 *****************************************************************************/
4668static void 4612static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
4669e1000_shift_out_ee_bits(struct e1000_hw *hw,
4670 u16 data,
4671 u16 count)
4672{ 4613{
4673 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4614 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4674 u32 eecd; 4615 u32 eecd;
@@ -4679,7 +4620,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4679 * In order to do this, "data" must be broken down into bits. 4620 * In order to do this, "data" must be broken down into bits.
4680 */ 4621 */
4681 mask = 0x01 << (count - 1); 4622 mask = 0x01 << (count - 1);
4682 eecd = E1000_READ_REG(hw, EECD); 4623 eecd = er32(EECD);
4683 if (eeprom->type == e1000_eeprom_microwire) { 4624 if (eeprom->type == e1000_eeprom_microwire) {
4684 eecd &= ~E1000_EECD_DO; 4625 eecd &= ~E1000_EECD_DO;
4685 } else if (eeprom->type == e1000_eeprom_spi) { 4626 } else if (eeprom->type == e1000_eeprom_spi) {
@@ -4696,8 +4637,8 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4696 if (data & mask) 4637 if (data & mask)
4697 eecd |= E1000_EECD_DI; 4638 eecd |= E1000_EECD_DI;
4698 4639
4699 E1000_WRITE_REG(hw, EECD, eecd); 4640 ew32(EECD, eecd);
4700 E1000_WRITE_FLUSH(hw); 4641 E1000_WRITE_FLUSH();
4701 4642
4702 udelay(eeprom->delay_usec); 4643 udelay(eeprom->delay_usec);
4703 4644
@@ -4710,7 +4651,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4710 4651
4711 /* We leave the "DI" bit set to "0" when we leave this routine. */ 4652 /* We leave the "DI" bit set to "0" when we leave this routine. */
4712 eecd &= ~E1000_EECD_DI; 4653 eecd &= ~E1000_EECD_DI;
4713 E1000_WRITE_REG(hw, EECD, eecd); 4654 ew32(EECD, eecd);
4714} 4655}
4715 4656
4716/****************************************************************************** 4657/******************************************************************************
@@ -4718,9 +4659,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4718 * 4659 *
4719 * hw - Struct containing variables accessed by shared code 4660 * hw - Struct containing variables accessed by shared code
4720 *****************************************************************************/ 4661 *****************************************************************************/
4721static u16 4662static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
4722e1000_shift_in_ee_bits(struct e1000_hw *hw,
4723 u16 count)
4724{ 4663{
4725 u32 eecd; 4664 u32 eecd;
4726 u32 i; 4665 u32 i;
@@ -4733,7 +4672,7 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4733 * always be clear. 4672 * always be clear.
4734 */ 4673 */
4735 4674
4736 eecd = E1000_READ_REG(hw, EECD); 4675 eecd = er32(EECD);
4737 4676
4738 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 4677 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4739 data = 0; 4678 data = 0;
@@ -4742,7 +4681,7 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4742 data = data << 1; 4681 data = data << 1;
4743 e1000_raise_ee_clk(hw, &eecd); 4682 e1000_raise_ee_clk(hw, &eecd);
4744 4683
4745 eecd = E1000_READ_REG(hw, EECD); 4684 eecd = er32(EECD);
4746 4685
4747 eecd &= ~(E1000_EECD_DI); 4686 eecd &= ~(E1000_EECD_DI);
4748 if (eecd & E1000_EECD_DO) 4687 if (eecd & E1000_EECD_DO)
@@ -4762,8 +4701,7 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4762 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 4701 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4763 * function should be called before issuing a command to the EEPROM. 4702 * function should be called before issuing a command to the EEPROM.
4764 *****************************************************************************/ 4703 *****************************************************************************/
4765static s32 4704static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
4766e1000_acquire_eeprom(struct e1000_hw *hw)
4767{ 4705{
4768 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4706 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4769 u32 eecd, i=0; 4707 u32 eecd, i=0;
@@ -4772,23 +4710,23 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
4772 4710
4773 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 4711 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4774 return -E1000_ERR_SWFW_SYNC; 4712 return -E1000_ERR_SWFW_SYNC;
4775 eecd = E1000_READ_REG(hw, EECD); 4713 eecd = er32(EECD);
4776 4714
4777 if (hw->mac_type != e1000_82573) { 4715 if (hw->mac_type != e1000_82573) {
4778 /* Request EEPROM Access */ 4716 /* Request EEPROM Access */
4779 if (hw->mac_type > e1000_82544) { 4717 if (hw->mac_type > e1000_82544) {
4780 eecd |= E1000_EECD_REQ; 4718 eecd |= E1000_EECD_REQ;
4781 E1000_WRITE_REG(hw, EECD, eecd); 4719 ew32(EECD, eecd);
4782 eecd = E1000_READ_REG(hw, EECD); 4720 eecd = er32(EECD);
4783 while ((!(eecd & E1000_EECD_GNT)) && 4721 while ((!(eecd & E1000_EECD_GNT)) &&
4784 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 4722 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4785 i++; 4723 i++;
4786 udelay(5); 4724 udelay(5);
4787 eecd = E1000_READ_REG(hw, EECD); 4725 eecd = er32(EECD);
4788 } 4726 }
4789 if (!(eecd & E1000_EECD_GNT)) { 4727 if (!(eecd & E1000_EECD_GNT)) {
4790 eecd &= ~E1000_EECD_REQ; 4728 eecd &= ~E1000_EECD_REQ;
4791 E1000_WRITE_REG(hw, EECD, eecd); 4729 ew32(EECD, eecd);
4792 DEBUGOUT("Could not acquire EEPROM grant\n"); 4730 DEBUGOUT("Could not acquire EEPROM grant\n");
4793 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4731 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4794 return -E1000_ERR_EEPROM; 4732 return -E1000_ERR_EEPROM;
@@ -4801,15 +4739,15 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
4801 if (eeprom->type == e1000_eeprom_microwire) { 4739 if (eeprom->type == e1000_eeprom_microwire) {
4802 /* Clear SK and DI */ 4740 /* Clear SK and DI */
4803 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 4741 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4804 E1000_WRITE_REG(hw, EECD, eecd); 4742 ew32(EECD, eecd);
4805 4743
4806 /* Set CS */ 4744 /* Set CS */
4807 eecd |= E1000_EECD_CS; 4745 eecd |= E1000_EECD_CS;
4808 E1000_WRITE_REG(hw, EECD, eecd); 4746 ew32(EECD, eecd);
4809 } else if (eeprom->type == e1000_eeprom_spi) { 4747 } else if (eeprom->type == e1000_eeprom_spi) {
4810 /* Clear SK and CS */ 4748 /* Clear SK and CS */
4811 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4749 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4812 E1000_WRITE_REG(hw, EECD, eecd); 4750 ew32(EECD, eecd);
4813 udelay(1); 4751 udelay(1);
4814 } 4752 }
4815 4753
@@ -4821,46 +4759,45 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
4821 * 4759 *
4822 * hw - Struct containing variables accessed by shared code 4760 * hw - Struct containing variables accessed by shared code
4823 *****************************************************************************/ 4761 *****************************************************************************/
4824static void 4762static void e1000_standby_eeprom(struct e1000_hw *hw)
4825e1000_standby_eeprom(struct e1000_hw *hw)
4826{ 4763{
4827 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4764 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4828 u32 eecd; 4765 u32 eecd;
4829 4766
4830 eecd = E1000_READ_REG(hw, EECD); 4767 eecd = er32(EECD);
4831 4768
4832 if (eeprom->type == e1000_eeprom_microwire) { 4769 if (eeprom->type == e1000_eeprom_microwire) {
4833 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4770 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4834 E1000_WRITE_REG(hw, EECD, eecd); 4771 ew32(EECD, eecd);
4835 E1000_WRITE_FLUSH(hw); 4772 E1000_WRITE_FLUSH();
4836 udelay(eeprom->delay_usec); 4773 udelay(eeprom->delay_usec);
4837 4774
4838 /* Clock high */ 4775 /* Clock high */
4839 eecd |= E1000_EECD_SK; 4776 eecd |= E1000_EECD_SK;
4840 E1000_WRITE_REG(hw, EECD, eecd); 4777 ew32(EECD, eecd);
4841 E1000_WRITE_FLUSH(hw); 4778 E1000_WRITE_FLUSH();
4842 udelay(eeprom->delay_usec); 4779 udelay(eeprom->delay_usec);
4843 4780
4844 /* Select EEPROM */ 4781 /* Select EEPROM */
4845 eecd |= E1000_EECD_CS; 4782 eecd |= E1000_EECD_CS;
4846 E1000_WRITE_REG(hw, EECD, eecd); 4783 ew32(EECD, eecd);
4847 E1000_WRITE_FLUSH(hw); 4784 E1000_WRITE_FLUSH();
4848 udelay(eeprom->delay_usec); 4785 udelay(eeprom->delay_usec);
4849 4786
4850 /* Clock low */ 4787 /* Clock low */
4851 eecd &= ~E1000_EECD_SK; 4788 eecd &= ~E1000_EECD_SK;
4852 E1000_WRITE_REG(hw, EECD, eecd); 4789 ew32(EECD, eecd);
4853 E1000_WRITE_FLUSH(hw); 4790 E1000_WRITE_FLUSH();
4854 udelay(eeprom->delay_usec); 4791 udelay(eeprom->delay_usec);
4855 } else if (eeprom->type == e1000_eeprom_spi) { 4792 } else if (eeprom->type == e1000_eeprom_spi) {
4856 /* Toggle CS to flush commands */ 4793 /* Toggle CS to flush commands */
4857 eecd |= E1000_EECD_CS; 4794 eecd |= E1000_EECD_CS;
4858 E1000_WRITE_REG(hw, EECD, eecd); 4795 ew32(EECD, eecd);
4859 E1000_WRITE_FLUSH(hw); 4796 E1000_WRITE_FLUSH();
4860 udelay(eeprom->delay_usec); 4797 udelay(eeprom->delay_usec);
4861 eecd &= ~E1000_EECD_CS; 4798 eecd &= ~E1000_EECD_CS;
4862 E1000_WRITE_REG(hw, EECD, eecd); 4799 ew32(EECD, eecd);
4863 E1000_WRITE_FLUSH(hw); 4800 E1000_WRITE_FLUSH();
4864 udelay(eeprom->delay_usec); 4801 udelay(eeprom->delay_usec);
4865 } 4802 }
4866} 4803}
@@ -4870,20 +4807,19 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4870 * 4807 *
4871 * hw - Struct containing variables accessed by shared code 4808 * hw - Struct containing variables accessed by shared code
4872 *****************************************************************************/ 4809 *****************************************************************************/
4873static void 4810static void e1000_release_eeprom(struct e1000_hw *hw)
4874e1000_release_eeprom(struct e1000_hw *hw)
4875{ 4811{
4876 u32 eecd; 4812 u32 eecd;
4877 4813
4878 DEBUGFUNC("e1000_release_eeprom"); 4814 DEBUGFUNC("e1000_release_eeprom");
4879 4815
4880 eecd = E1000_READ_REG(hw, EECD); 4816 eecd = er32(EECD);
4881 4817
4882 if (hw->eeprom.type == e1000_eeprom_spi) { 4818 if (hw->eeprom.type == e1000_eeprom_spi) {
4883 eecd |= E1000_EECD_CS; /* Pull CS high */ 4819 eecd |= E1000_EECD_CS; /* Pull CS high */
4884 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 4820 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4885 4821
4886 E1000_WRITE_REG(hw, EECD, eecd); 4822 ew32(EECD, eecd);
4887 4823
4888 udelay(hw->eeprom.delay_usec); 4824 udelay(hw->eeprom.delay_usec);
4889 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 4825 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
@@ -4892,25 +4828,25 @@ e1000_release_eeprom(struct e1000_hw *hw)
4892 /* CS on Microwire is active-high */ 4828 /* CS on Microwire is active-high */
4893 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 4829 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4894 4830
4895 E1000_WRITE_REG(hw, EECD, eecd); 4831 ew32(EECD, eecd);
4896 4832
4897 /* Rising edge of clock */ 4833 /* Rising edge of clock */
4898 eecd |= E1000_EECD_SK; 4834 eecd |= E1000_EECD_SK;
4899 E1000_WRITE_REG(hw, EECD, eecd); 4835 ew32(EECD, eecd);
4900 E1000_WRITE_FLUSH(hw); 4836 E1000_WRITE_FLUSH();
4901 udelay(hw->eeprom.delay_usec); 4837 udelay(hw->eeprom.delay_usec);
4902 4838
4903 /* Falling edge of clock */ 4839 /* Falling edge of clock */
4904 eecd &= ~E1000_EECD_SK; 4840 eecd &= ~E1000_EECD_SK;
4905 E1000_WRITE_REG(hw, EECD, eecd); 4841 ew32(EECD, eecd);
4906 E1000_WRITE_FLUSH(hw); 4842 E1000_WRITE_FLUSH();
4907 udelay(hw->eeprom.delay_usec); 4843 udelay(hw->eeprom.delay_usec);
4908 } 4844 }
4909 4845
4910 /* Stop requesting EEPROM access */ 4846 /* Stop requesting EEPROM access */
4911 if (hw->mac_type > e1000_82544) { 4847 if (hw->mac_type > e1000_82544) {
4912 eecd &= ~E1000_EECD_REQ; 4848 eecd &= ~E1000_EECD_REQ;
4913 E1000_WRITE_REG(hw, EECD, eecd); 4849 ew32(EECD, eecd);
4914 } 4850 }
4915 4851
4916 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4852 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
@@ -4921,8 +4857,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4921 * 4857 *
4922 * hw - Struct containing variables accessed by shared code 4858 * hw - Struct containing variables accessed by shared code
4923 *****************************************************************************/ 4859 *****************************************************************************/
4924static s32 4860static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4925e1000_spi_eeprom_ready(struct e1000_hw *hw)
4926{ 4861{
4927 u16 retry_count = 0; 4862 u16 retry_count = 0;
4928 u8 spi_stat_reg; 4863 u8 spi_stat_reg;
@@ -4967,11 +4902,7 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4967 * data - word read from the EEPROM 4902 * data - word read from the EEPROM
4968 * words - number of words to read 4903 * words - number of words to read
4969 *****************************************************************************/ 4904 *****************************************************************************/
4970s32 4905s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4971e1000_read_eeprom(struct e1000_hw *hw,
4972 u16 offset,
4973 u16 words,
4974 u16 *data)
4975{ 4906{
4976 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4907 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4977 u32 i = 0; 4908 u32 i = 0;
@@ -5068,11 +4999,8 @@ e1000_read_eeprom(struct e1000_hw *hw,
5068 * data - word read from the EEPROM 4999 * data - word read from the EEPROM
5069 * words - number of words to read 5000 * words - number of words to read
5070 *****************************************************************************/ 5001 *****************************************************************************/
5071static s32 5002static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
5072e1000_read_eeprom_eerd(struct e1000_hw *hw, 5003 u16 *data)
5073 u16 offset,
5074 u16 words,
5075 u16 *data)
5076{ 5004{
5077 u32 i, eerd = 0; 5005 u32 i, eerd = 0;
5078 s32 error = 0; 5006 s32 error = 0;
@@ -5081,13 +5009,13 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 5009 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5082 E1000_EEPROM_RW_REG_START; 5010 E1000_EEPROM_RW_REG_START;
5083 5011
5084 E1000_WRITE_REG(hw, EERD, eerd); 5012 ew32(EERD, eerd);
5085 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 5013 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5086 5014
5087 if (error) { 5015 if (error) {
5088 break; 5016 break;
5089 } 5017 }
5090 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); 5018 data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
5091 5019
5092 } 5020 }
5093 5021
@@ -5102,11 +5030,8 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
5102 * data - word read from the EEPROM 5030 * data - word read from the EEPROM
5103 * words - number of words to read 5031 * words - number of words to read
5104 *****************************************************************************/ 5032 *****************************************************************************/
5105static s32 5033static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
5106e1000_write_eeprom_eewr(struct e1000_hw *hw, 5034 u16 *data)
5107 u16 offset,
5108 u16 words,
5109 u16 *data)
5110{ 5035{
5111 u32 register_value = 0; 5036 u32 register_value = 0;
5112 u32 i = 0; 5037 u32 i = 0;
@@ -5125,7 +5050,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
5125 break; 5050 break;
5126 } 5051 }
5127 5052
5128 E1000_WRITE_REG(hw, EEWR, register_value); 5053 ew32(EEWR, register_value);
5129 5054
5130 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5055 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5131 5056
@@ -5143,8 +5068,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
5143 * 5068 *
5144 * hw - Struct containing variables accessed by shared code 5069 * hw - Struct containing variables accessed by shared code
5145 *****************************************************************************/ 5070 *****************************************************************************/
5146static s32 5071static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5147e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5148{ 5072{
5149 u32 attempts = 100000; 5073 u32 attempts = 100000;
5150 u32 i, reg = 0; 5074 u32 i, reg = 0;
@@ -5152,9 +5076,9 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5152 5076
5153 for (i = 0; i < attempts; i++) { 5077 for (i = 0; i < attempts; i++) {
5154 if (eerd == E1000_EEPROM_POLL_READ) 5078 if (eerd == E1000_EEPROM_POLL_READ)
5155 reg = E1000_READ_REG(hw, EERD); 5079 reg = er32(EERD);
5156 else 5080 else
5157 reg = E1000_READ_REG(hw, EEWR); 5081 reg = er32(EEWR);
5158 5082
5159 if (reg & E1000_EEPROM_RW_REG_DONE) { 5083 if (reg & E1000_EEPROM_RW_REG_DONE) {
5160 done = E1000_SUCCESS; 5084 done = E1000_SUCCESS;
@@ -5171,8 +5095,7 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5171* 5095*
5172* hw - Struct containing variables accessed by shared code 5096* hw - Struct containing variables accessed by shared code
5173****************************************************************************/ 5097****************************************************************************/
5174static bool 5098static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5175e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5176{ 5099{
5177 u32 eecd = 0; 5100 u32 eecd = 0;
5178 5101
@@ -5182,7 +5105,7 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5182 return false; 5105 return false;
5183 5106
5184 if (hw->mac_type == e1000_82573) { 5107 if (hw->mac_type == e1000_82573) {
5185 eecd = E1000_READ_REG(hw, EECD); 5108 eecd = er32(EECD);
5186 5109
5187 /* Isolate bits 15 & 16 */ 5110 /* Isolate bits 15 & 16 */
5188 eecd = ((eecd >> 15) & 0x03); 5111 eecd = ((eecd >> 15) & 0x03);
@@ -5204,8 +5127,7 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 5127 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5205 * valid. 5128 * valid.
5206 *****************************************************************************/ 5129 *****************************************************************************/
5207s32 5130s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5208e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5209{ 5131{
5210 u16 checksum = 0; 5132 u16 checksum = 0;
5211 u16 i, eeprom_data; 5133 u16 i, eeprom_data;
@@ -5252,7 +5174,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5252 checksum += eeprom_data; 5174 checksum += eeprom_data;
5253 } 5175 }
5254 5176
5255 if (checksum == (u16) EEPROM_SUM) 5177 if (checksum == (u16)EEPROM_SUM)
5256 return E1000_SUCCESS; 5178 return E1000_SUCCESS;
5257 else { 5179 else {
5258 DEBUGOUT("EEPROM Checksum Invalid\n"); 5180 DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -5268,8 +5190,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5268 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 5190 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5269 * Writes the difference to word offset 63 of the EEPROM. 5191 * Writes the difference to word offset 63 of the EEPROM.
5270 *****************************************************************************/ 5192 *****************************************************************************/
5271s32 5193s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5272e1000_update_eeprom_checksum(struct e1000_hw *hw)
5273{ 5194{
5274 u32 ctrl_ext; 5195 u32 ctrl_ext;
5275 u16 checksum = 0; 5196 u16 checksum = 0;
@@ -5284,7 +5205,7 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5284 } 5205 }
5285 checksum += eeprom_data; 5206 checksum += eeprom_data;
5286 } 5207 }
5287 checksum = (u16) EEPROM_SUM - checksum; 5208 checksum = (u16)EEPROM_SUM - checksum;
5288 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5209 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5289 DEBUGOUT("EEPROM Write Error\n"); 5210 DEBUGOUT("EEPROM Write Error\n");
5290 return -E1000_ERR_EEPROM; 5211 return -E1000_ERR_EEPROM;
@@ -5294,9 +5215,9 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5294 e1000_commit_shadow_ram(hw); 5215 e1000_commit_shadow_ram(hw);
5295 /* Reload the EEPROM, or else modifications will not appear 5216 /* Reload the EEPROM, or else modifications will not appear
5296 * until after next adapter reset. */ 5217 * until after next adapter reset. */
5297 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5218 ctrl_ext = er32(CTRL_EXT);
5298 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 5219 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5299 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5220 ew32(CTRL_EXT, ctrl_ext);
5300 msleep(10); 5221 msleep(10);
5301 } 5222 }
5302 return E1000_SUCCESS; 5223 return E1000_SUCCESS;
@@ -5313,11 +5234,7 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5313 * If e1000_update_eeprom_checksum is not called after this function, the 5234 * If e1000_update_eeprom_checksum is not called after this function, the
5314 * EEPROM will most likely contain an invalid checksum. 5235 * EEPROM will most likely contain an invalid checksum.
5315 *****************************************************************************/ 5236 *****************************************************************************/
5316s32 5237s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5317e1000_write_eeprom(struct e1000_hw *hw,
5318 u16 offset,
5319 u16 words,
5320 u16 *data)
5321{ 5238{
5322 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5239 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5323 s32 status = 0; 5240 s32 status = 0;
@@ -5370,11 +5287,8 @@ e1000_write_eeprom(struct e1000_hw *hw,
5370 * data - pointer to array of 8 bit words to be written to the EEPROM 5287 * data - pointer to array of 8 bit words to be written to the EEPROM
5371 * 5288 *
5372 *****************************************************************************/ 5289 *****************************************************************************/
5373static s32 5290static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
5374e1000_write_eeprom_spi(struct e1000_hw *hw, 5291 u16 *data)
5375 u16 offset,
5376 u16 words,
5377 u16 *data)
5378{ 5292{
5379 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5293 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5380 u16 widx = 0; 5294 u16 widx = 0;
@@ -5436,11 +5350,8 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5436 * data - pointer to array of 16 bit words to be written to the EEPROM 5350 * data - pointer to array of 16 bit words to be written to the EEPROM
5437 * 5351 *
5438 *****************************************************************************/ 5352 *****************************************************************************/
5439static s32 5353static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
5440e1000_write_eeprom_microwire(struct e1000_hw *hw, 5354 u16 words, u16 *data)
5441 u16 offset,
5442 u16 words,
5443 u16 *data)
5444{ 5355{
5445 struct e1000_eeprom_info *eeprom = &hw->eeprom; 5356 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5446 u32 eecd; 5357 u32 eecd;
@@ -5484,7 +5395,7 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5484 * If DO does not go high in 10 milliseconds, then error out. 5395 * If DO does not go high in 10 milliseconds, then error out.
5485 */ 5396 */
5486 for (i = 0; i < 200; i++) { 5397 for (i = 0; i < 200; i++) {
5487 eecd = E1000_READ_REG(hw, EECD); 5398 eecd = er32(EECD);
5488 if (eecd & E1000_EECD_DO) break; 5399 if (eecd & E1000_EECD_DO) break;
5489 udelay(50); 5400 udelay(50);
5490 } 5401 }
@@ -5523,8 +5434,7 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5523 * data - word read from the EEPROM 5434 * data - word read from the EEPROM
5524 * words - number of words to read 5435 * words - number of words to read
5525 *****************************************************************************/ 5436 *****************************************************************************/
5526static s32 5437static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
5527e1000_commit_shadow_ram(struct e1000_hw *hw)
5528{ 5438{
5529 u32 attempts = 100000; 5439 u32 attempts = 100000;
5530 u32 eecd = 0; 5440 u32 eecd = 0;
@@ -5539,9 +5449,9 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5539 5449
5540 if (hw->mac_type == e1000_82573) { 5450 if (hw->mac_type == e1000_82573) {
5541 /* The flop register will be used to determine if flash type is STM */ 5451 /* The flop register will be used to determine if flash type is STM */
5542 flop = E1000_READ_REG(hw, FLOP); 5452 flop = er32(FLOP);
5543 for (i=0; i < attempts; i++) { 5453 for (i=0; i < attempts; i++) {
5544 eecd = E1000_READ_REG(hw, EECD); 5454 eecd = er32(EECD);
5545 if ((eecd & E1000_EECD_FLUPD) == 0) { 5455 if ((eecd & E1000_EECD_FLUPD) == 0) {
5546 break; 5456 break;
5547 } 5457 }
@@ -5554,14 +5464,14 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5554 5464
5555 /* If STM opcode located in bits 15:8 of flop, reset firmware */ 5465 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5556 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 5466 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5557 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 5467 ew32(HICR, E1000_HICR_FW_RESET);
5558 } 5468 }
5559 5469
5560 /* Perform the flash update */ 5470 /* Perform the flash update */
5561 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 5471 ew32(EECD, eecd | E1000_EECD_FLUPD);
5562 5472
5563 for (i=0; i < attempts; i++) { 5473 for (i=0; i < attempts; i++) {
5564 eecd = E1000_READ_REG(hw, EECD); 5474 eecd = er32(EECD);
5565 if ((eecd & E1000_EECD_FLUPD) == 0) { 5475 if ((eecd & E1000_EECD_FLUPD) == 0) {
5566 break; 5476 break;
5567 } 5477 }
@@ -5577,7 +5487,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5577 /* We're writing to the opposite bank so if we're on bank 1, 5487 /* We're writing to the opposite bank so if we're on bank 1,
5578 * write to bank 0 etc. We also need to erase the segment that 5488 * write to bank 0 etc. We also need to erase the segment that
5579 * is going to be written */ 5489 * is going to be written */
5580 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 5490 if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
5581 new_bank_offset = hw->flash_bank_size * 2; 5491 new_bank_offset = hw->flash_bank_size * 2;
5582 old_bank_offset = 0; 5492 old_bank_offset = 0;
5583 e1000_erase_ich8_4k_segment(hw, 1); 5493 e1000_erase_ich8_4k_segment(hw, 1);
@@ -5687,8 +5597,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5687 * 5597 *
5688 * hw - Struct containing variables accessed by shared code 5598 * hw - Struct containing variables accessed by shared code
5689 *****************************************************************************/ 5599 *****************************************************************************/
5690s32 5600s32 e1000_read_mac_addr(struct e1000_hw *hw)
5691e1000_read_mac_addr(struct e1000_hw * hw)
5692{ 5601{
5693 u16 offset; 5602 u16 offset;
5694 u16 eeprom_data, i; 5603 u16 eeprom_data, i;
@@ -5701,8 +5610,8 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5701 DEBUGOUT("EEPROM Read Error\n"); 5610 DEBUGOUT("EEPROM Read Error\n");
5702 return -E1000_ERR_EEPROM; 5611 return -E1000_ERR_EEPROM;
5703 } 5612 }
5704 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); 5613 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
5705 hw->perm_mac_addr[i+1] = (u8) (eeprom_data >> 8); 5614 hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8);
5706 } 5615 }
5707 5616
5708 switch (hw->mac_type) { 5617 switch (hw->mac_type) {
@@ -5712,7 +5621,7 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5712 case e1000_82546_rev_3: 5621 case e1000_82546_rev_3:
5713 case e1000_82571: 5622 case e1000_82571:
5714 case e1000_80003es2lan: 5623 case e1000_80003es2lan:
5715 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 5624 if (er32(STATUS) & E1000_STATUS_FUNC_1)
5716 hw->perm_mac_addr[5] ^= 0x01; 5625 hw->perm_mac_addr[5] ^= 0x01;
5717 break; 5626 break;
5718 } 5627 }
@@ -5731,8 +5640,7 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5731 * of the receive addresss registers. Clears the multicast table. Assumes 5640 * of the receive addresss registers. Clears the multicast table. Assumes
5732 * the receiver is in reset when the routine is called. 5641 * the receiver is in reset when the routine is called.
5733 *****************************************************************************/ 5642 *****************************************************************************/
5734static void 5643static void e1000_init_rx_addrs(struct e1000_hw *hw)
5735e1000_init_rx_addrs(struct e1000_hw *hw)
5736{ 5644{
5737 u32 i; 5645 u32 i;
5738 u32 rar_num; 5646 u32 rar_num;
@@ -5758,9 +5666,9 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5758 DEBUGOUT("Clearing RAR[1-15]\n"); 5666 DEBUGOUT("Clearing RAR[1-15]\n");
5759 for (i = 1; i < rar_num; i++) { 5667 for (i = 1; i < rar_num; i++) {
5760 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5668 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5761 E1000_WRITE_FLUSH(hw); 5669 E1000_WRITE_FLUSH();
5762 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5670 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5763 E1000_WRITE_FLUSH(hw); 5671 E1000_WRITE_FLUSH();
5764 } 5672 }
5765} 5673}
5766 5674
@@ -5770,9 +5678,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5770 * hw - Struct containing variables accessed by shared code 5678 * hw - Struct containing variables accessed by shared code
5771 * mc_addr - the multicast address to hash 5679 * mc_addr - the multicast address to hash
5772 *****************************************************************************/ 5680 *****************************************************************************/
5773u32 5681u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
5774e1000_hash_mc_addr(struct e1000_hw *hw,
5775 u8 *mc_addr)
5776{ 5682{
5777 u32 hash_value = 0; 5683 u32 hash_value = 0;
5778 5684
@@ -5787,37 +5693,37 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5787 case 0: 5693 case 0:
5788 if (hw->mac_type == e1000_ich8lan) { 5694 if (hw->mac_type == e1000_ich8lan) {
5789 /* [47:38] i.e. 0x158 for above example address */ 5695 /* [47:38] i.e. 0x158 for above example address */
5790 hash_value = ((mc_addr[4] >> 6) | (((u16) mc_addr[5]) << 2)); 5696 hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2));
5791 } else { 5697 } else {
5792 /* [47:36] i.e. 0x563 for above example address */ 5698 /* [47:36] i.e. 0x563 for above example address */
5793 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); 5699 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5794 } 5700 }
5795 break; 5701 break;
5796 case 1: 5702 case 1:
5797 if (hw->mac_type == e1000_ich8lan) { 5703 if (hw->mac_type == e1000_ich8lan) {
5798 /* [46:37] i.e. 0x2B1 for above example address */ 5704 /* [46:37] i.e. 0x2B1 for above example address */
5799 hash_value = ((mc_addr[4] >> 5) | (((u16) mc_addr[5]) << 3)); 5705 hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3));
5800 } else { 5706 } else {
5801 /* [46:35] i.e. 0xAC6 for above example address */ 5707 /* [46:35] i.e. 0xAC6 for above example address */
5802 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); 5708 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
5803 } 5709 }
5804 break; 5710 break;
5805 case 2: 5711 case 2:
5806 if (hw->mac_type == e1000_ich8lan) { 5712 if (hw->mac_type == e1000_ich8lan) {
5807 /*[45:36] i.e. 0x163 for above example address */ 5713 /*[45:36] i.e. 0x163 for above example address */
5808 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); 5714 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5809 } else { 5715 } else {
5810 /* [45:34] i.e. 0x5D8 for above example address */ 5716 /* [45:34] i.e. 0x5D8 for above example address */
5811 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); 5717 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5812 } 5718 }
5813 break; 5719 break;
5814 case 3: 5720 case 3:
5815 if (hw->mac_type == e1000_ich8lan) { 5721 if (hw->mac_type == e1000_ich8lan) {
5816 /* [43:34] i.e. 0x18D for above example address */ 5722 /* [43:34] i.e. 0x18D for above example address */
5817 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); 5723 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5818 } else { 5724 } else {
5819 /* [43:32] i.e. 0x634 for above example address */ 5725 /* [43:32] i.e. 0x634 for above example address */
5820 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); 5726 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
5821 } 5727 }
5822 break; 5728 break;
5823 } 5729 }
@@ -5835,9 +5741,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5835 * hw - Struct containing variables accessed by shared code 5741 * hw - Struct containing variables accessed by shared code
5836 * hash_value - Multicast address hash value 5742 * hash_value - Multicast address hash value
5837 *****************************************************************************/ 5743 *****************************************************************************/
5838void 5744void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
5839e1000_mta_set(struct e1000_hw *hw,
5840 u32 hash_value)
5841{ 5745{
5842 u32 hash_bit, hash_reg; 5746 u32 hash_bit, hash_reg;
5843 u32 mta; 5747 u32 mta;
@@ -5868,12 +5772,12 @@ e1000_mta_set(struct e1000_hw *hw,
5868 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5772 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5869 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5773 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5870 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5774 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5871 E1000_WRITE_FLUSH(hw); 5775 E1000_WRITE_FLUSH();
5872 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5776 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5873 E1000_WRITE_FLUSH(hw); 5777 E1000_WRITE_FLUSH();
5874 } else { 5778 } else {
5875 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5779 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5876 E1000_WRITE_FLUSH(hw); 5780 E1000_WRITE_FLUSH();
5877 } 5781 }
5878} 5782}
5879 5783
@@ -5884,20 +5788,16 @@ e1000_mta_set(struct e1000_hw *hw,
5884 * addr - Address to put into receive address register 5788 * addr - Address to put into receive address register
5885 * index - Receive address register to write 5789 * index - Receive address register to write
5886 *****************************************************************************/ 5790 *****************************************************************************/
5887void 5791void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
5888e1000_rar_set(struct e1000_hw *hw,
5889 u8 *addr,
5890 u32 index)
5891{ 5792{
5892 u32 rar_low, rar_high; 5793 u32 rar_low, rar_high;
5893 5794
5894 /* HW expects these in little endian so we reverse the byte order 5795 /* HW expects these in little endian so we reverse the byte order
5895 * from network order (big endian) to little endian 5796 * from network order (big endian) to little endian
5896 */ 5797 */
5897 rar_low = ((u32) addr[0] | 5798 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
5898 ((u32) addr[1] << 8) | 5799 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
5899 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 5800 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
5900 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5901 5801
5902 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 5802 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5903 * unit hang. 5803 * unit hang.
@@ -5930,9 +5830,9 @@ e1000_rar_set(struct e1000_hw *hw,
5930 } 5830 }
5931 5831
5932 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5832 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5933 E1000_WRITE_FLUSH(hw); 5833 E1000_WRITE_FLUSH();
5934 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5834 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5935 E1000_WRITE_FLUSH(hw); 5835 E1000_WRITE_FLUSH();
5936} 5836}
5937 5837
5938/****************************************************************************** 5838/******************************************************************************
@@ -5942,10 +5842,7 @@ e1000_rar_set(struct e1000_hw *hw,
5942 * offset - Offset in VLAN filer table to write 5842 * offset - Offset in VLAN filer table to write
5943 * value - Value to write into VLAN filter table 5843 * value - Value to write into VLAN filter table
5944 *****************************************************************************/ 5844 *****************************************************************************/
5945void 5845void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
5946e1000_write_vfta(struct e1000_hw *hw,
5947 u32 offset,
5948 u32 value)
5949{ 5846{
5950 u32 temp; 5847 u32 temp;
5951 5848
@@ -5955,12 +5852,12 @@ e1000_write_vfta(struct e1000_hw *hw,
5955 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5852 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5956 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5853 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5957 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5854 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5958 E1000_WRITE_FLUSH(hw); 5855 E1000_WRITE_FLUSH();
5959 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 5856 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5960 E1000_WRITE_FLUSH(hw); 5857 E1000_WRITE_FLUSH();
5961 } else { 5858 } else {
5962 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5859 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5963 E1000_WRITE_FLUSH(hw); 5860 E1000_WRITE_FLUSH();
5964 } 5861 }
5965} 5862}
5966 5863
@@ -5969,8 +5866,7 @@ e1000_write_vfta(struct e1000_hw *hw,
5969 * 5866 *
5970 * hw - Struct containing variables accessed by shared code 5867 * hw - Struct containing variables accessed by shared code
5971 *****************************************************************************/ 5868 *****************************************************************************/
5972static void 5869static void e1000_clear_vfta(struct e1000_hw *hw)
5973e1000_clear_vfta(struct e1000_hw *hw)
5974{ 5870{
5975 u32 offset; 5871 u32 offset;
5976 u32 vfta_value = 0; 5872 u32 vfta_value = 0;
@@ -5999,12 +5895,11 @@ e1000_clear_vfta(struct e1000_hw *hw)
5999 * manageability unit */ 5895 * manageability unit */
6000 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5896 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6001 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5897 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6002 E1000_WRITE_FLUSH(hw); 5898 E1000_WRITE_FLUSH();
6003 } 5899 }
6004} 5900}
6005 5901
6006static s32 5902static s32 e1000_id_led_init(struct e1000_hw *hw)
6007e1000_id_led_init(struct e1000_hw * hw)
6008{ 5903{
6009 u32 ledctl; 5904 u32 ledctl;
6010 const u32 ledctl_mask = 0x000000FF; 5905 const u32 ledctl_mask = 0x000000FF;
@@ -6020,7 +5915,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6020 return E1000_SUCCESS; 5915 return E1000_SUCCESS;
6021 } 5916 }
6022 5917
6023 ledctl = E1000_READ_REG(hw, LEDCTL); 5918 ledctl = er32(LEDCTL);
6024 hw->ledctl_default = ledctl; 5919 hw->ledctl_default = ledctl;
6025 hw->ledctl_mode1 = hw->ledctl_default; 5920 hw->ledctl_mode1 = hw->ledctl_default;
6026 hw->ledctl_mode2 = hw->ledctl_default; 5921 hw->ledctl_mode2 = hw->ledctl_default;
@@ -6086,8 +5981,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6086 * 5981 *
6087 * hw - Struct containing variables accessed by shared code 5982 * hw - Struct containing variables accessed by shared code
6088 *****************************************************************************/ 5983 *****************************************************************************/
6089s32 5984s32 e1000_setup_led(struct e1000_hw *hw)
6090e1000_setup_led(struct e1000_hw *hw)
6091{ 5985{
6092 u32 ledctl; 5986 u32 ledctl;
6093 s32 ret_val = E1000_SUCCESS; 5987 s32 ret_val = E1000_SUCCESS;
@@ -6118,7 +6012,7 @@ e1000_setup_led(struct e1000_hw *hw)
6118 /* Fall Through */ 6012 /* Fall Through */
6119 default: 6013 default:
6120 if (hw->media_type == e1000_media_type_fiber) { 6014 if (hw->media_type == e1000_media_type_fiber) {
6121 ledctl = E1000_READ_REG(hw, LEDCTL); 6015 ledctl = er32(LEDCTL);
6122 /* Save current LEDCTL settings */ 6016 /* Save current LEDCTL settings */
6123 hw->ledctl_default = ledctl; 6017 hw->ledctl_default = ledctl;
6124 /* Turn off LED0 */ 6018 /* Turn off LED0 */
@@ -6127,9 +6021,9 @@ e1000_setup_led(struct e1000_hw *hw)
6127 E1000_LEDCTL_LED0_MODE_MASK); 6021 E1000_LEDCTL_LED0_MODE_MASK);
6128 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 6022 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6129 E1000_LEDCTL_LED0_MODE_SHIFT); 6023 E1000_LEDCTL_LED0_MODE_SHIFT);
6130 E1000_WRITE_REG(hw, LEDCTL, ledctl); 6024 ew32(LEDCTL, ledctl);
6131 } else if (hw->media_type == e1000_media_type_copper) 6025 } else if (hw->media_type == e1000_media_type_copper)
6132 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6026 ew32(LEDCTL, hw->ledctl_mode1);
6133 break; 6027 break;
6134 } 6028 }
6135 6029
@@ -6145,8 +6039,7 @@ e1000_setup_led(struct e1000_hw *hw)
6145 * 6039 *
6146 * hw - Struct containing variables accessed by shared code 6040 * hw - Struct containing variables accessed by shared code
6147 *****************************************************************************/ 6041 *****************************************************************************/
6148s32 6042s32 e1000_blink_led_start(struct e1000_hw *hw)
6149e1000_blink_led_start(struct e1000_hw *hw)
6150{ 6043{
6151 s16 i; 6044 s16 i;
6152 u32 ledctl_blink = 0; 6045 u32 ledctl_blink = 0;
@@ -6170,7 +6063,7 @@ e1000_blink_led_start(struct e1000_hw *hw)
6170 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); 6063 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6171 } 6064 }
6172 6065
6173 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); 6066 ew32(LEDCTL, ledctl_blink);
6174 6067
6175 return E1000_SUCCESS; 6068 return E1000_SUCCESS;
6176} 6069}
@@ -6180,8 +6073,7 @@ e1000_blink_led_start(struct e1000_hw *hw)
6180 * 6073 *
6181 * hw - Struct containing variables accessed by shared code 6074 * hw - Struct containing variables accessed by shared code
6182 *****************************************************************************/ 6075 *****************************************************************************/
6183s32 6076s32 e1000_cleanup_led(struct e1000_hw *hw)
6184e1000_cleanup_led(struct e1000_hw *hw)
6185{ 6077{
6186 s32 ret_val = E1000_SUCCESS; 6078 s32 ret_val = E1000_SUCCESS;
6187 6079
@@ -6210,7 +6102,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
6210 break; 6102 break;
6211 } 6103 }
6212 /* Restore LEDCTL settings */ 6104 /* Restore LEDCTL settings */
6213 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6105 ew32(LEDCTL, hw->ledctl_default);
6214 break; 6106 break;
6215 } 6107 }
6216 6108
@@ -6222,10 +6114,9 @@ e1000_cleanup_led(struct e1000_hw *hw)
6222 * 6114 *
6223 * hw - Struct containing variables accessed by shared code 6115 * hw - Struct containing variables accessed by shared code
6224 *****************************************************************************/ 6116 *****************************************************************************/
6225s32 6117s32 e1000_led_on(struct e1000_hw *hw)
6226e1000_led_on(struct e1000_hw *hw)
6227{ 6118{
6228 u32 ctrl = E1000_READ_REG(hw, CTRL); 6119 u32 ctrl = er32(CTRL);
6229 6120
6230 DEBUGFUNC("e1000_led_on"); 6121 DEBUGFUNC("e1000_led_on");
6231 6122
@@ -6257,13 +6148,13 @@ e1000_led_on(struct e1000_hw *hw)
6257 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 6148 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6258 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 6149 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6259 } else if (hw->media_type == e1000_media_type_copper) { 6150 } else if (hw->media_type == e1000_media_type_copper) {
6260 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6151 ew32(LEDCTL, hw->ledctl_mode2);
6261 return E1000_SUCCESS; 6152 return E1000_SUCCESS;
6262 } 6153 }
6263 break; 6154 break;
6264 } 6155 }
6265 6156
6266 E1000_WRITE_REG(hw, CTRL, ctrl); 6157 ew32(CTRL, ctrl);
6267 6158
6268 return E1000_SUCCESS; 6159 return E1000_SUCCESS;
6269} 6160}
@@ -6273,10 +6164,9 @@ e1000_led_on(struct e1000_hw *hw)
6273 * 6164 *
6274 * hw - Struct containing variables accessed by shared code 6165 * hw - Struct containing variables accessed by shared code
6275 *****************************************************************************/ 6166 *****************************************************************************/
6276s32 6167s32 e1000_led_off(struct e1000_hw *hw)
6277e1000_led_off(struct e1000_hw *hw)
6278{ 6168{
6279 u32 ctrl = E1000_READ_REG(hw, CTRL); 6169 u32 ctrl = er32(CTRL);
6280 6170
6281 DEBUGFUNC("e1000_led_off"); 6171 DEBUGFUNC("e1000_led_off");
6282 6172
@@ -6308,13 +6198,13 @@ e1000_led_off(struct e1000_hw *hw)
6308 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 6198 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6309 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 6199 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6310 } else if (hw->media_type == e1000_media_type_copper) { 6200 } else if (hw->media_type == e1000_media_type_copper) {
6311 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6201 ew32(LEDCTL, hw->ledctl_mode1);
6312 return E1000_SUCCESS; 6202 return E1000_SUCCESS;
6313 } 6203 }
6314 break; 6204 break;
6315 } 6205 }
6316 6206
6317 E1000_WRITE_REG(hw, CTRL, ctrl); 6207 ew32(CTRL, ctrl);
6318 6208
6319 return E1000_SUCCESS; 6209 return E1000_SUCCESS;
6320} 6210}
@@ -6324,98 +6214,97 @@ e1000_led_off(struct e1000_hw *hw)
6324 * 6214 *
6325 * hw - Struct containing variables accessed by shared code 6215 * hw - Struct containing variables accessed by shared code
6326 *****************************************************************************/ 6216 *****************************************************************************/
6327static void 6217static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6328e1000_clear_hw_cntrs(struct e1000_hw *hw)
6329{ 6218{
6330 volatile u32 temp; 6219 volatile u32 temp;
6331 6220
6332 temp = E1000_READ_REG(hw, CRCERRS); 6221 temp = er32(CRCERRS);
6333 temp = E1000_READ_REG(hw, SYMERRS); 6222 temp = er32(SYMERRS);
6334 temp = E1000_READ_REG(hw, MPC); 6223 temp = er32(MPC);
6335 temp = E1000_READ_REG(hw, SCC); 6224 temp = er32(SCC);
6336 temp = E1000_READ_REG(hw, ECOL); 6225 temp = er32(ECOL);
6337 temp = E1000_READ_REG(hw, MCC); 6226 temp = er32(MCC);
6338 temp = E1000_READ_REG(hw, LATECOL); 6227 temp = er32(LATECOL);
6339 temp = E1000_READ_REG(hw, COLC); 6228 temp = er32(COLC);
6340 temp = E1000_READ_REG(hw, DC); 6229 temp = er32(DC);
6341 temp = E1000_READ_REG(hw, SEC); 6230 temp = er32(SEC);
6342 temp = E1000_READ_REG(hw, RLEC); 6231 temp = er32(RLEC);
6343 temp = E1000_READ_REG(hw, XONRXC); 6232 temp = er32(XONRXC);
6344 temp = E1000_READ_REG(hw, XONTXC); 6233 temp = er32(XONTXC);
6345 temp = E1000_READ_REG(hw, XOFFRXC); 6234 temp = er32(XOFFRXC);
6346 temp = E1000_READ_REG(hw, XOFFTXC); 6235 temp = er32(XOFFTXC);
6347 temp = E1000_READ_REG(hw, FCRUC); 6236 temp = er32(FCRUC);
6348 6237
6349 if (hw->mac_type != e1000_ich8lan) { 6238 if (hw->mac_type != e1000_ich8lan) {
6350 temp = E1000_READ_REG(hw, PRC64); 6239 temp = er32(PRC64);
6351 temp = E1000_READ_REG(hw, PRC127); 6240 temp = er32(PRC127);
6352 temp = E1000_READ_REG(hw, PRC255); 6241 temp = er32(PRC255);
6353 temp = E1000_READ_REG(hw, PRC511); 6242 temp = er32(PRC511);
6354 temp = E1000_READ_REG(hw, PRC1023); 6243 temp = er32(PRC1023);
6355 temp = E1000_READ_REG(hw, PRC1522); 6244 temp = er32(PRC1522);
6356 } 6245 }
6357 6246
6358 temp = E1000_READ_REG(hw, GPRC); 6247 temp = er32(GPRC);
6359 temp = E1000_READ_REG(hw, BPRC); 6248 temp = er32(BPRC);
6360 temp = E1000_READ_REG(hw, MPRC); 6249 temp = er32(MPRC);
6361 temp = E1000_READ_REG(hw, GPTC); 6250 temp = er32(GPTC);
6362 temp = E1000_READ_REG(hw, GORCL); 6251 temp = er32(GORCL);
6363 temp = E1000_READ_REG(hw, GORCH); 6252 temp = er32(GORCH);
6364 temp = E1000_READ_REG(hw, GOTCL); 6253 temp = er32(GOTCL);
6365 temp = E1000_READ_REG(hw, GOTCH); 6254 temp = er32(GOTCH);
6366 temp = E1000_READ_REG(hw, RNBC); 6255 temp = er32(RNBC);
6367 temp = E1000_READ_REG(hw, RUC); 6256 temp = er32(RUC);
6368 temp = E1000_READ_REG(hw, RFC); 6257 temp = er32(RFC);
6369 temp = E1000_READ_REG(hw, ROC); 6258 temp = er32(ROC);
6370 temp = E1000_READ_REG(hw, RJC); 6259 temp = er32(RJC);
6371 temp = E1000_READ_REG(hw, TORL); 6260 temp = er32(TORL);
6372 temp = E1000_READ_REG(hw, TORH); 6261 temp = er32(TORH);
6373 temp = E1000_READ_REG(hw, TOTL); 6262 temp = er32(TOTL);
6374 temp = E1000_READ_REG(hw, TOTH); 6263 temp = er32(TOTH);
6375 temp = E1000_READ_REG(hw, TPR); 6264 temp = er32(TPR);
6376 temp = E1000_READ_REG(hw, TPT); 6265 temp = er32(TPT);
6377 6266
6378 if (hw->mac_type != e1000_ich8lan) { 6267 if (hw->mac_type != e1000_ich8lan) {
6379 temp = E1000_READ_REG(hw, PTC64); 6268 temp = er32(PTC64);
6380 temp = E1000_READ_REG(hw, PTC127); 6269 temp = er32(PTC127);
6381 temp = E1000_READ_REG(hw, PTC255); 6270 temp = er32(PTC255);
6382 temp = E1000_READ_REG(hw, PTC511); 6271 temp = er32(PTC511);
6383 temp = E1000_READ_REG(hw, PTC1023); 6272 temp = er32(PTC1023);
6384 temp = E1000_READ_REG(hw, PTC1522); 6273 temp = er32(PTC1522);
6385 } 6274 }
6386 6275
6387 temp = E1000_READ_REG(hw, MPTC); 6276 temp = er32(MPTC);
6388 temp = E1000_READ_REG(hw, BPTC); 6277 temp = er32(BPTC);
6389 6278
6390 if (hw->mac_type < e1000_82543) return; 6279 if (hw->mac_type < e1000_82543) return;
6391 6280
6392 temp = E1000_READ_REG(hw, ALGNERRC); 6281 temp = er32(ALGNERRC);
6393 temp = E1000_READ_REG(hw, RXERRC); 6282 temp = er32(RXERRC);
6394 temp = E1000_READ_REG(hw, TNCRS); 6283 temp = er32(TNCRS);
6395 temp = E1000_READ_REG(hw, CEXTERR); 6284 temp = er32(CEXTERR);
6396 temp = E1000_READ_REG(hw, TSCTC); 6285 temp = er32(TSCTC);
6397 temp = E1000_READ_REG(hw, TSCTFC); 6286 temp = er32(TSCTFC);
6398 6287
6399 if (hw->mac_type <= e1000_82544) return; 6288 if (hw->mac_type <= e1000_82544) return;
6400 6289
6401 temp = E1000_READ_REG(hw, MGTPRC); 6290 temp = er32(MGTPRC);
6402 temp = E1000_READ_REG(hw, MGTPDC); 6291 temp = er32(MGTPDC);
6403 temp = E1000_READ_REG(hw, MGTPTC); 6292 temp = er32(MGTPTC);
6404 6293
6405 if (hw->mac_type <= e1000_82547_rev_2) return; 6294 if (hw->mac_type <= e1000_82547_rev_2) return;
6406 6295
6407 temp = E1000_READ_REG(hw, IAC); 6296 temp = er32(IAC);
6408 temp = E1000_READ_REG(hw, ICRXOC); 6297 temp = er32(ICRXOC);
6409 6298
6410 if (hw->mac_type == e1000_ich8lan) return; 6299 if (hw->mac_type == e1000_ich8lan) return;
6411 6300
6412 temp = E1000_READ_REG(hw, ICRXPTC); 6301 temp = er32(ICRXPTC);
6413 temp = E1000_READ_REG(hw, ICRXATC); 6302 temp = er32(ICRXATC);
6414 temp = E1000_READ_REG(hw, ICTXPTC); 6303 temp = er32(ICTXPTC);
6415 temp = E1000_READ_REG(hw, ICTXATC); 6304 temp = er32(ICTXATC);
6416 temp = E1000_READ_REG(hw, ICTXQEC); 6305 temp = er32(ICTXQEC);
6417 temp = E1000_READ_REG(hw, ICTXQMTC); 6306 temp = er32(ICTXQMTC);
6418 temp = E1000_READ_REG(hw, ICRXDMTC); 6307 temp = er32(ICRXDMTC);
6419} 6308}
6420 6309
6421/****************************************************************************** 6310/******************************************************************************
@@ -6428,8 +6317,7 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
6428 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 6317 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6429 * before calling this function. 6318 * before calling this function.
6430 *****************************************************************************/ 6319 *****************************************************************************/
6431void 6320void e1000_reset_adaptive(struct e1000_hw *hw)
6432e1000_reset_adaptive(struct e1000_hw *hw)
6433{ 6321{
6434 DEBUGFUNC("e1000_reset_adaptive"); 6322 DEBUGFUNC("e1000_reset_adaptive");
6435 6323
@@ -6442,7 +6330,7 @@ e1000_reset_adaptive(struct e1000_hw *hw)
6442 hw->ifs_ratio = IFS_RATIO; 6330 hw->ifs_ratio = IFS_RATIO;
6443 } 6331 }
6444 hw->in_ifs_mode = false; 6332 hw->in_ifs_mode = false;
6445 E1000_WRITE_REG(hw, AIT, 0); 6333 ew32(AIT, 0);
6446 } else { 6334 } else {
6447 DEBUGOUT("Not in Adaptive IFS mode!\n"); 6335 DEBUGOUT("Not in Adaptive IFS mode!\n");
6448 } 6336 }
@@ -6456,8 +6344,7 @@ e1000_reset_adaptive(struct e1000_hw *hw)
6456 * tx_packets - Number of transmits since last callback 6344 * tx_packets - Number of transmits since last callback
6457 * total_collisions - Number of collisions since last callback 6345 * total_collisions - Number of collisions since last callback
6458 *****************************************************************************/ 6346 *****************************************************************************/
6459void 6347void e1000_update_adaptive(struct e1000_hw *hw)
6460e1000_update_adaptive(struct e1000_hw *hw)
6461{ 6348{
6462 DEBUGFUNC("e1000_update_adaptive"); 6349 DEBUGFUNC("e1000_update_adaptive");
6463 6350
@@ -6470,14 +6357,14 @@ e1000_update_adaptive(struct e1000_hw *hw)
6470 hw->current_ifs_val = hw->ifs_min_val; 6357 hw->current_ifs_val = hw->ifs_min_val;
6471 else 6358 else
6472 hw->current_ifs_val += hw->ifs_step_size; 6359 hw->current_ifs_val += hw->ifs_step_size;
6473 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); 6360 ew32(AIT, hw->current_ifs_val);
6474 } 6361 }
6475 } 6362 }
6476 } else { 6363 } else {
6477 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 6364 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6478 hw->current_ifs_val = 0; 6365 hw->current_ifs_val = 0;
6479 hw->in_ifs_mode = false; 6366 hw->in_ifs_mode = false;
6480 E1000_WRITE_REG(hw, AIT, 0); 6367 ew32(AIT, 0);
6481 } 6368 }
6482 } 6369 }
6483 } else { 6370 } else {
@@ -6492,11 +6379,8 @@ e1000_update_adaptive(struct e1000_hw *hw)
6492 * frame_len - The length of the frame in question 6379 * frame_len - The length of the frame in question
6493 * mac_addr - The Ethernet destination address of the frame in question 6380 * mac_addr - The Ethernet destination address of the frame in question
6494 *****************************************************************************/ 6381 *****************************************************************************/
6495void 6382void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
6496e1000_tbi_adjust_stats(struct e1000_hw *hw, 6383 u32 frame_len, u8 *mac_addr)
6497 struct e1000_hw_stats *stats,
6498 u32 frame_len,
6499 u8 *mac_addr)
6500{ 6384{
6501 u64 carry_bit; 6385 u64 carry_bit;
6502 6386
@@ -6527,7 +6411,7 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6527 * since the test for a multicast frame will test positive on 6411 * since the test for a multicast frame will test positive on
6528 * a broadcast frame. 6412 * a broadcast frame.
6529 */ 6413 */
6530 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) 6414 if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff))
6531 /* Broadcast packet */ 6415 /* Broadcast packet */
6532 stats->bprc++; 6416 stats->bprc++;
6533 else if (*mac_addr & 0x01) 6417 else if (*mac_addr & 0x01)
@@ -6570,8 +6454,7 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6570 * 6454 *
6571 * hw - Struct containing variables accessed by shared code 6455 * hw - Struct containing variables accessed by shared code
6572 *****************************************************************************/ 6456 *****************************************************************************/
6573void 6457void e1000_get_bus_info(struct e1000_hw *hw)
6574e1000_get_bus_info(struct e1000_hw *hw)
6575{ 6458{
6576 s32 ret_val; 6459 s32 ret_val;
6577 u16 pci_ex_link_status; 6460 u16 pci_ex_link_status;
@@ -6605,7 +6488,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
6605 hw->bus_width = e1000_bus_width_pciex_1; 6488 hw->bus_width = e1000_bus_width_pciex_1;
6606 break; 6489 break;
6607 default: 6490 default:
6608 status = E1000_READ_REG(hw, STATUS); 6491 status = er32(STATUS);
6609 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 6492 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6610 e1000_bus_type_pcix : e1000_bus_type_pci; 6493 e1000_bus_type_pcix : e1000_bus_type_pci;
6611 6494
@@ -6645,10 +6528,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
6645 * offset - offset to write to 6528 * offset - offset to write to
6646 * value - value to write 6529 * value - value to write
6647 *****************************************************************************/ 6530 *****************************************************************************/
6648static void 6531static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
6649e1000_write_reg_io(struct e1000_hw *hw,
6650 u32 offset,
6651 u32 value)
6652{ 6532{
6653 unsigned long io_addr = hw->io_base; 6533 unsigned long io_addr = hw->io_base;
6654 unsigned long io_data = hw->io_base + 4; 6534 unsigned long io_data = hw->io_base + 4;
@@ -6672,10 +6552,8 @@ e1000_write_reg_io(struct e1000_hw *hw,
6672 * register to the minimum and maximum range. 6552 * register to the minimum and maximum range.
6673 * For IGP phy's, the function calculates the range by the AGC registers. 6553 * For IGP phy's, the function calculates the range by the AGC registers.
6674 *****************************************************************************/ 6554 *****************************************************************************/
6675static s32 6555static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
6676e1000_get_cable_length(struct e1000_hw *hw, 6556 u16 *max_length)
6677 u16 *min_length,
6678 u16 *max_length)
6679{ 6557{
6680 s32 ret_val; 6558 s32 ret_val;
6681 u16 agc_value = 0; 6559 u16 agc_value = 0;
@@ -6863,9 +6741,8 @@ e1000_get_cable_length(struct e1000_hw *hw,
6863 * return 0. If the link speed is 1000 Mbps the polarity status is in the 6741 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6864 * IGP01E1000_PHY_PCS_INIT_REG. 6742 * IGP01E1000_PHY_PCS_INIT_REG.
6865 *****************************************************************************/ 6743 *****************************************************************************/
6866static s32 6744static s32 e1000_check_polarity(struct e1000_hw *hw,
6867e1000_check_polarity(struct e1000_hw *hw, 6745 e1000_rev_polarity *polarity)
6868 e1000_rev_polarity *polarity)
6869{ 6746{
6870 s32 ret_val; 6747 s32 ret_val;
6871 u16 phy_data; 6748 u16 phy_data;
@@ -6939,8 +6816,7 @@ e1000_check_polarity(struct e1000_hw *hw,
6939 * Link Health register. In IGP this bit is latched high, so the driver must 6816 * Link Health register. In IGP this bit is latched high, so the driver must
6940 * read it immediately after link is established. 6817 * read it immediately after link is established.
6941 *****************************************************************************/ 6818 *****************************************************************************/
6942static s32 6819static s32 e1000_check_downshift(struct e1000_hw *hw)
6943e1000_check_downshift(struct e1000_hw *hw)
6944{ 6820{
6945 s32 ret_val; 6821 s32 ret_val;
6946 u16 phy_data; 6822 u16 phy_data;
@@ -6985,9 +6861,7 @@ e1000_check_downshift(struct e1000_hw *hw)
6985 * 6861 *
6986 ****************************************************************************/ 6862 ****************************************************************************/
6987 6863
6988static s32 6864static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
6989e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6990 bool link_up)
6991{ 6865{
6992 s32 ret_val; 6866 s32 ret_val;
6993 u16 phy_data, phy_saved_data, speed, duplex, i; 6867 u16 phy_data, phy_saved_data, speed, duplex, i;
@@ -7173,8 +7047,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7173 * 7047 *
7174 * hw - Struct containing variables accessed by shared code 7048 * hw - Struct containing variables accessed by shared code
7175 ****************************************************************************/ 7049 ****************************************************************************/
7176static s32 7050static s32 e1000_set_phy_mode(struct e1000_hw *hw)
7177e1000_set_phy_mode(struct e1000_hw *hw)
7178{ 7051{
7179 s32 ret_val; 7052 s32 ret_val;
7180 u16 eeprom_data; 7053 u16 eeprom_data;
@@ -7218,9 +7091,7 @@ e1000_set_phy_mode(struct e1000_hw *hw)
7218 * 7091 *
7219 ****************************************************************************/ 7092 ****************************************************************************/
7220 7093
7221static s32 7094static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7222e1000_set_d3_lplu_state(struct e1000_hw *hw,
7223 bool active)
7224{ 7095{
7225 u32 phy_ctrl = 0; 7096 u32 phy_ctrl = 0;
7226 s32 ret_val; 7097 s32 ret_val;
@@ -7242,7 +7113,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7242 /* MAC writes into PHY register based on the state transition 7113 /* MAC writes into PHY register based on the state transition
7243 * and start auto-negotiation. SW driver can overwrite the settings 7114 * and start auto-negotiation. SW driver can overwrite the settings
7244 * in CSR PHY power control E1000_PHY_CTRL register. */ 7115 * in CSR PHY power control E1000_PHY_CTRL register. */
7245 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7116 phy_ctrl = er32(PHY_CTRL);
7246 } else { 7117 } else {
7247 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7118 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7248 if (ret_val) 7119 if (ret_val)
@@ -7259,7 +7130,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7259 } else { 7130 } else {
7260 if (hw->mac_type == e1000_ich8lan) { 7131 if (hw->mac_type == e1000_ich8lan) {
7261 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 7132 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7262 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7133 ew32(PHY_CTRL, phy_ctrl);
7263 } else { 7134 } else {
7264 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7135 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7265 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7136 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
@@ -7310,7 +7181,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7310 } else { 7181 } else {
7311 if (hw->mac_type == e1000_ich8lan) { 7182 if (hw->mac_type == e1000_ich8lan) {
7312 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 7183 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7313 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7184 ew32(PHY_CTRL, phy_ctrl);
7314 } else { 7185 } else {
7315 phy_data |= IGP02E1000_PM_D3_LPLU; 7186 phy_data |= IGP02E1000_PM_D3_LPLU;
7316 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7187 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
@@ -7348,9 +7219,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7348 * 7219 *
7349 ****************************************************************************/ 7220 ****************************************************************************/
7350 7221
7351static s32 7222static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7352e1000_set_d0_lplu_state(struct e1000_hw *hw,
7353 bool active)
7354{ 7223{
7355 u32 phy_ctrl = 0; 7224 u32 phy_ctrl = 0;
7356 s32 ret_val; 7225 s32 ret_val;
@@ -7361,7 +7230,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7361 return E1000_SUCCESS; 7230 return E1000_SUCCESS;
7362 7231
7363 if (hw->mac_type == e1000_ich8lan) { 7232 if (hw->mac_type == e1000_ich8lan) {
7364 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7233 phy_ctrl = er32(PHY_CTRL);
7365 } else { 7234 } else {
7366 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7235 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7367 if (ret_val) 7236 if (ret_val)
@@ -7371,7 +7240,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7371 if (!active) { 7240 if (!active) {
7372 if (hw->mac_type == e1000_ich8lan) { 7241 if (hw->mac_type == e1000_ich8lan) {
7373 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 7242 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7374 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7243 ew32(PHY_CTRL, phy_ctrl);
7375 } else { 7244 } else {
7376 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7245 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7377 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7246 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
@@ -7412,7 +7281,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7412 7281
7413 if (hw->mac_type == e1000_ich8lan) { 7282 if (hw->mac_type == e1000_ich8lan) {
7414 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 7283 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7415 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7284 ew32(PHY_CTRL, phy_ctrl);
7416 } else { 7285 } else {
7417 phy_data |= IGP02E1000_PM_D0_LPLU; 7286 phy_data |= IGP02E1000_PM_D0_LPLU;
7418 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7287 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
@@ -7439,8 +7308,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7439 * 7308 *
7440 * hw - Struct containing variables accessed by shared code 7309 * hw - Struct containing variables accessed by shared code
7441 *****************************************************************************/ 7310 *****************************************************************************/
7442static s32 7311static s32 e1000_set_vco_speed(struct e1000_hw *hw)
7443e1000_set_vco_speed(struct e1000_hw *hw)
7444{ 7312{
7445 s32 ret_val; 7313 s32 ret_val;
7446 u16 default_page = 0; 7314 u16 default_page = 0;
@@ -7503,8 +7371,7 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7503 * 7371 *
7504 * returns: - E1000_SUCCESS . 7372 * returns: - E1000_SUCCESS .
7505 ****************************************************************************/ 7373 ****************************************************************************/
7506static s32 7374static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer)
7507e1000_host_if_read_cookie(struct e1000_hw * hw, u8 *buffer)
7508{ 7375{
7509 u8 i; 7376 u8 i;
7510 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET; 7377 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
@@ -7514,7 +7381,7 @@ e1000_host_if_read_cookie(struct e1000_hw * hw, u8 *buffer)
7514 offset = (offset >> 2); 7381 offset = (offset >> 2);
7515 7382
7516 for (i = 0; i < length; i++) { 7383 for (i = 0; i < length; i++) {
7517 *((u32 *) buffer + i) = 7384 *((u32 *)buffer + i) =
7518 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 7385 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7519 } 7386 }
7520 return E1000_SUCCESS; 7387 return E1000_SUCCESS;
@@ -7530,21 +7397,20 @@ e1000_host_if_read_cookie(struct e1000_hw * hw, u8 *buffer)
7530 * timeout 7397 * timeout
7531 * - E1000_SUCCESS for success. 7398 * - E1000_SUCCESS for success.
7532 ****************************************************************************/ 7399 ****************************************************************************/
7533static s32 7400static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
7534e1000_mng_enable_host_if(struct e1000_hw * hw)
7535{ 7401{
7536 u32 hicr; 7402 u32 hicr;
7537 u8 i; 7403 u8 i;
7538 7404
7539 /* Check that the host interface is enabled. */ 7405 /* Check that the host interface is enabled. */
7540 hicr = E1000_READ_REG(hw, HICR); 7406 hicr = er32(HICR);
7541 if ((hicr & E1000_HICR_EN) == 0) { 7407 if ((hicr & E1000_HICR_EN) == 0) {
7542 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 7408 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7543 return -E1000_ERR_HOST_INTERFACE_COMMAND; 7409 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7544 } 7410 }
7545 /* check the previous command is completed */ 7411 /* check the previous command is completed */
7546 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 7412 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7547 hicr = E1000_READ_REG(hw, HICR); 7413 hicr = er32(HICR);
7548 if (!(hicr & E1000_HICR_C)) 7414 if (!(hicr & E1000_HICR_C))
7549 break; 7415 break;
7550 mdelay(1); 7416 mdelay(1);
@@ -7564,9 +7430,8 @@ e1000_mng_enable_host_if(struct e1000_hw * hw)
7564 * 7430 *
7565 * returns - E1000_SUCCESS for success. 7431 * returns - E1000_SUCCESS for success.
7566 ****************************************************************************/ 7432 ****************************************************************************/
7567static s32 7433static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
7568e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, 7434 u16 offset, u8 *sum)
7569 u16 length, u16 offset, u8 *sum)
7570{ 7435{
7571 u8 *tmp; 7436 u8 *tmp;
7572 u8 *bufptr = buffer; 7437 u8 *bufptr = buffer;
@@ -7632,9 +7497,8 @@ e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer,
7632 * 7497 *
7633 * returns - E1000_SUCCESS for success. 7498 * returns - E1000_SUCCESS for success.
7634 ****************************************************************************/ 7499 ****************************************************************************/
7635static s32 7500static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
7636e1000_mng_write_cmd_header(struct e1000_hw * hw, 7501 struct e1000_host_mng_command_header *hdr)
7637 struct e1000_host_mng_command_header * hdr)
7638{ 7502{
7639 u16 i; 7503 u16 i;
7640 u8 sum; 7504 u8 sum;
@@ -7648,7 +7512,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7648 sum = hdr->checksum; 7512 sum = hdr->checksum;
7649 hdr->checksum = 0; 7513 hdr->checksum = 0;
7650 7514
7651 buffer = (u8 *) hdr; 7515 buffer = (u8 *)hdr;
7652 i = length; 7516 i = length;
7653 while (i--) 7517 while (i--)
7654 sum += buffer[i]; 7518 sum += buffer[i];
@@ -7658,8 +7522,8 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7658 length >>= 2; 7522 length >>= 2;
7659 /* The device driver writes the relevant command block into the ram area. */ 7523 /* The device driver writes the relevant command block into the ram area. */
7660 for (i = 0; i < length; i++) { 7524 for (i = 0; i < length; i++) {
7661 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *) hdr + i)); 7525 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i));
7662 E1000_WRITE_FLUSH(hw); 7526 E1000_WRITE_FLUSH();
7663 } 7527 }
7664 7528
7665 return E1000_SUCCESS; 7529 return E1000_SUCCESS;
@@ -7672,14 +7536,13 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7672 * 7536 *
7673 * returns - E1000_SUCCESS for success. 7537 * returns - E1000_SUCCESS for success.
7674 ****************************************************************************/ 7538 ****************************************************************************/
7675static s32 7539static s32 e1000_mng_write_commit(struct e1000_hw *hw)
7676e1000_mng_write_commit(struct e1000_hw * hw)
7677{ 7540{
7678 u32 hicr; 7541 u32 hicr;
7679 7542
7680 hicr = E1000_READ_REG(hw, HICR); 7543 hicr = er32(HICR);
7681 /* Setting this bit tells the ARC that a new command is pending. */ 7544 /* Setting this bit tells the ARC that a new command is pending. */
7682 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); 7545 ew32(HICR, hicr | E1000_HICR_C);
7683 7546
7684 return E1000_SUCCESS; 7547 return E1000_SUCCESS;
7685} 7548}
@@ -7690,12 +7553,11 @@ e1000_mng_write_commit(struct e1000_hw * hw)
7690 * 7553 *
7691 * returns - true when the mode is IAMT or false. 7554 * returns - true when the mode is IAMT or false.
7692 ****************************************************************************/ 7555 ****************************************************************************/
7693bool 7556bool e1000_check_mng_mode(struct e1000_hw *hw)
7694e1000_check_mng_mode(struct e1000_hw *hw)
7695{ 7557{
7696 u32 fwsm; 7558 u32 fwsm;
7697 7559
7698 fwsm = E1000_READ_REG(hw, FWSM); 7560 fwsm = er32(FWSM);
7699 7561
7700 if (hw->mac_type == e1000_ich8lan) { 7562 if (hw->mac_type == e1000_ich8lan) {
7701 if ((fwsm & E1000_FWSM_MODE_MASK) == 7563 if ((fwsm & E1000_FWSM_MODE_MASK) ==
@@ -7712,9 +7574,7 @@ e1000_check_mng_mode(struct e1000_hw *hw)
7712/***************************************************************************** 7574/*****************************************************************************
7713 * This function writes the dhcp info . 7575 * This function writes the dhcp info .
7714 ****************************************************************************/ 7576 ****************************************************************************/
7715s32 7577s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
7716e1000_mng_write_dhcp_info(struct e1000_hw * hw, u8 *buffer,
7717 u16 length)
7718{ 7578{
7719 s32 ret_val; 7579 s32 ret_val;
7720 struct e1000_host_mng_command_header hdr; 7580 struct e1000_host_mng_command_header hdr;
@@ -7744,8 +7604,7 @@ e1000_mng_write_dhcp_info(struct e1000_hw * hw, u8 *buffer,
7744 * 7604 *
7745 * returns - checksum of buffer contents. 7605 * returns - checksum of buffer contents.
7746 ****************************************************************************/ 7606 ****************************************************************************/
7747static u8 7607static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
7748e1000_calculate_mng_checksum(char *buffer, u32 length)
7749{ 7608{
7750 u8 sum = 0; 7609 u8 sum = 0;
7751 u32 i; 7610 u32 i;
@@ -7756,7 +7615,7 @@ e1000_calculate_mng_checksum(char *buffer, u32 length)
7756 for (i=0; i < length; i++) 7615 for (i=0; i < length; i++)
7757 sum += buffer[i]; 7616 sum += buffer[i];
7758 7617
7759 return (u8) (0 - sum); 7618 return (u8)(0 - sum);
7760} 7619}
7761 7620
7762/***************************************************************************** 7621/*****************************************************************************
@@ -7764,8 +7623,7 @@ e1000_calculate_mng_checksum(char *buffer, u32 length)
7764 * 7623 *
7765 * returns - true for packet filtering or false. 7624 * returns - true for packet filtering or false.
7766 ****************************************************************************/ 7625 ****************************************************************************/
7767bool 7626bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7768e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7769{ 7627{
7770 /* called in init as well as watchdog timer functions */ 7628 /* called in init as well as watchdog timer functions */
7771 7629
@@ -7806,21 +7664,20 @@ e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7806 * returns: - true/false 7664 * returns: - true/false
7807 * 7665 *
7808 *****************************************************************************/ 7666 *****************************************************************************/
7809u32 7667u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7810e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7811{ 7668{
7812 u32 manc; 7669 u32 manc;
7813 u32 fwsm, factps; 7670 u32 fwsm, factps;
7814 7671
7815 if (hw->asf_firmware_present) { 7672 if (hw->asf_firmware_present) {
7816 manc = E1000_READ_REG(hw, MANC); 7673 manc = er32(MANC);
7817 7674
7818 if (!(manc & E1000_MANC_RCV_TCO_EN) || 7675 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7819 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 7676 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7820 return false; 7677 return false;
7821 if (e1000_arc_subsystem_valid(hw)) { 7678 if (e1000_arc_subsystem_valid(hw)) {
7822 fwsm = E1000_READ_REG(hw, FWSM); 7679 fwsm = er32(FWSM);
7823 factps = E1000_READ_REG(hw, FACTPS); 7680 factps = er32(FACTPS);
7824 7681
7825 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == 7682 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7826 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) 7683 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
@@ -7832,8 +7689,7 @@ e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7832 return false; 7689 return false;
7833} 7690}
7834 7691
7835static s32 7692static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7836e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7837{ 7693{
7838 s32 ret_val; 7694 s32 ret_val;
7839 u16 mii_status_reg; 7695 u16 mii_status_reg;
@@ -7926,8 +7782,7 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7926 * returns: - none. 7782 * returns: - none.
7927 * 7783 *
7928 ***************************************************************************/ 7784 ***************************************************************************/
7929static void 7785static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7930e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7931{ 7786{
7932 u32 ctrl; 7787 u32 ctrl;
7933 7788
@@ -7936,9 +7791,9 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7936 if (hw->bus_type != e1000_bus_type_pci_express) 7791 if (hw->bus_type != e1000_bus_type_pci_express)
7937 return; 7792 return;
7938 7793
7939 ctrl = E1000_READ_REG(hw, CTRL); 7794 ctrl = er32(CTRL);
7940 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 7795 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7941 E1000_WRITE_REG(hw, CTRL, ctrl); 7796 ew32(CTRL, ctrl);
7942} 7797}
7943 7798
7944/******************************************************************************* 7799/*******************************************************************************
@@ -7952,8 +7807,7 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7952 * E1000_SUCCESS master requests disabled. 7807 * E1000_SUCCESS master requests disabled.
7953 * 7808 *
7954 ******************************************************************************/ 7809 ******************************************************************************/
7955s32 7810s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7956e1000_disable_pciex_master(struct e1000_hw *hw)
7957{ 7811{
7958 s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 7812 s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7959 7813
@@ -7965,7 +7819,7 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
7965 e1000_set_pci_express_master_disable(hw); 7819 e1000_set_pci_express_master_disable(hw);
7966 7820
7967 while (timeout) { 7821 while (timeout) {
7968 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 7822 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7969 break; 7823 break;
7970 else 7824 else
7971 udelay(100); 7825 udelay(100);
@@ -7990,8 +7844,7 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
7990 * E1000_SUCCESS at any other case. 7844 * E1000_SUCCESS at any other case.
7991 * 7845 *
7992 ******************************************************************************/ 7846 ******************************************************************************/
7993static s32 7847static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7994e1000_get_auto_rd_done(struct e1000_hw *hw)
7995{ 7848{
7996 s32 timeout = AUTO_READ_DONE_TIMEOUT; 7849 s32 timeout = AUTO_READ_DONE_TIMEOUT;
7997 7850
@@ -8007,7 +7860,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8007 case e1000_80003es2lan: 7860 case e1000_80003es2lan:
8008 case e1000_ich8lan: 7861 case e1000_ich8lan:
8009 while (timeout) { 7862 while (timeout) {
8010 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 7863 if (er32(EECD) & E1000_EECD_AUTO_RD)
8011 break; 7864 break;
8012 else msleep(1); 7865 else msleep(1);
8013 timeout--; 7866 timeout--;
@@ -8038,8 +7891,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8038 * E1000_SUCCESS at any other case. 7891 * E1000_SUCCESS at any other case.
8039 * 7892 *
8040 ***************************************************************************/ 7893 ***************************************************************************/
8041static s32 7894static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8042e1000_get_phy_cfg_done(struct e1000_hw *hw)
8043{ 7895{
8044 s32 timeout = PHY_CFG_TIMEOUT; 7896 s32 timeout = PHY_CFG_TIMEOUT;
8045 u32 cfg_mask = E1000_EEPROM_CFG_DONE; 7897 u32 cfg_mask = E1000_EEPROM_CFG_DONE;
@@ -8052,13 +7904,13 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
8052 break; 7904 break;
8053 case e1000_80003es2lan: 7905 case e1000_80003es2lan:
8054 /* Separate *_CFG_DONE_* bit for each port */ 7906 /* Separate *_CFG_DONE_* bit for each port */
8055 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7907 if (er32(STATUS) & E1000_STATUS_FUNC_1)
8056 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 7908 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8057 /* Fall Through */ 7909 /* Fall Through */
8058 case e1000_82571: 7910 case e1000_82571:
8059 case e1000_82572: 7911 case e1000_82572:
8060 while (timeout) { 7912 while (timeout) {
8061 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 7913 if (er32(EEMNGCTL) & cfg_mask)
8062 break; 7914 break;
8063 else 7915 else
8064 msleep(1); 7916 msleep(1);
@@ -8085,8 +7937,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
8085 * E1000_SUCCESS at any other case. 7937 * E1000_SUCCESS at any other case.
8086 * 7938 *
8087 ***************************************************************************/ 7939 ***************************************************************************/
8088static s32 7940static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8089e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8090{ 7941{
8091 s32 timeout; 7942 s32 timeout;
8092 u32 swsm; 7943 u32 swsm;
@@ -8105,11 +7956,11 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8105 /* Get the FW semaphore. */ 7956 /* Get the FW semaphore. */
8106 timeout = hw->eeprom.word_size + 1; 7957 timeout = hw->eeprom.word_size + 1;
8107 while (timeout) { 7958 while (timeout) {
8108 swsm = E1000_READ_REG(hw, SWSM); 7959 swsm = er32(SWSM);
8109 swsm |= E1000_SWSM_SWESMBI; 7960 swsm |= E1000_SWSM_SWESMBI;
8110 E1000_WRITE_REG(hw, SWSM, swsm); 7961 ew32(SWSM, swsm);
8111 /* if we managed to set the bit we got the semaphore. */ 7962 /* if we managed to set the bit we got the semaphore. */
8112 swsm = E1000_READ_REG(hw, SWSM); 7963 swsm = er32(SWSM);
8113 if (swsm & E1000_SWSM_SWESMBI) 7964 if (swsm & E1000_SWSM_SWESMBI)
8114 break; 7965 break;
8115 7966
@@ -8135,8 +7986,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8135 * returns: - None. 7986 * returns: - None.
8136 * 7987 *
8137 ***************************************************************************/ 7988 ***************************************************************************/
8138static void 7989static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8139e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8140{ 7990{
8141 u32 swsm; 7991 u32 swsm;
8142 7992
@@ -8145,13 +7995,13 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8145 if (!hw->eeprom_semaphore_present) 7995 if (!hw->eeprom_semaphore_present)
8146 return; 7996 return;
8147 7997
8148 swsm = E1000_READ_REG(hw, SWSM); 7998 swsm = er32(SWSM);
8149 if (hw->mac_type == e1000_80003es2lan) { 7999 if (hw->mac_type == e1000_80003es2lan) {
8150 /* Release both semaphores. */ 8000 /* Release both semaphores. */
8151 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 8001 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8152 } else 8002 } else
8153 swsm &= ~(E1000_SWSM_SWESMBI); 8003 swsm &= ~(E1000_SWSM_SWESMBI);
8154 E1000_WRITE_REG(hw, SWSM, swsm); 8004 ew32(SWSM, swsm);
8155} 8005}
8156 8006
8157/*************************************************************************** 8007/***************************************************************************
@@ -8164,8 +8014,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8164 * E1000_SUCCESS at any other case. 8014 * E1000_SUCCESS at any other case.
8165 * 8015 *
8166 ***************************************************************************/ 8016 ***************************************************************************/
8167static s32 8017static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
8168e1000_get_software_semaphore(struct e1000_hw *hw)
8169{ 8018{
8170 s32 timeout = hw->eeprom.word_size + 1; 8019 s32 timeout = hw->eeprom.word_size + 1;
8171 u32 swsm; 8020 u32 swsm;
@@ -8177,7 +8026,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8177 } 8026 }
8178 8027
8179 while (timeout) { 8028 while (timeout) {
8180 swsm = E1000_READ_REG(hw, SWSM); 8029 swsm = er32(SWSM);
8181 /* If SMBI bit cleared, it is now set and we hold the semaphore */ 8030 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8182 if (!(swsm & E1000_SWSM_SMBI)) 8031 if (!(swsm & E1000_SWSM_SMBI))
8183 break; 8032 break;
@@ -8200,8 +8049,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8200 * hw: Struct containing variables accessed by shared code 8049 * hw: Struct containing variables accessed by shared code
8201 * 8050 *
8202 ***************************************************************************/ 8051 ***************************************************************************/
8203static void 8052static void e1000_release_software_semaphore(struct e1000_hw *hw)
8204e1000_release_software_semaphore(struct e1000_hw *hw)
8205{ 8053{
8206 u32 swsm; 8054 u32 swsm;
8207 8055
@@ -8211,10 +8059,10 @@ e1000_release_software_semaphore(struct e1000_hw *hw)
8211 return; 8059 return;
8212 } 8060 }
8213 8061
8214 swsm = E1000_READ_REG(hw, SWSM); 8062 swsm = er32(SWSM);
8215 /* Release the SW semaphores.*/ 8063 /* Release the SW semaphores.*/
8216 swsm &= ~E1000_SWSM_SMBI; 8064 swsm &= ~E1000_SWSM_SMBI;
8217 E1000_WRITE_REG(hw, SWSM, swsm); 8065 ew32(SWSM, swsm);
8218} 8066}
8219 8067
8220/****************************************************************************** 8068/******************************************************************************
@@ -8228,26 +8076,24 @@ e1000_release_software_semaphore(struct e1000_hw *hw)
8228 * E1000_SUCCESS 8076 * E1000_SUCCESS
8229 * 8077 *
8230 *****************************************************************************/ 8078 *****************************************************************************/
8231s32 8079s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
8232e1000_check_phy_reset_block(struct e1000_hw *hw)
8233{ 8080{
8234 u32 manc = 0; 8081 u32 manc = 0;
8235 u32 fwsm = 0; 8082 u32 fwsm = 0;
8236 8083
8237 if (hw->mac_type == e1000_ich8lan) { 8084 if (hw->mac_type == e1000_ich8lan) {
8238 fwsm = E1000_READ_REG(hw, FWSM); 8085 fwsm = er32(FWSM);
8239 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 8086 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8240 : E1000_BLK_PHY_RESET; 8087 : E1000_BLK_PHY_RESET;
8241 } 8088 }
8242 8089
8243 if (hw->mac_type > e1000_82547_rev_2) 8090 if (hw->mac_type > e1000_82547_rev_2)
8244 manc = E1000_READ_REG(hw, MANC); 8091 manc = er32(MANC);
8245 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8092 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8246 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8093 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8247} 8094}
8248 8095
8249static u8 8096static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8250e1000_arc_subsystem_valid(struct e1000_hw *hw)
8251{ 8097{
8252 u32 fwsm; 8098 u32 fwsm;
8253 8099
@@ -8261,7 +8107,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
8261 case e1000_82572: 8107 case e1000_82572:
8262 case e1000_82573: 8108 case e1000_82573:
8263 case e1000_80003es2lan: 8109 case e1000_80003es2lan:
8264 fwsm = E1000_READ_REG(hw, FWSM); 8110 fwsm = er32(FWSM);
8265 if ((fwsm & E1000_FWSM_MODE_MASK) != 0) 8111 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8266 return true; 8112 return true;
8267 break; 8113 break;
@@ -8283,8 +8129,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
8283 * returns: E1000_SUCCESS 8129 * returns: E1000_SUCCESS
8284 * 8130 *
8285 *****************************************************************************/ 8131 *****************************************************************************/
8286static s32 8132static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8287e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8288{ 8133{
8289 u32 gcr_reg = 0; 8134 u32 gcr_reg = 0;
8290 8135
@@ -8297,19 +8142,19 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8297 return E1000_SUCCESS; 8142 return E1000_SUCCESS;
8298 8143
8299 if (no_snoop) { 8144 if (no_snoop) {
8300 gcr_reg = E1000_READ_REG(hw, GCR); 8145 gcr_reg = er32(GCR);
8301 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 8146 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8302 gcr_reg |= no_snoop; 8147 gcr_reg |= no_snoop;
8303 E1000_WRITE_REG(hw, GCR, gcr_reg); 8148 ew32(GCR, gcr_reg);
8304 } 8149 }
8305 if (hw->mac_type == e1000_ich8lan) { 8150 if (hw->mac_type == e1000_ich8lan) {
8306 u32 ctrl_ext; 8151 u32 ctrl_ext;
8307 8152
8308 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); 8153 ew32(GCR, PCI_EX_82566_SNOOP_ALL);
8309 8154
8310 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8155 ctrl_ext = er32(CTRL_EXT);
8311 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 8156 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8312 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8157 ew32(CTRL_EXT, ctrl_ext);
8313 } 8158 }
8314 8159
8315 return E1000_SUCCESS; 8160 return E1000_SUCCESS;
@@ -8324,8 +8169,7 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8324 * hw: Struct containing variables accessed by shared code 8169 * hw: Struct containing variables accessed by shared code
8325 * 8170 *
8326 ***************************************************************************/ 8171 ***************************************************************************/
8327static s32 8172static s32 e1000_get_software_flag(struct e1000_hw *hw)
8328e1000_get_software_flag(struct e1000_hw *hw)
8329{ 8173{
8330 s32 timeout = PHY_CFG_TIMEOUT; 8174 s32 timeout = PHY_CFG_TIMEOUT;
8331 u32 extcnf_ctrl; 8175 u32 extcnf_ctrl;
@@ -8334,11 +8178,11 @@ e1000_get_software_flag(struct e1000_hw *hw)
8334 8178
8335 if (hw->mac_type == e1000_ich8lan) { 8179 if (hw->mac_type == e1000_ich8lan) {
8336 while (timeout) { 8180 while (timeout) {
8337 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8181 extcnf_ctrl = er32(EXTCNF_CTRL);
8338 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 8182 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8339 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8183 ew32(EXTCNF_CTRL, extcnf_ctrl);
8340 8184
8341 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8185 extcnf_ctrl = er32(EXTCNF_CTRL);
8342 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 8186 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8343 break; 8187 break;
8344 mdelay(1); 8188 mdelay(1);
@@ -8363,17 +8207,16 @@ e1000_get_software_flag(struct e1000_hw *hw)
8363 * hw: Struct containing variables accessed by shared code 8207 * hw: Struct containing variables accessed by shared code
8364 * 8208 *
8365 ***************************************************************************/ 8209 ***************************************************************************/
8366static void 8210static void e1000_release_software_flag(struct e1000_hw *hw)
8367e1000_release_software_flag(struct e1000_hw *hw)
8368{ 8211{
8369 u32 extcnf_ctrl; 8212 u32 extcnf_ctrl;
8370 8213
8371 DEBUGFUNC("e1000_release_software_flag"); 8214 DEBUGFUNC("e1000_release_software_flag");
8372 8215
8373 if (hw->mac_type == e1000_ich8lan) { 8216 if (hw->mac_type == e1000_ich8lan) {
8374 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); 8217 extcnf_ctrl= er32(EXTCNF_CTRL);
8375 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 8218 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8376 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8219 ew32(EXTCNF_CTRL, extcnf_ctrl);
8377 } 8220 }
8378 8221
8379 return; 8222 return;
@@ -8388,9 +8231,8 @@ e1000_release_software_flag(struct e1000_hw *hw)
8388 * data - word read from the EEPROM 8231 * data - word read from the EEPROM
8389 * words - number of words to read 8232 * words - number of words to read
8390 *****************************************************************************/ 8233 *****************************************************************************/
8391static s32 8234static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8392e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, 8235 u16 *data)
8393 u16 *data)
8394{ 8236{
8395 s32 error = E1000_SUCCESS; 8237 s32 error = E1000_SUCCESS;
8396 u32 flash_bank = 0; 8238 u32 flash_bank = 0;
@@ -8405,7 +8247,7 @@ e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8405 * to be updated with each read. 8247 * to be updated with each read.
8406 */ 8248 */
8407 /* Value of bit 22 corresponds to the flash bank we're on. */ 8249 /* Value of bit 22 corresponds to the flash bank we're on. */
8408 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; 8250 flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8409 8251
8410 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ 8252 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8411 bank_offset = flash_bank * (hw->flash_bank_size * 2); 8253 bank_offset = flash_bank * (hw->flash_bank_size * 2);
@@ -8444,9 +8286,8 @@ e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8444 * words - number of words to write 8286 * words - number of words to write
8445 * data - words to write to the EEPROM 8287 * data - words to write to the EEPROM
8446 *****************************************************************************/ 8288 *****************************************************************************/
8447static s32 8289static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8448e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, 8290 u16 *data)
8449 u16 *data)
8450{ 8291{
8451 u32 i = 0; 8292 u32 i = 0;
8452 s32 error = E1000_SUCCESS; 8293 s32 error = E1000_SUCCESS;
@@ -8491,8 +8332,7 @@ e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8491 * 8332 *
8492 * hw - The pointer to the hw structure 8333 * hw - The pointer to the hw structure
8493 ****************************************************************************/ 8334 ****************************************************************************/
8494static s32 8335static s32 e1000_ich8_cycle_init(struct e1000_hw *hw)
8495e1000_ich8_cycle_init(struct e1000_hw *hw)
8496{ 8336{
8497 union ich8_hws_flash_status hsfsts; 8337 union ich8_hws_flash_status hsfsts;
8498 s32 error = E1000_ERR_EEPROM; 8338 s32 error = E1000_ERR_EEPROM;
@@ -8558,8 +8398,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8558 * 8398 *
8559 * hw - The pointer to the hw structure 8399 * hw - The pointer to the hw structure
8560 ****************************************************************************/ 8400 ****************************************************************************/
8561static s32 8401static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8562e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8563{ 8402{
8564 union ich8_hws_flash_ctrl hsflctl; 8403 union ich8_hws_flash_ctrl hsflctl;
8565 union ich8_hws_flash_status hsfsts; 8404 union ich8_hws_flash_status hsfsts;
@@ -8593,9 +8432,8 @@ e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8593 * size - Size of data to read, 1=byte 2=word 8432 * size - Size of data to read, 1=byte 2=word
8594 * data - Pointer to the word to store the value read. 8433 * data - Pointer to the word to store the value read.
8595 *****************************************************************************/ 8434 *****************************************************************************/
8596static s32 8435static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8597e1000_read_ich8_data(struct e1000_hw *hw, u32 index, 8436 u16 *data)
8598 u32 size, u16* data)
8599{ 8437{
8600 union ich8_hws_flash_status hsfsts; 8438 union ich8_hws_flash_status hsfsts;
8601 union ich8_hws_flash_ctrl hsflctl; 8439 union ich8_hws_flash_ctrl hsflctl;
@@ -8672,9 +8510,8 @@ e1000_read_ich8_data(struct e1000_hw *hw, u32 index,
8672 * size - Size of data to read, 1=byte 2=word 8510 * size - Size of data to read, 1=byte 2=word
8673 * data - The byte(s) to write to the NVM. 8511 * data - The byte(s) to write to the NVM.
8674 *****************************************************************************/ 8512 *****************************************************************************/
8675static s32 8513static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8676e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, 8514 u16 data)
8677 u16 data)
8678{ 8515{
8679 union ich8_hws_flash_status hsfsts; 8516 union ich8_hws_flash_status hsfsts;
8680 union ich8_hws_flash_ctrl hsflctl; 8517 union ich8_hws_flash_ctrl hsflctl;
@@ -8747,8 +8584,7 @@ e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8747 * index - The index of the byte to read. 8584 * index - The index of the byte to read.
8748 * data - Pointer to a byte to store the value read. 8585 * data - Pointer to a byte to store the value read.
8749 *****************************************************************************/ 8586 *****************************************************************************/
8750static s32 8587static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data)
8751e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8* data)
8752{ 8588{
8753 s32 status = E1000_SUCCESS; 8589 s32 status = E1000_SUCCESS;
8754 u16 word = 0; 8590 u16 word = 0;
@@ -8770,8 +8606,7 @@ e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8* data)
8770 * index - The index of the byte to write. 8606 * index - The index of the byte to write.
8771 * byte - The byte to write to the NVM. 8607 * byte - The byte to write to the NVM.
8772 *****************************************************************************/ 8608 *****************************************************************************/
8773static s32 8609static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8774e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8775{ 8610{
8776 s32 error = E1000_SUCCESS; 8611 s32 error = E1000_SUCCESS;
8777 s32 program_retries = 0; 8612 s32 program_retries = 0;
@@ -8803,8 +8638,7 @@ e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8803 * index - The index of the byte to read. 8638 * index - The index of the byte to read.
8804 * data - The byte to write to the NVM. 8639 * data - The byte to write to the NVM.
8805 *****************************************************************************/ 8640 *****************************************************************************/
8806static s32 8641static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8807e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8808{ 8642{
8809 s32 status = E1000_SUCCESS; 8643 s32 status = E1000_SUCCESS;
8810 u16 word = (u16)data; 8644 u16 word = (u16)data;
@@ -8821,8 +8655,7 @@ e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8821 * index - The starting byte index of the word to read. 8655 * index - The starting byte index of the word to read.
8822 * data - Pointer to a word to store the value read. 8656 * data - Pointer to a word to store the value read.
8823 *****************************************************************************/ 8657 *****************************************************************************/
8824static s32 8658static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8825e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8826{ 8659{
8827 s32 status = E1000_SUCCESS; 8660 s32 status = E1000_SUCCESS;
8828 status = e1000_read_ich8_data(hw, index, 2, data); 8661 status = e1000_read_ich8_data(hw, index, 2, data);
@@ -8840,8 +8673,7 @@ e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8840 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 8673 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8841 * bank size may be 4, 8 or 64 KBytes 8674 * bank size may be 4, 8 or 64 KBytes
8842 *****************************************************************************/ 8675 *****************************************************************************/
8843static s32 8676static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8844e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8845{ 8677{
8846 union ich8_hws_flash_status hsfsts; 8678 union ich8_hws_flash_status hsfsts;
8847 union ich8_hws_flash_ctrl hsflctl; 8679 union ich8_hws_flash_ctrl hsflctl;
@@ -8930,9 +8762,9 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8930 return error; 8762 return error;
8931} 8763}
8932 8764
8933static s32 8765static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8934e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, 8766 u32 cnf_base_addr,
8935 u32 cnf_base_addr, u32 cnf_size) 8767 u32 cnf_size)
8936{ 8768{
8937 u32 ret_val = E1000_SUCCESS; 8769 u32 ret_val = E1000_SUCCESS;
8938 u16 word_addr, reg_data, reg_addr; 8770 u16 word_addr, reg_data, reg_addr;
@@ -8972,8 +8804,7 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8972 * 8804 *
8973 * hw: Struct containing variables accessed by shared code 8805 * hw: Struct containing variables accessed by shared code
8974 *****************************************************************************/ 8806 *****************************************************************************/
8975static s32 8807static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8976e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8977{ 8808{
8978 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop; 8809 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8979 8810
@@ -8981,32 +8812,32 @@ e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8981 return E1000_SUCCESS; 8812 return E1000_SUCCESS;
8982 8813
8983 /* Check if SW needs configure the PHY */ 8814 /* Check if SW needs configure the PHY */
8984 reg_data = E1000_READ_REG(hw, FEXTNVM); 8815 reg_data = er32(FEXTNVM);
8985 if (!(reg_data & FEXTNVM_SW_CONFIG)) 8816 if (!(reg_data & FEXTNVM_SW_CONFIG))
8986 return E1000_SUCCESS; 8817 return E1000_SUCCESS;
8987 8818
8988 /* Wait for basic configuration completes before proceeding*/ 8819 /* Wait for basic configuration completes before proceeding*/
8989 loop = 0; 8820 loop = 0;
8990 do { 8821 do {
8991 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 8822 reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
8992 udelay(100); 8823 udelay(100);
8993 loop++; 8824 loop++;
8994 } while ((!reg_data) && (loop < 50)); 8825 } while ((!reg_data) && (loop < 50));
8995 8826
8996 /* Clear the Init Done bit for the next init event */ 8827 /* Clear the Init Done bit for the next init event */
8997 reg_data = E1000_READ_REG(hw, STATUS); 8828 reg_data = er32(STATUS);
8998 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 8829 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8999 E1000_WRITE_REG(hw, STATUS, reg_data); 8830 ew32(STATUS, reg_data);
9000 8831
9001 /* Make sure HW does not configure LCD from PHY extended configuration 8832 /* Make sure HW does not configure LCD from PHY extended configuration
9002 before SW configuration */ 8833 before SW configuration */
9003 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8834 reg_data = er32(EXTCNF_CTRL);
9004 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 8835 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9005 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 8836 reg_data = er32(EXTCNF_SIZE);
9006 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 8837 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9007 cnf_size >>= 16; 8838 cnf_size >>= 16;
9008 if (cnf_size) { 8839 if (cnf_size) {
9009 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8840 reg_data = er32(EXTCNF_CTRL);
9010 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 8841 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9011 /* cnf_base_addr is in DWORD */ 8842 /* cnf_base_addr is in DWORD */
9012 cnf_base_addr >>= 16; 8843 cnf_base_addr >>= 16;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 17:18:30 -0500